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pseries: fix TCG migration
[qemu/ar7.git] / hw / ppc / spapr.c
bloba471de6cab739f30436e7e29671d8fd8d5e7fdfe
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "qapi/visitor.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/numa.h"
32 #include "hw/hw.h"
33 #include "qemu/log.h"
34 #include "hw/fw-path-provider.h"
35 #include "elf.h"
36 #include "net/net.h"
37 #include "sysemu/device_tree.h"
38 #include "sysemu/block-backend.h"
39 #include "sysemu/cpus.h"
40 #include "sysemu/hw_accel.h"
41 #include "kvm_ppc.h"
42 #include "migration/misc.h"
43 #include "migration/global_state.h"
44 #include "migration/register.h"
45 #include "mmu-hash64.h"
46 #include "mmu-book3s-v3.h"
47 #include "cpu-models.h"
48 #include "qom/cpu.h"
49
50 #include "hw/boards.h"
51 #include "hw/ppc/ppc.h"
52 #include "hw/loader.h"
53
54 #include "hw/ppc/fdt.h"
55 #include "hw/ppc/spapr.h"
56 #include "hw/ppc/spapr_vio.h"
57 #include "hw/pci-host/spapr.h"
58 #include "hw/ppc/xics.h"
59 #include "hw/pci/msi.h"
60
61 #include "hw/pci/pci.h"
62 #include "hw/scsi/scsi.h"
63 #include "hw/virtio/virtio-scsi.h"
64 #include "hw/virtio/vhost-scsi-common.h"
65
66 #include "exec/address-spaces.h"
67 #include "hw/usb.h"
68 #include "qemu/config-file.h"
69 #include "qemu/error-report.h"
70 #include "trace.h"
71 #include "hw/nmi.h"
72 #include "hw/intc/intc.h"
73
74 #include "hw/compat.h"
75 #include "qemu/cutils.h"
76 #include "hw/ppc/spapr_cpu_core.h"
77 #include "qmp-commands.h"
78
79 #include <libfdt.h>
80
81 /* SLOF memory layout:
82 *
83 * SLOF raw image loaded at 0, copies its romfs right below the flat
84 * device-tree, then position SLOF itself 31M below that
85 *
86 * So we set FW_OVERHEAD to 40MB which should account for all of that
87 * and more
88 *
89 * We load our kernel at 4M, leaving space for SLOF initial image
90 */
91 #define FDT_MAX_SIZE 0x100000
92 #define RTAS_MAX_SIZE 0x10000
93 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
94 #define FW_MAX_SIZE 0x400000
95 #define FW_FILE_NAME "slof.bin"
96 #define FW_OVERHEAD 0x2800000
97 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
98
99 #define MIN_RMA_SLOF 128UL
100
101 #define PHANDLE_XICP 0x00001111
102
103 static ICSState *spapr_ics_create(sPAPRMachineState *spapr,
104 const char *type_ics,
105 int nr_irqs, Error **errp)
106 {
107 Error *local_err = NULL;
108 Object *obj;
109
110 obj = object_new(type_ics);
111 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
112 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
113 &error_abort);
114 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err);
115 if (local_err) {
116 goto error;
117 }
118 object_property_set_bool(obj, true, "realized", &local_err);
119 if (local_err) {
120 goto error;
121 }
122
123 return ICS_SIMPLE(obj);
124
125 error:
126 error_propagate(errp, local_err);
127 return NULL;
128 }
129
130 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
131 {
132 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
133 * and newer QEMUs don't even have them. In both cases, we don't want
134 * to send anything on the wire.
135 */
136 return false;
137 }
138
139 static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
140 .name = "icp/server",
141 .version_id = 1,
142 .minimum_version_id = 1,
143 .needed = pre_2_10_vmstate_dummy_icp_needed,
144 .fields = (VMStateField[]) {
145 VMSTATE_UNUSED(4), /* uint32_t xirr */
146 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
147 VMSTATE_UNUSED(1), /* uint8_t mfrr */
148 VMSTATE_END_OF_LIST()
149 },
150 };
151
152 static void pre_2_10_vmstate_register_dummy_icp(int i)
153 {
154 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
155 (void *)(uintptr_t) i);
156 }
157
158 static void pre_2_10_vmstate_unregister_dummy_icp(int i)
159 {
160 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
161 (void *)(uintptr_t) i);
162 }
163
164 static inline int xics_max_server_number(void)
165 {
166 return DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), smp_threads);
167 }
168
169 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp)
170 {
171 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
172 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
173
174 if (kvm_enabled()) {
175 if (machine_kernel_irqchip_allowed(machine) &&
176 !xics_kvm_init(spapr, errp)) {
177 spapr->icp_type = TYPE_KVM_ICP;
178 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp);
179 }
180 if (machine_kernel_irqchip_required(machine) && !spapr->ics) {
181 error_prepend(errp, "kernel_irqchip requested but unavailable: ");
182 return;
183 }
184 }
185
186 if (!spapr->ics) {
187 xics_spapr_init(spapr);
188 spapr->icp_type = TYPE_ICP;
189 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp);
190 if (!spapr->ics) {
191 return;
192 }
193 }
194
195 if (smc->pre_2_10_has_unused_icps) {
196 int i;
197
198 for (i = 0; i < xics_max_server_number(); i++) {
199 /* Dummy entries get deregistered when real ICPState objects
200 * are registered during CPU core hotplug.
201 */
202 pre_2_10_vmstate_register_dummy_icp(i);
203 }
204 }
205 }
206
207 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
208 int smt_threads)
209 {
210 int i, ret = 0;
211 uint32_t servers_prop[smt_threads];
212 uint32_t gservers_prop[smt_threads * 2];
213 int index = spapr_vcpu_id(cpu);
214
215 if (cpu->compat_pvr) {
216 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
217 if (ret < 0) {
218 return ret;
219 }
220 }
221
222 /* Build interrupt servers and gservers properties */
223 for (i = 0; i < smt_threads; i++) {
224 servers_prop[i] = cpu_to_be32(index + i);
225 /* Hack, direct the group queues back to cpu 0 */
226 gservers_prop[i*2] = cpu_to_be32(index + i);
227 gservers_prop[i*2 + 1] = 0;
228 }
229 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
230 servers_prop, sizeof(servers_prop));
231 if (ret < 0) {
232 return ret;
233 }
234 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
235 gservers_prop, sizeof(gservers_prop));
236
237 return ret;
238 }
239
240 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
241 {
242 int index = spapr_vcpu_id(cpu);
243 uint32_t associativity[] = {cpu_to_be32(0x5),
244 cpu_to_be32(0x0),
245 cpu_to_be32(0x0),
246 cpu_to_be32(0x0),
247 cpu_to_be32(cpu->node_id),
248 cpu_to_be32(index)};
249
250 /* Advertise NUMA via ibm,associativity */
251 return fdt_setprop(fdt, offset, "ibm,associativity", associativity,
252 sizeof(associativity));
253 }
254
255 /* Populate the "ibm,pa-features" property */
256 static void spapr_populate_pa_features(PowerPCCPU *cpu, void *fdt, int offset,
257 bool legacy_guest)
258 {
259 CPUPPCState *env = &cpu->env;
260 uint8_t pa_features_206[] = { 6, 0,
261 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
262 uint8_t pa_features_207[] = { 24, 0,
263 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
264 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
265 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
266 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
267 uint8_t pa_features_300[] = { 66, 0,
268 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
269 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
270 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
271 /* 6: DS207 */
272 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
273 /* 16: Vector */
274 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
275 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
276 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
277 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
278 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
279 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
280 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
281 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
282 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
283 /* 42: PM, 44: PC RA, 46: SC vec'd */
284 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
285 /* 48: SIMD, 50: QP BFP, 52: String */
286 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
287 /* 54: DecFP, 56: DecI, 58: SHA */
288 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
289 /* 60: NM atomic, 62: RNG */
290 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
291 };
292 uint8_t *pa_features = NULL;
293 size_t pa_size;
294
295 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) {
296 pa_features = pa_features_206;
297 pa_size = sizeof(pa_features_206);
298 }
299 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) {
300 pa_features = pa_features_207;
301 pa_size = sizeof(pa_features_207);
302 }
303 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) {
304 pa_features = pa_features_300;
305 pa_size = sizeof(pa_features_300);
306 }
307 if (!pa_features) {
308 return;
309 }
310
311 if (env->ci_large_pages) {
312 /*
313 * Note: we keep CI large pages off by default because a 64K capable
314 * guest provisioned with large pages might otherwise try to map a qemu
315 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
316 * even if that qemu runs on a 4k host.
317 * We dd this bit back here if we are confident this is not an issue
318 */
319 pa_features[3] |= 0x20;
320 }
321 if (kvmppc_has_cap_htm() && pa_size > 24) {
322 pa_features[24] |= 0x80; /* Transactional memory support */
323 }
324 if (legacy_guest && pa_size > 40) {
325 /* Workaround for broken kernels that attempt (guest) radix
326 * mode when they can't handle it, if they see the radix bit set
327 * in pa-features. So hide it from them. */
328 pa_features[40 + 2] &= ~0x80; /* Radix MMU */
329 }
330
331 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
332 }
333
334 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
335 {
336 int ret = 0, offset, cpus_offset;
337 CPUState *cs;
338 char cpu_model[32];
339 int smt = kvmppc_smt_threads();
340 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
341
342 CPU_FOREACH(cs) {
343 PowerPCCPU *cpu = POWERPC_CPU(cs);
344 DeviceClass *dc = DEVICE_GET_CLASS(cs);
345 int index = spapr_vcpu_id(cpu);
346 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
347
348 if ((index % smt) != 0) {
349 continue;
350 }
351
352 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
353
354 cpus_offset = fdt_path_offset(fdt, "/cpus");
355 if (cpus_offset < 0) {
356 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
357 if (cpus_offset < 0) {
358 return cpus_offset;
359 }
360 }
361 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
362 if (offset < 0) {
363 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
364 if (offset < 0) {
365 return offset;
366 }
367 }
368
369 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
370 pft_size_prop, sizeof(pft_size_prop));
371 if (ret < 0) {
372 return ret;
373 }
374
375 if (nb_numa_nodes > 1) {
376 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu);
377 if (ret < 0) {
378 return ret;
379 }
380 }
381
382 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
383 if (ret < 0) {
384 return ret;
385 }
386
387 spapr_populate_pa_features(cpu, fdt, offset,
388 spapr->cas_legacy_guest_workaround);
389 }
390 return ret;
391 }
392
393 static hwaddr spapr_node0_size(MachineState *machine)
394 {
395 if (nb_numa_nodes) {
396 int i;
397 for (i = 0; i < nb_numa_nodes; ++i) {
398 if (numa_info[i].node_mem) {
399 return MIN(pow2floor(numa_info[i].node_mem),
400 machine->ram_size);
401 }
402 }
403 }
404 return machine->ram_size;
405 }
406
407 static void add_str(GString *s, const gchar *s1)
408 {
409 g_string_append_len(s, s1, strlen(s1) + 1);
410 }
411
412 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
413 hwaddr size)
414 {
415 uint32_t associativity[] = {
416 cpu_to_be32(0x4), /* length */
417 cpu_to_be32(0x0), cpu_to_be32(0x0),
418 cpu_to_be32(0x0), cpu_to_be32(nodeid)
419 };
420 char mem_name[32];
421 uint64_t mem_reg_property[2];
422 int off;
423
424 mem_reg_property[0] = cpu_to_be64(start);
425 mem_reg_property[1] = cpu_to_be64(size);
426
427 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
428 off = fdt_add_subnode(fdt, 0, mem_name);
429 _FDT(off);
430 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
431 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
432 sizeof(mem_reg_property))));
433 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
434 sizeof(associativity))));
435 return off;
436 }
437
438 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
439 {
440 MachineState *machine = MACHINE(spapr);
441 hwaddr mem_start, node_size;
442 int i, nb_nodes = nb_numa_nodes;
443 NodeInfo *nodes = numa_info;
444 NodeInfo ramnode;
445
446 /* No NUMA nodes, assume there is just one node with whole RAM */
447 if (!nb_numa_nodes) {
448 nb_nodes = 1;
449 ramnode.node_mem = machine->ram_size;
450 nodes = &ramnode;
451 }
452
453 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
454 if (!nodes[i].node_mem) {
455 continue;
456 }
457 if (mem_start >= machine->ram_size) {
458 node_size = 0;
459 } else {
460 node_size = nodes[i].node_mem;
461 if (node_size > machine->ram_size - mem_start) {
462 node_size = machine->ram_size - mem_start;
463 }
464 }
465 if (!mem_start) {
466 /* ppc_spapr_init() checks for rma_size <= node0_size already */
467 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
468 mem_start += spapr->rma_size;
469 node_size -= spapr->rma_size;
470 }
471 for ( ; node_size; ) {
472 hwaddr sizetmp = pow2floor(node_size);
473
474 /* mem_start != 0 here */
475 if (ctzl(mem_start) < ctzl(sizetmp)) {
476 sizetmp = 1ULL << ctzl(mem_start);
477 }
478
479 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
480 node_size -= sizetmp;
481 mem_start += sizetmp;
482 }
483 }
484
485 return 0;
486 }
487
488 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
489 sPAPRMachineState *spapr)
490 {
491 PowerPCCPU *cpu = POWERPC_CPU(cs);
492 CPUPPCState *env = &cpu->env;
493 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
494 int index = spapr_vcpu_id(cpu);
495 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
496 0xffffffff, 0xffffffff};
497 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
498 : SPAPR_TIMEBASE_FREQ;
499 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
500 uint32_t page_sizes_prop[64];
501 size_t page_sizes_prop_size;
502 uint32_t vcpus_per_socket = smp_threads * smp_cores;
503 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
504 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
505 sPAPRDRConnector *drc;
506 int drc_index;
507 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
508 int i;
509
510 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
511 if (drc) {
512 drc_index = spapr_drc_index(drc);
513 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
514 }
515
516 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
517 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
518
519 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
520 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
521 env->dcache_line_size)));
522 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
523 env->dcache_line_size)));
524 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
525 env->icache_line_size)));
526 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
527 env->icache_line_size)));
528
529 if (pcc->l1_dcache_size) {
530 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
531 pcc->l1_dcache_size)));
532 } else {
533 warn_report("Unknown L1 dcache size for cpu");
534 }
535 if (pcc->l1_icache_size) {
536 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
537 pcc->l1_icache_size)));
538 } else {
539 warn_report("Unknown L1 icache size for cpu");
540 }
541
542 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
543 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
544 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
545 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
546 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
547 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
548
549 if (env->spr_cb[SPR_PURR].oea_read) {
550 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
551 }
552
553 if (env->mmu_model & POWERPC_MMU_1TSEG) {
554 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
555 segs, sizeof(segs))));
556 }
557
558 /* Advertise VMX/VSX (vector extensions) if available
559 * 0 / no property == no vector extensions
560 * 1 == VMX / Altivec available
561 * 2 == VSX available */
562 if (env->insns_flags & PPC_ALTIVEC) {
563 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
564
565 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
566 }
567
568 /* Advertise DFP (Decimal Floating Point) if available
569 * 0 / no property == no DFP
570 * 1 == DFP available */
571 if (env->insns_flags2 & PPC2_DFP) {
572 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
573 }
574
575 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
576 sizeof(page_sizes_prop));
577 if (page_sizes_prop_size) {
578 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
579 page_sizes_prop, page_sizes_prop_size)));
580 }
581
582 spapr_populate_pa_features(cpu, fdt, offset, false);
583
584 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
585 cs->cpu_index / vcpus_per_socket)));
586
587 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
588 pft_size_prop, sizeof(pft_size_prop))));
589
590 if (nb_numa_nodes > 1) {
591 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu));
592 }
593
594 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
595
596 if (pcc->radix_page_info) {
597 for (i = 0; i < pcc->radix_page_info->count; i++) {
598 radix_AP_encodings[i] =
599 cpu_to_be32(pcc->radix_page_info->entries[i]);
600 }
601 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
602 radix_AP_encodings,
603 pcc->radix_page_info->count *
604 sizeof(radix_AP_encodings[0]))));
605 }
606 }
607
608 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
609 {
610 CPUState *cs;
611 int cpus_offset;
612 char *nodename;
613 int smt = kvmppc_smt_threads();
614
615 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
616 _FDT(cpus_offset);
617 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
618 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
619
620 /*
621 * We walk the CPUs in reverse order to ensure that CPU DT nodes
622 * created by fdt_add_subnode() end up in the right order in FDT
623 * for the guest kernel the enumerate the CPUs correctly.
624 */
625 CPU_FOREACH_REVERSE(cs) {
626 PowerPCCPU *cpu = POWERPC_CPU(cs);
627 int index = spapr_vcpu_id(cpu);
628 DeviceClass *dc = DEVICE_GET_CLASS(cs);
629 int offset;
630
631 if ((index % smt) != 0) {
632 continue;
633 }
634
635 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
636 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
637 g_free(nodename);
638 _FDT(offset);
639 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
640 }
641
642 }
643
644 /*
645 * Adds ibm,dynamic-reconfiguration-memory node.
646 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
647 * of this device tree node.
648 */
649 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
650 {
651 MachineState *machine = MACHINE(spapr);
652 int ret, i, offset;
653 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
654 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
655 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
656 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
657 memory_region_size(&spapr->hotplug_memory.mr)) /
658 lmb_size;
659 uint32_t *int_buf, *cur_index, buf_len;
660 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
661
662 /*
663 * Don't create the node if there is no hotpluggable memory
664 */
665 if (machine->ram_size == machine->maxram_size) {
666 return 0;
667 }
668
669 /*
670 * Allocate enough buffer size to fit in ibm,dynamic-memory
671 * or ibm,associativity-lookup-arrays
672 */
673 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
674 * sizeof(uint32_t);
675 cur_index = int_buf = g_malloc0(buf_len);
676
677 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
678
679 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
680 sizeof(prop_lmb_size));
681 if (ret < 0) {
682 goto out;
683 }
684
685 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
686 if (ret < 0) {
687 goto out;
688 }
689
690 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
691 if (ret < 0) {
692 goto out;
693 }
694
695 /* ibm,dynamic-memory */
696 int_buf[0] = cpu_to_be32(nr_lmbs);
697 cur_index++;
698 for (i = 0; i < nr_lmbs; i++) {
699 uint64_t addr = i * lmb_size;
700 uint32_t *dynamic_memory = cur_index;
701
702 if (i >= hotplug_lmb_start) {
703 sPAPRDRConnector *drc;
704
705 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
706 g_assert(drc);
707
708 dynamic_memory[0] = cpu_to_be32(addr >> 32);
709 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
710 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
711 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
712 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
713 if (memory_region_present(get_system_memory(), addr)) {
714 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
715 } else {
716 dynamic_memory[5] = cpu_to_be32(0);
717 }
718 } else {
719 /*
720 * LMB information for RMA, boot time RAM and gap b/n RAM and
721 * hotplug memory region -- all these are marked as reserved
722 * and as having no valid DRC.
723 */
724 dynamic_memory[0] = cpu_to_be32(addr >> 32);
725 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
726 dynamic_memory[2] = cpu_to_be32(0);
727 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
728 dynamic_memory[4] = cpu_to_be32(-1);
729 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
730 SPAPR_LMB_FLAGS_DRC_INVALID);
731 }
732
733 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
734 }
735 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
736 if (ret < 0) {
737 goto out;
738 }
739
740 /* ibm,associativity-lookup-arrays */
741 cur_index = int_buf;
742 int_buf[0] = cpu_to_be32(nr_nodes);
743 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
744 cur_index += 2;
745 for (i = 0; i < nr_nodes; i++) {
746 uint32_t associativity[] = {
747 cpu_to_be32(0x0),
748 cpu_to_be32(0x0),
749 cpu_to_be32(0x0),
750 cpu_to_be32(i)
751 };
752 memcpy(cur_index, associativity, sizeof(associativity));
753 cur_index += 4;
754 }
755 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
756 (cur_index - int_buf) * sizeof(uint32_t));
757 out:
758 g_free(int_buf);
759 return ret;
760 }
761
762 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt,
763 sPAPROptionVector *ov5_updates)
764 {
765 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
766 int ret = 0, offset;
767
768 /* Generate ibm,dynamic-reconfiguration-memory node if required */
769 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
770 g_assert(smc->dr_lmb_enabled);
771 ret = spapr_populate_drconf_memory(spapr, fdt);
772 if (ret) {
773 goto out;
774 }
775 }
776
777 offset = fdt_path_offset(fdt, "/chosen");
778 if (offset < 0) {
779 offset = fdt_add_subnode(fdt, 0, "chosen");
780 if (offset < 0) {
781 return offset;
782 }
783 }
784 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
785 "ibm,architecture-vec-5");
786
787 out:
788 return ret;
789 }
790
791 static bool spapr_hotplugged_dev_before_cas(void)
792 {
793 Object *drc_container, *obj;
794 ObjectProperty *prop;
795 ObjectPropertyIterator iter;
796
797 drc_container = container_get(object_get_root(), "/dr-connector");
798 object_property_iter_init(&iter, drc_container);
799 while ((prop = object_property_iter_next(&iter))) {
800 if (!strstart(prop->type, "link<", NULL)) {
801 continue;
802 }
803 obj = object_property_get_link(drc_container, prop->name, NULL);
804 if (spapr_drc_needed(obj)) {
805 return true;
806 }
807 }
808 return false;
809 }
810
811 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
812 target_ulong addr, target_ulong size,
813 sPAPROptionVector *ov5_updates)
814 {
815 void *fdt, *fdt_skel;
816 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
817
818 if (spapr_hotplugged_dev_before_cas()) {
819 return 1;
820 }
821
822 if (size < sizeof(hdr) || size > FW_MAX_SIZE) {
823 error_report("SLOF provided an unexpected CAS buffer size "
824 TARGET_FMT_lu " (min: %zu, max: %u)",
825 size, sizeof(hdr), FW_MAX_SIZE);
826 exit(EXIT_FAILURE);
827 }
828
829 size -= sizeof(hdr);
830
831 /* Create skeleton */
832 fdt_skel = g_malloc0(size);
833 _FDT((fdt_create(fdt_skel, size)));
834 _FDT((fdt_begin_node(fdt_skel, "")));
835 _FDT((fdt_end_node(fdt_skel)));
836 _FDT((fdt_finish(fdt_skel)));
837 fdt = g_malloc0(size);
838 _FDT((fdt_open_into(fdt_skel, fdt, size)));
839 g_free(fdt_skel);
840
841 /* Fixup cpu nodes */
842 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
843
844 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
845 return -1;
846 }
847
848 /* Pack resulting tree */
849 _FDT((fdt_pack(fdt)));
850
851 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
852 trace_spapr_cas_failed(size);
853 return -1;
854 }
855
856 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
857 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
858 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
859 g_free(fdt);
860
861 return 0;
862 }
863
864 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
865 {
866 int rtas;
867 GString *hypertas = g_string_sized_new(256);
868 GString *qemu_hypertas = g_string_sized_new(256);
869 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
870 uint64_t max_hotplug_addr = spapr->hotplug_memory.base +
871 memory_region_size(&spapr->hotplug_memory.mr);
872 uint32_t lrdr_capacity[] = {
873 cpu_to_be32(max_hotplug_addr >> 32),
874 cpu_to_be32(max_hotplug_addr & 0xffffffff),
875 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
876 cpu_to_be32(max_cpus / smp_threads),
877 };
878
879 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
880
881 /* hypertas */
882 add_str(hypertas, "hcall-pft");
883 add_str(hypertas, "hcall-term");
884 add_str(hypertas, "hcall-dabr");
885 add_str(hypertas, "hcall-interrupt");
886 add_str(hypertas, "hcall-tce");
887 add_str(hypertas, "hcall-vio");
888 add_str(hypertas, "hcall-splpar");
889 add_str(hypertas, "hcall-bulk");
890 add_str(hypertas, "hcall-set-mode");
891 add_str(hypertas, "hcall-sprg0");
892 add_str(hypertas, "hcall-copy");
893 add_str(hypertas, "hcall-debug");
894 add_str(qemu_hypertas, "hcall-memop1");
895
896 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
897 add_str(hypertas, "hcall-multi-tce");
898 }
899
900 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
901 add_str(hypertas, "hcall-hpt-resize");
902 }
903
904 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
905 hypertas->str, hypertas->len));
906 g_string_free(hypertas, TRUE);
907 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
908 qemu_hypertas->str, qemu_hypertas->len));
909 g_string_free(qemu_hypertas, TRUE);
910
911 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
912 refpoints, sizeof(refpoints)));
913
914 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
915 RTAS_ERROR_LOG_MAX));
916 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
917 RTAS_EVENT_SCAN_RATE));
918
919 if (msi_nonbroken) {
920 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
921 }
922
923 /*
924 * According to PAPR, rtas ibm,os-term does not guarantee a return
925 * back to the guest cpu.
926 *
927 * While an additional ibm,extended-os-term property indicates
928 * that rtas call return will always occur. Set this property.
929 */
930 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
931
932 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
933 lrdr_capacity, sizeof(lrdr_capacity)));
934
935 spapr_dt_rtas_tokens(fdt, rtas);
936 }
937
938 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features
939 * that the guest may request and thus the valid values for bytes 24..26 of
940 * option vector 5: */
941 static void spapr_dt_ov5_platform_support(void *fdt, int chosen)
942 {
943 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
944
945 char val[2 * 4] = {
946 23, 0x00, /* Xive mode, filled in below. */
947 24, 0x00, /* Hash/Radix, filled in below. */
948 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
949 26, 0x40, /* Radix options: GTSE == yes. */
950 };
951
952 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
953 first_ppc_cpu->compat_pvr)) {
954 /* If we're in a pre POWER9 compat mode then the guest should do hash */
955 val[3] = 0x00; /* Hash */
956 } else if (kvm_enabled()) {
957 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
958 val[3] = 0x80; /* OV5_MMU_BOTH */
959 } else if (kvmppc_has_cap_mmu_radix()) {
960 val[3] = 0x40; /* OV5_MMU_RADIX_300 */
961 } else {
962 val[3] = 0x00; /* Hash */
963 }
964 } else {
965 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
966 val[3] = 0xC0;
967 }
968 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
969 val, sizeof(val)));
970 }
971
972 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
973 {
974 MachineState *machine = MACHINE(spapr);
975 int chosen;
976 const char *boot_device = machine->boot_order;
977 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
978 size_t cb = 0;
979 char *bootlist = get_boot_devices_list(&cb, true);
980
981 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
982
983 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
984 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
985 spapr->initrd_base));
986 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
987 spapr->initrd_base + spapr->initrd_size));
988
989 if (spapr->kernel_size) {
990 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
991 cpu_to_be64(spapr->kernel_size) };
992
993 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
994 &kprop, sizeof(kprop)));
995 if (spapr->kernel_le) {
996 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
997 }
998 }
999 if (boot_menu) {
1000 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
1001 }
1002 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
1003 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
1004 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1005
1006 if (cb && bootlist) {
1007 int i;
1008
1009 for (i = 0; i < cb; i++) {
1010 if (bootlist[i] == '\n') {
1011 bootlist[i] = ' ';
1012 }
1013 }
1014 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1015 }
1016
1017 if (boot_device && strlen(boot_device)) {
1018 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1019 }
1020
1021 if (!spapr->has_graphics && stdout_path) {
1022 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
1023 }
1024
1025 spapr_dt_ov5_platform_support(fdt, chosen);
1026
1027 g_free(stdout_path);
1028 g_free(bootlist);
1029 }
1030
1031 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt)
1032 {
1033 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1034 * KVM to work under pHyp with some guest co-operation */
1035 int hypervisor;
1036 uint8_t hypercall[16];
1037
1038 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1039 /* indicate KVM hypercall interface */
1040 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1041 if (kvmppc_has_cap_fixup_hcalls()) {
1042 /*
1043 * Older KVM versions with older guest kernels were broken
1044 * with the magic page, don't allow the guest to map it.
1045 */
1046 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1047 sizeof(hypercall))) {
1048 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1049 hypercall, sizeof(hypercall)));
1050 }
1051 }
1052 }
1053
1054 static void *spapr_build_fdt(sPAPRMachineState *spapr,
1055 hwaddr rtas_addr,
1056 hwaddr rtas_size)
1057 {
1058 MachineState *machine = MACHINE(spapr);
1059 MachineClass *mc = MACHINE_GET_CLASS(machine);
1060 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1061 int ret;
1062 void *fdt;
1063 sPAPRPHBState *phb;
1064 char *buf;
1065
1066 fdt = g_malloc0(FDT_MAX_SIZE);
1067 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
1068
1069 /* Root node */
1070 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1071 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1072 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1073
1074 /*
1075 * Add info to guest to indentify which host is it being run on
1076 * and what is the uuid of the guest
1077 */
1078 if (kvmppc_get_host_model(&buf)) {
1079 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1080 g_free(buf);
1081 }
1082 if (kvmppc_get_host_serial(&buf)) {
1083 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1084 g_free(buf);
1085 }
1086
1087 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1088
1089 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1090 if (qemu_uuid_set) {
1091 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1092 }
1093 g_free(buf);
1094
1095 if (qemu_get_vm_name()) {
1096 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1097 qemu_get_vm_name()));
1098 }
1099
1100 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1101 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1102
1103 /* /interrupt controller */
1104 spapr_dt_xics(xics_max_server_number(), fdt, PHANDLE_XICP);
1105
1106 ret = spapr_populate_memory(spapr, fdt);
1107 if (ret < 0) {
1108 error_report("couldn't setup memory nodes in fdt");
1109 exit(1);
1110 }
1111
1112 /* /vdevice */
1113 spapr_dt_vdevice(spapr->vio_bus, fdt);
1114
1115 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1116 ret = spapr_rng_populate_dt(fdt);
1117 if (ret < 0) {
1118 error_report("could not set up rng device in the fdt");
1119 exit(1);
1120 }
1121 }
1122
1123 QLIST_FOREACH(phb, &spapr->phbs, list) {
1124 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
1125 if (ret < 0) {
1126 error_report("couldn't setup PCI devices in fdt");
1127 exit(1);
1128 }
1129 }
1130
1131 /* cpus */
1132 spapr_populate_cpus_dt_node(fdt, spapr);
1133
1134 if (smc->dr_lmb_enabled) {
1135 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1136 }
1137
1138 if (mc->has_hotpluggable_cpus) {
1139 int offset = fdt_path_offset(fdt, "/cpus");
1140 ret = spapr_drc_populate_dt(fdt, offset, NULL,
1141 SPAPR_DR_CONNECTOR_TYPE_CPU);
1142 if (ret < 0) {
1143 error_report("Couldn't set up CPU DR device tree properties");
1144 exit(1);
1145 }
1146 }
1147
1148 /* /event-sources */
1149 spapr_dt_events(spapr, fdt);
1150
1151 /* /rtas */
1152 spapr_dt_rtas(spapr, fdt);
1153
1154 /* /chosen */
1155 spapr_dt_chosen(spapr, fdt);
1156
1157 /* /hypervisor */
1158 if (kvm_enabled()) {
1159 spapr_dt_hypervisor(spapr, fdt);
1160 }
1161
1162 /* Build memory reserve map */
1163 if (spapr->kernel_size) {
1164 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1165 }
1166 if (spapr->initrd_size) {
1167 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
1168 }
1169
1170 /* ibm,client-architecture-support updates */
1171 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1172 if (ret < 0) {
1173 error_report("couldn't setup CAS properties fdt");
1174 exit(1);
1175 }
1176
1177 return fdt;
1178 }
1179
1180 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1181 {
1182 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1183 }
1184
1185 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1186 PowerPCCPU *cpu)
1187 {
1188 CPUPPCState *env = &cpu->env;
1189
1190 /* The TCG path should also be holding the BQL at this point */
1191 g_assert(qemu_mutex_iothread_locked());
1192
1193 if (msr_pr) {
1194 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1195 env->gpr[3] = H_PRIVILEGE;
1196 } else {
1197 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1198 }
1199 }
1200
1201 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp)
1202 {
1203 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1204
1205 return spapr->patb_entry;
1206 }
1207
1208 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1209 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1210 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1211 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1212 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1213
1214 /*
1215 * Get the fd to access the kernel htab, re-opening it if necessary
1216 */
1217 static int get_htab_fd(sPAPRMachineState *spapr)
1218 {
1219 Error *local_err = NULL;
1220
1221 if (spapr->htab_fd >= 0) {
1222 return spapr->htab_fd;
1223 }
1224
1225 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err);
1226 if (spapr->htab_fd < 0) {
1227 error_report_err(local_err);
1228 }
1229
1230 return spapr->htab_fd;
1231 }
1232
1233 void close_htab_fd(sPAPRMachineState *spapr)
1234 {
1235 if (spapr->htab_fd >= 0) {
1236 close(spapr->htab_fd);
1237 }
1238 spapr->htab_fd = -1;
1239 }
1240
1241 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1242 {
1243 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1244
1245 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1246 }
1247
1248 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
1249 {
1250 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1251
1252 assert(kvm_enabled());
1253
1254 if (!spapr->htab) {
1255 return 0;
1256 }
1257
1258 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18);
1259 }
1260
1261 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1262 hwaddr ptex, int n)
1263 {
1264 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1265 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1266
1267 if (!spapr->htab) {
1268 /*
1269 * HTAB is controlled by KVM. Fetch into temporary buffer
1270 */
1271 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1272 kvmppc_read_hptes(hptes, ptex, n);
1273 return hptes;
1274 }
1275
1276 /*
1277 * HTAB is controlled by QEMU. Just point to the internally
1278 * accessible PTEG.
1279 */
1280 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1281 }
1282
1283 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1284 const ppc_hash_pte64_t *hptes,
1285 hwaddr ptex, int n)
1286 {
1287 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1288
1289 if (!spapr->htab) {
1290 g_free((void *)hptes);
1291 }
1292
1293 /* Nothing to do for qemu managed HPT */
1294 }
1295
1296 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1297 uint64_t pte0, uint64_t pte1)
1298 {
1299 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1300 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1301
1302 if (!spapr->htab) {
1303 kvmppc_write_hpte(ptex, pte0, pte1);
1304 } else {
1305 stq_p(spapr->htab + offset, pte0);
1306 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1307 }
1308 }
1309
1310 int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1311 {
1312 int shift;
1313
1314 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1315 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1316 * that's much more than is needed for Linux guests */
1317 shift = ctz64(pow2ceil(ramsize)) - 7;
1318 shift = MAX(shift, 18); /* Minimum architected size */
1319 shift = MIN(shift, 46); /* Maximum architected size */
1320 return shift;
1321 }
1322
1323 void spapr_free_hpt(sPAPRMachineState *spapr)
1324 {
1325 g_free(spapr->htab);
1326 spapr->htab = NULL;
1327 spapr->htab_shift = 0;
1328 close_htab_fd(spapr);
1329 }
1330
1331 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1332 Error **errp)
1333 {
1334 long rc;
1335
1336 /* Clean up any HPT info from a previous boot */
1337 spapr_free_hpt(spapr);
1338
1339 rc = kvmppc_reset_htab(shift);
1340 if (rc < 0) {
1341 /* kernel-side HPT needed, but couldn't allocate one */
1342 error_setg_errno(errp, errno,
1343 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1344 shift);
1345 /* This is almost certainly fatal, but if the caller really
1346 * wants to carry on with shift == 0, it's welcome to try */
1347 } else if (rc > 0) {
1348 /* kernel-side HPT allocated */
1349 if (rc != shift) {
1350 error_setg(errp,
1351 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1352 shift, rc);
1353 }
1354
1355 spapr->htab_shift = shift;
1356 spapr->htab = NULL;
1357 } else {
1358 /* kernel-side HPT not needed, allocate in userspace instead */
1359 size_t size = 1ULL << shift;
1360 int i;
1361
1362 spapr->htab = qemu_memalign(size, size);
1363 if (!spapr->htab) {
1364 error_setg_errno(errp, errno,
1365 "Could not allocate HPT of order %d", shift);
1366 return;
1367 }
1368
1369 memset(spapr->htab, 0, size);
1370 spapr->htab_shift = shift;
1371
1372 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1373 DIRTY_HPTE(HPTE(spapr->htab, i));
1374 }
1375 }
1376 /* We're setting up a hash table, so that means we're not radix */
1377 spapr->patb_entry = 0;
1378 }
1379
1380 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr)
1381 {
1382 int hpt_shift;
1383
1384 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED)
1385 || (spapr->cas_reboot
1386 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) {
1387 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1388 } else {
1389 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->ram_size);
1390 }
1391 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1392
1393 if (spapr->vrma_adjust) {
1394 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)),
1395 spapr->htab_shift);
1396 }
1397 }
1398
1399 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1400 {
1401 bool matched = false;
1402
1403 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1404 matched = true;
1405 }
1406
1407 if (!matched) {
1408 error_report("Device %s is not supported by this machine yet.",
1409 qdev_fw_name(DEVICE(sbdev)));
1410 exit(1);
1411 }
1412 }
1413
1414 static int spapr_reset_drcs(Object *child, void *opaque)
1415 {
1416 sPAPRDRConnector *drc =
1417 (sPAPRDRConnector *) object_dynamic_cast(child,
1418 TYPE_SPAPR_DR_CONNECTOR);
1419
1420 if (drc) {
1421 spapr_drc_reset(drc);
1422 }
1423
1424 return 0;
1425 }
1426
1427 static void ppc_spapr_reset(void)
1428 {
1429 MachineState *machine = MACHINE(qdev_get_machine());
1430 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1431 PowerPCCPU *first_ppc_cpu;
1432 uint32_t rtas_limit;
1433 hwaddr rtas_addr, fdt_addr;
1434 void *fdt;
1435 int rc;
1436
1437 /* Check for unknown sysbus devices */
1438 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1439
1440 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()) {
1441 /* If using KVM with radix mode available, VCPUs can be started
1442 * without a HPT because KVM will start them in radix mode.
1443 * Set the GR bit in PATB so that we know there is no HPT. */
1444 spapr->patb_entry = PATBE1_GR;
1445 } else {
1446 spapr_setup_hpt_and_vrma(spapr);
1447 }
1448
1449 qemu_devices_reset();
1450
1451 /* DRC reset may cause a device to be unplugged. This will cause troubles
1452 * if this device is used by another device (eg, a running vhost backend
1453 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1454 * situations, we reset DRCs after all devices have been reset.
1455 */
1456 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL);
1457
1458 spapr_clear_pending_events(spapr);
1459
1460 /*
1461 * We place the device tree and RTAS just below either the top of the RMA,
1462 * or just below 2GB, whichever is lowere, so that it can be
1463 * processed with 32-bit real mode code if necessary
1464 */
1465 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1466 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1467 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1468
1469 /* if this reset wasn't generated by CAS, we should reset our
1470 * negotiated options and start from scratch */
1471 if (!spapr->cas_reboot) {
1472 spapr_ovec_cleanup(spapr->ov5_cas);
1473 spapr->ov5_cas = spapr_ovec_new();
1474
1475 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);
1476 }
1477
1478 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size);
1479
1480 spapr_load_rtas(spapr, fdt, rtas_addr);
1481
1482 rc = fdt_pack(fdt);
1483
1484 /* Should only fail if we've built a corrupted tree */
1485 assert(rc == 0);
1486
1487 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1488 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1489 fdt_totalsize(fdt), FDT_MAX_SIZE);
1490 exit(1);
1491 }
1492
1493 /* Load the fdt */
1494 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1495 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1496 g_free(fdt);
1497
1498 /* Set up the entry state */
1499 first_ppc_cpu = POWERPC_CPU(first_cpu);
1500 first_ppc_cpu->env.gpr[3] = fdt_addr;
1501 first_ppc_cpu->env.gpr[5] = 0;
1502 first_cpu->halted = 0;
1503 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1504
1505 spapr->cas_reboot = false;
1506 }
1507
1508 static void spapr_create_nvram(sPAPRMachineState *spapr)
1509 {
1510 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1511 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1512
1513 if (dinfo) {
1514 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1515 &error_fatal);
1516 }
1517
1518 qdev_init_nofail(dev);
1519
1520 spapr->nvram = (struct sPAPRNVRAM *)dev;
1521 }
1522
1523 static void spapr_rtc_create(sPAPRMachineState *spapr)
1524 {
1525 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC);
1526 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc),
1527 &error_fatal);
1528 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
1529 &error_fatal);
1530 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1531 "date", &error_fatal);
1532 }
1533
1534 /* Returns whether we want to use VGA or not */
1535 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1536 {
1537 switch (vga_interface_type) {
1538 case VGA_NONE:
1539 return false;
1540 case VGA_DEVICE:
1541 return true;
1542 case VGA_STD:
1543 case VGA_VIRTIO:
1544 return pci_vga_init(pci_bus) != NULL;
1545 default:
1546 error_setg(errp,
1547 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1548 return false;
1549 }
1550 }
1551
1552 static int spapr_post_load(void *opaque, int version_id)
1553 {
1554 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1555 int err = 0;
1556
1557 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
1558 CPUState *cs;
1559 CPU_FOREACH(cs) {
1560 PowerPCCPU *cpu = POWERPC_CPU(cs);
1561 icp_resend(ICP(cpu->intc));
1562 }
1563 }
1564
1565 /* In earlier versions, there was no separate qdev for the PAPR
1566 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1567 * So when migrating from those versions, poke the incoming offset
1568 * value into the RTC device */
1569 if (version_id < 3) {
1570 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1571 }
1572
1573 if (kvm_enabled() && spapr->patb_entry) {
1574 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1575 bool radix = !!(spapr->patb_entry & PATBE1_GR);
1576 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1577
1578 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1579 if (err) {
1580 error_report("Process table config unsupported by the host");
1581 return -EINVAL;
1582 }
1583 }
1584
1585 return err;
1586 }
1587
1588 static bool version_before_3(void *opaque, int version_id)
1589 {
1590 return version_id < 3;
1591 }
1592
1593 static bool spapr_pending_events_needed(void *opaque)
1594 {
1595 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1596 return !QTAILQ_EMPTY(&spapr->pending_events);
1597 }
1598
1599 static const VMStateDescription vmstate_spapr_event_entry = {
1600 .name = "spapr_event_log_entry",
1601 .version_id = 1,
1602 .minimum_version_id = 1,
1603 .fields = (VMStateField[]) {
1604 VMSTATE_UINT32(summary, sPAPREventLogEntry),
1605 VMSTATE_UINT32(extended_length, sPAPREventLogEntry),
1606 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0,
1607 NULL, extended_length),
1608 VMSTATE_END_OF_LIST()
1609 },
1610 };
1611
1612 static const VMStateDescription vmstate_spapr_pending_events = {
1613 .name = "spapr_pending_events",
1614 .version_id = 1,
1615 .minimum_version_id = 1,
1616 .needed = spapr_pending_events_needed,
1617 .fields = (VMStateField[]) {
1618 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1,
1619 vmstate_spapr_event_entry, sPAPREventLogEntry, next),
1620 VMSTATE_END_OF_LIST()
1621 },
1622 };
1623
1624 static bool spapr_ov5_cas_needed(void *opaque)
1625 {
1626 sPAPRMachineState *spapr = opaque;
1627 sPAPROptionVector *ov5_mask = spapr_ovec_new();
1628 sPAPROptionVector *ov5_legacy = spapr_ovec_new();
1629 sPAPROptionVector *ov5_removed = spapr_ovec_new();
1630 bool cas_needed;
1631
1632 /* Prior to the introduction of sPAPROptionVector, we had two option
1633 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1634 * Both of these options encode machine topology into the device-tree
1635 * in such a way that the now-booted OS should still be able to interact
1636 * appropriately with QEMU regardless of what options were actually
1637 * negotiatied on the source side.
1638 *
1639 * As such, we can avoid migrating the CAS-negotiated options if these
1640 * are the only options available on the current machine/platform.
1641 * Since these are the only options available for pseries-2.7 and
1642 * earlier, this allows us to maintain old->new/new->old migration
1643 * compatibility.
1644 *
1645 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1646 * via default pseries-2.8 machines and explicit command-line parameters.
1647 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1648 * of the actual CAS-negotiated values to continue working properly. For
1649 * example, availability of memory unplug depends on knowing whether
1650 * OV5_HP_EVT was negotiated via CAS.
1651 *
1652 * Thus, for any cases where the set of available CAS-negotiatable
1653 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1654 * include the CAS-negotiated options in the migration stream.
1655 */
1656 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1657 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1658
1659 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1660 * the mask itself since in the future it's possible "legacy" bits may be
1661 * removed via machine options, which could generate a false positive
1662 * that breaks migration.
1663 */
1664 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
1665 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
1666
1667 spapr_ovec_cleanup(ov5_mask);
1668 spapr_ovec_cleanup(ov5_legacy);
1669 spapr_ovec_cleanup(ov5_removed);
1670
1671 return cas_needed;
1672 }
1673
1674 static const VMStateDescription vmstate_spapr_ov5_cas = {
1675 .name = "spapr_option_vector_ov5_cas",
1676 .version_id = 1,
1677 .minimum_version_id = 1,
1678 .needed = spapr_ov5_cas_needed,
1679 .fields = (VMStateField[]) {
1680 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1,
1681 vmstate_spapr_ovec, sPAPROptionVector),
1682 VMSTATE_END_OF_LIST()
1683 },
1684 };
1685
1686 static bool spapr_patb_entry_needed(void *opaque)
1687 {
1688 sPAPRMachineState *spapr = opaque;
1689
1690 return !!spapr->patb_entry;
1691 }
1692
1693 static const VMStateDescription vmstate_spapr_patb_entry = {
1694 .name = "spapr_patb_entry",
1695 .version_id = 1,
1696 .minimum_version_id = 1,
1697 .needed = spapr_patb_entry_needed,
1698 .fields = (VMStateField[]) {
1699 VMSTATE_UINT64(patb_entry, sPAPRMachineState),
1700 VMSTATE_END_OF_LIST()
1701 },
1702 };
1703
1704 static const VMStateDescription vmstate_spapr = {
1705 .name = "spapr",
1706 .version_id = 3,
1707 .minimum_version_id = 1,
1708 .post_load = spapr_post_load,
1709 .fields = (VMStateField[]) {
1710 /* used to be @next_irq */
1711 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1712
1713 /* RTC offset */
1714 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1715
1716 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1717 VMSTATE_END_OF_LIST()
1718 },
1719 .subsections = (const VMStateDescription*[]) {
1720 &vmstate_spapr_ov5_cas,
1721 &vmstate_spapr_patb_entry,
1722 &vmstate_spapr_pending_events,
1723 NULL
1724 }
1725 };
1726
1727 static int htab_save_setup(QEMUFile *f, void *opaque)
1728 {
1729 sPAPRMachineState *spapr = opaque;
1730
1731 /* "Iteration" header */
1732 if (!spapr->htab_shift) {
1733 qemu_put_be32(f, -1);
1734 } else {
1735 qemu_put_be32(f, spapr->htab_shift);
1736 }
1737
1738 if (spapr->htab) {
1739 spapr->htab_save_index = 0;
1740 spapr->htab_first_pass = true;
1741 } else {
1742 if (spapr->htab_shift) {
1743 assert(kvm_enabled());
1744 }
1745 }
1746
1747
1748 return 0;
1749 }
1750
1751 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr,
1752 int chunkstart, int n_valid, int n_invalid)
1753 {
1754 qemu_put_be32(f, chunkstart);
1755 qemu_put_be16(f, n_valid);
1756 qemu_put_be16(f, n_invalid);
1757 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1758 HASH_PTE_SIZE_64 * n_valid);
1759 }
1760
1761 static void htab_save_end_marker(QEMUFile *f)
1762 {
1763 qemu_put_be32(f, 0);
1764 qemu_put_be16(f, 0);
1765 qemu_put_be16(f, 0);
1766 }
1767
1768 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1769 int64_t max_ns)
1770 {
1771 bool has_timeout = max_ns != -1;
1772 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1773 int index = spapr->htab_save_index;
1774 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1775
1776 assert(spapr->htab_first_pass);
1777
1778 do {
1779 int chunkstart;
1780
1781 /* Consume invalid HPTEs */
1782 while ((index < htabslots)
1783 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1784 CLEAN_HPTE(HPTE(spapr->htab, index));
1785 index++;
1786 }
1787
1788 /* Consume valid HPTEs */
1789 chunkstart = index;
1790 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1791 && HPTE_VALID(HPTE(spapr->htab, index))) {
1792 CLEAN_HPTE(HPTE(spapr->htab, index));
1793 index++;
1794 }
1795
1796 if (index > chunkstart) {
1797 int n_valid = index - chunkstart;
1798
1799 htab_save_chunk(f, spapr, chunkstart, n_valid, 0);
1800
1801 if (has_timeout &&
1802 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1803 break;
1804 }
1805 }
1806 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1807
1808 if (index >= htabslots) {
1809 assert(index == htabslots);
1810 index = 0;
1811 spapr->htab_first_pass = false;
1812 }
1813 spapr->htab_save_index = index;
1814 }
1815
1816 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1817 int64_t max_ns)
1818 {
1819 bool final = max_ns < 0;
1820 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1821 int examined = 0, sent = 0;
1822 int index = spapr->htab_save_index;
1823 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1824
1825 assert(!spapr->htab_first_pass);
1826
1827 do {
1828 int chunkstart, invalidstart;
1829
1830 /* Consume non-dirty HPTEs */
1831 while ((index < htabslots)
1832 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1833 index++;
1834 examined++;
1835 }
1836
1837 chunkstart = index;
1838 /* Consume valid dirty HPTEs */
1839 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1840 && HPTE_DIRTY(HPTE(spapr->htab, index))
1841 && HPTE_VALID(HPTE(spapr->htab, index))) {
1842 CLEAN_HPTE(HPTE(spapr->htab, index));
1843 index++;
1844 examined++;
1845 }
1846
1847 invalidstart = index;
1848 /* Consume invalid dirty HPTEs */
1849 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1850 && HPTE_DIRTY(HPTE(spapr->htab, index))
1851 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1852 CLEAN_HPTE(HPTE(spapr->htab, index));
1853 index++;
1854 examined++;
1855 }
1856
1857 if (index > chunkstart) {
1858 int n_valid = invalidstart - chunkstart;
1859 int n_invalid = index - invalidstart;
1860
1861 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid);
1862 sent += index - chunkstart;
1863
1864 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1865 break;
1866 }
1867 }
1868
1869 if (examined >= htabslots) {
1870 break;
1871 }
1872
1873 if (index >= htabslots) {
1874 assert(index == htabslots);
1875 index = 0;
1876 }
1877 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1878
1879 if (index >= htabslots) {
1880 assert(index == htabslots);
1881 index = 0;
1882 }
1883
1884 spapr->htab_save_index = index;
1885
1886 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1887 }
1888
1889 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1890 #define MAX_KVM_BUF_SIZE 2048
1891
1892 static int htab_save_iterate(QEMUFile *f, void *opaque)
1893 {
1894 sPAPRMachineState *spapr = opaque;
1895 int fd;
1896 int rc = 0;
1897
1898 /* Iteration header */
1899 if (!spapr->htab_shift) {
1900 qemu_put_be32(f, -1);
1901 return 1;
1902 } else {
1903 qemu_put_be32(f, 0);
1904 }
1905
1906 if (!spapr->htab) {
1907 assert(kvm_enabled());
1908
1909 fd = get_htab_fd(spapr);
1910 if (fd < 0) {
1911 return fd;
1912 }
1913
1914 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1915 if (rc < 0) {
1916 return rc;
1917 }
1918 } else if (spapr->htab_first_pass) {
1919 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1920 } else {
1921 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1922 }
1923
1924 htab_save_end_marker(f);
1925
1926 return rc;
1927 }
1928
1929 static int htab_save_complete(QEMUFile *f, void *opaque)
1930 {
1931 sPAPRMachineState *spapr = opaque;
1932 int fd;
1933
1934 /* Iteration header */
1935 if (!spapr->htab_shift) {
1936 qemu_put_be32(f, -1);
1937 return 0;
1938 } else {
1939 qemu_put_be32(f, 0);
1940 }
1941
1942 if (!spapr->htab) {
1943 int rc;
1944
1945 assert(kvm_enabled());
1946
1947 fd = get_htab_fd(spapr);
1948 if (fd < 0) {
1949 return fd;
1950 }
1951
1952 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
1953 if (rc < 0) {
1954 return rc;
1955 }
1956 } else {
1957 if (spapr->htab_first_pass) {
1958 htab_save_first_pass(f, spapr, -1);
1959 }
1960 htab_save_later_pass(f, spapr, -1);
1961 }
1962
1963 /* End marker */
1964 htab_save_end_marker(f);
1965
1966 return 0;
1967 }
1968
1969 static int htab_load(QEMUFile *f, void *opaque, int version_id)
1970 {
1971 sPAPRMachineState *spapr = opaque;
1972 uint32_t section_hdr;
1973 int fd = -1;
1974 Error *local_err = NULL;
1975
1976 if (version_id < 1 || version_id > 1) {
1977 error_report("htab_load() bad version");
1978 return -EINVAL;
1979 }
1980
1981 section_hdr = qemu_get_be32(f);
1982
1983 if (section_hdr == -1) {
1984 spapr_free_hpt(spapr);
1985 return 0;
1986 }
1987
1988 if (section_hdr) {
1989 /* First section gives the htab size */
1990 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1991 if (local_err) {
1992 error_report_err(local_err);
1993 return -EINVAL;
1994 }
1995 return 0;
1996 }
1997
1998 if (!spapr->htab) {
1999 assert(kvm_enabled());
2000
2001 fd = kvmppc_get_htab_fd(true, 0, &local_err);
2002 if (fd < 0) {
2003 error_report_err(local_err);
2004 return fd;
2005 }
2006 }
2007
2008 while (true) {
2009 uint32_t index;
2010 uint16_t n_valid, n_invalid;
2011
2012 index = qemu_get_be32(f);
2013 n_valid = qemu_get_be16(f);
2014 n_invalid = qemu_get_be16(f);
2015
2016 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
2017 /* End of Stream */
2018 break;
2019 }
2020
2021 if ((index + n_valid + n_invalid) >
2022 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
2023 /* Bad index in stream */
2024 error_report(
2025 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2026 index, n_valid, n_invalid, spapr->htab_shift);
2027 return -EINVAL;
2028 }
2029
2030 if (spapr->htab) {
2031 if (n_valid) {
2032 qemu_get_buffer(f, HPTE(spapr->htab, index),
2033 HASH_PTE_SIZE_64 * n_valid);
2034 }
2035 if (n_invalid) {
2036 memset(HPTE(spapr->htab, index + n_valid), 0,
2037 HASH_PTE_SIZE_64 * n_invalid);
2038 }
2039 } else {
2040 int rc;
2041
2042 assert(fd >= 0);
2043
2044 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
2045 if (rc < 0) {
2046 return rc;
2047 }
2048 }
2049 }
2050
2051 if (!spapr->htab) {
2052 assert(fd >= 0);
2053 close(fd);
2054 }
2055
2056 return 0;
2057 }
2058
2059 static void htab_save_cleanup(void *opaque)
2060 {
2061 sPAPRMachineState *spapr = opaque;
2062
2063 close_htab_fd(spapr);
2064 }
2065
2066 static SaveVMHandlers savevm_htab_handlers = {
2067 .save_setup = htab_save_setup,
2068 .save_live_iterate = htab_save_iterate,
2069 .save_live_complete_precopy = htab_save_complete,
2070 .save_cleanup = htab_save_cleanup,
2071 .load_state = htab_load,
2072 };
2073
2074 static void spapr_boot_set(void *opaque, const char *boot_device,
2075 Error **errp)
2076 {
2077 MachineState *machine = MACHINE(opaque);
2078 machine->boot_order = g_strdup(boot_device);
2079 }
2080
2081 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
2082 {
2083 MachineState *machine = MACHINE(spapr);
2084 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2085 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2086 int i;
2087
2088 for (i = 0; i < nr_lmbs; i++) {
2089 uint64_t addr;
2090
2091 addr = i * lmb_size + spapr->hotplug_memory.base;
2092 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2093 addr / lmb_size);
2094 }
2095 }
2096
2097 /*
2098 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2099 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2100 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2101 */
2102 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2103 {
2104 int i;
2105
2106 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2107 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2108 " is not aligned to %llu MiB",
2109 machine->ram_size,
2110 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2111 return;
2112 }
2113
2114 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2115 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2116 " is not aligned to %llu MiB",
2117 machine->ram_size,
2118 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2119 return;
2120 }
2121
2122 for (i = 0; i < nb_numa_nodes; i++) {
2123 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2124 error_setg(errp,
2125 "Node %d memory size 0x%" PRIx64
2126 " is not aligned to %llu MiB",
2127 i, numa_info[i].node_mem,
2128 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2129 return;
2130 }
2131 }
2132 }
2133
2134 /* find cpu slot in machine->possible_cpus by core_id */
2135 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2136 {
2137 int index = id / smp_threads;
2138
2139 if (index >= ms->possible_cpus->len) {
2140 return NULL;
2141 }
2142 if (idx) {
2143 *idx = index;
2144 }
2145 return &ms->possible_cpus->cpus[index];
2146 }
2147
2148 static void spapr_init_cpus(sPAPRMachineState *spapr)
2149 {
2150 MachineState *machine = MACHINE(spapr);
2151 MachineClass *mc = MACHINE_GET_CLASS(machine);
2152 const char *type = spapr_get_cpu_core_type(machine->cpu_type);
2153 int smt = kvmppc_smt_threads();
2154 const CPUArchIdList *possible_cpus;
2155 int boot_cores_nr = smp_cpus / smp_threads;
2156 int i;
2157
2158 if (!type) {
2159 error_report("Unable to find sPAPR CPU Core definition");
2160 exit(1);
2161 }
2162
2163 possible_cpus = mc->possible_cpu_arch_ids(machine);
2164 if (mc->has_hotpluggable_cpus) {
2165 if (smp_cpus % smp_threads) {
2166 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2167 smp_cpus, smp_threads);
2168 exit(1);
2169 }
2170 if (max_cpus % smp_threads) {
2171 error_report("max_cpus (%u) must be multiple of threads (%u)",
2172 max_cpus, smp_threads);
2173 exit(1);
2174 }
2175 } else {
2176 if (max_cpus != smp_cpus) {
2177 error_report("This machine version does not support CPU hotplug");
2178 exit(1);
2179 }
2180 boot_cores_nr = possible_cpus->len;
2181 }
2182
2183 for (i = 0; i < possible_cpus->len; i++) {
2184 int core_id = i * smp_threads;
2185
2186 if (mc->has_hotpluggable_cpus) {
2187 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2188 (core_id / smp_threads) * smt);
2189 }
2190
2191 if (i < boot_cores_nr) {
2192 Object *core = object_new(type);
2193 int nr_threads = smp_threads;
2194
2195 /* Handle the partially filled core for older machine types */
2196 if ((i + 1) * smp_threads >= smp_cpus) {
2197 nr_threads = smp_cpus - i * smp_threads;
2198 }
2199
2200 object_property_set_int(core, nr_threads, "nr-threads",
2201 &error_fatal);
2202 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
2203 &error_fatal);
2204 object_property_set_bool(core, true, "realized", &error_fatal);
2205 }
2206 }
2207 }
2208
2209 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp)
2210 {
2211 Error *local_err = NULL;
2212 bool vsmt_user = !!spapr->vsmt;
2213 int kvm_smt = kvmppc_smt_threads();
2214 int ret;
2215
2216 if (!kvm_enabled() && (smp_threads > 1)) {
2217 error_setg(&local_err, "TCG cannot support more than 1 thread/core "
2218 "on a pseries machine");
2219 goto out;
2220 }
2221 if (!is_power_of_2(smp_threads)) {
2222 error_setg(&local_err, "Cannot support %d threads/core on a pseries "
2223 "machine because it must be a power of 2", smp_threads);
2224 goto out;
2225 }
2226
2227 /* Detemine the VSMT mode to use: */
2228 if (vsmt_user) {
2229 if (spapr->vsmt < smp_threads) {
2230 error_setg(&local_err, "Cannot support VSMT mode %d"
2231 " because it must be >= threads/core (%d)",
2232 spapr->vsmt, smp_threads);
2233 goto out;
2234 }
2235 /* In this case, spapr->vsmt has been set by the command line */
2236 } else {
2237 /* Choose a VSMT mode that may be higher than necessary but is
2238 * likely to be compatible with hosts that don't have VSMT. */
2239 spapr->vsmt = MAX(kvm_smt, smp_threads);
2240 }
2241
2242 /* KVM: If necessary, set the SMT mode: */
2243 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
2244 ret = kvmppc_set_smt_threads(spapr->vsmt);
2245 if (ret) {
2246 error_setg(&local_err,
2247 "Failed to set KVM's VSMT mode to %d (errno %d)",
2248 spapr->vsmt, ret);
2249 if (!vsmt_user) {
2250 error_append_hint(&local_err, "On PPC, a VM with %d threads/"
2251 "core on a host with %d threads/core requires "
2252 " the use of VSMT mode %d.\n",
2253 smp_threads, kvm_smt, spapr->vsmt);
2254 }
2255 kvmppc_hint_smt_possible(&local_err);
2256 goto out;
2257 }
2258 }
2259 /* else TCG: nothing to do currently */
2260 out:
2261 error_propagate(errp, local_err);
2262 }
2263
2264 /* pSeries LPAR / sPAPR hardware init */
2265 static void ppc_spapr_init(MachineState *machine)
2266 {
2267 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2268 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2269 const char *kernel_filename = machine->kernel_filename;
2270 const char *initrd_filename = machine->initrd_filename;
2271 PCIHostState *phb;
2272 int i;
2273 MemoryRegion *sysmem = get_system_memory();
2274 MemoryRegion *ram = g_new(MemoryRegion, 1);
2275 MemoryRegion *rma_region;
2276 void *rma = NULL;
2277 hwaddr rma_alloc_size;
2278 hwaddr node0_size = spapr_node0_size(machine);
2279 long load_limit, fw_size;
2280 char *filename;
2281 Error *resize_hpt_err = NULL;
2282
2283 msi_nonbroken = true;
2284
2285 QLIST_INIT(&spapr->phbs);
2286 QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2287
2288 /* Check HPT resizing availability */
2289 kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2290 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2291 /*
2292 * If the user explicitly requested a mode we should either
2293 * supply it, or fail completely (which we do below). But if
2294 * it's not set explicitly, we reset our mode to something
2295 * that works
2296 */
2297 if (resize_hpt_err) {
2298 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2299 error_free(resize_hpt_err);
2300 resize_hpt_err = NULL;
2301 } else {
2302 spapr->resize_hpt = smc->resize_hpt_default;
2303 }
2304 }
2305
2306 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2307
2308 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2309 /*
2310 * User requested HPT resize, but this host can't supply it. Bail out
2311 */
2312 error_report_err(resize_hpt_err);
2313 exit(1);
2314 }
2315
2316 /* Allocate RMA if necessary */
2317 rma_alloc_size = kvmppc_alloc_rma(&rma);
2318
2319 if (rma_alloc_size == -1) {
2320 error_report("Unable to create RMA");
2321 exit(1);
2322 }
2323
2324 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
2325 spapr->rma_size = rma_alloc_size;
2326 } else {
2327 spapr->rma_size = node0_size;
2328
2329 /* With KVM, we don't actually know whether KVM supports an
2330 * unbounded RMA (PR KVM) or is limited by the hash table size
2331 * (HV KVM using VRMA), so we always assume the latter
2332 *
2333 * In that case, we also limit the initial allocations for RTAS
2334 * etc... to 256M since we have no way to know what the VRMA size
2335 * is going to be as it depends on the size of the hash table
2336 * isn't determined yet.
2337 */
2338 if (kvm_enabled()) {
2339 spapr->vrma_adjust = 1;
2340 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
2341 }
2342
2343 /* Actually we don't support unbounded RMA anymore since we
2344 * added proper emulation of HV mode. The max we can get is
2345 * 16G which also happens to be what we configure for PAPR
2346 * mode so make sure we don't do anything bigger than that
2347 */
2348 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
2349 }
2350
2351 if (spapr->rma_size > node0_size) {
2352 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2353 spapr->rma_size);
2354 exit(1);
2355 }
2356
2357 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2358 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2359
2360 /* Set up Interrupt Controller before we create the VCPUs */
2361 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal);
2362
2363 /* Set up containers for ibm,client-architecture-support negotiated options
2364 */
2365 spapr->ov5 = spapr_ovec_new();
2366 spapr->ov5_cas = spapr_ovec_new();
2367
2368 if (smc->dr_lmb_enabled) {
2369 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2370 spapr_validate_node_memory(machine, &error_fatal);
2371 }
2372
2373 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2374 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) {
2375 /* KVM and TCG always allow GTSE with radix... */
2376 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2377 }
2378 /* ... but not with hash (currently). */
2379
2380 /* advertise support for dedicated HP event source to guests */
2381 if (spapr->use_hotplug_event_source) {
2382 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2383 }
2384
2385 /* advertise support for HPT resizing */
2386 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2387 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2388 }
2389
2390 /* init CPUs */
2391 spapr_set_vsmt_mode(spapr, &error_fatal);
2392
2393 spapr_init_cpus(spapr);
2394
2395 if (kvm_enabled()) {
2396 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2397 kvmppc_enable_logical_ci_hcalls();
2398 kvmppc_enable_set_mode_hcall();
2399
2400 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2401 kvmppc_enable_clear_ref_mod_hcalls();
2402 }
2403
2404 /* allocate RAM */
2405 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2406 machine->ram_size);
2407 memory_region_add_subregion(sysmem, 0, ram);
2408
2409 if (rma_alloc_size && rma) {
2410 rma_region = g_new(MemoryRegion, 1);
2411 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
2412 rma_alloc_size, rma);
2413 vmstate_register_ram_global(rma_region);
2414 memory_region_add_subregion(sysmem, 0, rma_region);
2415 }
2416
2417 /* initialize hotplug memory address space */
2418 if (machine->ram_size < machine->maxram_size) {
2419 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
2420 /*
2421 * Limit the number of hotpluggable memory slots to half the number
2422 * slots that KVM supports, leaving the other half for PCI and other
2423 * devices. However ensure that number of slots doesn't drop below 32.
2424 */
2425 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2426 SPAPR_MAX_RAM_SLOTS;
2427
2428 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2429 max_memslots = SPAPR_MAX_RAM_SLOTS;
2430 }
2431 if (machine->ram_slots > max_memslots) {
2432 error_report("Specified number of memory slots %"
2433 PRIu64" exceeds max supported %d",
2434 machine->ram_slots, max_memslots);
2435 exit(1);
2436 }
2437
2438 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
2439 SPAPR_HOTPLUG_MEM_ALIGN);
2440 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
2441 "hotplug-memory", hotplug_mem_size);
2442 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
2443 &spapr->hotplug_memory.mr);
2444 }
2445
2446 if (smc->dr_lmb_enabled) {
2447 spapr_create_lmb_dr_connectors(spapr);
2448 }
2449
2450 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
2451 if (!filename) {
2452 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2453 exit(1);
2454 }
2455 spapr->rtas_size = get_image_size(filename);
2456 if (spapr->rtas_size < 0) {
2457 error_report("Could not get size of LPAR rtas '%s'", filename);
2458 exit(1);
2459 }
2460 spapr->rtas_blob = g_malloc(spapr->rtas_size);
2461 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
2462 error_report("Could not load LPAR rtas '%s'", filename);
2463 exit(1);
2464 }
2465 if (spapr->rtas_size > RTAS_MAX_SIZE) {
2466 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2467 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
2468 exit(1);
2469 }
2470 g_free(filename);
2471
2472 /* Set up RTAS event infrastructure */
2473 spapr_events_init(spapr);
2474
2475 /* Set up the RTC RTAS interfaces */
2476 spapr_rtc_create(spapr);
2477
2478 /* Set up VIO bus */
2479 spapr->vio_bus = spapr_vio_bus_init();
2480
2481 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
2482 if (serial_hds[i]) {
2483 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
2484 }
2485 }
2486
2487 /* We always have at least the nvram device on VIO */
2488 spapr_create_nvram(spapr);
2489
2490 /* Set up PCI */
2491 spapr_pci_rtas_init();
2492
2493 phb = spapr_create_phb(spapr, 0);
2494
2495 for (i = 0; i < nb_nics; i++) {
2496 NICInfo *nd = &nd_table[i];
2497
2498 if (!nd->model) {
2499 nd->model = g_strdup("ibmveth");
2500 }
2501
2502 if (strcmp(nd->model, "ibmveth") == 0) {
2503 spapr_vlan_create(spapr->vio_bus, nd);
2504 } else {
2505 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2506 }
2507 }
2508
2509 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2510 spapr_vscsi_create(spapr->vio_bus);
2511 }
2512
2513 /* Graphics */
2514 if (spapr_vga_init(phb->bus, &error_fatal)) {
2515 spapr->has_graphics = true;
2516 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2517 }
2518
2519 if (machine->usb) {
2520 if (smc->use_ohci_by_default) {
2521 pci_create_simple(phb->bus, -1, "pci-ohci");
2522 } else {
2523 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2524 }
2525
2526 if (spapr->has_graphics) {
2527 USBBus *usb_bus = usb_bus_find(-1);
2528
2529 usb_create_simple(usb_bus, "usb-kbd");
2530 usb_create_simple(usb_bus, "usb-mouse");
2531 }
2532 }
2533
2534 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
2535 error_report(
2536 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2537 MIN_RMA_SLOF);
2538 exit(1);
2539 }
2540
2541 if (kernel_filename) {
2542 uint64_t lowaddr = 0;
2543
2544 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address,
2545 NULL, NULL, &lowaddr, NULL, 1,
2546 PPC_ELF_MACHINE, 0, 0);
2547 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2548 spapr->kernel_size = load_elf(kernel_filename,
2549 translate_kernel_address, NULL, NULL,
2550 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2551 0, 0);
2552 spapr->kernel_le = spapr->kernel_size > 0;
2553 }
2554 if (spapr->kernel_size < 0) {
2555 error_report("error loading %s: %s", kernel_filename,
2556 load_elf_strerror(spapr->kernel_size));
2557 exit(1);
2558 }
2559
2560 /* load initrd */
2561 if (initrd_filename) {
2562 /* Try to locate the initrd in the gap between the kernel
2563 * and the firmware. Add a bit of space just in case
2564 */
2565 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2566 + 0x1ffff) & ~0xffff;
2567 spapr->initrd_size = load_image_targphys(initrd_filename,
2568 spapr->initrd_base,
2569 load_limit
2570 - spapr->initrd_base);
2571 if (spapr->initrd_size < 0) {
2572 error_report("could not load initial ram disk '%s'",
2573 initrd_filename);
2574 exit(1);
2575 }
2576 }
2577 }
2578
2579 if (bios_name == NULL) {
2580 bios_name = FW_FILE_NAME;
2581 }
2582 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2583 if (!filename) {
2584 error_report("Could not find LPAR firmware '%s'", bios_name);
2585 exit(1);
2586 }
2587 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2588 if (fw_size <= 0) {
2589 error_report("Could not load LPAR firmware '%s'", filename);
2590 exit(1);
2591 }
2592 g_free(filename);
2593
2594 /* FIXME: Should register things through the MachineState's qdev
2595 * interface, this is a legacy from the sPAPREnvironment structure
2596 * which predated MachineState but had a similar function */
2597 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2598 register_savevm_live(NULL, "spapr/htab", -1, 1,
2599 &savevm_htab_handlers, spapr);
2600
2601 qemu_register_boot_set(spapr_boot_set, spapr);
2602
2603 if (kvm_enabled()) {
2604 /* to stop and start vmclock */
2605 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
2606 &spapr->tb);
2607
2608 kvmppc_spapr_enable_inkernel_multitce();
2609 }
2610 }
2611
2612 static int spapr_kvm_type(const char *vm_type)
2613 {
2614 if (!vm_type) {
2615 return 0;
2616 }
2617
2618 if (!strcmp(vm_type, "HV")) {
2619 return 1;
2620 }
2621
2622 if (!strcmp(vm_type, "PR")) {
2623 return 2;
2624 }
2625
2626 error_report("Unknown kvm-type specified '%s'", vm_type);
2627 exit(1);
2628 }
2629
2630 /*
2631 * Implementation of an interface to adjust firmware path
2632 * for the bootindex property handling.
2633 */
2634 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2635 DeviceState *dev)
2636 {
2637 #define CAST(type, obj, name) \
2638 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2639 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2640 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2641 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
2642
2643 if (d) {
2644 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2645 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2646 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2647
2648 if (spapr) {
2649 /*
2650 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2651 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2652 * in the top 16 bits of the 64-bit LUN
2653 */
2654 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2655 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2656 (uint64_t)id << 48);
2657 } else if (virtio) {
2658 /*
2659 * We use SRP luns of the form 01000000 | (target << 8) | lun
2660 * in the top 32 bits of the 64-bit LUN
2661 * Note: the quote above is from SLOF and it is wrong,
2662 * the actual binding is:
2663 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2664 */
2665 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2666 if (d->lun >= 256) {
2667 /* Use the LUN "flat space addressing method" */
2668 id |= 0x4000;
2669 }
2670 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2671 (uint64_t)id << 32);
2672 } else if (usb) {
2673 /*
2674 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2675 * in the top 32 bits of the 64-bit LUN
2676 */
2677 unsigned usb_port = atoi(usb->port->path);
2678 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2679 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2680 (uint64_t)id << 32);
2681 }
2682 }
2683
2684 /*
2685 * SLOF probes the USB devices, and if it recognizes that the device is a
2686 * storage device, it changes its name to "storage" instead of "usb-host",
2687 * and additionally adds a child node for the SCSI LUN, so the correct
2688 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
2689 */
2690 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
2691 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
2692 if (usb_host_dev_is_scsi_storage(usbdev)) {
2693 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
2694 }
2695 }
2696
2697 if (phb) {
2698 /* Replace "pci" with "pci@800000020000000" */
2699 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2700 }
2701
2702 if (vsc) {
2703 /* Same logic as virtio above */
2704 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
2705 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
2706 }
2707
2708 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
2709 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
2710 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
2711 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
2712 }
2713
2714 return NULL;
2715 }
2716
2717 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2718 {
2719 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2720
2721 return g_strdup(spapr->kvm_type);
2722 }
2723
2724 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2725 {
2726 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2727
2728 g_free(spapr->kvm_type);
2729 spapr->kvm_type = g_strdup(value);
2730 }
2731
2732 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
2733 {
2734 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2735
2736 return spapr->use_hotplug_event_source;
2737 }
2738
2739 static void spapr_set_modern_hotplug_events(Object *obj, bool value,
2740 Error **errp)
2741 {
2742 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2743
2744 spapr->use_hotplug_event_source = value;
2745 }
2746
2747 static char *spapr_get_resize_hpt(Object *obj, Error **errp)
2748 {
2749 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2750
2751 switch (spapr->resize_hpt) {
2752 case SPAPR_RESIZE_HPT_DEFAULT:
2753 return g_strdup("default");
2754 case SPAPR_RESIZE_HPT_DISABLED:
2755 return g_strdup("disabled");
2756 case SPAPR_RESIZE_HPT_ENABLED:
2757 return g_strdup("enabled");
2758 case SPAPR_RESIZE_HPT_REQUIRED:
2759 return g_strdup("required");
2760 }
2761 g_assert_not_reached();
2762 }
2763
2764 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
2765 {
2766 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2767
2768 if (strcmp(value, "default") == 0) {
2769 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
2770 } else if (strcmp(value, "disabled") == 0) {
2771 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2772 } else if (strcmp(value, "enabled") == 0) {
2773 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
2774 } else if (strcmp(value, "required") == 0) {
2775 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
2776 } else {
2777 error_setg(errp, "Bad value for \"resize-hpt\" property");
2778 }
2779 }
2780
2781 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name,
2782 void *opaque, Error **errp)
2783 {
2784 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
2785 }
2786
2787 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name,
2788 void *opaque, Error **errp)
2789 {
2790 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
2791 }
2792
2793 static void spapr_machine_initfn(Object *obj)
2794 {
2795 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2796
2797 spapr->htab_fd = -1;
2798 spapr->use_hotplug_event_source = true;
2799 object_property_add_str(obj, "kvm-type",
2800 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2801 object_property_set_description(obj, "kvm-type",
2802 "Specifies the KVM virtualization mode (HV, PR)",
2803 NULL);
2804 object_property_add_bool(obj, "modern-hotplug-events",
2805 spapr_get_modern_hotplug_events,
2806 spapr_set_modern_hotplug_events,
2807 NULL);
2808 object_property_set_description(obj, "modern-hotplug-events",
2809 "Use dedicated hotplug event mechanism in"
2810 " place of standard EPOW events when possible"
2811 " (required for memory hot-unplug support)",
2812 NULL);
2813
2814 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
2815 "Maximum permitted CPU compatibility mode",
2816 &error_fatal);
2817
2818 object_property_add_str(obj, "resize-hpt",
2819 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL);
2820 object_property_set_description(obj, "resize-hpt",
2821 "Resizing of the Hash Page Table (enabled, disabled, required)",
2822 NULL);
2823 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt,
2824 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort);
2825 object_property_set_description(obj, "vsmt",
2826 "Virtual SMT: KVM behaves as if this were"
2827 " the host's SMT mode", &error_abort);
2828 }
2829
2830 static void spapr_machine_finalizefn(Object *obj)
2831 {
2832 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2833
2834 g_free(spapr->kvm_type);
2835 }
2836
2837 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
2838 {
2839 cpu_synchronize_state(cs);
2840 ppc_cpu_do_system_reset(cs);
2841 }
2842
2843 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2844 {
2845 CPUState *cs;
2846
2847 CPU_FOREACH(cs) {
2848 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
2849 }
2850 }
2851
2852 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
2853 uint32_t node, bool dedicated_hp_event_source,
2854 Error **errp)
2855 {
2856 sPAPRDRConnector *drc;
2857 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2858 int i, fdt_offset, fdt_size;
2859 void *fdt;
2860 uint64_t addr = addr_start;
2861 bool hotplugged = spapr_drc_hotplugged(dev);
2862 Error *local_err = NULL;
2863
2864 for (i = 0; i < nr_lmbs; i++) {
2865 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2866 addr / SPAPR_MEMORY_BLOCK_SIZE);
2867 g_assert(drc);
2868
2869 fdt = create_device_tree(&fdt_size);
2870 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2871 SPAPR_MEMORY_BLOCK_SIZE);
2872
2873 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
2874 if (local_err) {
2875 while (addr > addr_start) {
2876 addr -= SPAPR_MEMORY_BLOCK_SIZE;
2877 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2878 addr / SPAPR_MEMORY_BLOCK_SIZE);
2879 spapr_drc_detach(drc);
2880 }
2881 g_free(fdt);
2882 error_propagate(errp, local_err);
2883 return;
2884 }
2885 if (!hotplugged) {
2886 spapr_drc_reset(drc);
2887 }
2888 addr += SPAPR_MEMORY_BLOCK_SIZE;
2889 }
2890 /* send hotplug notification to the
2891 * guest only in case of hotplugged memory
2892 */
2893 if (hotplugged) {
2894 if (dedicated_hp_event_source) {
2895 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2896 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2897 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2898 nr_lmbs,
2899 spapr_drc_index(drc));
2900 } else {
2901 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
2902 nr_lmbs);
2903 }
2904 }
2905 }
2906
2907 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2908 uint32_t node, Error **errp)
2909 {
2910 Error *local_err = NULL;
2911 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2912 PCDIMMDevice *dimm = PC_DIMM(dev);
2913 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2914 MemoryRegion *mr;
2915 uint64_t align, size, addr;
2916
2917 mr = ddc->get_memory_region(dimm, &local_err);
2918 if (local_err) {
2919 goto out;
2920 }
2921 align = memory_region_get_alignment(mr);
2922 size = memory_region_size(mr);
2923
2924 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
2925 if (local_err) {
2926 goto out;
2927 }
2928
2929 addr = object_property_get_uint(OBJECT(dimm),
2930 PC_DIMM_ADDR_PROP, &local_err);
2931 if (local_err) {
2932 goto out_unplug;
2933 }
2934
2935 spapr_add_lmbs(dev, addr, size, node,
2936 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
2937 &local_err);
2938 if (local_err) {
2939 goto out_unplug;
2940 }
2941
2942 return;
2943
2944 out_unplug:
2945 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2946 out:
2947 error_propagate(errp, local_err);
2948 }
2949
2950 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2951 Error **errp)
2952 {
2953 PCDIMMDevice *dimm = PC_DIMM(dev);
2954 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2955 MemoryRegion *mr;
2956 uint64_t size;
2957 char *mem_dev;
2958
2959 mr = ddc->get_memory_region(dimm, errp);
2960 if (!mr) {
2961 return;
2962 }
2963 size = memory_region_size(mr);
2964
2965 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2966 error_setg(errp, "Hotplugged memory size must be a multiple of "
2967 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2968 return;
2969 }
2970
2971 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL);
2972 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) {
2973 error_setg(errp, "Memory backend has bad page size. "
2974 "Use 'memory-backend-file' with correct mem-path.");
2975 goto out;
2976 }
2977
2978 out:
2979 g_free(mem_dev);
2980 }
2981
2982 struct sPAPRDIMMState {
2983 PCDIMMDevice *dimm;
2984 uint32_t nr_lmbs;
2985 QTAILQ_ENTRY(sPAPRDIMMState) next;
2986 };
2987
2988 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s,
2989 PCDIMMDevice *dimm)
2990 {
2991 sPAPRDIMMState *dimm_state = NULL;
2992
2993 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) {
2994 if (dimm_state->dimm == dimm) {
2995 break;
2996 }
2997 }
2998 return dimm_state;
2999 }
3000
3001 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr,
3002 uint32_t nr_lmbs,
3003 PCDIMMDevice *dimm)
3004 {
3005 sPAPRDIMMState *ds = NULL;
3006
3007 /*
3008 * If this request is for a DIMM whose removal had failed earlier
3009 * (due to guest's refusal to remove the LMBs), we would have this
3010 * dimm already in the pending_dimm_unplugs list. In that
3011 * case don't add again.
3012 */
3013 ds = spapr_pending_dimm_unplugs_find(spapr, dimm);
3014 if (!ds) {
3015 ds = g_malloc0(sizeof(sPAPRDIMMState));
3016 ds->nr_lmbs = nr_lmbs;
3017 ds->dimm = dimm;
3018 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next);
3019 }
3020 return ds;
3021 }
3022
3023 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr,
3024 sPAPRDIMMState *dimm_state)
3025 {
3026 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next);
3027 g_free(dimm_state);
3028 }
3029
3030 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms,
3031 PCDIMMDevice *dimm)
3032 {
3033 sPAPRDRConnector *drc;
3034 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3035 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort);
3036 uint64_t size = memory_region_size(mr);
3037 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3038 uint32_t avail_lmbs = 0;
3039 uint64_t addr_start, addr;
3040 int i;
3041
3042 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3043 &error_abort);
3044
3045 addr = addr_start;
3046 for (i = 0; i < nr_lmbs; i++) {
3047 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3048 addr / SPAPR_MEMORY_BLOCK_SIZE);
3049 g_assert(drc);
3050 if (drc->dev) {
3051 avail_lmbs++;
3052 }
3053 addr += SPAPR_MEMORY_BLOCK_SIZE;
3054 }
3055
3056 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm);
3057 }
3058
3059 /* Callback to be called during DRC release. */
3060 void spapr_lmb_release(DeviceState *dev)
3061 {
3062 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_hotplug_handler(dev));
3063 PCDIMMDevice *dimm = PC_DIMM(dev);
3064 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3065 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort);
3066 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3067
3068 /* This information will get lost if a migration occurs
3069 * during the unplug process. In this case recover it. */
3070 if (ds == NULL) {
3071 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev));
3072 g_assert(ds);
3073 /* The DRC being examined by the caller at least must be counted */
3074 g_assert(ds->nr_lmbs);
3075 }
3076
3077 if (--ds->nr_lmbs) {
3078 return;
3079 }
3080
3081 /*
3082 * Now that all the LMBs have been removed by the guest, call the
3083 * pc-dimm unplug handler to cleanup up the pc-dimm device.
3084 */
3085 pc_dimm_memory_unplug(dev, &spapr->hotplug_memory, mr);
3086 object_unparent(OBJECT(dev));
3087 spapr_pending_dimm_unplugs_remove(spapr, ds);
3088 }
3089
3090 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
3091 DeviceState *dev, Error **errp)
3092 {
3093 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3094 Error *local_err = NULL;
3095 PCDIMMDevice *dimm = PC_DIMM(dev);
3096 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3097 MemoryRegion *mr;
3098 uint32_t nr_lmbs;
3099 uint64_t size, addr_start, addr;
3100 int i;
3101 sPAPRDRConnector *drc;
3102
3103 mr = ddc->get_memory_region(dimm, &local_err);
3104 if (local_err) {
3105 goto out;
3106 }
3107 size = memory_region_size(mr);
3108 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3109
3110 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3111 &local_err);
3112 if (local_err) {
3113 goto out;
3114 }
3115
3116 /*
3117 * An existing pending dimm state for this DIMM means that there is an
3118 * unplug operation in progress, waiting for the spapr_lmb_release
3119 * callback to complete the job (BQL can't cover that far). In this case,
3120 * bail out to avoid detaching DRCs that were already released.
3121 */
3122 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) {
3123 error_setg(&local_err,
3124 "Memory unplug already in progress for device %s",
3125 dev->id);
3126 goto out;
3127 }
3128
3129 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm);
3130
3131 addr = addr_start;
3132 for (i = 0; i < nr_lmbs; i++) {
3133 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3134 addr / SPAPR_MEMORY_BLOCK_SIZE);
3135 g_assert(drc);
3136
3137 spapr_drc_detach(drc);
3138 addr += SPAPR_MEMORY_BLOCK_SIZE;
3139 }
3140
3141 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3142 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3143 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3144 nr_lmbs, spapr_drc_index(drc));
3145 out:
3146 error_propagate(errp, local_err);
3147 }
3148
3149 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
3150 sPAPRMachineState *spapr)
3151 {
3152 PowerPCCPU *cpu = POWERPC_CPU(cs);
3153 DeviceClass *dc = DEVICE_GET_CLASS(cs);
3154 int id = spapr_vcpu_id(cpu);
3155 void *fdt;
3156 int offset, fdt_size;
3157 char *nodename;
3158
3159 fdt = create_device_tree(&fdt_size);
3160 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
3161 offset = fdt_add_subnode(fdt, 0, nodename);
3162
3163 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
3164 g_free(nodename);
3165
3166 *fdt_offset = offset;
3167 return fdt;
3168 }
3169
3170 /* Callback to be called during DRC release. */
3171 void spapr_core_release(DeviceState *dev)
3172 {
3173 MachineState *ms = MACHINE(qdev_get_hotplug_handler(dev));
3174 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3175 CPUCore *cc = CPU_CORE(dev);
3176 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
3177
3178 if (smc->pre_2_10_has_unused_icps) {
3179 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
3180 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc));
3181 size_t size = object_type_get_instance_size(scc->cpu_type);
3182 int i;
3183
3184 for (i = 0; i < cc->nr_threads; i++) {
3185 CPUState *cs = CPU(sc->threads + i * size);
3186
3187 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index);
3188 }
3189 }
3190
3191 assert(core_slot);
3192 core_slot->cpu = NULL;
3193 object_unparent(OBJECT(dev));
3194 }
3195
3196 static
3197 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
3198 Error **errp)
3199 {
3200 int index;
3201 sPAPRDRConnector *drc;
3202 CPUCore *cc = CPU_CORE(dev);
3203 int smt = kvmppc_smt_threads();
3204
3205 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
3206 error_setg(errp, "Unable to find CPU core with core-id: %d",
3207 cc->core_id);
3208 return;
3209 }
3210 if (index == 0) {
3211 error_setg(errp, "Boot CPU core may not be unplugged");
3212 return;
3213 }
3214
3215 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt);
3216 g_assert(drc);
3217
3218 spapr_drc_detach(drc);
3219
3220 spapr_hotplug_req_remove_by_index(drc);
3221 }
3222
3223 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3224 Error **errp)
3225 {
3226 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3227 MachineClass *mc = MACHINE_GET_CLASS(spapr);
3228 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3229 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
3230 CPUCore *cc = CPU_CORE(dev);
3231 CPUState *cs = CPU(core->threads);
3232 sPAPRDRConnector *drc;
3233 Error *local_err = NULL;
3234 int smt = kvmppc_smt_threads();
3235 CPUArchId *core_slot;
3236 int index;
3237 bool hotplugged = spapr_drc_hotplugged(dev);
3238
3239 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3240 if (!core_slot) {
3241 error_setg(errp, "Unable to find CPU core with core-id: %d",
3242 cc->core_id);
3243 return;
3244 }
3245 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt);
3246
3247 g_assert(drc || !mc->has_hotpluggable_cpus);
3248
3249 if (drc) {
3250 void *fdt;
3251 int fdt_offset;
3252
3253 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
3254
3255 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
3256 if (local_err) {
3257 g_free(fdt);
3258 error_propagate(errp, local_err);
3259 return;
3260 }
3261
3262 if (hotplugged) {
3263 /*
3264 * Send hotplug notification interrupt to the guest only
3265 * in case of hotplugged CPUs.
3266 */
3267 spapr_hotplug_req_add_by_index(drc);
3268 } else {
3269 spapr_drc_reset(drc);
3270 }
3271 }
3272
3273 core_slot->cpu = OBJECT(dev);
3274
3275 if (smc->pre_2_10_has_unused_icps) {
3276 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc));
3277 size_t size = object_type_get_instance_size(scc->cpu_type);
3278 int i;
3279
3280 for (i = 0; i < cc->nr_threads; i++) {
3281 sPAPRCPUCore *sc = SPAPR_CPU_CORE(dev);
3282 void *obj = sc->threads + i * size;
3283
3284 cs = CPU(obj);
3285 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
3286 }
3287 }
3288 }
3289
3290 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3291 Error **errp)
3292 {
3293 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
3294 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
3295 Error *local_err = NULL;
3296 CPUCore *cc = CPU_CORE(dev);
3297 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type);
3298 const char *type = object_get_typename(OBJECT(dev));
3299 CPUArchId *core_slot;
3300 int index;
3301
3302 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
3303 error_setg(&local_err, "CPU hotplug not supported for this machine");
3304 goto out;
3305 }
3306
3307 if (strcmp(base_core_type, type)) {
3308 error_setg(&local_err, "CPU core type should be %s", base_core_type);
3309 goto out;
3310 }
3311
3312 if (cc->core_id % smp_threads) {
3313 error_setg(&local_err, "invalid core id %d", cc->core_id);
3314 goto out;
3315 }
3316
3317 /*
3318 * In general we should have homogeneous threads-per-core, but old
3319 * (pre hotplug support) machine types allow the last core to have
3320 * reduced threads as a compatibility hack for when we allowed
3321 * total vcpus not a multiple of threads-per-core.
3322 */
3323 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) {
3324 error_setg(&local_err, "invalid nr-threads %d, must be %d",
3325 cc->nr_threads, smp_threads);
3326 goto out;
3327 }
3328
3329 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3330 if (!core_slot) {
3331 error_setg(&local_err, "core id %d out of range", cc->core_id);
3332 goto out;
3333 }
3334
3335 if (core_slot->cpu) {
3336 error_setg(&local_err, "core %d already populated", cc->core_id);
3337 goto out;
3338 }
3339
3340 numa_cpu_pre_plug(core_slot, dev, &local_err);
3341
3342 out:
3343 error_propagate(errp, local_err);
3344 }
3345
3346 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
3347 DeviceState *dev, Error **errp)
3348 {
3349 MachineState *ms = MACHINE(hotplug_dev);
3350 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3351
3352 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3353 int node;
3354
3355 if (!smc->dr_lmb_enabled) {
3356 error_setg(errp, "Memory hotplug not supported for this machine");
3357 return;
3358 }
3359 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
3360 if (*errp) {
3361 return;
3362 }
3363 if (node < 0 || node >= MAX_NODES) {
3364 error_setg(errp, "Invaild node %d", node);
3365 return;
3366 }
3367
3368 /*
3369 * Currently PowerPC kernel doesn't allow hot-adding memory to
3370 * memory-less node, but instead will silently add the memory
3371 * to the first node that has some memory. This causes two
3372 * unexpected behaviours for the user.
3373 *
3374 * - Memory gets hotplugged to a different node than what the user
3375 * specified.
3376 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
3377 * to memory-less node, a reboot will set things accordingly
3378 * and the previously hotplugged memory now ends in the right node.
3379 * This appears as if some memory moved from one node to another.
3380 *
3381 * So until kernel starts supporting memory hotplug to memory-less
3382 * nodes, just prevent such attempts upfront in QEMU.
3383 */
3384 if (nb_numa_nodes && !numa_info[node].node_mem) {
3385 error_setg(errp, "Can't hotplug memory to memory-less node %d",
3386 node);
3387 return;
3388 }
3389
3390 spapr_memory_plug(hotplug_dev, dev, node, errp);
3391 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3392 spapr_core_plug(hotplug_dev, dev, errp);
3393 }
3394 }
3395
3396 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
3397 DeviceState *dev, Error **errp)
3398 {
3399 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev));
3400 MachineClass *mc = MACHINE_GET_CLASS(sms);
3401
3402 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3403 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
3404 spapr_memory_unplug_request(hotplug_dev, dev, errp);
3405 } else {
3406 /* NOTE: this means there is a window after guest reset, prior to
3407 * CAS negotiation, where unplug requests will fail due to the
3408 * capability not being detected yet. This is a bit different than
3409 * the case with PCI unplug, where the events will be queued and
3410 * eventually handled by the guest after boot
3411 */
3412 error_setg(errp, "Memory hot unplug not supported for this guest");
3413 }
3414 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3415 if (!mc->has_hotpluggable_cpus) {
3416 error_setg(errp, "CPU hot unplug not supported on this machine");
3417 return;
3418 }
3419 spapr_core_unplug_request(hotplug_dev, dev, errp);
3420 }
3421 }
3422
3423 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
3424 DeviceState *dev, Error **errp)
3425 {
3426 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3427 spapr_memory_pre_plug(hotplug_dev, dev, errp);
3428 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3429 spapr_core_pre_plug(hotplug_dev, dev, errp);
3430 }
3431 }
3432
3433 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
3434 DeviceState *dev)
3435 {
3436 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
3437 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3438 return HOTPLUG_HANDLER(machine);
3439 }
3440 return NULL;
3441 }
3442
3443 static CpuInstanceProperties
3444 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
3445 {
3446 CPUArchId *core_slot;
3447 MachineClass *mc = MACHINE_GET_CLASS(machine);
3448
3449 /* make sure possible_cpu are intialized */
3450 mc->possible_cpu_arch_ids(machine);
3451 /* get CPU core slot containing thread that matches cpu_index */
3452 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL);
3453 assert(core_slot);
3454 return core_slot->props;
3455 }
3456
3457 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx)
3458 {
3459 return idx / smp_cores % nb_numa_nodes;
3460 }
3461
3462 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
3463 {
3464 int i;
3465 int spapr_max_cores = max_cpus / smp_threads;
3466 MachineClass *mc = MACHINE_GET_CLASS(machine);
3467
3468 if (!mc->has_hotpluggable_cpus) {
3469 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
3470 }
3471 if (machine->possible_cpus) {
3472 assert(machine->possible_cpus->len == spapr_max_cores);
3473 return machine->possible_cpus;
3474 }
3475
3476 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
3477 sizeof(CPUArchId) * spapr_max_cores);
3478 machine->possible_cpus->len = spapr_max_cores;
3479 for (i = 0; i < machine->possible_cpus->len; i++) {
3480 int core_id = i * smp_threads;
3481
3482 machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
3483 machine->possible_cpus->cpus[i].arch_id = core_id;
3484 machine->possible_cpus->cpus[i].props.has_core_id = true;
3485 machine->possible_cpus->cpus[i].props.core_id = core_id;
3486 }
3487 return machine->possible_cpus;
3488 }
3489
3490 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
3491 uint64_t *buid, hwaddr *pio,
3492 hwaddr *mmio32, hwaddr *mmio64,
3493 unsigned n_dma, uint32_t *liobns, Error **errp)
3494 {
3495 /*
3496 * New-style PHB window placement.
3497 *
3498 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
3499 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
3500 * windows.
3501 *
3502 * Some guest kernels can't work with MMIO windows above 1<<46
3503 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
3504 *
3505 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
3506 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
3507 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
3508 * 1TiB 64-bit MMIO windows for each PHB.
3509 */
3510 const uint64_t base_buid = 0x800000020000000ULL;
3511 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
3512 SPAPR_PCI_MEM64_WIN_SIZE - 1)
3513 int i;
3514
3515 /* Sanity check natural alignments */
3516 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3517 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3518 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
3519 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
3520 /* Sanity check bounds */
3521 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
3522 SPAPR_PCI_MEM32_WIN_SIZE);
3523 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
3524 SPAPR_PCI_MEM64_WIN_SIZE);
3525
3526 if (index >= SPAPR_MAX_PHBS) {
3527 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
3528 SPAPR_MAX_PHBS - 1);
3529 return;
3530 }
3531
3532 *buid = base_buid + index;
3533 for (i = 0; i < n_dma; ++i) {
3534 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3535 }
3536
3537 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
3538 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
3539 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
3540 }
3541
3542 static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
3543 {
3544 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3545
3546 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
3547 }
3548
3549 static void spapr_ics_resend(XICSFabric *dev)
3550 {
3551 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3552
3553 ics_resend(spapr->ics);
3554 }
3555
3556 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
3557 {
3558 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id);
3559
3560 return cpu ? ICP(cpu->intc) : NULL;
3561 }
3562
3563 static void spapr_pic_print_info(InterruptStatsProvider *obj,
3564 Monitor *mon)
3565 {
3566 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3567 CPUState *cs;
3568
3569 CPU_FOREACH(cs) {
3570 PowerPCCPU *cpu = POWERPC_CPU(cs);
3571
3572 icp_pic_print_info(ICP(cpu->intc), mon);
3573 }
3574
3575 ics_pic_print_info(spapr->ics, mon);
3576 }
3577
3578 int spapr_vcpu_id(PowerPCCPU *cpu)
3579 {
3580 CPUState *cs = CPU(cpu);
3581
3582 if (kvm_enabled()) {
3583 return kvm_arch_vcpu_id(cs);
3584 } else {
3585 return cs->cpu_index;
3586 }
3587 }
3588
3589 PowerPCCPU *spapr_find_cpu(int vcpu_id)
3590 {
3591 CPUState *cs;
3592
3593 CPU_FOREACH(cs) {
3594 PowerPCCPU *cpu = POWERPC_CPU(cs);
3595
3596 if (spapr_vcpu_id(cpu) == vcpu_id) {
3597 return cpu;
3598 }
3599 }
3600
3601 return NULL;
3602 }
3603
3604 static void spapr_machine_class_init(ObjectClass *oc, void *data)
3605 {
3606 MachineClass *mc = MACHINE_CLASS(oc);
3607 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
3608 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
3609 NMIClass *nc = NMI_CLASS(oc);
3610 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
3611 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
3612 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
3613 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
3614
3615 mc->desc = "pSeries Logical Partition (PAPR compliant)";
3616
3617 /*
3618 * We set up the default / latest behaviour here. The class_init
3619 * functions for the specific versioned machine types can override
3620 * these details for backwards compatibility
3621 */
3622 mc->init = ppc_spapr_init;
3623 mc->reset = ppc_spapr_reset;
3624 mc->block_default_type = IF_SCSI;
3625 mc->max_cpus = 1024;
3626 mc->no_parallel = 1;
3627 mc->default_boot_order = "";
3628 mc->default_ram_size = 512 * M_BYTE;
3629 mc->kvm_type = spapr_kvm_type;
3630 mc->has_dynamic_sysbus = true;
3631 mc->pci_allow_0_address = true;
3632 mc->get_hotplug_handler = spapr_get_hotplug_handler;
3633 hc->pre_plug = spapr_machine_device_pre_plug;
3634 hc->plug = spapr_machine_device_plug;
3635 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props;
3636 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id;
3637 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
3638 hc->unplug_request = spapr_machine_device_unplug_request;
3639
3640 smc->dr_lmb_enabled = true;
3641 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
3642 mc->has_hotpluggable_cpus = true;
3643 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
3644 fwc->get_dev_path = spapr_get_fw_dev_path;
3645 nc->nmi_monitor_handler = spapr_nmi;
3646 smc->phb_placement = spapr_phb_placement;
3647 vhc->hypercall = emulate_spapr_hypercall;
3648 vhc->hpt_mask = spapr_hpt_mask;
3649 vhc->map_hptes = spapr_map_hptes;
3650 vhc->unmap_hptes = spapr_unmap_hptes;
3651 vhc->store_hpte = spapr_store_hpte;
3652 vhc->get_patbe = spapr_get_patbe;
3653 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr;
3654 xic->ics_get = spapr_ics_get;
3655 xic->ics_resend = spapr_ics_resend;
3656 xic->icp_get = spapr_icp_get;
3657 ispc->print_info = spapr_pic_print_info;
3658 /* Force NUMA node memory size to be a multiple of
3659 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
3660 * in which LMBs are represented and hot-added
3661 */
3662 mc->numa_mem_align_shift = 28;
3663 }
3664
3665 static const TypeInfo spapr_machine_info = {
3666 .name = TYPE_SPAPR_MACHINE,
3667 .parent = TYPE_MACHINE,
3668 .abstract = true,
3669 .instance_size = sizeof(sPAPRMachineState),
3670 .instance_init = spapr_machine_initfn,
3671 .instance_finalize = spapr_machine_finalizefn,
3672 .class_size = sizeof(sPAPRMachineClass),
3673 .class_init = spapr_machine_class_init,
3674 .interfaces = (InterfaceInfo[]) {
3675 { TYPE_FW_PATH_PROVIDER },
3676 { TYPE_NMI },
3677 { TYPE_HOTPLUG_HANDLER },
3678 { TYPE_PPC_VIRTUAL_HYPERVISOR },
3679 { TYPE_XICS_FABRIC },
3680 { TYPE_INTERRUPT_STATS_PROVIDER },
3681 { }
3682 },
3683 };
3684
3685 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
3686 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
3687 void *data) \
3688 { \
3689 MachineClass *mc = MACHINE_CLASS(oc); \
3690 spapr_machine_##suffix##_class_options(mc); \
3691 if (latest) { \
3692 mc->alias = "pseries"; \
3693 mc->is_default = 1; \
3694 } \
3695 } \
3696 static void spapr_machine_##suffix##_instance_init(Object *obj) \
3697 { \
3698 MachineState *machine = MACHINE(obj); \
3699 spapr_machine_##suffix##_instance_options(machine); \
3700 } \
3701 static const TypeInfo spapr_machine_##suffix##_info = { \
3702 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
3703 .parent = TYPE_SPAPR_MACHINE, \
3704 .class_init = spapr_machine_##suffix##_class_init, \
3705 .instance_init = spapr_machine_##suffix##_instance_init, \
3706 }; \
3707 static void spapr_machine_register_##suffix(void) \
3708 { \
3709 type_register(&spapr_machine_##suffix##_info); \
3710 } \
3711 type_init(spapr_machine_register_##suffix)
3712
3713 /*
3714 * pseries-2.11
3715 */
3716 static void spapr_machine_2_11_instance_options(MachineState *machine)
3717 {
3718 }
3719
3720 static void spapr_machine_2_11_class_options(MachineClass *mc)
3721 {
3722 /* Defaults for the latest behaviour inherited from the base class */
3723 }
3724
3725 DEFINE_SPAPR_MACHINE(2_11, "2.11", true);
3726
3727 /*
3728 * pseries-2.10
3729 */
3730 #define SPAPR_COMPAT_2_10 \
3731 HW_COMPAT_2_10 \
3732
3733 static void spapr_machine_2_10_instance_options(MachineState *machine)
3734 {
3735 }
3736
3737 static void spapr_machine_2_10_class_options(MachineClass *mc)
3738 {
3739 spapr_machine_2_11_class_options(mc);
3740 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10);
3741 }
3742
3743 DEFINE_SPAPR_MACHINE(2_10, "2.10", false);
3744
3745 /*
3746 * pseries-2.9
3747 */
3748 #define SPAPR_COMPAT_2_9 \
3749 HW_COMPAT_2_9 \
3750 { \
3751 .driver = TYPE_POWERPC_CPU, \
3752 .property = "pre-2.10-migration", \
3753 .value = "on", \
3754 }, \
3755
3756 static void spapr_machine_2_9_instance_options(MachineState *machine)
3757 {
3758 spapr_machine_2_10_instance_options(machine);
3759 }
3760
3761 static void spapr_machine_2_9_class_options(MachineClass *mc)
3762 {
3763 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3764
3765 spapr_machine_2_10_class_options(mc);
3766 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9);
3767 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
3768 smc->pre_2_10_has_unused_icps = true;
3769 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED;
3770 }
3771
3772 DEFINE_SPAPR_MACHINE(2_9, "2.9", false);
3773
3774 /*
3775 * pseries-2.8
3776 */
3777 #define SPAPR_COMPAT_2_8 \
3778 HW_COMPAT_2_8 \
3779 { \
3780 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3781 .property = "pcie-extended-configuration-space", \
3782 .value = "off", \
3783 },
3784
3785 static void spapr_machine_2_8_instance_options(MachineState *machine)
3786 {
3787 spapr_machine_2_9_instance_options(machine);
3788 }
3789
3790 static void spapr_machine_2_8_class_options(MachineClass *mc)
3791 {
3792 spapr_machine_2_9_class_options(mc);
3793 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8);
3794 mc->numa_mem_align_shift = 23;
3795 }
3796
3797 DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
3798
3799 /*
3800 * pseries-2.7
3801 */
3802 #define SPAPR_COMPAT_2_7 \
3803 HW_COMPAT_2_7 \
3804 { \
3805 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3806 .property = "mem_win_size", \
3807 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
3808 }, \
3809 { \
3810 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3811 .property = "mem64_win_size", \
3812 .value = "0", \
3813 }, \
3814 { \
3815 .driver = TYPE_POWERPC_CPU, \
3816 .property = "pre-2.8-migration", \
3817 .value = "on", \
3818 }, \
3819 { \
3820 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3821 .property = "pre-2.8-migration", \
3822 .value = "on", \
3823 },
3824
3825 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index,
3826 uint64_t *buid, hwaddr *pio,
3827 hwaddr *mmio32, hwaddr *mmio64,
3828 unsigned n_dma, uint32_t *liobns, Error **errp)
3829 {
3830 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
3831 const uint64_t base_buid = 0x800000020000000ULL;
3832 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
3833 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
3834 const hwaddr pio_offset = 0x80000000; /* 2 GiB */
3835 const uint32_t max_index = 255;
3836 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */
3837
3838 uint64_t ram_top = MACHINE(spapr)->ram_size;
3839 hwaddr phb0_base, phb_base;
3840 int i;
3841
3842 /* Do we have hotpluggable memory? */
3843 if (MACHINE(spapr)->maxram_size > ram_top) {
3844 /* Can't just use maxram_size, because there may be an
3845 * alignment gap between normal and hotpluggable memory
3846 * regions */
3847 ram_top = spapr->hotplug_memory.base +
3848 memory_region_size(&spapr->hotplug_memory.mr);
3849 }
3850
3851 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
3852
3853 if (index > max_index) {
3854 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
3855 max_index);
3856 return;
3857 }
3858
3859 *buid = base_buid + index;
3860 for (i = 0; i < n_dma; ++i) {
3861 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3862 }
3863
3864 phb_base = phb0_base + index * phb_spacing;
3865 *pio = phb_base + pio_offset;
3866 *mmio32 = phb_base + mmio_offset;
3867 /*
3868 * We don't set the 64-bit MMIO window, relying on the PHB's
3869 * fallback behaviour of automatically splitting a large "32-bit"
3870 * window into contiguous 32-bit and 64-bit windows
3871 */
3872 }
3873
3874 static void spapr_machine_2_7_instance_options(MachineState *machine)
3875 {
3876 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
3877
3878 spapr_machine_2_8_instance_options(machine);
3879 spapr->use_hotplug_event_source = false;
3880 }
3881
3882 static void spapr_machine_2_7_class_options(MachineClass *mc)
3883 {
3884 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3885
3886 spapr_machine_2_8_class_options(mc);
3887 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3");
3888 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
3889 smc->phb_placement = phb_placement_2_7;
3890 }
3891
3892 DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
3893
3894 /*
3895 * pseries-2.6
3896 */
3897 #define SPAPR_COMPAT_2_6 \
3898 HW_COMPAT_2_6 \
3899 { \
3900 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
3901 .property = "ddw",\
3902 .value = stringify(off),\
3903 },
3904
3905 static void spapr_machine_2_6_instance_options(MachineState *machine)
3906 {
3907 spapr_machine_2_7_instance_options(machine);
3908 }
3909
3910 static void spapr_machine_2_6_class_options(MachineClass *mc)
3911 {
3912 spapr_machine_2_7_class_options(mc);
3913 mc->has_hotpluggable_cpus = false;
3914 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
3915 }
3916
3917 DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
3918
3919 /*
3920 * pseries-2.5
3921 */
3922 #define SPAPR_COMPAT_2_5 \
3923 HW_COMPAT_2_5 \
3924 { \
3925 .driver = "spapr-vlan", \
3926 .property = "use-rx-buffer-pools", \
3927 .value = "off", \
3928 },
3929
3930 static void spapr_machine_2_5_instance_options(MachineState *machine)
3931 {
3932 spapr_machine_2_6_instance_options(machine);
3933 }
3934
3935 static void spapr_machine_2_5_class_options(MachineClass *mc)
3936 {
3937 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3938
3939 spapr_machine_2_6_class_options(mc);
3940 smc->use_ohci_by_default = true;
3941 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
3942 }
3943
3944 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
3945
3946 /*
3947 * pseries-2.4
3948 */
3949 #define SPAPR_COMPAT_2_4 \
3950 HW_COMPAT_2_4
3951
3952 static void spapr_machine_2_4_instance_options(MachineState *machine)
3953 {
3954 spapr_machine_2_5_instance_options(machine);
3955 }
3956
3957 static void spapr_machine_2_4_class_options(MachineClass *mc)
3958 {
3959 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3960
3961 spapr_machine_2_5_class_options(mc);
3962 smc->dr_lmb_enabled = false;
3963 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
3964 }
3965
3966 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
3967
3968 /*
3969 * pseries-2.3
3970 */
3971 #define SPAPR_COMPAT_2_3 \
3972 HW_COMPAT_2_3 \
3973 {\
3974 .driver = "spapr-pci-host-bridge",\
3975 .property = "dynamic-reconfiguration",\
3976 .value = "off",\
3977 },
3978
3979 static void spapr_machine_2_3_instance_options(MachineState *machine)
3980 {
3981 spapr_machine_2_4_instance_options(machine);
3982 }
3983
3984 static void spapr_machine_2_3_class_options(MachineClass *mc)
3985 {
3986 spapr_machine_2_4_class_options(mc);
3987 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
3988 }
3989 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
3990
3991 /*
3992 * pseries-2.2
3993 */
3994
3995 #define SPAPR_COMPAT_2_2 \
3996 HW_COMPAT_2_2 \
3997 {\
3998 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
3999 .property = "mem_win_size",\
4000 .value = "0x20000000",\
4001 },
4002
4003 static void spapr_machine_2_2_instance_options(MachineState *machine)
4004 {
4005 spapr_machine_2_3_instance_options(machine);
4006 machine->suppress_vmdesc = true;
4007 }
4008
4009 static void spapr_machine_2_2_class_options(MachineClass *mc)
4010 {
4011 spapr_machine_2_3_class_options(mc);
4012 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
4013 }
4014 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
4015
4016 /*
4017 * pseries-2.1
4018 */
4019 #define SPAPR_COMPAT_2_1 \
4020 HW_COMPAT_2_1
4021
4022 static void spapr_machine_2_1_instance_options(MachineState *machine)
4023 {
4024 spapr_machine_2_2_instance_options(machine);
4025 }
4026
4027 static void spapr_machine_2_1_class_options(MachineClass *mc)
4028 {
4029 spapr_machine_2_2_class_options(mc);
4030 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
4031 }
4032 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
4033
4034 static void spapr_machine_register_types(void)
4035 {
4036 type_register_static(&spapr_machine_info);
4037 }
4038
4039 type_init(spapr_machine_register_types)
AR7 emulation for QEMU