2 * CRIS emulation for qemu: main translation routines.
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 * The condition code translation is in need of attention.
26 #include "qemu/osdep.h"
28 #include "disas/disas.h"
29 #include "exec/exec-all.h"
31 #include "exec/helper-proto.h"
33 #include "exec/cpu_ldst.h"
34 #include "exec/translator.h"
35 #include "crisv32-decode.h"
37 #include "exec/helper-gen.h"
39 #include "trace-tcg.h"
45 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
47 # define LOG_DIS(...) do { } while (0)
51 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
52 #define BUG_ON(x) ({if (x) BUG();})
54 /* is_jmp field values */
55 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
56 #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
57 #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
58 #define DISAS_SWI DISAS_TARGET_3
60 /* Used by the decoder. */
61 #define EXTRACT_FIELD(src, start, end) \
62 (((src) >> start) & ((1 << (end - start + 1)) - 1))
64 #define CC_MASK_NZ 0xc
65 #define CC_MASK_NZV 0xe
66 #define CC_MASK_NZVC 0xf
67 #define CC_MASK_RNZV 0x10e
69 static TCGv cpu_R
[16];
70 static TCGv cpu_PR
[16];
74 static TCGv cc_result
;
79 static TCGv env_btaken
;
80 static TCGv env_btarget
;
83 #include "exec/gen-icount.h"
85 /* This is the state at translation time. */
86 typedef struct DisasContext
{
91 unsigned int (*decoder
)(CPUCRISState
*env
, struct DisasContext
*dc
);
96 unsigned int zsize
, zzsize
;
110 int cc_size_uptodate
; /* -1 invalid or last written value. */
112 int cc_x_uptodate
; /* 1 - ccs, 2 - known | X_FLAG. 0 not up-to-date. */
113 int flags_uptodate
; /* Whether or not $ccs is up-to-date. */
114 int flagx_known
; /* Whether or not flags_x has the x flag known at
118 int clear_x
; /* Clear x after this insn? */
119 int clear_prefix
; /* Clear prefix after this insn? */
120 int clear_locked_irq
; /* Clear the irq lockout. */
121 int cpustate_changed
;
122 unsigned int tb_flags
; /* tb dependent flags. */
127 #define JMP_DIRECT_CC 2
128 #define JMP_INDIRECT 3
129 int jmp
; /* 0=nojmp, 1=direct, 2=indirect. */
134 struct TranslationBlock
*tb
;
135 int singlestep_enabled
;
138 static void gen_BUG(DisasContext
*dc
, const char *file
, int line
)
140 fprintf(stderr
, "BUG: pc=%x %s %d\n", dc
->pc
, file
, line
);
141 if (qemu_log_separate()) {
142 qemu_log("BUG: pc=%x %s %d\n", dc
->pc
, file
, line
);
144 cpu_abort(CPU(dc
->cpu
), "%s:%d\n", file
, line
);
147 static const char *regnames_v32
[] =
149 "$r0", "$r1", "$r2", "$r3",
150 "$r4", "$r5", "$r6", "$r7",
151 "$r8", "$r9", "$r10", "$r11",
152 "$r12", "$r13", "$sp", "$acr",
154 static const char *pregnames_v32
[] =
156 "$bz", "$vr", "$pid", "$srs",
157 "$wz", "$exs", "$eda", "$mof",
158 "$dz", "$ebp", "$erp", "$srp",
159 "$nrp", "$ccs", "$usp", "$spc",
162 /* We need this table to handle preg-moves with implicit width. */
163 static int preg_sizes
[] = {
174 #define t_gen_mov_TN_env(tn, member) \
175 tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member))
176 #define t_gen_mov_env_TN(member, tn) \
177 tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member))
179 static inline void t_gen_mov_TN_preg(TCGv tn
, int r
)
181 assert(r
>= 0 && r
<= 15);
182 if (r
== PR_BZ
|| r
== PR_WZ
|| r
== PR_DZ
) {
183 tcg_gen_mov_tl(tn
, tcg_const_tl(0));
184 } else if (r
== PR_VR
) {
185 tcg_gen_mov_tl(tn
, tcg_const_tl(32));
187 tcg_gen_mov_tl(tn
, cpu_PR
[r
]);
190 static inline void t_gen_mov_preg_TN(DisasContext
*dc
, int r
, TCGv tn
)
192 assert(r
>= 0 && r
<= 15);
193 if (r
== PR_BZ
|| r
== PR_WZ
|| r
== PR_DZ
) {
195 } else if (r
== PR_SRS
) {
196 tcg_gen_andi_tl(cpu_PR
[r
], tn
, 3);
199 gen_helper_tlb_flush_pid(cpu_env
, tn
);
201 if (dc
->tb_flags
& S_FLAG
&& r
== PR_SPC
) {
202 gen_helper_spc_write(cpu_env
, tn
);
203 } else if (r
== PR_CCS
) {
204 dc
->cpustate_changed
= 1;
206 tcg_gen_mov_tl(cpu_PR
[r
], tn
);
210 /* Sign extend at translation time. */
211 static int sign_extend(unsigned int val
, unsigned int width
)
223 static int cris_fetch(CPUCRISState
*env
, DisasContext
*dc
, uint32_t addr
,
224 unsigned int size
, unsigned int sign
)
231 r
= cpu_ldl_code(env
, addr
);
237 r
= cpu_ldsw_code(env
, addr
);
239 r
= cpu_lduw_code(env
, addr
);
246 r
= cpu_ldsb_code(env
, addr
);
248 r
= cpu_ldub_code(env
, addr
);
253 cpu_abort(CPU(dc
->cpu
), "Invalid fetch size %d\n", size
);
259 static void cris_lock_irq(DisasContext
*dc
)
261 dc
->clear_locked_irq
= 0;
262 t_gen_mov_env_TN(locked_irq
, tcg_const_tl(1));
265 static inline void t_gen_raise_exception(uint32_t index
)
267 TCGv_i32 tmp
= tcg_const_i32(index
);
268 gen_helper_raise_exception(cpu_env
, tmp
);
269 tcg_temp_free_i32(tmp
);
272 static void t_gen_lsl(TCGv d
, TCGv a
, TCGv b
)
277 t_31
= tcg_const_tl(31);
278 tcg_gen_shl_tl(d
, a
, b
);
280 tcg_gen_sub_tl(t0
, t_31
, b
);
281 tcg_gen_sar_tl(t0
, t0
, t_31
);
282 tcg_gen_and_tl(t0
, t0
, d
);
283 tcg_gen_xor_tl(d
, d
, t0
);
288 static void t_gen_lsr(TCGv d
, TCGv a
, TCGv b
)
293 t_31
= tcg_temp_new();
294 tcg_gen_shr_tl(d
, a
, b
);
296 tcg_gen_movi_tl(t_31
, 31);
297 tcg_gen_sub_tl(t0
, t_31
, b
);
298 tcg_gen_sar_tl(t0
, t0
, t_31
);
299 tcg_gen_and_tl(t0
, t0
, d
);
300 tcg_gen_xor_tl(d
, d
, t0
);
305 static void t_gen_asr(TCGv d
, TCGv a
, TCGv b
)
310 t_31
= tcg_temp_new();
311 tcg_gen_sar_tl(d
, a
, b
);
313 tcg_gen_movi_tl(t_31
, 31);
314 tcg_gen_sub_tl(t0
, t_31
, b
);
315 tcg_gen_sar_tl(t0
, t0
, t_31
);
316 tcg_gen_or_tl(d
, d
, t0
);
321 static void t_gen_cris_dstep(TCGv d
, TCGv a
, TCGv b
)
323 TCGv t
= tcg_temp_new();
330 tcg_gen_shli_tl(d
, a
, 1);
331 tcg_gen_sub_tl(t
, d
, b
);
332 tcg_gen_movcond_tl(TCG_COND_GEU
, d
, d
, b
, t
, d
);
336 static void t_gen_cris_mstep(TCGv d
, TCGv a
, TCGv b
, TCGv ccs
)
346 tcg_gen_shli_tl(d
, a
, 1);
347 tcg_gen_shli_tl(t
, ccs
, 31 - 3);
348 tcg_gen_sari_tl(t
, t
, 31);
349 tcg_gen_and_tl(t
, t
, b
);
350 tcg_gen_add_tl(d
, d
, t
);
354 /* Extended arithmetics on CRIS. */
355 static inline void t_gen_add_flag(TCGv d
, int flag
)
360 t_gen_mov_TN_preg(c
, PR_CCS
);
361 /* Propagate carry into d. */
362 tcg_gen_andi_tl(c
, c
, 1 << flag
);
364 tcg_gen_shri_tl(c
, c
, flag
);
366 tcg_gen_add_tl(d
, d
, c
);
370 static inline void t_gen_addx_carry(DisasContext
*dc
, TCGv d
)
372 if (dc
->flagx_known
) {
377 t_gen_mov_TN_preg(c
, PR_CCS
);
378 /* C flag is already at bit 0. */
379 tcg_gen_andi_tl(c
, c
, C_FLAG
);
380 tcg_gen_add_tl(d
, d
, c
);
388 t_gen_mov_TN_preg(x
, PR_CCS
);
389 tcg_gen_mov_tl(c
, x
);
391 /* Propagate carry into d if X is set. Branch free. */
392 tcg_gen_andi_tl(c
, c
, C_FLAG
);
393 tcg_gen_andi_tl(x
, x
, X_FLAG
);
394 tcg_gen_shri_tl(x
, x
, 4);
396 tcg_gen_and_tl(x
, x
, c
);
397 tcg_gen_add_tl(d
, d
, x
);
403 static inline void t_gen_subx_carry(DisasContext
*dc
, TCGv d
)
405 if (dc
->flagx_known
) {
410 t_gen_mov_TN_preg(c
, PR_CCS
);
411 /* C flag is already at bit 0. */
412 tcg_gen_andi_tl(c
, c
, C_FLAG
);
413 tcg_gen_sub_tl(d
, d
, c
);
421 t_gen_mov_TN_preg(x
, PR_CCS
);
422 tcg_gen_mov_tl(c
, x
);
424 /* Propagate carry into d if X is set. Branch free. */
425 tcg_gen_andi_tl(c
, c
, C_FLAG
);
426 tcg_gen_andi_tl(x
, x
, X_FLAG
);
427 tcg_gen_shri_tl(x
, x
, 4);
429 tcg_gen_and_tl(x
, x
, c
);
430 tcg_gen_sub_tl(d
, d
, x
);
436 /* Swap the two bytes within each half word of the s operand.
437 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
438 static inline void t_gen_swapb(TCGv d
, TCGv s
)
443 org_s
= tcg_temp_new();
445 /* d and s may refer to the same object. */
446 tcg_gen_mov_tl(org_s
, s
);
447 tcg_gen_shli_tl(t
, org_s
, 8);
448 tcg_gen_andi_tl(d
, t
, 0xff00ff00);
449 tcg_gen_shri_tl(t
, org_s
, 8);
450 tcg_gen_andi_tl(t
, t
, 0x00ff00ff);
451 tcg_gen_or_tl(d
, d
, t
);
453 tcg_temp_free(org_s
);
456 /* Swap the halfwords of the s operand. */
457 static inline void t_gen_swapw(TCGv d
, TCGv s
)
460 /* d and s refer the same object. */
462 tcg_gen_mov_tl(t
, s
);
463 tcg_gen_shli_tl(d
, t
, 16);
464 tcg_gen_shri_tl(t
, t
, 16);
465 tcg_gen_or_tl(d
, d
, t
);
469 /* Reverse the within each byte.
470 T0 = (((T0 << 7) & 0x80808080) |
471 ((T0 << 5) & 0x40404040) |
472 ((T0 << 3) & 0x20202020) |
473 ((T0 << 1) & 0x10101010) |
474 ((T0 >> 1) & 0x08080808) |
475 ((T0 >> 3) & 0x04040404) |
476 ((T0 >> 5) & 0x02020202) |
477 ((T0 >> 7) & 0x01010101));
479 static inline void t_gen_swapr(TCGv d
, TCGv s
)
482 int shift
; /* LSL when positive, LSR when negative. */
497 /* d and s refer the same object. */
499 org_s
= tcg_temp_new();
500 tcg_gen_mov_tl(org_s
, s
);
502 tcg_gen_shli_tl(t
, org_s
, bitrev
[0].shift
);
503 tcg_gen_andi_tl(d
, t
, bitrev
[0].mask
);
504 for (i
= 1; i
< ARRAY_SIZE(bitrev
); i
++) {
505 if (bitrev
[i
].shift
>= 0) {
506 tcg_gen_shli_tl(t
, org_s
, bitrev
[i
].shift
);
508 tcg_gen_shri_tl(t
, org_s
, -bitrev
[i
].shift
);
510 tcg_gen_andi_tl(t
, t
, bitrev
[i
].mask
);
511 tcg_gen_or_tl(d
, d
, t
);
514 tcg_temp_free(org_s
);
517 static void t_gen_cc_jmp(TCGv pc_true
, TCGv pc_false
)
519 TCGLabel
*l1
= gen_new_label();
521 /* Conditional jmp. */
522 tcg_gen_mov_tl(env_pc
, pc_false
);
523 tcg_gen_brcondi_tl(TCG_COND_EQ
, env_btaken
, 0, l1
);
524 tcg_gen_mov_tl(env_pc
, pc_true
);
528 static inline bool use_goto_tb(DisasContext
*dc
, target_ulong dest
)
530 #ifndef CONFIG_USER_ONLY
531 return (dc
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) ||
532 (dc
->ppc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
538 static void gen_goto_tb(DisasContext
*dc
, int n
, target_ulong dest
)
540 if (use_goto_tb(dc
, dest
)) {
542 tcg_gen_movi_tl(env_pc
, dest
);
543 tcg_gen_exit_tb((uintptr_t)dc
->tb
+ n
);
545 tcg_gen_movi_tl(env_pc
, dest
);
550 static inline void cris_clear_x_flag(DisasContext
*dc
)
552 if (dc
->flagx_known
&& dc
->flags_x
) {
553 dc
->flags_uptodate
= 0;
560 static void cris_flush_cc_state(DisasContext
*dc
)
562 if (dc
->cc_size_uptodate
!= dc
->cc_size
) {
563 tcg_gen_movi_tl(cc_size
, dc
->cc_size
);
564 dc
->cc_size_uptodate
= dc
->cc_size
;
566 tcg_gen_movi_tl(cc_op
, dc
->cc_op
);
567 tcg_gen_movi_tl(cc_mask
, dc
->cc_mask
);
570 static void cris_evaluate_flags(DisasContext
*dc
)
572 if (dc
->flags_uptodate
) {
576 cris_flush_cc_state(dc
);
580 gen_helper_evaluate_flags_mcp(cpu_PR
[PR_CCS
], cpu_env
,
581 cpu_PR
[PR_CCS
], cc_src
,
585 gen_helper_evaluate_flags_muls(cpu_PR
[PR_CCS
], cpu_env
,
586 cpu_PR
[PR_CCS
], cc_result
,
590 gen_helper_evaluate_flags_mulu(cpu_PR
[PR_CCS
], cpu_env
,
591 cpu_PR
[PR_CCS
], cc_result
,
601 switch (dc
->cc_size
) {
603 gen_helper_evaluate_flags_move_4(cpu_PR
[PR_CCS
],
604 cpu_env
, cpu_PR
[PR_CCS
], cc_result
);
607 gen_helper_evaluate_flags_move_2(cpu_PR
[PR_CCS
],
608 cpu_env
, cpu_PR
[PR_CCS
], cc_result
);
611 gen_helper_evaluate_flags(cpu_env
);
620 if (dc
->cc_size
== 4) {
621 gen_helper_evaluate_flags_sub_4(cpu_PR
[PR_CCS
], cpu_env
,
622 cpu_PR
[PR_CCS
], cc_src
, cc_dest
, cc_result
);
624 gen_helper_evaluate_flags(cpu_env
);
629 switch (dc
->cc_size
) {
631 gen_helper_evaluate_flags_alu_4(cpu_PR
[PR_CCS
], cpu_env
,
632 cpu_PR
[PR_CCS
], cc_src
, cc_dest
, cc_result
);
635 gen_helper_evaluate_flags(cpu_env
);
641 if (dc
->flagx_known
) {
643 tcg_gen_ori_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], X_FLAG
);
644 } else if (dc
->cc_op
== CC_OP_FLAGS
) {
645 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~X_FLAG
);
648 dc
->flags_uptodate
= 1;
651 static void cris_cc_mask(DisasContext
*dc
, unsigned int mask
)
660 /* Check if we need to evaluate the condition codes due to
662 ovl
= (dc
->cc_mask
^ mask
) & ~mask
;
664 /* TODO: optimize this case. It trigs all the time. */
665 cris_evaluate_flags(dc
);
671 static void cris_update_cc_op(DisasContext
*dc
, int op
, int size
)
675 dc
->flags_uptodate
= 0;
678 static inline void cris_update_cc_x(DisasContext
*dc
)
680 /* Save the x flag state at the time of the cc snapshot. */
681 if (dc
->flagx_known
) {
682 if (dc
->cc_x_uptodate
== (2 | dc
->flags_x
)) {
685 tcg_gen_movi_tl(cc_x
, dc
->flags_x
);
686 dc
->cc_x_uptodate
= 2 | dc
->flags_x
;
688 tcg_gen_andi_tl(cc_x
, cpu_PR
[PR_CCS
], X_FLAG
);
689 dc
->cc_x_uptodate
= 1;
693 /* Update cc prior to executing ALU op. Needs source operands untouched. */
694 static void cris_pre_alu_update_cc(DisasContext
*dc
, int op
,
695 TCGv dst
, TCGv src
, int size
)
698 cris_update_cc_op(dc
, op
, size
);
699 tcg_gen_mov_tl(cc_src
, src
);
707 && op
!= CC_OP_LSL
) {
708 tcg_gen_mov_tl(cc_dest
, dst
);
711 cris_update_cc_x(dc
);
715 /* Update cc after executing ALU op. needs the result. */
716 static inline void cris_update_result(DisasContext
*dc
, TCGv res
)
719 tcg_gen_mov_tl(cc_result
, res
);
723 /* Returns one if the write back stage should execute. */
724 static void cris_alu_op_exec(DisasContext
*dc
, int op
,
725 TCGv dst
, TCGv a
, TCGv b
, int size
)
727 /* Emit the ALU insns. */
730 tcg_gen_add_tl(dst
, a
, b
);
731 /* Extended arithmetics. */
732 t_gen_addx_carry(dc
, dst
);
735 tcg_gen_add_tl(dst
, a
, b
);
736 t_gen_add_flag(dst
, 0); /* C_FLAG. */
739 tcg_gen_add_tl(dst
, a
, b
);
740 t_gen_add_flag(dst
, 8); /* R_FLAG. */
743 tcg_gen_sub_tl(dst
, a
, b
);
744 /* Extended arithmetics. */
745 t_gen_subx_carry(dc
, dst
);
748 tcg_gen_mov_tl(dst
, b
);
751 tcg_gen_or_tl(dst
, a
, b
);
754 tcg_gen_and_tl(dst
, a
, b
);
757 tcg_gen_xor_tl(dst
, a
, b
);
760 t_gen_lsl(dst
, a
, b
);
763 t_gen_lsr(dst
, a
, b
);
766 t_gen_asr(dst
, a
, b
);
769 tcg_gen_neg_tl(dst
, b
);
770 /* Extended arithmetics. */
771 t_gen_subx_carry(dc
, dst
);
774 tcg_gen_clzi_tl(dst
, b
, TARGET_LONG_BITS
);
777 tcg_gen_muls2_tl(dst
, cpu_PR
[PR_MOF
], a
, b
);
780 tcg_gen_mulu2_tl(dst
, cpu_PR
[PR_MOF
], a
, b
);
783 t_gen_cris_dstep(dst
, a
, b
);
786 t_gen_cris_mstep(dst
, a
, b
, cpu_PR
[PR_CCS
]);
789 tcg_gen_movcond_tl(TCG_COND_LEU
, dst
, a
, b
, a
, b
);
792 tcg_gen_sub_tl(dst
, a
, b
);
793 /* Extended arithmetics. */
794 t_gen_subx_carry(dc
, dst
);
797 qemu_log_mask(LOG_GUEST_ERROR
, "illegal ALU op.\n");
803 tcg_gen_andi_tl(dst
, dst
, 0xff);
804 } else if (size
== 2) {
805 tcg_gen_andi_tl(dst
, dst
, 0xffff);
809 static void cris_alu(DisasContext
*dc
, int op
,
810 TCGv d
, TCGv op_a
, TCGv op_b
, int size
)
817 if (op
== CC_OP_CMP
) {
818 tmp
= tcg_temp_new();
820 } else if (size
== 4) {
824 tmp
= tcg_temp_new();
828 cris_pre_alu_update_cc(dc
, op
, op_a
, op_b
, size
);
829 cris_alu_op_exec(dc
, op
, tmp
, op_a
, op_b
, size
);
830 cris_update_result(dc
, tmp
);
835 tcg_gen_andi_tl(d
, d
, ~0xff);
837 tcg_gen_andi_tl(d
, d
, ~0xffff);
839 tcg_gen_or_tl(d
, d
, tmp
);
846 static int arith_cc(DisasContext
*dc
)
850 case CC_OP_ADDC
: return 1;
851 case CC_OP_ADD
: return 1;
852 case CC_OP_SUB
: return 1;
853 case CC_OP_DSTEP
: return 1;
854 case CC_OP_LSL
: return 1;
855 case CC_OP_LSR
: return 1;
856 case CC_OP_ASR
: return 1;
857 case CC_OP_CMP
: return 1;
858 case CC_OP_NEG
: return 1;
859 case CC_OP_OR
: return 1;
860 case CC_OP_AND
: return 1;
861 case CC_OP_XOR
: return 1;
862 case CC_OP_MULU
: return 1;
863 case CC_OP_MULS
: return 1;
871 static void gen_tst_cc (DisasContext
*dc
, TCGv cc
, int cond
)
873 int arith_opt
, move_opt
;
875 /* TODO: optimize more condition codes. */
878 * If the flags are live, we've gotta look into the bits of CCS.
879 * Otherwise, if we just did an arithmetic operation we try to
880 * evaluate the condition code faster.
882 * When this function is done, T0 should be non-zero if the condition
885 arith_opt
= arith_cc(dc
) && !dc
->flags_uptodate
;
886 move_opt
= (dc
->cc_op
== CC_OP_MOVE
);
889 if ((arith_opt
|| move_opt
)
890 && dc
->cc_x_uptodate
!= (2 | X_FLAG
)) {
891 tcg_gen_setcond_tl(TCG_COND_EQ
, cc
,
892 cc_result
, tcg_const_tl(0));
894 cris_evaluate_flags(dc
);
896 cpu_PR
[PR_CCS
], Z_FLAG
);
900 if ((arith_opt
|| move_opt
)
901 && dc
->cc_x_uptodate
!= (2 | X_FLAG
)) {
902 tcg_gen_mov_tl(cc
, cc_result
);
904 cris_evaluate_flags(dc
);
905 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
],
907 tcg_gen_andi_tl(cc
, cc
, Z_FLAG
);
911 cris_evaluate_flags(dc
);
912 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
], C_FLAG
);
915 cris_evaluate_flags(dc
);
916 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
], C_FLAG
);
917 tcg_gen_andi_tl(cc
, cc
, C_FLAG
);
920 cris_evaluate_flags(dc
);
921 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
], V_FLAG
);
924 cris_evaluate_flags(dc
);
925 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
],
927 tcg_gen_andi_tl(cc
, cc
, V_FLAG
);
930 if (arith_opt
|| move_opt
) {
933 if (dc
->cc_size
== 1) {
935 } else if (dc
->cc_size
== 2) {
939 tcg_gen_shri_tl(cc
, cc_result
, bits
);
940 tcg_gen_xori_tl(cc
, cc
, 1);
942 cris_evaluate_flags(dc
);
943 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
],
945 tcg_gen_andi_tl(cc
, cc
, N_FLAG
);
949 if (arith_opt
|| move_opt
) {
952 if (dc
->cc_size
== 1) {
954 } else if (dc
->cc_size
== 2) {
958 tcg_gen_shri_tl(cc
, cc_result
, bits
);
959 tcg_gen_andi_tl(cc
, cc
, 1);
961 cris_evaluate_flags(dc
);
962 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
],
967 cris_evaluate_flags(dc
);
968 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
],
972 cris_evaluate_flags(dc
);
976 tmp
= tcg_temp_new();
977 tcg_gen_xori_tl(tmp
, cpu_PR
[PR_CCS
],
979 /* Overlay the C flag on top of the Z. */
980 tcg_gen_shli_tl(cc
, tmp
, 2);
981 tcg_gen_and_tl(cc
, tmp
, cc
);
982 tcg_gen_andi_tl(cc
, cc
, Z_FLAG
);
988 cris_evaluate_flags(dc
);
989 /* Overlay the V flag on top of the N. */
990 tcg_gen_shli_tl(cc
, cpu_PR
[PR_CCS
], 2);
993 tcg_gen_andi_tl(cc
, cc
, N_FLAG
);
994 tcg_gen_xori_tl(cc
, cc
, N_FLAG
);
997 cris_evaluate_flags(dc
);
998 /* Overlay the V flag on top of the N. */
999 tcg_gen_shli_tl(cc
, cpu_PR
[PR_CCS
], 2);
1001 cpu_PR
[PR_CCS
], cc
);
1002 tcg_gen_andi_tl(cc
, cc
, N_FLAG
);
1005 cris_evaluate_flags(dc
);
1012 /* To avoid a shift we overlay everything on
1014 tcg_gen_shri_tl(n
, cpu_PR
[PR_CCS
], 2);
1015 tcg_gen_shri_tl(z
, cpu_PR
[PR_CCS
], 1);
1017 tcg_gen_xori_tl(z
, z
, 2);
1019 tcg_gen_xor_tl(n
, n
, cpu_PR
[PR_CCS
]);
1020 tcg_gen_xori_tl(n
, n
, 2);
1021 tcg_gen_and_tl(cc
, z
, n
);
1022 tcg_gen_andi_tl(cc
, cc
, 2);
1029 cris_evaluate_flags(dc
);
1036 /* To avoid a shift we overlay everything on
1038 tcg_gen_shri_tl(n
, cpu_PR
[PR_CCS
], 2);
1039 tcg_gen_shri_tl(z
, cpu_PR
[PR_CCS
], 1);
1041 tcg_gen_xor_tl(n
, n
, cpu_PR
[PR_CCS
]);
1042 tcg_gen_or_tl(cc
, z
, n
);
1043 tcg_gen_andi_tl(cc
, cc
, 2);
1050 cris_evaluate_flags(dc
);
1051 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
], P_FLAG
);
1054 tcg_gen_movi_tl(cc
, 1);
1062 static void cris_store_direct_jmp(DisasContext
*dc
)
1064 /* Store the direct jmp state into the cpu-state. */
1065 if (dc
->jmp
== JMP_DIRECT
|| dc
->jmp
== JMP_DIRECT_CC
) {
1066 if (dc
->jmp
== JMP_DIRECT
) {
1067 tcg_gen_movi_tl(env_btaken
, 1);
1069 tcg_gen_movi_tl(env_btarget
, dc
->jmp_pc
);
1070 dc
->jmp
= JMP_INDIRECT
;
1074 static void cris_prepare_cc_branch (DisasContext
*dc
,
1075 int offset
, int cond
)
1077 /* This helps us re-schedule the micro-code to insns in delay-slots
1078 before the actual jump. */
1079 dc
->delayed_branch
= 2;
1080 dc
->jmp
= JMP_DIRECT_CC
;
1081 dc
->jmp_pc
= dc
->pc
+ offset
;
1083 gen_tst_cc(dc
, env_btaken
, cond
);
1084 tcg_gen_movi_tl(env_btarget
, dc
->jmp_pc
);
1088 /* jumps, when the dest is in a live reg for example. Direct should be set
1089 when the dest addr is constant to allow tb chaining. */
1090 static inline void cris_prepare_jmp (DisasContext
*dc
, unsigned int type
)
1092 /* This helps us re-schedule the micro-code to insns in delay-slots
1093 before the actual jump. */
1094 dc
->delayed_branch
= 2;
1096 if (type
== JMP_INDIRECT
) {
1097 tcg_gen_movi_tl(env_btaken
, 1);
1101 static void gen_load64(DisasContext
*dc
, TCGv_i64 dst
, TCGv addr
)
1103 int mem_index
= cpu_mmu_index(&dc
->cpu
->env
, false);
1105 /* If we get a fault on a delayslot we must keep the jmp state in
1106 the cpu-state to be able to re-execute the jmp. */
1107 if (dc
->delayed_branch
== 1) {
1108 cris_store_direct_jmp(dc
);
1111 tcg_gen_qemu_ld_i64(dst
, addr
, mem_index
, MO_TEQ
);
1114 static void gen_load(DisasContext
*dc
, TCGv dst
, TCGv addr
,
1115 unsigned int size
, int sign
)
1117 int mem_index
= cpu_mmu_index(&dc
->cpu
->env
, false);
1119 /* If we get a fault on a delayslot we must keep the jmp state in
1120 the cpu-state to be able to re-execute the jmp. */
1121 if (dc
->delayed_branch
== 1) {
1122 cris_store_direct_jmp(dc
);
1125 tcg_gen_qemu_ld_tl(dst
, addr
, mem_index
,
1126 MO_TE
+ ctz32(size
) + (sign
? MO_SIGN
: 0));
1129 static void gen_store (DisasContext
*dc
, TCGv addr
, TCGv val
,
1132 int mem_index
= cpu_mmu_index(&dc
->cpu
->env
, false);
1134 /* If we get a fault on a delayslot we must keep the jmp state in
1135 the cpu-state to be able to re-execute the jmp. */
1136 if (dc
->delayed_branch
== 1) {
1137 cris_store_direct_jmp(dc
);
1141 /* Conditional writes. We only support the kind were X and P are known
1142 at translation time. */
1143 if (dc
->flagx_known
&& dc
->flags_x
&& (dc
->tb_flags
& P_FLAG
)) {
1145 cris_evaluate_flags(dc
);
1146 tcg_gen_ori_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], C_FLAG
);
1150 tcg_gen_qemu_st_tl(val
, addr
, mem_index
, MO_TE
+ ctz32(size
));
1152 if (dc
->flagx_known
&& dc
->flags_x
) {
1153 cris_evaluate_flags(dc
);
1154 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~C_FLAG
);
1158 static inline void t_gen_sext(TCGv d
, TCGv s
, int size
)
1161 tcg_gen_ext8s_i32(d
, s
);
1162 } else if (size
== 2) {
1163 tcg_gen_ext16s_i32(d
, s
);
1165 tcg_gen_mov_tl(d
, s
);
1169 static inline void t_gen_zext(TCGv d
, TCGv s
, int size
)
1172 tcg_gen_ext8u_i32(d
, s
);
1173 } else if (size
== 2) {
1174 tcg_gen_ext16u_i32(d
, s
);
1176 tcg_gen_mov_tl(d
, s
);
1181 static char memsize_char(int size
)
1184 case 1: return 'b'; break;
1185 case 2: return 'w'; break;
1186 case 4: return 'd'; break;
1194 static inline unsigned int memsize_z(DisasContext
*dc
)
1196 return dc
->zsize
+ 1;
1199 static inline unsigned int memsize_zz(DisasContext
*dc
)
1201 switch (dc
->zzsize
) {
1209 static inline void do_postinc (DisasContext
*dc
, int size
)
1212 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], size
);
1216 static inline void dec_prep_move_r(DisasContext
*dc
, int rs
, int rd
,
1217 int size
, int s_ext
, TCGv dst
)
1220 t_gen_sext(dst
, cpu_R
[rs
], size
);
1222 t_gen_zext(dst
, cpu_R
[rs
], size
);
1226 /* Prepare T0 and T1 for a register alu operation.
1227 s_ext decides if the operand1 should be sign-extended or zero-extended when
1229 static void dec_prep_alu_r(DisasContext
*dc
, int rs
, int rd
,
1230 int size
, int s_ext
, TCGv dst
, TCGv src
)
1232 dec_prep_move_r(dc
, rs
, rd
, size
, s_ext
, src
);
1235 t_gen_sext(dst
, cpu_R
[rd
], size
);
1237 t_gen_zext(dst
, cpu_R
[rd
], size
);
1241 static int dec_prep_move_m(CPUCRISState
*env
, DisasContext
*dc
,
1242 int s_ext
, int memsize
, TCGv dst
)
1250 is_imm
= rs
== 15 && dc
->postinc
;
1252 /* Load [$rs] onto T1. */
1254 insn_len
= 2 + memsize
;
1259 imm
= cris_fetch(env
, dc
, dc
->pc
+ 2, memsize
, s_ext
);
1260 tcg_gen_movi_tl(dst
, imm
);
1263 cris_flush_cc_state(dc
);
1264 gen_load(dc
, dst
, cpu_R
[rs
], memsize
, 0);
1266 t_gen_sext(dst
, dst
, memsize
);
1268 t_gen_zext(dst
, dst
, memsize
);
1274 /* Prepare T0 and T1 for a memory + alu operation.
1275 s_ext decides if the operand1 should be sign-extended or zero-extended when
1277 static int dec_prep_alu_m(CPUCRISState
*env
, DisasContext
*dc
,
1278 int s_ext
, int memsize
, TCGv dst
, TCGv src
)
1282 insn_len
= dec_prep_move_m(env
, dc
, s_ext
, memsize
, src
);
1283 tcg_gen_mov_tl(dst
, cpu_R
[dc
->op2
]);
1288 static const char *cc_name(int cc
)
1290 static const char *cc_names
[16] = {
1291 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1292 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1295 return cc_names
[cc
];
1299 /* Start of insn decoders. */
1301 static int dec_bccq(CPUCRISState
*env
, DisasContext
*dc
)
1305 uint32_t cond
= dc
->op2
;
1307 offset
= EXTRACT_FIELD(dc
->ir
, 1, 7);
1308 sign
= EXTRACT_FIELD(dc
->ir
, 0, 0);
1311 offset
|= sign
<< 8;
1312 offset
= sign_extend(offset
, 8);
1314 LOG_DIS("b%s %x\n", cc_name(cond
), dc
->pc
+ offset
);
1316 /* op2 holds the condition-code. */
1317 cris_cc_mask(dc
, 0);
1318 cris_prepare_cc_branch(dc
, offset
, cond
);
1321 static int dec_addoq(CPUCRISState
*env
, DisasContext
*dc
)
1325 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 7);
1326 imm
= sign_extend(dc
->op1
, 7);
1328 LOG_DIS("addoq %d, $r%u\n", imm
, dc
->op2
);
1329 cris_cc_mask(dc
, 0);
1330 /* Fetch register operand, */
1331 tcg_gen_addi_tl(cpu_R
[R_ACR
], cpu_R
[dc
->op2
], imm
);
1335 static int dec_addq(CPUCRISState
*env
, DisasContext
*dc
)
1337 LOG_DIS("addq %u, $r%u\n", dc
->op1
, dc
->op2
);
1339 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1341 cris_cc_mask(dc
, CC_MASK_NZVC
);
1343 cris_alu(dc
, CC_OP_ADD
,
1344 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(dc
->op1
), 4);
1347 static int dec_moveq(CPUCRISState
*env
, DisasContext
*dc
)
1351 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1352 imm
= sign_extend(dc
->op1
, 5);
1353 LOG_DIS("moveq %d, $r%u\n", imm
, dc
->op2
);
1355 tcg_gen_movi_tl(cpu_R
[dc
->op2
], imm
);
1358 static int dec_subq(CPUCRISState
*env
, DisasContext
*dc
)
1360 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1362 LOG_DIS("subq %u, $r%u\n", dc
->op1
, dc
->op2
);
1364 cris_cc_mask(dc
, CC_MASK_NZVC
);
1365 cris_alu(dc
, CC_OP_SUB
,
1366 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(dc
->op1
), 4);
1369 static int dec_cmpq(CPUCRISState
*env
, DisasContext
*dc
)
1372 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1373 imm
= sign_extend(dc
->op1
, 5);
1375 LOG_DIS("cmpq %d, $r%d\n", imm
, dc
->op2
);
1376 cris_cc_mask(dc
, CC_MASK_NZVC
);
1378 cris_alu(dc
, CC_OP_CMP
,
1379 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(imm
), 4);
1382 static int dec_andq(CPUCRISState
*env
, DisasContext
*dc
)
1385 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1386 imm
= sign_extend(dc
->op1
, 5);
1388 LOG_DIS("andq %d, $r%d\n", imm
, dc
->op2
);
1389 cris_cc_mask(dc
, CC_MASK_NZ
);
1391 cris_alu(dc
, CC_OP_AND
,
1392 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(imm
), 4);
1395 static int dec_orq(CPUCRISState
*env
, DisasContext
*dc
)
1398 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1399 imm
= sign_extend(dc
->op1
, 5);
1400 LOG_DIS("orq %d, $r%d\n", imm
, dc
->op2
);
1401 cris_cc_mask(dc
, CC_MASK_NZ
);
1403 cris_alu(dc
, CC_OP_OR
,
1404 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(imm
), 4);
1407 static int dec_btstq(CPUCRISState
*env
, DisasContext
*dc
)
1409 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1410 LOG_DIS("btstq %u, $r%d\n", dc
->op1
, dc
->op2
);
1412 cris_cc_mask(dc
, CC_MASK_NZ
);
1413 cris_evaluate_flags(dc
);
1414 gen_helper_btst(cpu_PR
[PR_CCS
], cpu_env
, cpu_R
[dc
->op2
],
1415 tcg_const_tl(dc
->op1
), cpu_PR
[PR_CCS
]);
1416 cris_alu(dc
, CC_OP_MOVE
,
1417 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1418 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
1419 dc
->flags_uptodate
= 1;
1422 static int dec_asrq(CPUCRISState
*env
, DisasContext
*dc
)
1424 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1425 LOG_DIS("asrq %u, $r%d\n", dc
->op1
, dc
->op2
);
1426 cris_cc_mask(dc
, CC_MASK_NZ
);
1428 tcg_gen_sari_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], dc
->op1
);
1429 cris_alu(dc
, CC_OP_MOVE
,
1431 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1434 static int dec_lslq(CPUCRISState
*env
, DisasContext
*dc
)
1436 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1437 LOG_DIS("lslq %u, $r%d\n", dc
->op1
, dc
->op2
);
1439 cris_cc_mask(dc
, CC_MASK_NZ
);
1441 tcg_gen_shli_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], dc
->op1
);
1443 cris_alu(dc
, CC_OP_MOVE
,
1445 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1448 static int dec_lsrq(CPUCRISState
*env
, DisasContext
*dc
)
1450 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1451 LOG_DIS("lsrq %u, $r%d\n", dc
->op1
, dc
->op2
);
1453 cris_cc_mask(dc
, CC_MASK_NZ
);
1455 tcg_gen_shri_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], dc
->op1
);
1456 cris_alu(dc
, CC_OP_MOVE
,
1458 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1462 static int dec_move_r(CPUCRISState
*env
, DisasContext
*dc
)
1464 int size
= memsize_zz(dc
);
1466 LOG_DIS("move.%c $r%u, $r%u\n",
1467 memsize_char(size
), dc
->op1
, dc
->op2
);
1469 cris_cc_mask(dc
, CC_MASK_NZ
);
1471 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, cpu_R
[dc
->op2
]);
1472 cris_cc_mask(dc
, CC_MASK_NZ
);
1473 cris_update_cc_op(dc
, CC_OP_MOVE
, 4);
1474 cris_update_cc_x(dc
);
1475 cris_update_result(dc
, cpu_R
[dc
->op2
]);
1479 t0
= tcg_temp_new();
1480 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t0
);
1481 cris_alu(dc
, CC_OP_MOVE
,
1483 cpu_R
[dc
->op2
], t0
, size
);
1489 static int dec_scc_r(CPUCRISState
*env
, DisasContext
*dc
)
1493 LOG_DIS("s%s $r%u\n",
1494 cc_name(cond
), dc
->op1
);
1496 gen_tst_cc(dc
, cpu_R
[dc
->op1
], cond
);
1497 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], 0);
1499 cris_cc_mask(dc
, 0);
1503 static inline void cris_alu_alloc_temps(DisasContext
*dc
, int size
, TCGv
*t
)
1506 t
[0] = cpu_R
[dc
->op2
];
1507 t
[1] = cpu_R
[dc
->op1
];
1509 t
[0] = tcg_temp_new();
1510 t
[1] = tcg_temp_new();
1514 static inline void cris_alu_free_temps(DisasContext
*dc
, int size
, TCGv
*t
)
1517 tcg_temp_free(t
[0]);
1518 tcg_temp_free(t
[1]);
1522 static int dec_and_r(CPUCRISState
*env
, DisasContext
*dc
)
1525 int size
= memsize_zz(dc
);
1527 LOG_DIS("and.%c $r%u, $r%u\n",
1528 memsize_char(size
), dc
->op1
, dc
->op2
);
1530 cris_cc_mask(dc
, CC_MASK_NZ
);
1532 cris_alu_alloc_temps(dc
, size
, t
);
1533 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1534 cris_alu(dc
, CC_OP_AND
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1535 cris_alu_free_temps(dc
, size
, t
);
1539 static int dec_lz_r(CPUCRISState
*env
, DisasContext
*dc
)
1542 LOG_DIS("lz $r%u, $r%u\n",
1544 cris_cc_mask(dc
, CC_MASK_NZ
);
1545 t0
= tcg_temp_new();
1546 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, 4, 0, cpu_R
[dc
->op2
], t0
);
1547 cris_alu(dc
, CC_OP_LZ
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1552 static int dec_lsl_r(CPUCRISState
*env
, DisasContext
*dc
)
1555 int size
= memsize_zz(dc
);
1557 LOG_DIS("lsl.%c $r%u, $r%u\n",
1558 memsize_char(size
), dc
->op1
, dc
->op2
);
1560 cris_cc_mask(dc
, CC_MASK_NZ
);
1561 cris_alu_alloc_temps(dc
, size
, t
);
1562 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1563 tcg_gen_andi_tl(t
[1], t
[1], 63);
1564 cris_alu(dc
, CC_OP_LSL
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1565 cris_alu_alloc_temps(dc
, size
, t
);
1569 static int dec_lsr_r(CPUCRISState
*env
, DisasContext
*dc
)
1572 int size
= memsize_zz(dc
);
1574 LOG_DIS("lsr.%c $r%u, $r%u\n",
1575 memsize_char(size
), dc
->op1
, dc
->op2
);
1577 cris_cc_mask(dc
, CC_MASK_NZ
);
1578 cris_alu_alloc_temps(dc
, size
, t
);
1579 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1580 tcg_gen_andi_tl(t
[1], t
[1], 63);
1581 cris_alu(dc
, CC_OP_LSR
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1582 cris_alu_free_temps(dc
, size
, t
);
1586 static int dec_asr_r(CPUCRISState
*env
, DisasContext
*dc
)
1589 int size
= memsize_zz(dc
);
1591 LOG_DIS("asr.%c $r%u, $r%u\n",
1592 memsize_char(size
), dc
->op1
, dc
->op2
);
1594 cris_cc_mask(dc
, CC_MASK_NZ
);
1595 cris_alu_alloc_temps(dc
, size
, t
);
1596 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 1, t
[0], t
[1]);
1597 tcg_gen_andi_tl(t
[1], t
[1], 63);
1598 cris_alu(dc
, CC_OP_ASR
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1599 cris_alu_free_temps(dc
, size
, t
);
1603 static int dec_muls_r(CPUCRISState
*env
, DisasContext
*dc
)
1606 int size
= memsize_zz(dc
);
1608 LOG_DIS("muls.%c $r%u, $r%u\n",
1609 memsize_char(size
), dc
->op1
, dc
->op2
);
1610 cris_cc_mask(dc
, CC_MASK_NZV
);
1611 cris_alu_alloc_temps(dc
, size
, t
);
1612 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 1, t
[0], t
[1]);
1614 cris_alu(dc
, CC_OP_MULS
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
1615 cris_alu_free_temps(dc
, size
, t
);
1619 static int dec_mulu_r(CPUCRISState
*env
, DisasContext
*dc
)
1622 int size
= memsize_zz(dc
);
1624 LOG_DIS("mulu.%c $r%u, $r%u\n",
1625 memsize_char(size
), dc
->op1
, dc
->op2
);
1626 cris_cc_mask(dc
, CC_MASK_NZV
);
1627 cris_alu_alloc_temps(dc
, size
, t
);
1628 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1630 cris_alu(dc
, CC_OP_MULU
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
1631 cris_alu_alloc_temps(dc
, size
, t
);
1636 static int dec_dstep_r(CPUCRISState
*env
, DisasContext
*dc
)
1638 LOG_DIS("dstep $r%u, $r%u\n", dc
->op1
, dc
->op2
);
1639 cris_cc_mask(dc
, CC_MASK_NZ
);
1640 cris_alu(dc
, CC_OP_DSTEP
,
1641 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], 4);
1645 static int dec_xor_r(CPUCRISState
*env
, DisasContext
*dc
)
1648 int size
= memsize_zz(dc
);
1649 LOG_DIS("xor.%c $r%u, $r%u\n",
1650 memsize_char(size
), dc
->op1
, dc
->op2
);
1651 BUG_ON(size
!= 4); /* xor is dword. */
1652 cris_cc_mask(dc
, CC_MASK_NZ
);
1653 cris_alu_alloc_temps(dc
, size
, t
);
1654 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1656 cris_alu(dc
, CC_OP_XOR
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
1657 cris_alu_free_temps(dc
, size
, t
);
1661 static int dec_bound_r(CPUCRISState
*env
, DisasContext
*dc
)
1664 int size
= memsize_zz(dc
);
1665 LOG_DIS("bound.%c $r%u, $r%u\n",
1666 memsize_char(size
), dc
->op1
, dc
->op2
);
1667 cris_cc_mask(dc
, CC_MASK_NZ
);
1668 l0
= tcg_temp_local_new();
1669 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, l0
);
1670 cris_alu(dc
, CC_OP_BOUND
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], l0
, 4);
1675 static int dec_cmp_r(CPUCRISState
*env
, DisasContext
*dc
)
1678 int size
= memsize_zz(dc
);
1679 LOG_DIS("cmp.%c $r%u, $r%u\n",
1680 memsize_char(size
), dc
->op1
, dc
->op2
);
1681 cris_cc_mask(dc
, CC_MASK_NZVC
);
1682 cris_alu_alloc_temps(dc
, size
, t
);
1683 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1685 cris_alu(dc
, CC_OP_CMP
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1686 cris_alu_free_temps(dc
, size
, t
);
1690 static int dec_abs_r(CPUCRISState
*env
, DisasContext
*dc
)
1694 LOG_DIS("abs $r%u, $r%u\n",
1696 cris_cc_mask(dc
, CC_MASK_NZ
);
1698 t0
= tcg_temp_new();
1699 tcg_gen_sari_tl(t0
, cpu_R
[dc
->op1
], 31);
1700 tcg_gen_xor_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], t0
);
1701 tcg_gen_sub_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
);
1704 cris_alu(dc
, CC_OP_MOVE
,
1705 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1709 static int dec_add_r(CPUCRISState
*env
, DisasContext
*dc
)
1712 int size
= memsize_zz(dc
);
1713 LOG_DIS("add.%c $r%u, $r%u\n",
1714 memsize_char(size
), dc
->op1
, dc
->op2
);
1715 cris_cc_mask(dc
, CC_MASK_NZVC
);
1716 cris_alu_alloc_temps(dc
, size
, t
);
1717 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1719 cris_alu(dc
, CC_OP_ADD
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1720 cris_alu_free_temps(dc
, size
, t
);
1724 static int dec_addc_r(CPUCRISState
*env
, DisasContext
*dc
)
1726 LOG_DIS("addc $r%u, $r%u\n",
1728 cris_evaluate_flags(dc
);
1729 /* Set for this insn. */
1730 dc
->flagx_known
= 1;
1731 dc
->flags_x
= X_FLAG
;
1733 cris_cc_mask(dc
, CC_MASK_NZVC
);
1734 cris_alu(dc
, CC_OP_ADDC
,
1735 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], 4);
1739 static int dec_mcp_r(CPUCRISState
*env
, DisasContext
*dc
)
1741 LOG_DIS("mcp $p%u, $r%u\n",
1743 cris_evaluate_flags(dc
);
1744 cris_cc_mask(dc
, CC_MASK_RNZV
);
1745 cris_alu(dc
, CC_OP_MCP
,
1746 cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], cpu_PR
[dc
->op2
], 4);
1751 static char * swapmode_name(int mode
, char *modename
) {
1754 modename
[i
++] = 'n';
1757 modename
[i
++] = 'w';
1760 modename
[i
++] = 'b';
1763 modename
[i
++] = 'r';
1770 static int dec_swap_r(CPUCRISState
*env
, DisasContext
*dc
)
1776 LOG_DIS("swap%s $r%u\n",
1777 swapmode_name(dc
->op2
, modename
), dc
->op1
);
1779 cris_cc_mask(dc
, CC_MASK_NZ
);
1780 t0
= tcg_temp_new();
1781 tcg_gen_mov_tl(t0
, cpu_R
[dc
->op1
]);
1783 tcg_gen_not_tl(t0
, t0
);
1786 t_gen_swapw(t0
, t0
);
1789 t_gen_swapb(t0
, t0
);
1792 t_gen_swapr(t0
, t0
);
1794 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], t0
, 4);
1799 static int dec_or_r(CPUCRISState
*env
, DisasContext
*dc
)
1802 int size
= memsize_zz(dc
);
1803 LOG_DIS("or.%c $r%u, $r%u\n",
1804 memsize_char(size
), dc
->op1
, dc
->op2
);
1805 cris_cc_mask(dc
, CC_MASK_NZ
);
1806 cris_alu_alloc_temps(dc
, size
, t
);
1807 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1808 cris_alu(dc
, CC_OP_OR
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1809 cris_alu_free_temps(dc
, size
, t
);
1813 static int dec_addi_r(CPUCRISState
*env
, DisasContext
*dc
)
1816 LOG_DIS("addi.%c $r%u, $r%u\n",
1817 memsize_char(memsize_zz(dc
)), dc
->op2
, dc
->op1
);
1818 cris_cc_mask(dc
, 0);
1819 t0
= tcg_temp_new();
1820 tcg_gen_shl_tl(t0
, cpu_R
[dc
->op2
], tcg_const_tl(dc
->zzsize
));
1821 tcg_gen_add_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], t0
);
1826 static int dec_addi_acr(CPUCRISState
*env
, DisasContext
*dc
)
1829 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1830 memsize_char(memsize_zz(dc
)), dc
->op2
, dc
->op1
);
1831 cris_cc_mask(dc
, 0);
1832 t0
= tcg_temp_new();
1833 tcg_gen_shl_tl(t0
, cpu_R
[dc
->op2
], tcg_const_tl(dc
->zzsize
));
1834 tcg_gen_add_tl(cpu_R
[R_ACR
], cpu_R
[dc
->op1
], t0
);
1839 static int dec_neg_r(CPUCRISState
*env
, DisasContext
*dc
)
1842 int size
= memsize_zz(dc
);
1843 LOG_DIS("neg.%c $r%u, $r%u\n",
1844 memsize_char(size
), dc
->op1
, dc
->op2
);
1845 cris_cc_mask(dc
, CC_MASK_NZVC
);
1846 cris_alu_alloc_temps(dc
, size
, t
);
1847 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1849 cris_alu(dc
, CC_OP_NEG
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1850 cris_alu_free_temps(dc
, size
, t
);
1854 static int dec_btst_r(CPUCRISState
*env
, DisasContext
*dc
)
1856 LOG_DIS("btst $r%u, $r%u\n",
1858 cris_cc_mask(dc
, CC_MASK_NZ
);
1859 cris_evaluate_flags(dc
);
1860 gen_helper_btst(cpu_PR
[PR_CCS
], cpu_env
, cpu_R
[dc
->op2
],
1861 cpu_R
[dc
->op1
], cpu_PR
[PR_CCS
]);
1862 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->op2
],
1863 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1864 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
1865 dc
->flags_uptodate
= 1;
1869 static int dec_sub_r(CPUCRISState
*env
, DisasContext
*dc
)
1872 int size
= memsize_zz(dc
);
1873 LOG_DIS("sub.%c $r%u, $r%u\n",
1874 memsize_char(size
), dc
->op1
, dc
->op2
);
1875 cris_cc_mask(dc
, CC_MASK_NZVC
);
1876 cris_alu_alloc_temps(dc
, size
, t
);
1877 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1878 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1879 cris_alu_free_temps(dc
, size
, t
);
1883 /* Zero extension. From size to dword. */
1884 static int dec_movu_r(CPUCRISState
*env
, DisasContext
*dc
)
1887 int size
= memsize_z(dc
);
1888 LOG_DIS("movu.%c $r%u, $r%u\n",
1892 cris_cc_mask(dc
, CC_MASK_NZ
);
1893 t0
= tcg_temp_new();
1894 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t0
);
1895 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1900 /* Sign extension. From size to dword. */
1901 static int dec_movs_r(CPUCRISState
*env
, DisasContext
*dc
)
1904 int size
= memsize_z(dc
);
1905 LOG_DIS("movs.%c $r%u, $r%u\n",
1909 cris_cc_mask(dc
, CC_MASK_NZ
);
1910 t0
= tcg_temp_new();
1911 /* Size can only be qi or hi. */
1912 t_gen_sext(t0
, cpu_R
[dc
->op1
], size
);
1913 cris_alu(dc
, CC_OP_MOVE
,
1914 cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], t0
, 4);
1919 /* zero extension. From size to dword. */
1920 static int dec_addu_r(CPUCRISState
*env
, DisasContext
*dc
)
1923 int size
= memsize_z(dc
);
1924 LOG_DIS("addu.%c $r%u, $r%u\n",
1928 cris_cc_mask(dc
, CC_MASK_NZVC
);
1929 t0
= tcg_temp_new();
1930 /* Size can only be qi or hi. */
1931 t_gen_zext(t0
, cpu_R
[dc
->op1
], size
);
1932 cris_alu(dc
, CC_OP_ADD
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1937 /* Sign extension. From size to dword. */
1938 static int dec_adds_r(CPUCRISState
*env
, DisasContext
*dc
)
1941 int size
= memsize_z(dc
);
1942 LOG_DIS("adds.%c $r%u, $r%u\n",
1946 cris_cc_mask(dc
, CC_MASK_NZVC
);
1947 t0
= tcg_temp_new();
1948 /* Size can only be qi or hi. */
1949 t_gen_sext(t0
, cpu_R
[dc
->op1
], size
);
1950 cris_alu(dc
, CC_OP_ADD
,
1951 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1956 /* Zero extension. From size to dword. */
1957 static int dec_subu_r(CPUCRISState
*env
, DisasContext
*dc
)
1960 int size
= memsize_z(dc
);
1961 LOG_DIS("subu.%c $r%u, $r%u\n",
1965 cris_cc_mask(dc
, CC_MASK_NZVC
);
1966 t0
= tcg_temp_new();
1967 /* Size can only be qi or hi. */
1968 t_gen_zext(t0
, cpu_R
[dc
->op1
], size
);
1969 cris_alu(dc
, CC_OP_SUB
,
1970 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1975 /* Sign extension. From size to dword. */
1976 static int dec_subs_r(CPUCRISState
*env
, DisasContext
*dc
)
1979 int size
= memsize_z(dc
);
1980 LOG_DIS("subs.%c $r%u, $r%u\n",
1984 cris_cc_mask(dc
, CC_MASK_NZVC
);
1985 t0
= tcg_temp_new();
1986 /* Size can only be qi or hi. */
1987 t_gen_sext(t0
, cpu_R
[dc
->op1
], size
);
1988 cris_alu(dc
, CC_OP_SUB
,
1989 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1994 static int dec_setclrf(CPUCRISState
*env
, DisasContext
*dc
)
1997 int set
= (~dc
->opcode
>> 2) & 1;
2000 flags
= (EXTRACT_FIELD(dc
->ir
, 12, 15) << 4)
2001 | EXTRACT_FIELD(dc
->ir
, 0, 3);
2002 if (set
&& flags
== 0) {
2005 } else if (!set
&& (flags
& 0x20)) {
2008 LOG_DIS("%sf %x\n", set
? "set" : "clr", flags
);
2011 /* User space is not allowed to touch these. Silently ignore. */
2012 if (dc
->tb_flags
& U_FLAG
) {
2013 flags
&= ~(S_FLAG
| I_FLAG
| U_FLAG
);
2016 if (flags
& X_FLAG
) {
2017 dc
->flagx_known
= 1;
2019 dc
->flags_x
= X_FLAG
;
2025 /* Break the TB if any of the SPI flag changes. */
2026 if (flags
& (P_FLAG
| S_FLAG
)) {
2027 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
2028 dc
->is_jmp
= DISAS_UPDATE
;
2029 dc
->cpustate_changed
= 1;
2032 /* For the I flag, only act on posedge. */
2033 if ((flags
& I_FLAG
)) {
2034 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
2035 dc
->is_jmp
= DISAS_UPDATE
;
2036 dc
->cpustate_changed
= 1;
2040 /* Simply decode the flags. */
2041 cris_evaluate_flags(dc
);
2042 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
2043 cris_update_cc_x(dc
);
2044 tcg_gen_movi_tl(cc_op
, dc
->cc_op
);
2047 if (!(dc
->tb_flags
& U_FLAG
) && (flags
& U_FLAG
)) {
2048 /* Enter user mode. */
2049 t_gen_mov_env_TN(ksp
, cpu_R
[R_SP
]);
2050 tcg_gen_mov_tl(cpu_R
[R_SP
], cpu_PR
[PR_USP
]);
2051 dc
->cpustate_changed
= 1;
2053 tcg_gen_ori_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], flags
);
2055 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~flags
);
2058 dc
->flags_uptodate
= 1;
2063 static int dec_move_rs(CPUCRISState
*env
, DisasContext
*dc
)
2065 LOG_DIS("move $r%u, $s%u\n", dc
->op1
, dc
->op2
);
2066 cris_cc_mask(dc
, 0);
2067 gen_helper_movl_sreg_reg(cpu_env
, tcg_const_tl(dc
->op2
),
2068 tcg_const_tl(dc
->op1
));
2071 static int dec_move_sr(CPUCRISState
*env
, DisasContext
*dc
)
2073 LOG_DIS("move $s%u, $r%u\n", dc
->op2
, dc
->op1
);
2074 cris_cc_mask(dc
, 0);
2075 gen_helper_movl_reg_sreg(cpu_env
, tcg_const_tl(dc
->op1
),
2076 tcg_const_tl(dc
->op2
));
2080 static int dec_move_rp(CPUCRISState
*env
, DisasContext
*dc
)
2083 LOG_DIS("move $r%u, $p%u\n", dc
->op1
, dc
->op2
);
2084 cris_cc_mask(dc
, 0);
2086 t
[0] = tcg_temp_new();
2087 if (dc
->op2
== PR_CCS
) {
2088 cris_evaluate_flags(dc
);
2089 tcg_gen_mov_tl(t
[0], cpu_R
[dc
->op1
]);
2090 if (dc
->tb_flags
& U_FLAG
) {
2091 t
[1] = tcg_temp_new();
2092 /* User space is not allowed to touch all flags. */
2093 tcg_gen_andi_tl(t
[0], t
[0], 0x39f);
2094 tcg_gen_andi_tl(t
[1], cpu_PR
[PR_CCS
], ~0x39f);
2095 tcg_gen_or_tl(t
[0], t
[1], t
[0]);
2096 tcg_temp_free(t
[1]);
2099 tcg_gen_mov_tl(t
[0], cpu_R
[dc
->op1
]);
2102 t_gen_mov_preg_TN(dc
, dc
->op2
, t
[0]);
2103 if (dc
->op2
== PR_CCS
) {
2104 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
2105 dc
->flags_uptodate
= 1;
2107 tcg_temp_free(t
[0]);
2110 static int dec_move_pr(CPUCRISState
*env
, DisasContext
*dc
)
2113 LOG_DIS("move $p%u, $r%u\n", dc
->op2
, dc
->op1
);
2114 cris_cc_mask(dc
, 0);
2116 if (dc
->op2
== PR_CCS
) {
2117 cris_evaluate_flags(dc
);
2120 if (dc
->op2
== PR_DZ
) {
2121 tcg_gen_movi_tl(cpu_R
[dc
->op1
], 0);
2123 t0
= tcg_temp_new();
2124 t_gen_mov_TN_preg(t0
, dc
->op2
);
2125 cris_alu(dc
, CC_OP_MOVE
,
2126 cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], t0
,
2127 preg_sizes
[dc
->op2
]);
2133 static int dec_move_mr(CPUCRISState
*env
, DisasContext
*dc
)
2135 int memsize
= memsize_zz(dc
);
2137 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2138 memsize_char(memsize
),
2139 dc
->op1
, dc
->postinc
? "+]" : "]",
2143 insn_len
= dec_prep_move_m(env
, dc
, 0, 4, cpu_R
[dc
->op2
]);
2144 cris_cc_mask(dc
, CC_MASK_NZ
);
2145 cris_update_cc_op(dc
, CC_OP_MOVE
, 4);
2146 cris_update_cc_x(dc
);
2147 cris_update_result(dc
, cpu_R
[dc
->op2
]);
2151 t0
= tcg_temp_new();
2152 insn_len
= dec_prep_move_m(env
, dc
, 0, memsize
, t0
);
2153 cris_cc_mask(dc
, CC_MASK_NZ
);
2154 cris_alu(dc
, CC_OP_MOVE
,
2155 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, memsize
);
2158 do_postinc(dc
, memsize
);
2162 static inline void cris_alu_m_alloc_temps(TCGv
*t
)
2164 t
[0] = tcg_temp_new();
2165 t
[1] = tcg_temp_new();
2168 static inline void cris_alu_m_free_temps(TCGv
*t
)
2170 tcg_temp_free(t
[0]);
2171 tcg_temp_free(t
[1]);
2174 static int dec_movs_m(CPUCRISState
*env
, DisasContext
*dc
)
2177 int memsize
= memsize_z(dc
);
2179 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2180 memsize_char(memsize
),
2181 dc
->op1
, dc
->postinc
? "+]" : "]",
2184 cris_alu_m_alloc_temps(t
);
2186 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2187 cris_cc_mask(dc
, CC_MASK_NZ
);
2188 cris_alu(dc
, CC_OP_MOVE
,
2189 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2190 do_postinc(dc
, memsize
);
2191 cris_alu_m_free_temps(t
);
2195 static int dec_addu_m(CPUCRISState
*env
, DisasContext
*dc
)
2198 int memsize
= memsize_z(dc
);
2200 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2201 memsize_char(memsize
),
2202 dc
->op1
, dc
->postinc
? "+]" : "]",
2205 cris_alu_m_alloc_temps(t
);
2207 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2208 cris_cc_mask(dc
, CC_MASK_NZVC
);
2209 cris_alu(dc
, CC_OP_ADD
,
2210 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2211 do_postinc(dc
, memsize
);
2212 cris_alu_m_free_temps(t
);
2216 static int dec_adds_m(CPUCRISState
*env
, DisasContext
*dc
)
2219 int memsize
= memsize_z(dc
);
2221 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2222 memsize_char(memsize
),
2223 dc
->op1
, dc
->postinc
? "+]" : "]",
2226 cris_alu_m_alloc_temps(t
);
2228 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2229 cris_cc_mask(dc
, CC_MASK_NZVC
);
2230 cris_alu(dc
, CC_OP_ADD
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2231 do_postinc(dc
, memsize
);
2232 cris_alu_m_free_temps(t
);
2236 static int dec_subu_m(CPUCRISState
*env
, DisasContext
*dc
)
2239 int memsize
= memsize_z(dc
);
2241 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2242 memsize_char(memsize
),
2243 dc
->op1
, dc
->postinc
? "+]" : "]",
2246 cris_alu_m_alloc_temps(t
);
2248 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2249 cris_cc_mask(dc
, CC_MASK_NZVC
);
2250 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2251 do_postinc(dc
, memsize
);
2252 cris_alu_m_free_temps(t
);
2256 static int dec_subs_m(CPUCRISState
*env
, DisasContext
*dc
)
2259 int memsize
= memsize_z(dc
);
2261 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2262 memsize_char(memsize
),
2263 dc
->op1
, dc
->postinc
? "+]" : "]",
2266 cris_alu_m_alloc_temps(t
);
2268 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2269 cris_cc_mask(dc
, CC_MASK_NZVC
);
2270 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2271 do_postinc(dc
, memsize
);
2272 cris_alu_m_free_temps(t
);
2276 static int dec_movu_m(CPUCRISState
*env
, DisasContext
*dc
)
2279 int memsize
= memsize_z(dc
);
2282 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2283 memsize_char(memsize
),
2284 dc
->op1
, dc
->postinc
? "+]" : "]",
2287 cris_alu_m_alloc_temps(t
);
2288 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2289 cris_cc_mask(dc
, CC_MASK_NZ
);
2290 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2291 do_postinc(dc
, memsize
);
2292 cris_alu_m_free_temps(t
);
2296 static int dec_cmpu_m(CPUCRISState
*env
, DisasContext
*dc
)
2299 int memsize
= memsize_z(dc
);
2301 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2302 memsize_char(memsize
),
2303 dc
->op1
, dc
->postinc
? "+]" : "]",
2306 cris_alu_m_alloc_temps(t
);
2307 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2308 cris_cc_mask(dc
, CC_MASK_NZVC
);
2309 cris_alu(dc
, CC_OP_CMP
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2310 do_postinc(dc
, memsize
);
2311 cris_alu_m_free_temps(t
);
2315 static int dec_cmps_m(CPUCRISState
*env
, DisasContext
*dc
)
2318 int memsize
= memsize_z(dc
);
2320 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2321 memsize_char(memsize
),
2322 dc
->op1
, dc
->postinc
? "+]" : "]",
2325 cris_alu_m_alloc_temps(t
);
2326 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2327 cris_cc_mask(dc
, CC_MASK_NZVC
);
2328 cris_alu(dc
, CC_OP_CMP
,
2329 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1],
2331 do_postinc(dc
, memsize
);
2332 cris_alu_m_free_temps(t
);
2336 static int dec_cmp_m(CPUCRISState
*env
, DisasContext
*dc
)
2339 int memsize
= memsize_zz(dc
);
2341 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2342 memsize_char(memsize
),
2343 dc
->op1
, dc
->postinc
? "+]" : "]",
2346 cris_alu_m_alloc_temps(t
);
2347 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2348 cris_cc_mask(dc
, CC_MASK_NZVC
);
2349 cris_alu(dc
, CC_OP_CMP
,
2350 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1],
2352 do_postinc(dc
, memsize
);
2353 cris_alu_m_free_temps(t
);
2357 static int dec_test_m(CPUCRISState
*env
, DisasContext
*dc
)
2360 int memsize
= memsize_zz(dc
);
2362 LOG_DIS("test.%c [$r%u%s] op2=%x\n",
2363 memsize_char(memsize
),
2364 dc
->op1
, dc
->postinc
? "+]" : "]",
2367 cris_evaluate_flags(dc
);
2369 cris_alu_m_alloc_temps(t
);
2370 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2371 cris_cc_mask(dc
, CC_MASK_NZ
);
2372 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~3);
2374 cris_alu(dc
, CC_OP_CMP
,
2375 cpu_R
[dc
->op2
], t
[1], tcg_const_tl(0), memsize_zz(dc
));
2376 do_postinc(dc
, memsize
);
2377 cris_alu_m_free_temps(t
);
2381 static int dec_and_m(CPUCRISState
*env
, DisasContext
*dc
)
2384 int memsize
= memsize_zz(dc
);
2386 LOG_DIS("and.%c [$r%u%s, $r%u\n",
2387 memsize_char(memsize
),
2388 dc
->op1
, dc
->postinc
? "+]" : "]",
2391 cris_alu_m_alloc_temps(t
);
2392 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2393 cris_cc_mask(dc
, CC_MASK_NZ
);
2394 cris_alu(dc
, CC_OP_AND
, cpu_R
[dc
->op2
], t
[0], t
[1], memsize_zz(dc
));
2395 do_postinc(dc
, memsize
);
2396 cris_alu_m_free_temps(t
);
2400 static int dec_add_m(CPUCRISState
*env
, DisasContext
*dc
)
2403 int memsize
= memsize_zz(dc
);
2405 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2406 memsize_char(memsize
),
2407 dc
->op1
, dc
->postinc
? "+]" : "]",
2410 cris_alu_m_alloc_temps(t
);
2411 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2412 cris_cc_mask(dc
, CC_MASK_NZVC
);
2413 cris_alu(dc
, CC_OP_ADD
,
2414 cpu_R
[dc
->op2
], t
[0], t
[1], memsize_zz(dc
));
2415 do_postinc(dc
, memsize
);
2416 cris_alu_m_free_temps(t
);
2420 static int dec_addo_m(CPUCRISState
*env
, DisasContext
*dc
)
2423 int memsize
= memsize_zz(dc
);
2425 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2426 memsize_char(memsize
),
2427 dc
->op1
, dc
->postinc
? "+]" : "]",
2430 cris_alu_m_alloc_temps(t
);
2431 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2432 cris_cc_mask(dc
, 0);
2433 cris_alu(dc
, CC_OP_ADD
, cpu_R
[R_ACR
], t
[0], t
[1], 4);
2434 do_postinc(dc
, memsize
);
2435 cris_alu_m_free_temps(t
);
2439 static int dec_bound_m(CPUCRISState
*env
, DisasContext
*dc
)
2442 int memsize
= memsize_zz(dc
);
2444 LOG_DIS("bound.%c [$r%u%s, $r%u\n",
2445 memsize_char(memsize
),
2446 dc
->op1
, dc
->postinc
? "+]" : "]",
2449 l
[0] = tcg_temp_local_new();
2450 l
[1] = tcg_temp_local_new();
2451 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, l
[0], l
[1]);
2452 cris_cc_mask(dc
, CC_MASK_NZ
);
2453 cris_alu(dc
, CC_OP_BOUND
, cpu_R
[dc
->op2
], l
[0], l
[1], 4);
2454 do_postinc(dc
, memsize
);
2455 tcg_temp_free(l
[0]);
2456 tcg_temp_free(l
[1]);
2460 static int dec_addc_mr(CPUCRISState
*env
, DisasContext
*dc
)
2464 LOG_DIS("addc [$r%u%s, $r%u\n",
2465 dc
->op1
, dc
->postinc
? "+]" : "]",
2468 cris_evaluate_flags(dc
);
2470 /* Set for this insn. */
2471 dc
->flagx_known
= 1;
2472 dc
->flags_x
= X_FLAG
;
2474 cris_alu_m_alloc_temps(t
);
2475 insn_len
= dec_prep_alu_m(env
, dc
, 0, 4, t
[0], t
[1]);
2476 cris_cc_mask(dc
, CC_MASK_NZVC
);
2477 cris_alu(dc
, CC_OP_ADDC
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
2479 cris_alu_m_free_temps(t
);
2483 static int dec_sub_m(CPUCRISState
*env
, DisasContext
*dc
)
2486 int memsize
= memsize_zz(dc
);
2488 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2489 memsize_char(memsize
),
2490 dc
->op1
, dc
->postinc
? "+]" : "]",
2491 dc
->op2
, dc
->ir
, dc
->zzsize
);
2493 cris_alu_m_alloc_temps(t
);
2494 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2495 cris_cc_mask(dc
, CC_MASK_NZVC
);
2496 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], t
[0], t
[1], memsize
);
2497 do_postinc(dc
, memsize
);
2498 cris_alu_m_free_temps(t
);
2502 static int dec_or_m(CPUCRISState
*env
, DisasContext
*dc
)
2505 int memsize
= memsize_zz(dc
);
2507 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
2508 memsize_char(memsize
),
2509 dc
->op1
, dc
->postinc
? "+]" : "]",
2512 cris_alu_m_alloc_temps(t
);
2513 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2514 cris_cc_mask(dc
, CC_MASK_NZ
);
2515 cris_alu(dc
, CC_OP_OR
,
2516 cpu_R
[dc
->op2
], t
[0], t
[1], memsize_zz(dc
));
2517 do_postinc(dc
, memsize
);
2518 cris_alu_m_free_temps(t
);
2522 static int dec_move_mp(CPUCRISState
*env
, DisasContext
*dc
)
2525 int memsize
= memsize_zz(dc
);
2528 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2529 memsize_char(memsize
),
2531 dc
->postinc
? "+]" : "]",
2534 cris_alu_m_alloc_temps(t
);
2535 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2536 cris_cc_mask(dc
, 0);
2537 if (dc
->op2
== PR_CCS
) {
2538 cris_evaluate_flags(dc
);
2539 if (dc
->tb_flags
& U_FLAG
) {
2540 /* User space is not allowed to touch all flags. */
2541 tcg_gen_andi_tl(t
[1], t
[1], 0x39f);
2542 tcg_gen_andi_tl(t
[0], cpu_PR
[PR_CCS
], ~0x39f);
2543 tcg_gen_or_tl(t
[1], t
[0], t
[1]);
2547 t_gen_mov_preg_TN(dc
, dc
->op2
, t
[1]);
2549 do_postinc(dc
, memsize
);
2550 cris_alu_m_free_temps(t
);
2554 static int dec_move_pm(CPUCRISState
*env
, DisasContext
*dc
)
2559 memsize
= preg_sizes
[dc
->op2
];
2561 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2562 memsize_char(memsize
),
2563 dc
->op2
, dc
->op1
, dc
->postinc
? "+]" : "]");
2565 /* prepare store. Address in T0, value in T1. */
2566 if (dc
->op2
== PR_CCS
) {
2567 cris_evaluate_flags(dc
);
2569 t0
= tcg_temp_new();
2570 t_gen_mov_TN_preg(t0
, dc
->op2
);
2571 cris_flush_cc_state(dc
);
2572 gen_store(dc
, cpu_R
[dc
->op1
], t0
, memsize
);
2575 cris_cc_mask(dc
, 0);
2577 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], memsize
);
2582 static int dec_movem_mr(CPUCRISState
*env
, DisasContext
*dc
)
2588 int nr
= dc
->op2
+ 1;
2590 LOG_DIS("movem [$r%u%s, $r%u\n", dc
->op1
,
2591 dc
->postinc
? "+]" : "]", dc
->op2
);
2593 addr
= tcg_temp_new();
2594 /* There are probably better ways of doing this. */
2595 cris_flush_cc_state(dc
);
2596 for (i
= 0; i
< (nr
>> 1); i
++) {
2597 tmp
[i
] = tcg_temp_new_i64();
2598 tcg_gen_addi_tl(addr
, cpu_R
[dc
->op1
], i
* 8);
2599 gen_load64(dc
, tmp
[i
], addr
);
2602 tmp32
= tcg_temp_new_i32();
2603 tcg_gen_addi_tl(addr
, cpu_R
[dc
->op1
], i
* 8);
2604 gen_load(dc
, tmp32
, addr
, 4, 0);
2608 tcg_temp_free(addr
);
2610 for (i
= 0; i
< (nr
>> 1); i
++) {
2611 tcg_gen_extrl_i64_i32(cpu_R
[i
* 2], tmp
[i
]);
2612 tcg_gen_shri_i64(tmp
[i
], tmp
[i
], 32);
2613 tcg_gen_extrl_i64_i32(cpu_R
[i
* 2 + 1], tmp
[i
]);
2614 tcg_temp_free_i64(tmp
[i
]);
2617 tcg_gen_mov_tl(cpu_R
[dc
->op2
], tmp32
);
2618 tcg_temp_free(tmp32
);
2621 /* writeback the updated pointer value. */
2623 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], nr
* 4);
2626 /* gen_load might want to evaluate the previous insns flags. */
2627 cris_cc_mask(dc
, 0);
2631 static int dec_movem_rm(CPUCRISState
*env
, DisasContext
*dc
)
2637 LOG_DIS("movem $r%u, [$r%u%s\n", dc
->op2
, dc
->op1
,
2638 dc
->postinc
? "+]" : "]");
2640 cris_flush_cc_state(dc
);
2642 tmp
= tcg_temp_new();
2643 addr
= tcg_temp_new();
2644 tcg_gen_movi_tl(tmp
, 4);
2645 tcg_gen_mov_tl(addr
, cpu_R
[dc
->op1
]);
2646 for (i
= 0; i
<= dc
->op2
; i
++) {
2647 /* Displace addr. */
2648 /* Perform the store. */
2649 gen_store(dc
, addr
, cpu_R
[i
], 4);
2650 tcg_gen_add_tl(addr
, addr
, tmp
);
2653 tcg_gen_mov_tl(cpu_R
[dc
->op1
], addr
);
2655 cris_cc_mask(dc
, 0);
2657 tcg_temp_free(addr
);
2661 static int dec_move_rm(CPUCRISState
*env
, DisasContext
*dc
)
2665 memsize
= memsize_zz(dc
);
2667 LOG_DIS("move.%c $r%u, [$r%u]\n",
2668 memsize_char(memsize
), dc
->op2
, dc
->op1
);
2670 /* prepare store. */
2671 cris_flush_cc_state(dc
);
2672 gen_store(dc
, cpu_R
[dc
->op1
], cpu_R
[dc
->op2
], memsize
);
2675 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], memsize
);
2677 cris_cc_mask(dc
, 0);
2681 static int dec_lapcq(CPUCRISState
*env
, DisasContext
*dc
)
2683 LOG_DIS("lapcq %x, $r%u\n",
2684 dc
->pc
+ dc
->op1
*2, dc
->op2
);
2685 cris_cc_mask(dc
, 0);
2686 tcg_gen_movi_tl(cpu_R
[dc
->op2
], dc
->pc
+ dc
->op1
* 2);
2690 static int dec_lapc_im(CPUCRISState
*env
, DisasContext
*dc
)
2698 cris_cc_mask(dc
, 0);
2699 imm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2700 LOG_DIS("lapc 0x%x, $r%u\n", imm
+ dc
->pc
, dc
->op2
);
2704 tcg_gen_movi_tl(cpu_R
[rd
], pc
);
2708 /* Jump to special reg. */
2709 static int dec_jump_p(CPUCRISState
*env
, DisasContext
*dc
)
2711 LOG_DIS("jump $p%u\n", dc
->op2
);
2713 if (dc
->op2
== PR_CCS
) {
2714 cris_evaluate_flags(dc
);
2716 t_gen_mov_TN_preg(env_btarget
, dc
->op2
);
2717 /* rete will often have low bit set to indicate delayslot. */
2718 tcg_gen_andi_tl(env_btarget
, env_btarget
, ~1);
2719 cris_cc_mask(dc
, 0);
2720 cris_prepare_jmp(dc
, JMP_INDIRECT
);
2724 /* Jump and save. */
2725 static int dec_jas_r(CPUCRISState
*env
, DisasContext
*dc
)
2727 LOG_DIS("jas $r%u, $p%u\n", dc
->op1
, dc
->op2
);
2728 cris_cc_mask(dc
, 0);
2729 /* Store the return address in Pd. */
2730 tcg_gen_mov_tl(env_btarget
, cpu_R
[dc
->op1
]);
2734 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 4));
2736 cris_prepare_jmp(dc
, JMP_INDIRECT
);
2740 static int dec_jas_im(CPUCRISState
*env
, DisasContext
*dc
)
2744 imm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2746 LOG_DIS("jas 0x%x\n", imm
);
2747 cris_cc_mask(dc
, 0);
2748 /* Store the return address in Pd. */
2749 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 8));
2752 cris_prepare_jmp(dc
, JMP_DIRECT
);
2756 static int dec_jasc_im(CPUCRISState
*env
, DisasContext
*dc
)
2760 imm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2762 LOG_DIS("jasc 0x%x\n", imm
);
2763 cris_cc_mask(dc
, 0);
2764 /* Store the return address in Pd. */
2765 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 8 + 4));
2768 cris_prepare_jmp(dc
, JMP_DIRECT
);
2772 static int dec_jasc_r(CPUCRISState
*env
, DisasContext
*dc
)
2774 LOG_DIS("jasc_r $r%u, $p%u\n", dc
->op1
, dc
->op2
);
2775 cris_cc_mask(dc
, 0);
2776 /* Store the return address in Pd. */
2777 tcg_gen_mov_tl(env_btarget
, cpu_R
[dc
->op1
]);
2778 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 4 + 4));
2779 cris_prepare_jmp(dc
, JMP_INDIRECT
);
2783 static int dec_bcc_im(CPUCRISState
*env
, DisasContext
*dc
)
2786 uint32_t cond
= dc
->op2
;
2788 offset
= cris_fetch(env
, dc
, dc
->pc
+ 2, 2, 1);
2790 LOG_DIS("b%s %d pc=%x dst=%x\n",
2791 cc_name(cond
), offset
,
2792 dc
->pc
, dc
->pc
+ offset
);
2794 cris_cc_mask(dc
, 0);
2795 /* op2 holds the condition-code. */
2796 cris_prepare_cc_branch(dc
, offset
, cond
);
2800 static int dec_bas_im(CPUCRISState
*env
, DisasContext
*dc
)
2804 simm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2806 LOG_DIS("bas 0x%x, $p%u\n", dc
->pc
+ simm
, dc
->op2
);
2807 cris_cc_mask(dc
, 0);
2808 /* Store the return address in Pd. */
2809 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 8));
2811 dc
->jmp_pc
= dc
->pc
+ simm
;
2812 cris_prepare_jmp(dc
, JMP_DIRECT
);
2816 static int dec_basc_im(CPUCRISState
*env
, DisasContext
*dc
)
2819 simm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2821 LOG_DIS("basc 0x%x, $p%u\n", dc
->pc
+ simm
, dc
->op2
);
2822 cris_cc_mask(dc
, 0);
2823 /* Store the return address in Pd. */
2824 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 12));
2826 dc
->jmp_pc
= dc
->pc
+ simm
;
2827 cris_prepare_jmp(dc
, JMP_DIRECT
);
2831 static int dec_rfe_etc(CPUCRISState
*env
, DisasContext
*dc
)
2833 cris_cc_mask(dc
, 0);
2835 if (dc
->op2
== 15) {
2836 tcg_gen_st_i32(tcg_const_i32(1), cpu_env
,
2837 -offsetof(CRISCPU
, env
) + offsetof(CPUState
, halted
));
2838 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
2839 t_gen_raise_exception(EXCP_HLT
);
2843 switch (dc
->op2
& 7) {
2847 cris_evaluate_flags(dc
);
2848 gen_helper_rfe(cpu_env
);
2849 dc
->is_jmp
= DISAS_UPDATE
;
2854 cris_evaluate_flags(dc
);
2855 gen_helper_rfn(cpu_env
);
2856 dc
->is_jmp
= DISAS_UPDATE
;
2859 LOG_DIS("break %d\n", dc
->op1
);
2860 cris_evaluate_flags(dc
);
2862 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
2864 /* Breaks start at 16 in the exception vector. */
2865 t_gen_mov_env_TN(trap_vector
,
2866 tcg_const_tl(dc
->op1
+ 16));
2867 t_gen_raise_exception(EXCP_BREAK
);
2868 dc
->is_jmp
= DISAS_UPDATE
;
2871 printf("op2=%x\n", dc
->op2
);
2879 static int dec_ftag_fidx_d_m(CPUCRISState
*env
, DisasContext
*dc
)
2884 static int dec_ftag_fidx_i_m(CPUCRISState
*env
, DisasContext
*dc
)
2889 static int dec_null(CPUCRISState
*env
, DisasContext
*dc
)
2891 printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2892 dc
->pc
, dc
->opcode
, dc
->op1
, dc
->op2
);
2898 static struct decoder_info
{
2903 int (*dec
)(CPUCRISState
*env
, DisasContext
*dc
);
2905 /* Order matters here. */
2906 {DEC_MOVEQ
, dec_moveq
},
2907 {DEC_BTSTQ
, dec_btstq
},
2908 {DEC_CMPQ
, dec_cmpq
},
2909 {DEC_ADDOQ
, dec_addoq
},
2910 {DEC_ADDQ
, dec_addq
},
2911 {DEC_SUBQ
, dec_subq
},
2912 {DEC_ANDQ
, dec_andq
},
2914 {DEC_ASRQ
, dec_asrq
},
2915 {DEC_LSLQ
, dec_lslq
},
2916 {DEC_LSRQ
, dec_lsrq
},
2917 {DEC_BCCQ
, dec_bccq
},
2919 {DEC_BCC_IM
, dec_bcc_im
},
2920 {DEC_JAS_IM
, dec_jas_im
},
2921 {DEC_JAS_R
, dec_jas_r
},
2922 {DEC_JASC_IM
, dec_jasc_im
},
2923 {DEC_JASC_R
, dec_jasc_r
},
2924 {DEC_BAS_IM
, dec_bas_im
},
2925 {DEC_BASC_IM
, dec_basc_im
},
2926 {DEC_JUMP_P
, dec_jump_p
},
2927 {DEC_LAPC_IM
, dec_lapc_im
},
2928 {DEC_LAPCQ
, dec_lapcq
},
2930 {DEC_RFE_ETC
, dec_rfe_etc
},
2931 {DEC_ADDC_MR
, dec_addc_mr
},
2933 {DEC_MOVE_MP
, dec_move_mp
},
2934 {DEC_MOVE_PM
, dec_move_pm
},
2935 {DEC_MOVEM_MR
, dec_movem_mr
},
2936 {DEC_MOVEM_RM
, dec_movem_rm
},
2937 {DEC_MOVE_PR
, dec_move_pr
},
2938 {DEC_SCC_R
, dec_scc_r
},
2939 {DEC_SETF
, dec_setclrf
},
2940 {DEC_CLEARF
, dec_setclrf
},
2942 {DEC_MOVE_SR
, dec_move_sr
},
2943 {DEC_MOVE_RP
, dec_move_rp
},
2944 {DEC_SWAP_R
, dec_swap_r
},
2945 {DEC_ABS_R
, dec_abs_r
},
2946 {DEC_LZ_R
, dec_lz_r
},
2947 {DEC_MOVE_RS
, dec_move_rs
},
2948 {DEC_BTST_R
, dec_btst_r
},
2949 {DEC_ADDC_R
, dec_addc_r
},
2951 {DEC_DSTEP_R
, dec_dstep_r
},
2952 {DEC_XOR_R
, dec_xor_r
},
2953 {DEC_MCP_R
, dec_mcp_r
},
2954 {DEC_CMP_R
, dec_cmp_r
},
2956 {DEC_ADDI_R
, dec_addi_r
},
2957 {DEC_ADDI_ACR
, dec_addi_acr
},
2959 {DEC_ADD_R
, dec_add_r
},
2960 {DEC_SUB_R
, dec_sub_r
},
2962 {DEC_ADDU_R
, dec_addu_r
},
2963 {DEC_ADDS_R
, dec_adds_r
},
2964 {DEC_SUBU_R
, dec_subu_r
},
2965 {DEC_SUBS_R
, dec_subs_r
},
2966 {DEC_LSL_R
, dec_lsl_r
},
2968 {DEC_AND_R
, dec_and_r
},
2969 {DEC_OR_R
, dec_or_r
},
2970 {DEC_BOUND_R
, dec_bound_r
},
2971 {DEC_ASR_R
, dec_asr_r
},
2972 {DEC_LSR_R
, dec_lsr_r
},
2974 {DEC_MOVU_R
, dec_movu_r
},
2975 {DEC_MOVS_R
, dec_movs_r
},
2976 {DEC_NEG_R
, dec_neg_r
},
2977 {DEC_MOVE_R
, dec_move_r
},
2979 {DEC_FTAG_FIDX_I_M
, dec_ftag_fidx_i_m
},
2980 {DEC_FTAG_FIDX_D_M
, dec_ftag_fidx_d_m
},
2982 {DEC_MULS_R
, dec_muls_r
},
2983 {DEC_MULU_R
, dec_mulu_r
},
2985 {DEC_ADDU_M
, dec_addu_m
},
2986 {DEC_ADDS_M
, dec_adds_m
},
2987 {DEC_SUBU_M
, dec_subu_m
},
2988 {DEC_SUBS_M
, dec_subs_m
},
2990 {DEC_CMPU_M
, dec_cmpu_m
},
2991 {DEC_CMPS_M
, dec_cmps_m
},
2992 {DEC_MOVU_M
, dec_movu_m
},
2993 {DEC_MOVS_M
, dec_movs_m
},
2995 {DEC_CMP_M
, dec_cmp_m
},
2996 {DEC_ADDO_M
, dec_addo_m
},
2997 {DEC_BOUND_M
, dec_bound_m
},
2998 {DEC_ADD_M
, dec_add_m
},
2999 {DEC_SUB_M
, dec_sub_m
},
3000 {DEC_AND_M
, dec_and_m
},
3001 {DEC_OR_M
, dec_or_m
},
3002 {DEC_MOVE_RM
, dec_move_rm
},
3003 {DEC_TEST_M
, dec_test_m
},
3004 {DEC_MOVE_MR
, dec_move_mr
},
3009 static unsigned int crisv32_decoder(CPUCRISState
*env
, DisasContext
*dc
)
3014 /* Load a halfword onto the instruction register. */
3015 dc
->ir
= cris_fetch(env
, dc
, dc
->pc
, 2, 0);
3017 /* Now decode it. */
3018 dc
->opcode
= EXTRACT_FIELD(dc
->ir
, 4, 11);
3019 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 3);
3020 dc
->op2
= EXTRACT_FIELD(dc
->ir
, 12, 15);
3021 dc
->zsize
= EXTRACT_FIELD(dc
->ir
, 4, 4);
3022 dc
->zzsize
= EXTRACT_FIELD(dc
->ir
, 4, 5);
3023 dc
->postinc
= EXTRACT_FIELD(dc
->ir
, 10, 10);
3025 /* Large switch for all insns. */
3026 for (i
= 0; i
< ARRAY_SIZE(decinfo
); i
++) {
3027 if ((dc
->opcode
& decinfo
[i
].mask
) == decinfo
[i
].bits
) {
3028 insn_len
= decinfo
[i
].dec(env
, dc
);
3033 #if !defined(CONFIG_USER_ONLY)
3034 /* Single-stepping ? */
3035 if (dc
->tb_flags
& S_FLAG
) {
3036 TCGLabel
*l1
= gen_new_label();
3037 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_PR
[PR_SPC
], dc
->pc
, l1
);
3038 /* We treat SPC as a break with an odd trap vector. */
3039 cris_evaluate_flags(dc
);
3040 t_gen_mov_env_TN(trap_vector
, tcg_const_tl(3));
3041 tcg_gen_movi_tl(env_pc
, dc
->pc
+ insn_len
);
3042 tcg_gen_movi_tl(cpu_PR
[PR_SPC
], dc
->pc
+ insn_len
);
3043 t_gen_raise_exception(EXCP_BREAK
);
3050 #include "translate_v10.c"
3053 * Delay slots on QEMU/CRIS.
3055 * If an exception hits on a delayslot, the core will let ERP (the Exception
3056 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3057 * to give SW a hint that the exception actually hit on the dslot.
3059 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3060 * the core and any jmp to an odd addresses will mask off that lsb. It is
3061 * simply there to let sw know there was an exception on a dslot.
3063 * When the software returns from an exception, the branch will re-execute.
3064 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3065 * and the branch and delayslot don't share pages.
3067 * The TB contaning the branch insn will set up env->btarget and evaluate
3068 * env->btaken. When the translation loop exits we will note that the branch
3069 * sequence is broken and let env->dslot be the size of the branch insn (those
3072 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3073 * set). It will also expect to have env->dslot setup with the size of the
3074 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3075 * will execute the dslot and take the branch, either to btarget or just one
3078 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3079 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3080 * branch and set lsb). Then env->dslot gets cleared so that the exception
3081 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3082 * masked off and we will reexecute the branch insn.
3086 /* generate intermediate code for basic block 'tb'. */
3087 void gen_intermediate_code(CPUState
*cs
, struct TranslationBlock
*tb
)
3089 CPUCRISState
*env
= cs
->env_ptr
;
3091 unsigned int insn_len
;
3092 struct DisasContext ctx
;
3093 struct DisasContext
*dc
= &ctx
;
3094 uint32_t next_page_start
;
3099 if (env
->pregs
[PR_VR
] == 32) {
3100 dc
->decoder
= crisv32_decoder
;
3101 dc
->clear_locked_irq
= 0;
3103 dc
->decoder
= crisv10_decoder
;
3104 dc
->clear_locked_irq
= 1;
3107 /* Odd PC indicates that branch is rexecuting due to exception in the
3108 * delayslot, like in real hw.
3110 pc_start
= tb
->pc
& ~1;
3111 dc
->cpu
= cris_env_get_cpu(env
);
3114 dc
->is_jmp
= DISAS_NEXT
;
3117 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
3118 dc
->flags_uptodate
= 1;
3119 dc
->flagx_known
= 1;
3120 dc
->flags_x
= tb
->flags
& X_FLAG
;
3121 dc
->cc_x_uptodate
= 0;
3124 dc
->clear_prefix
= 0;
3126 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
3127 dc
->cc_size_uptodate
= -1;
3129 /* Decode TB flags. */
3130 dc
->tb_flags
= tb
->flags
& (S_FLAG
| P_FLAG
| U_FLAG \
3131 | X_FLAG
| PFIX_FLAG
);
3132 dc
->delayed_branch
= !!(tb
->flags
& 7);
3133 if (dc
->delayed_branch
) {
3134 dc
->jmp
= JMP_INDIRECT
;
3136 dc
->jmp
= JMP_NOJMP
;
3139 dc
->cpustate_changed
= 0;
3141 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
3143 max_insns
= tb_cflags(tb
) & CF_COUNT_MASK
;
3144 if (max_insns
== 0) {
3145 max_insns
= CF_COUNT_MASK
;
3147 if (max_insns
> TCG_MAX_INSNS
) {
3148 max_insns
= TCG_MAX_INSNS
;
3153 tcg_gen_insn_start(dc
->delayed_branch
== 1
3154 ? dc
->ppc
| 1 : dc
->pc
);
3157 if (unlikely(cpu_breakpoint_test(cs
, dc
->pc
, BP_ANY
))) {
3158 cris_evaluate_flags(dc
);
3159 tcg_gen_movi_tl(env_pc
, dc
->pc
);
3160 t_gen_raise_exception(EXCP_DEBUG
);
3161 dc
->is_jmp
= DISAS_UPDATE
;
3162 /* The address covered by the breakpoint must be included in
3163 [tb->pc, tb->pc + tb->size) in order to for it to be
3164 properly cleared -- thus we increment the PC here so that
3165 the logic setting tb->size below does the right thing. */
3171 LOG_DIS("%8.8x:\t", dc
->pc
);
3173 if (num_insns
== max_insns
&& (tb_cflags(tb
) & CF_LAST_IO
)) {
3178 insn_len
= dc
->decoder(env
, dc
);
3182 cris_clear_x_flag(dc
);
3185 /* Check for delayed branches here. If we do it before
3186 actually generating any host code, the simulator will just
3187 loop doing nothing for on this program location. */
3188 if (dc
->delayed_branch
) {
3189 dc
->delayed_branch
--;
3190 if (dc
->delayed_branch
== 0) {
3191 if (tb
->flags
& 7) {
3192 t_gen_mov_env_TN(dslot
, tcg_const_tl(0));
3194 if (dc
->cpustate_changed
|| !dc
->flagx_known
3195 || (dc
->flags_x
!= (tb
->flags
& X_FLAG
))) {
3196 cris_store_direct_jmp(dc
);
3199 if (dc
->clear_locked_irq
) {
3200 dc
->clear_locked_irq
= 0;
3201 t_gen_mov_env_TN(locked_irq
, tcg_const_tl(0));
3204 if (dc
->jmp
== JMP_DIRECT_CC
) {
3205 TCGLabel
*l1
= gen_new_label();
3206 cris_evaluate_flags(dc
);
3208 /* Conditional jmp. */
3209 tcg_gen_brcondi_tl(TCG_COND_EQ
,
3211 gen_goto_tb(dc
, 1, dc
->jmp_pc
);
3213 gen_goto_tb(dc
, 0, dc
->pc
);
3214 dc
->is_jmp
= DISAS_TB_JUMP
;
3215 dc
->jmp
= JMP_NOJMP
;
3216 } else if (dc
->jmp
== JMP_DIRECT
) {
3217 cris_evaluate_flags(dc
);
3218 gen_goto_tb(dc
, 0, dc
->jmp_pc
);
3219 dc
->is_jmp
= DISAS_TB_JUMP
;
3220 dc
->jmp
= JMP_NOJMP
;
3222 t_gen_cc_jmp(env_btarget
, tcg_const_tl(dc
->pc
));
3223 dc
->is_jmp
= DISAS_JUMP
;
3229 /* If we are rexecuting a branch due to exceptions on
3230 delay slots don't break. */
3231 if (!(tb
->pc
& 1) && cs
->singlestep_enabled
) {
3234 } while (!dc
->is_jmp
&& !dc
->cpustate_changed
3235 && !tcg_op_buf_full()
3237 && (dc
->pc
< next_page_start
)
3238 && num_insns
< max_insns
);
3240 if (dc
->clear_locked_irq
) {
3241 t_gen_mov_env_TN(locked_irq
, tcg_const_tl(0));
3246 if (tb_cflags(tb
) & CF_LAST_IO
)
3248 /* Force an update if the per-tb cpu state has changed. */
3249 if (dc
->is_jmp
== DISAS_NEXT
3250 && (dc
->cpustate_changed
|| !dc
->flagx_known
3251 || (dc
->flags_x
!= (tb
->flags
& X_FLAG
)))) {
3252 dc
->is_jmp
= DISAS_UPDATE
;
3253 tcg_gen_movi_tl(env_pc
, npc
);
3255 /* Broken branch+delayslot sequence. */
3256 if (dc
->delayed_branch
== 1) {
3257 /* Set env->dslot to the size of the branch insn. */
3258 t_gen_mov_env_TN(dslot
, tcg_const_tl(dc
->pc
- dc
->ppc
));
3259 cris_store_direct_jmp(dc
);
3262 cris_evaluate_flags(dc
);
3264 if (unlikely(cs
->singlestep_enabled
)) {
3265 if (dc
->is_jmp
== DISAS_NEXT
) {
3266 tcg_gen_movi_tl(env_pc
, npc
);
3268 t_gen_raise_exception(EXCP_DEBUG
);
3270 switch (dc
->is_jmp
) {
3272 gen_goto_tb(dc
, 1, npc
);
3277 /* indicate that the hash table must be used
3278 to find the next TB */
3283 /* nothing more to generate */
3287 gen_tb_end(tb
, num_insns
);
3289 tb
->size
= dc
->pc
- pc_start
;
3290 tb
->icount
= num_insns
;
3294 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
3295 && qemu_log_in_addr_range(pc_start
)) {
3297 qemu_log("--------------\n");
3298 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
3299 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
);
3306 void cris_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
3309 CRISCPU
*cpu
= CRIS_CPU(cs
);
3310 CPUCRISState
*env
= &cpu
->env
;
3311 const char **regnames
;
3312 const char **pregnames
;
3318 if (env
->pregs
[PR_VR
] < 32) {
3319 pregnames
= pregnames_v10
;
3320 regnames
= regnames_v10
;
3322 pregnames
= pregnames_v32
;
3323 regnames
= regnames_v32
;
3326 cpu_fprintf(f
, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3327 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3328 env
->pc
, env
->pregs
[PR_CCS
], env
->btaken
, env
->btarget
,
3330 env
->cc_src
, env
->cc_dest
, env
->cc_result
, env
->cc_mask
);
3333 for (i
= 0; i
< 16; i
++) {
3334 cpu_fprintf(f
, "%s=%8.8x ", regnames
[i
], env
->regs
[i
]);
3335 if ((i
+ 1) % 4 == 0) {
3336 cpu_fprintf(f
, "\n");
3339 cpu_fprintf(f
, "\nspecial regs:\n");
3340 for (i
= 0; i
< 16; i
++) {
3341 cpu_fprintf(f
, "%s=%8.8x ", pregnames
[i
], env
->pregs
[i
]);
3342 if ((i
+ 1) % 4 == 0) {
3343 cpu_fprintf(f
, "\n");
3346 if (env
->pregs
[PR_VR
] >= 32) {
3347 uint32_t srs
= env
->pregs
[PR_SRS
];
3348 cpu_fprintf(f
, "\nsupport function regs bank %x:\n", srs
);
3349 if (srs
< ARRAY_SIZE(env
->sregs
)) {
3350 for (i
= 0; i
< 16; i
++) {
3351 cpu_fprintf(f
, "s%2.2d=%8.8x ",
3352 i
, env
->sregs
[srs
][i
]);
3353 if ((i
+ 1) % 4 == 0) {
3354 cpu_fprintf(f
, "\n");
3359 cpu_fprintf(f
, "\n\n");
3363 void cris_initialize_tcg(void)
3367 cc_x
= tcg_global_mem_new(cpu_env
,
3368 offsetof(CPUCRISState
, cc_x
), "cc_x");
3369 cc_src
= tcg_global_mem_new(cpu_env
,
3370 offsetof(CPUCRISState
, cc_src
), "cc_src");
3371 cc_dest
= tcg_global_mem_new(cpu_env
,
3372 offsetof(CPUCRISState
, cc_dest
),
3374 cc_result
= tcg_global_mem_new(cpu_env
,
3375 offsetof(CPUCRISState
, cc_result
),
3377 cc_op
= tcg_global_mem_new(cpu_env
,
3378 offsetof(CPUCRISState
, cc_op
), "cc_op");
3379 cc_size
= tcg_global_mem_new(cpu_env
,
3380 offsetof(CPUCRISState
, cc_size
),
3382 cc_mask
= tcg_global_mem_new(cpu_env
,
3383 offsetof(CPUCRISState
, cc_mask
),
3386 env_pc
= tcg_global_mem_new(cpu_env
,
3387 offsetof(CPUCRISState
, pc
),
3389 env_btarget
= tcg_global_mem_new(cpu_env
,
3390 offsetof(CPUCRISState
, btarget
),
3392 env_btaken
= tcg_global_mem_new(cpu_env
,
3393 offsetof(CPUCRISState
, btaken
),
3395 for (i
= 0; i
< 16; i
++) {
3396 cpu_R
[i
] = tcg_global_mem_new(cpu_env
,
3397 offsetof(CPUCRISState
, regs
[i
]),
3400 for (i
= 0; i
< 16; i
++) {
3401 cpu_PR
[i
] = tcg_global_mem_new(cpu_env
,
3402 offsetof(CPUCRISState
, pregs
[i
]),
3407 void restore_state_to_opc(CPUCRISState
*env
, TranslationBlock
*tb
,