2 #include "exec/gdbstub.h"
4 #include "qemu/host-utils.h"
5 #include "sysemu/arch_init.h"
6 #include "sysemu/sysemu.h"
7 #include "qemu/bitops.h"
8 #include "qemu/crc32c.h"
9 #include <zlib.h> /* For crc32 */
11 #ifndef CONFIG_USER_ONLY
12 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
13 int access_type
, int is_user
,
14 hwaddr
*phys_ptr
, int *prot
,
15 target_ulong
*page_size
);
17 /* Definitions for the PMCCNTR and PMCR registers */
23 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
27 /* VFP data registers are always little-endian. */
28 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
30 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
33 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
34 /* Aliases for Q regs. */
37 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
38 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
42 switch (reg
- nregs
) {
43 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
44 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
45 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
50 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
54 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
56 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
59 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
62 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
63 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
67 switch (reg
- nregs
) {
68 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
69 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
70 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
75 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
79 /* 128 bit FP register */
80 stfq_le_p(buf
, env
->vfp
.regs
[reg
* 2]);
81 stfq_le_p(buf
+ 8, env
->vfp
.regs
[reg
* 2 + 1]);
85 stl_p(buf
, vfp_get_fpsr(env
));
89 stl_p(buf
, vfp_get_fpcr(env
));
96 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
100 /* 128 bit FP register */
101 env
->vfp
.regs
[reg
* 2] = ldfq_le_p(buf
);
102 env
->vfp
.regs
[reg
* 2 + 1] = ldfq_le_p(buf
+ 8);
106 vfp_set_fpsr(env
, ldl_p(buf
));
110 vfp_set_fpcr(env
, ldl_p(buf
));
117 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
119 if (cpreg_field_is_64bit(ri
)) {
120 return CPREG_FIELD64(env
, ri
);
122 return CPREG_FIELD32(env
, ri
);
126 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
129 if (cpreg_field_is_64bit(ri
)) {
130 CPREG_FIELD64(env
, ri
) = value
;
132 CPREG_FIELD32(env
, ri
) = value
;
136 static uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
138 /* Raw read of a coprocessor register (as needed for migration, etc). */
139 if (ri
->type
& ARM_CP_CONST
) {
140 return ri
->resetvalue
;
141 } else if (ri
->raw_readfn
) {
142 return ri
->raw_readfn(env
, ri
);
143 } else if (ri
->readfn
) {
144 return ri
->readfn(env
, ri
);
146 return raw_read(env
, ri
);
150 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
153 /* Raw write of a coprocessor register (as needed for migration, etc).
154 * Note that constant registers are treated as write-ignored; the
155 * caller should check for success by whether a readback gives the
158 if (ri
->type
& ARM_CP_CONST
) {
160 } else if (ri
->raw_writefn
) {
161 ri
->raw_writefn(env
, ri
, v
);
162 } else if (ri
->writefn
) {
163 ri
->writefn(env
, ri
, v
);
165 raw_write(env
, ri
, v
);
169 bool write_cpustate_to_list(ARMCPU
*cpu
)
171 /* Write the coprocessor state from cpu->env to the (index,value) list. */
175 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
176 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
177 const ARMCPRegInfo
*ri
;
179 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
184 if (ri
->type
& ARM_CP_NO_MIGRATE
) {
187 cpu
->cpreg_values
[i
] = read_raw_cp_reg(&cpu
->env
, ri
);
192 bool write_list_to_cpustate(ARMCPU
*cpu
)
197 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
198 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
199 uint64_t v
= cpu
->cpreg_values
[i
];
200 const ARMCPRegInfo
*ri
;
202 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
207 if (ri
->type
& ARM_CP_NO_MIGRATE
) {
210 /* Write value and confirm it reads back as written
211 * (to catch read-only registers and partially read-only
212 * registers where the incoming migration value doesn't match)
214 write_raw_cp_reg(&cpu
->env
, ri
, v
);
215 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
222 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
224 ARMCPU
*cpu
= opaque
;
226 const ARMCPRegInfo
*ri
;
228 regidx
= *(uint32_t *)key
;
229 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
231 if (!(ri
->type
& ARM_CP_NO_MIGRATE
)) {
232 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
233 /* The value array need not be initialized at this point */
234 cpu
->cpreg_array_len
++;
238 static void count_cpreg(gpointer key
, gpointer opaque
)
240 ARMCPU
*cpu
= opaque
;
242 const ARMCPRegInfo
*ri
;
244 regidx
= *(uint32_t *)key
;
245 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
247 if (!(ri
->type
& ARM_CP_NO_MIGRATE
)) {
248 cpu
->cpreg_array_len
++;
252 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
254 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
255 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
266 static void cpreg_make_keylist(gpointer key
, gpointer value
, gpointer udata
)
268 GList
**plist
= udata
;
270 *plist
= g_list_prepend(*plist
, key
);
273 void init_cpreg_list(ARMCPU
*cpu
)
275 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
276 * Note that we require cpreg_tuples[] to be sorted by key ID.
281 g_hash_table_foreach(cpu
->cp_regs
, cpreg_make_keylist
, &keys
);
283 keys
= g_list_sort(keys
, cpreg_key_compare
);
285 cpu
->cpreg_array_len
= 0;
287 g_list_foreach(keys
, count_cpreg
, cpu
);
289 arraylen
= cpu
->cpreg_array_len
;
290 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
291 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
292 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
293 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
294 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
295 cpu
->cpreg_array_len
= 0;
297 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
299 assert(cpu
->cpreg_array_len
== arraylen
);
304 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
306 ARMCPU
*cpu
= arm_env_get_cpu(env
);
308 env
->cp15
.c3
= value
;
309 tlb_flush(CPU(cpu
), 1); /* Flush TLB as domain not tracked in TLB */
312 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
314 ARMCPU
*cpu
= arm_env_get_cpu(env
);
316 if (env
->cp15
.c13_fcse
!= value
) {
317 /* Unlike real hardware the qemu TLB uses virtual addresses,
318 * not modified virtual addresses, so this causes a TLB flush.
320 tlb_flush(CPU(cpu
), 1);
321 env
->cp15
.c13_fcse
= value
;
325 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
328 ARMCPU
*cpu
= arm_env_get_cpu(env
);
330 if (env
->cp15
.c13_context
!= value
&& !arm_feature(env
, ARM_FEATURE_MPU
)) {
331 /* For VMSA (when not using the LPAE long descriptor page table
332 * format) this register includes the ASID, so do a TLB flush.
333 * For PMSA it is purely a process ID and no action is needed.
335 tlb_flush(CPU(cpu
), 1);
337 env
->cp15
.c13_context
= value
;
340 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
343 /* Invalidate all (TLBIALL) */
344 ARMCPU
*cpu
= arm_env_get_cpu(env
);
346 tlb_flush(CPU(cpu
), 1);
349 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
352 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
353 ARMCPU
*cpu
= arm_env_get_cpu(env
);
355 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
358 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
361 /* Invalidate by ASID (TLBIASID) */
362 ARMCPU
*cpu
= arm_env_get_cpu(env
);
364 tlb_flush(CPU(cpu
), value
== 0);
367 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
370 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
371 ARMCPU
*cpu
= arm_env_get_cpu(env
);
373 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
376 static const ARMCPRegInfo cp_reginfo
[] = {
377 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
378 * version" bits will read as a reserved value, which should cause
379 * Linux to not try to use the debug hardware.
381 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
382 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
383 /* MMU Domain access control / MPU write buffer control */
384 { .name
= "DACR", .cp
= 15,
385 .crn
= 3, .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
386 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c3
),
387 .resetvalue
= 0, .writefn
= dacr_write
, .raw_writefn
= raw_write
, },
388 { .name
= "FCSEIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 0,
389 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
390 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
391 { .name
= "CONTEXTIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 1,
392 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_context
),
393 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
394 /* ??? This covers not just the impdef TLB lockdown registers but also
395 * some v7VMSA registers relating to TEX remap, so it is overly broad.
397 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= CP_ANY
,
398 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
399 /* MMU TLB control. Note that the wildcarding means we cover not just
400 * the unified TLB ops but also the dside/iside/inner-shareable variants.
402 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
403 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
404 .type
= ARM_CP_NO_MIGRATE
},
405 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
406 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
407 .type
= ARM_CP_NO_MIGRATE
},
408 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
409 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
410 .type
= ARM_CP_NO_MIGRATE
},
411 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
412 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
413 .type
= ARM_CP_NO_MIGRATE
},
414 /* Cache maintenance ops; some of this space may be overridden later. */
415 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
416 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
417 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
421 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
422 /* Not all pre-v6 cores implemented this WFI, so this is slightly
425 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
426 .access
= PL1_W
, .type
= ARM_CP_WFI
},
430 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
431 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
432 * is UNPREDICTABLE; we choose to NOP as most implementations do).
434 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
435 .access
= PL1_W
, .type
= ARM_CP_WFI
},
436 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
437 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
438 * OMAPCP will override this space.
440 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
441 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
443 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
444 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
446 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
447 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
448 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
453 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
456 if (env
->cp15
.c1_coproc
!= value
) {
457 env
->cp15
.c1_coproc
= value
;
458 /* ??? Is this safe when called from within a TB? */
463 static const ARMCPRegInfo v6_cp_reginfo
[] = {
464 /* prefetch by MVA in v6, NOP in v7 */
465 { .name
= "MVA_prefetch",
466 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
467 .access
= PL1_W
, .type
= ARM_CP_NOP
},
468 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
469 .access
= PL0_W
, .type
= ARM_CP_NOP
},
470 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
471 .access
= PL0_W
, .type
= ARM_CP_NOP
},
472 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
473 .access
= PL0_W
, .type
= ARM_CP_NOP
},
474 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
475 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_insn
),
477 /* Watchpoint Fault Address Register : should actually only be present
478 * for 1136, 1176, 11MPCore.
480 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
481 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
482 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
483 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2,
484 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_coproc
),
485 .resetvalue
= 0, .writefn
= cpacr_write
},
489 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
491 /* Perfomance monitor registers user accessibility is controlled
494 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
495 return CP_ACCESS_TRAP
;
500 #ifndef CONFIG_USER_ONLY
501 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
504 /* Don't computer the number of ticks in user mode */
507 temp_ticks
= qemu_clock_get_us(QEMU_CLOCK_VIRTUAL
) *
508 get_ticks_per_sec() / 1000000;
510 if (env
->cp15
.c9_pmcr
& PMCRE
) {
511 /* If the counter is enabled */
512 if (env
->cp15
.c9_pmcr
& PMCRD
) {
513 /* Increment once every 64 processor clock cycles */
514 env
->cp15
.c15_ccnt
= (temp_ticks
/64) - env
->cp15
.c15_ccnt
;
516 env
->cp15
.c15_ccnt
= temp_ticks
- env
->cp15
.c15_ccnt
;
521 /* The counter has been reset */
522 env
->cp15
.c15_ccnt
= 0;
525 /* only the DP, X, D and E bits are writable */
526 env
->cp15
.c9_pmcr
&= ~0x39;
527 env
->cp15
.c9_pmcr
|= (value
& 0x39);
529 if (env
->cp15
.c9_pmcr
& PMCRE
) {
530 if (env
->cp15
.c9_pmcr
& PMCRD
) {
531 /* Increment once every 64 processor clock cycles */
534 env
->cp15
.c15_ccnt
= temp_ticks
- env
->cp15
.c15_ccnt
;
538 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
540 uint32_t total_ticks
;
542 if (!(env
->cp15
.c9_pmcr
& PMCRE
)) {
543 /* Counter is disabled, do not change value */
544 return env
->cp15
.c15_ccnt
;
547 total_ticks
= qemu_clock_get_us(QEMU_CLOCK_VIRTUAL
) *
548 get_ticks_per_sec() / 1000000;
550 if (env
->cp15
.c9_pmcr
& PMCRD
) {
551 /* Increment once every 64 processor clock cycles */
554 return total_ticks
- env
->cp15
.c15_ccnt
;
557 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
560 uint32_t total_ticks
;
562 if (!(env
->cp15
.c9_pmcr
& PMCRE
)) {
563 /* Counter is disabled, set the absolute value */
564 env
->cp15
.c15_ccnt
= value
;
568 total_ticks
= qemu_clock_get_us(QEMU_CLOCK_VIRTUAL
) *
569 get_ticks_per_sec() / 1000000;
571 if (env
->cp15
.c9_pmcr
& PMCRD
) {
572 /* Increment once every 64 processor clock cycles */
575 env
->cp15
.c15_ccnt
= total_ticks
- value
;
579 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
583 env
->cp15
.c9_pmcnten
|= value
;
586 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
590 env
->cp15
.c9_pmcnten
&= ~value
;
593 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
596 env
->cp15
.c9_pmovsr
&= ~value
;
599 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
602 env
->cp15
.c9_pmxevtyper
= value
& 0xff;
605 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
608 env
->cp15
.c9_pmuserenr
= value
& 1;
611 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
614 /* We have no event counters so only the C bit can be changed */
616 env
->cp15
.c9_pminten
|= value
;
619 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
623 env
->cp15
.c9_pminten
&= ~value
;
626 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
629 /* Note that even though the AArch64 view of this register has bits
630 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
631 * architectural requirements for bits which are RES0 only in some
632 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
633 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
635 env
->cp15
.c12_vbar
= value
& ~0x1Ful
;
638 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
640 ARMCPU
*cpu
= arm_env_get_cpu(env
);
641 return cpu
->ccsidr
[env
->cp15
.c0_cssel
];
644 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
647 env
->cp15
.c0_cssel
= value
& 0xf;
650 static const ARMCPRegInfo v7_cp_reginfo
[] = {
651 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
654 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
655 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
656 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
657 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
658 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
659 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
660 .access
= PL1_W
, .type
= ARM_CP_NOP
},
661 /* Performance monitors are implementation defined in v7,
662 * but with an ARM recommended set of registers, which we
663 * follow (although we don't actually implement any counters)
665 * Performance registers fall into three categories:
666 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
667 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
668 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
669 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
670 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
672 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
673 .access
= PL0_RW
, .resetvalue
= 0,
674 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
675 .writefn
= pmcntenset_write
,
676 .accessfn
= pmreg_access
,
677 .raw_writefn
= raw_write
},
678 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
679 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
680 .accessfn
= pmreg_access
,
681 .writefn
= pmcntenclr_write
,
682 .type
= ARM_CP_NO_MIGRATE
},
683 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
684 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
685 .accessfn
= pmreg_access
,
686 .writefn
= pmovsr_write
,
687 .raw_writefn
= raw_write
},
688 /* Unimplemented so WI. */
689 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
690 .access
= PL0_W
, .accessfn
= pmreg_access
, .type
= ARM_CP_NOP
},
691 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
692 * We choose to RAZ/WI.
694 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
695 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
696 .accessfn
= pmreg_access
},
697 #ifndef CONFIG_USER_ONLY
698 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
699 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_IO
,
700 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
701 .accessfn
= pmreg_access
},
703 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
705 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmxevtyper
),
706 .accessfn
= pmreg_access
, .writefn
= pmxevtyper_write
,
707 .raw_writefn
= raw_write
},
708 /* Unimplemented, RAZ/WI. */
709 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
710 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
711 .accessfn
= pmreg_access
},
712 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
713 .access
= PL0_R
| PL1_RW
,
714 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
716 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
717 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
719 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
721 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
722 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
723 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
,
724 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
725 .resetvalue
= 0, .writefn
= pmintenclr_write
, },
726 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
727 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
728 .access
= PL1_RW
, .writefn
= vbar_write
,
729 .fieldoffset
= offsetof(CPUARMState
, cp15
.c12_vbar
),
731 { .name
= "SCR", .cp
= 15, .crn
= 1, .crm
= 1, .opc1
= 0, .opc2
= 0,
732 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_scr
),
734 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
735 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
736 .access
= PL1_R
, .readfn
= ccsidr_read
, .type
= ARM_CP_NO_MIGRATE
},
737 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
738 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
739 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cssel
),
740 .writefn
= csselr_write
, .resetvalue
= 0 },
741 /* Auxiliary ID register: this actually has an IMPDEF value but for now
742 * just RAZ for all cores:
744 { .name
= "AIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 7,
745 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
746 /* MAIR can just read-as-written because we don't implement caches
747 * and so don't need to care about memory attributes.
749 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
750 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
751 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el1
),
753 /* For non-long-descriptor page tables these are PRRR and NMRR;
754 * regardless they still act as reads-as-written for QEMU.
755 * The override is necessary because of the overly-broad TLB_LOCKDOWN
758 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
, .type
= ARM_CP_OVERRIDE
,
759 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0, .access
= PL1_RW
,
760 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mair_el1
),
761 .resetfn
= arm_cp_reset_ignore
},
762 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
, .type
= ARM_CP_OVERRIDE
,
763 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1, .access
= PL1_RW
,
764 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el1
),
765 .resetfn
= arm_cp_reset_ignore
},
769 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
776 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
778 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
779 return CP_ACCESS_TRAP
;
784 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
785 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
786 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
788 .writefn
= teecr_write
},
789 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
790 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
791 .accessfn
= teehbr_access
, .resetvalue
= 0 },
795 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
796 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
797 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
799 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el0
), .resetvalue
= 0 },
800 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
802 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.tpidr_el0
),
803 .resetfn
= arm_cp_reset_ignore
},
804 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
805 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
806 .access
= PL0_R
|PL1_W
,
807 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el0
), .resetvalue
= 0 },
808 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
809 .access
= PL0_R
|PL1_W
,
810 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.tpidrro_el0
),
811 .resetfn
= arm_cp_reset_ignore
},
812 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
813 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
815 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el1
), .resetvalue
= 0 },
819 #ifndef CONFIG_USER_ONLY
821 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
823 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
824 if (arm_current_pl(env
) == 0 && !extract32(env
->cp15
.c14_cntkctl
, 0, 2)) {
825 return CP_ACCESS_TRAP
;
830 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
)
832 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
833 if (arm_current_pl(env
) == 0 &&
834 !extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
835 return CP_ACCESS_TRAP
;
840 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
)
842 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
843 * EL0[PV]TEN is zero.
845 if (arm_current_pl(env
) == 0 &&
846 !extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
847 return CP_ACCESS_TRAP
;
852 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
853 const ARMCPRegInfo
*ri
)
855 return gt_counter_access(env
, GTIMER_PHYS
);
858 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
859 const ARMCPRegInfo
*ri
)
861 return gt_counter_access(env
, GTIMER_VIRT
);
864 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
866 return gt_timer_access(env
, GTIMER_PHYS
);
869 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
871 return gt_timer_access(env
, GTIMER_VIRT
);
874 static uint64_t gt_get_countervalue(CPUARMState
*env
)
876 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / GTIMER_SCALE
;
879 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
881 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
884 /* Timer enabled: calculate and set current ISTATUS, irq, and
885 * reset timer to when ISTATUS next has to change
887 uint64_t count
= gt_get_countervalue(&cpu
->env
);
888 /* Note that this must be unsigned 64 bit arithmetic: */
889 int istatus
= count
>= gt
->cval
;
892 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
893 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
],
894 (istatus
&& !(gt
->ctl
& 2)));
896 /* Next transition is when count rolls back over to zero */
897 nexttick
= UINT64_MAX
;
899 /* Next transition is when we hit cval */
902 /* Note that the desired next expiry time might be beyond the
903 * signed-64-bit range of a QEMUTimer -- in this case we just
904 * set the timer for as far in the future as possible. When the
905 * timer expires we will reset the timer for any remaining period.
907 if (nexttick
> INT64_MAX
/ GTIMER_SCALE
) {
908 nexttick
= INT64_MAX
/ GTIMER_SCALE
;
910 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
912 /* Timer disabled: ISTATUS and timer output always clear */
914 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
915 timer_del(cpu
->gt_timer
[timeridx
]);
919 static void gt_cnt_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
921 ARMCPU
*cpu
= arm_env_get_cpu(env
);
922 int timeridx
= ri
->opc1
& 1;
924 timer_del(cpu
->gt_timer
[timeridx
]);
927 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
929 return gt_get_countervalue(env
);
932 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
935 int timeridx
= ri
->opc1
& 1;
937 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
938 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
941 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
943 int timeridx
= ri
->crm
& 1;
945 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
946 gt_get_countervalue(env
));
949 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
952 int timeridx
= ri
->crm
& 1;
954 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) +
955 + sextract64(value
, 0, 32);
956 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
959 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
962 ARMCPU
*cpu
= arm_env_get_cpu(env
);
963 int timeridx
= ri
->crm
& 1;
964 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
966 env
->cp15
.c14_timer
[timeridx
].ctl
= value
& 3;
967 if ((oldval
^ value
) & 1) {
969 gt_recalc_timer(cpu
, timeridx
);
970 } else if ((oldval
& value
) & 2) {
971 /* IMASK toggled: don't need to recalculate,
972 * just set the interrupt line based on ISTATUS
974 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
],
975 (oldval
& 4) && (value
& 2));
979 void arm_gt_ptimer_cb(void *opaque
)
981 ARMCPU
*cpu
= opaque
;
983 gt_recalc_timer(cpu
, GTIMER_PHYS
);
986 void arm_gt_vtimer_cb(void *opaque
)
988 ARMCPU
*cpu
= opaque
;
990 gt_recalc_timer(cpu
, GTIMER_VIRT
);
993 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
994 /* Note that CNTFRQ is purely reads-as-written for the benefit
995 * of software; writing it doesn't actually change the timer frequency.
996 * Our reset value matches the fixed frequency we implement the timer at.
998 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
999 .type
= ARM_CP_NO_MIGRATE
,
1000 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1001 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
1002 .resetfn
= arm_cp_reset_ignore
,
1004 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
1005 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
1006 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1007 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
1008 .resetvalue
= (1000 * 1000 * 1000) / GTIMER_SCALE
,
1010 /* overall control: mostly access permissions */
1011 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
1012 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
1014 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
1017 /* per-timer control */
1018 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
1019 .type
= ARM_CP_IO
| ARM_CP_NO_MIGRATE
, .access
= PL1_RW
| PL0_R
,
1020 .accessfn
= gt_ptimer_access
,
1021 .fieldoffset
= offsetoflow32(CPUARMState
,
1022 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1023 .resetfn
= arm_cp_reset_ignore
,
1024 .writefn
= gt_ctl_write
, .raw_writefn
= raw_write
,
1026 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1027 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
1028 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1029 .accessfn
= gt_ptimer_access
,
1030 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1032 .writefn
= gt_ctl_write
, .raw_writefn
= raw_write
,
1034 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
1035 .type
= ARM_CP_IO
| ARM_CP_NO_MIGRATE
, .access
= PL1_RW
| PL0_R
,
1036 .accessfn
= gt_vtimer_access
,
1037 .fieldoffset
= offsetoflow32(CPUARMState
,
1038 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1039 .resetfn
= arm_cp_reset_ignore
,
1040 .writefn
= gt_ctl_write
, .raw_writefn
= raw_write
,
1042 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1043 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
1044 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1045 .accessfn
= gt_vtimer_access
,
1046 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1048 .writefn
= gt_ctl_write
, .raw_writefn
= raw_write
,
1050 /* TimerValue views: a 32 bit downcounting view of the underlying state */
1051 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
1052 .type
= ARM_CP_NO_MIGRATE
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1053 .accessfn
= gt_ptimer_access
,
1054 .readfn
= gt_tval_read
, .writefn
= gt_tval_write
,
1056 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1057 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
1058 .type
= ARM_CP_NO_MIGRATE
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1059 .readfn
= gt_tval_read
, .writefn
= gt_tval_write
,
1061 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
1062 .type
= ARM_CP_NO_MIGRATE
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1063 .accessfn
= gt_vtimer_access
,
1064 .readfn
= gt_tval_read
, .writefn
= gt_tval_write
,
1066 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1067 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
1068 .type
= ARM_CP_NO_MIGRATE
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1069 .readfn
= gt_tval_read
, .writefn
= gt_tval_write
,
1071 /* The counter itself */
1072 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
1073 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_MIGRATE
| ARM_CP_IO
,
1074 .accessfn
= gt_pct_access
,
1075 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
1077 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
1078 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
1079 .access
= PL0_R
, .type
= ARM_CP_NO_MIGRATE
| ARM_CP_IO
,
1080 .accessfn
= gt_pct_access
,
1081 .readfn
= gt_cnt_read
, .resetfn
= gt_cnt_reset
,
1083 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
1084 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_MIGRATE
| ARM_CP_IO
,
1085 .accessfn
= gt_vct_access
,
1086 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
1088 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
1089 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
1090 .access
= PL0_R
, .type
= ARM_CP_NO_MIGRATE
| ARM_CP_IO
,
1091 .accessfn
= gt_vct_access
,
1092 .readfn
= gt_cnt_read
, .resetfn
= gt_cnt_reset
,
1094 /* Comparison value, indicating when the timer goes off */
1095 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
1096 .access
= PL1_RW
| PL0_R
,
1097 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_NO_MIGRATE
,
1098 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
1099 .accessfn
= gt_ptimer_access
, .resetfn
= arm_cp_reset_ignore
,
1100 .writefn
= gt_cval_write
, .raw_writefn
= raw_write
,
1102 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1103 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
1104 .access
= PL1_RW
| PL0_R
,
1106 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
1107 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
1108 .writefn
= gt_cval_write
, .raw_writefn
= raw_write
,
1110 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
1111 .access
= PL1_RW
| PL0_R
,
1112 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_NO_MIGRATE
,
1113 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
1114 .accessfn
= gt_vtimer_access
, .resetfn
= arm_cp_reset_ignore
,
1115 .writefn
= gt_cval_write
, .raw_writefn
= raw_write
,
1117 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1118 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
1119 .access
= PL1_RW
| PL0_R
,
1121 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
1122 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
1123 .writefn
= gt_cval_write
, .raw_writefn
= raw_write
,
1129 /* In user-mode none of the generic timer registers are accessible,
1130 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1131 * so instead just don't register any of them.
1133 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
1139 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1141 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1142 env
->cp15
.c7_par
= value
;
1143 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
1144 env
->cp15
.c7_par
= value
& 0xfffff6ff;
1146 env
->cp15
.c7_par
= value
& 0xfffff1ff;
1150 #ifndef CONFIG_USER_ONLY
1151 /* get_phys_addr() isn't present for user-mode-only targets */
1153 /* Return true if extended addresses are enabled, ie this is an
1154 * LPAE implementation and we are using the long-descriptor translation
1155 * table format because the TTBCR EAE bit is set.
1157 static inline bool extended_addresses_enabled(CPUARMState
*env
)
1159 return arm_feature(env
, ARM_FEATURE_LPAE
)
1160 && (env
->cp15
.c2_control
& (1U << 31));
1163 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1166 /* Other states are only available with TrustZone; in
1167 * a non-TZ implementation these registers don't exist
1168 * at all, which is an Uncategorized trap. This underdecoding
1169 * is safe because the reginfo is NO_MIGRATE.
1171 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1173 return CP_ACCESS_OK
;
1176 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1179 target_ulong page_size
;
1181 int ret
, is_user
= ri
->opc2
& 2;
1182 int access_type
= ri
->opc2
& 1;
1184 ret
= get_phys_addr(env
, value
, access_type
, is_user
,
1185 &phys_addr
, &prot
, &page_size
);
1186 if (extended_addresses_enabled(env
)) {
1187 /* ret is a DFSR/IFSR value for the long descriptor
1188 * translation table format, but with WnR always clear.
1189 * Convert it to a 64-bit PAR.
1191 uint64_t par64
= (1 << 11); /* LPAE bit always set */
1193 par64
|= phys_addr
& ~0xfffULL
;
1194 /* We don't set the ATTR or SH fields in the PAR. */
1197 par64
|= (ret
& 0x3f) << 1; /* FS */
1198 /* Note that S2WLK and FSTAGE are always zero, because we don't
1199 * implement virtualization and therefore there can't be a stage 2
1203 env
->cp15
.c7_par
= par64
;
1204 env
->cp15
.c7_par_hi
= par64
>> 32;
1206 /* ret is a DFSR/IFSR value for the short descriptor
1207 * translation table format (with WnR always clear).
1208 * Convert it to a 32-bit PAR.
1211 /* We do not set any attribute bits in the PAR */
1212 if (page_size
== (1 << 24)
1213 && arm_feature(env
, ARM_FEATURE_V7
)) {
1214 env
->cp15
.c7_par
= (phys_addr
& 0xff000000) | 1 << 1;
1216 env
->cp15
.c7_par
= phys_addr
& 0xfffff000;
1219 env
->cp15
.c7_par
= ((ret
& (1 << 10)) >> 5) |
1220 ((ret
& (1 << 12)) >> 6) |
1221 ((ret
& 0xf) << 1) | 1;
1223 env
->cp15
.c7_par_hi
= 0;
1228 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
1229 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
1230 .access
= PL1_RW
, .resetvalue
= 0,
1231 .fieldoffset
= offsetof(CPUARMState
, cp15
.c7_par
),
1232 .writefn
= par_write
},
1233 #ifndef CONFIG_USER_ONLY
1234 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
1235 .access
= PL1_W
, .accessfn
= ats_access
,
1236 .writefn
= ats_write
, .type
= ARM_CP_NO_MIGRATE
},
1241 /* Return basic MPU access permission bits. */
1242 static uint32_t simple_mpu_ap_bits(uint32_t val
)
1249 for (i
= 0; i
< 16; i
+= 2) {
1250 ret
|= (val
>> i
) & mask
;
1256 /* Pad basic MPU access permission bits to extended format. */
1257 static uint32_t extended_mpu_ap_bits(uint32_t val
)
1264 for (i
= 0; i
< 16; i
+= 2) {
1265 ret
|= (val
& mask
) << i
;
1271 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1274 env
->cp15
.c5_data
= extended_mpu_ap_bits(value
);
1277 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1279 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1282 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1285 env
->cp15
.c5_insn
= extended_mpu_ap_bits(value
);
1288 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1290 return simple_mpu_ap_bits(env
->cp15
.c5_insn
);
1293 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
1294 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
1295 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
,
1296 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0,
1297 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
1298 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
1299 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
,
1300 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0,
1301 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
1302 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
1304 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
1305 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
1307 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
1308 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
1310 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
1311 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
1313 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
1314 /* Protection region base and size registers */
1315 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
1316 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1317 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
1318 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
1319 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1320 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
1321 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
1322 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1323 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
1324 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
1325 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1326 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
1327 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
1328 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1329 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
1330 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
1331 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1332 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
1333 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
1334 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1335 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
1336 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
1337 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1338 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
1342 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1345 int maskshift
= extract32(value
, 0, 3);
1347 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& (1 << 31))) {
1348 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
1352 /* Note that we always calculate c2_mask and c2_base_mask, but
1353 * they are only used for short-descriptor tables (ie if EAE is 0);
1354 * for long-descriptor tables the TTBCR fields are used differently
1355 * and the c2_mask and c2_base_mask values are meaningless.
1357 env
->cp15
.c2_control
= value
;
1358 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
1359 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
1362 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1365 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1367 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1368 /* With LPAE the TTBCR could result in a change of ASID
1369 * via the TTBCR.A1 bit, so do a TLB flush.
1371 tlb_flush(CPU(cpu
), 1);
1373 vmsa_ttbcr_raw_write(env
, ri
, value
);
1376 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1378 env
->cp15
.c2_base_mask
= 0xffffc000u
;
1379 env
->cp15
.c2_control
= 0;
1380 env
->cp15
.c2_mask
= 0;
1383 static void vmsa_tcr_el1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1386 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1388 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1389 tlb_flush(CPU(cpu
), 1);
1390 env
->cp15
.c2_control
= value
;
1393 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1396 /* 64 bit accesses to the TTBRs can change the ASID and so we
1397 * must flush the TLB.
1399 if (cpreg_field_is_64bit(ri
)) {
1400 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1402 tlb_flush(CPU(cpu
), 1);
1404 raw_write(env
, ri
, value
);
1407 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
1408 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
1410 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
1411 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
1413 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
1414 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
1415 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
1416 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el1
),
1417 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0 },
1418 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
1419 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
1420 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el1
),
1421 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0 },
1422 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
1423 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
1424 .access
= PL1_RW
, .writefn
= vmsa_tcr_el1_write
,
1425 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
1426 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_control
) },
1427 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
1428 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
, .writefn
= vmsa_ttbcr_write
,
1429 .resetfn
= arm_cp_reset_ignore
, .raw_writefn
= vmsa_ttbcr_raw_write
,
1430 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c2_control
) },
1431 { .name
= "DFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
1432 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_data
),
1437 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1440 env
->cp15
.c15_ticonfig
= value
& 0xe7;
1441 /* The OS_TYPE bit in this register changes the reported CPUID! */
1442 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
1443 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
1446 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1449 env
->cp15
.c15_threadid
= value
& 0xffff;
1452 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1455 /* Wait-for-interrupt (deprecated) */
1456 cpu_interrupt(CPU(arm_env_get_cpu(env
)), CPU_INTERRUPT_HALT
);
1459 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1462 /* On OMAP there are registers indicating the max/min index of dcache lines
1463 * containing a dirty line; cache flush operations have to reset these.
1465 env
->cp15
.c15_i_max
= 0x000;
1466 env
->cp15
.c15_i_min
= 0xff0;
1469 static const ARMCPRegInfo omap_cp_reginfo
[] = {
1470 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
1471 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
1472 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
1473 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
1474 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
1475 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
1477 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
1478 .writefn
= omap_ticonfig_write
},
1479 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
1481 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
1482 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
1483 .access
= PL1_RW
, .resetvalue
= 0xff0,
1484 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
1485 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
1487 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
1488 .writefn
= omap_threadid_write
},
1489 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
1490 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
1491 .type
= ARM_CP_NO_MIGRATE
,
1492 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
1493 /* TODO: Peripheral port remap register:
1494 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1495 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1498 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
1499 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
1500 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_MIGRATE
,
1501 .writefn
= omap_cachemaint_write
},
1502 { .name
= "C9", .cp
= 15, .crn
= 9,
1503 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
1504 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
1508 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1512 if (env
->cp15
.c15_cpar
!= value
) {
1513 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1515 env
->cp15
.c15_cpar
= value
;
1519 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
1520 { .name
= "XSCALE_CPAR",
1521 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
1522 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
1523 .writefn
= xscale_cpar_write
, },
1524 { .name
= "XSCALE_AUXCR",
1525 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
1526 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
1531 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
1532 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1533 * implementation of this implementation-defined space.
1534 * Ideally this should eventually disappear in favour of actually
1535 * implementing the correct behaviour for all cores.
1537 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
1538 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
1540 .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
| ARM_CP_OVERRIDE
,
1545 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
1546 /* Cache status: RAZ because we have no cache so it's always clean */
1547 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
1548 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
1553 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
1554 /* We never have a a block transfer operation in progress */
1555 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
1556 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
1558 /* The cache ops themselves: these all NOP for QEMU */
1559 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
1560 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1561 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
1562 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1563 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
1564 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1565 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
1566 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1567 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
1568 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1569 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
1570 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1574 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
1575 /* The cache test-and-clean instructions always return (1 << 30)
1576 * to indicate that there are no dirty cache lines.
1578 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
1579 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
1580 .resetvalue
= (1 << 30) },
1581 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
1582 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
1583 .resetvalue
= (1 << 30) },
1587 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
1588 /* Ignore ReadBuffer accesses */
1589 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
1590 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
1591 .access
= PL1_RW
, .resetvalue
= 0,
1592 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_MIGRATE
},
1596 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1598 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
1599 uint32_t mpidr
= cs
->cpu_index
;
1600 /* We don't support setting cluster ID ([8..11]) (known as Aff1
1601 * in later ARM ARM versions), or any of the higher affinity level fields,
1602 * so these bits always RAZ.
1604 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
1605 mpidr
|= (1U << 31);
1606 /* Cores which are uniprocessor (non-coherent)
1607 * but still implement the MP extensions set
1608 * bit 30. (For instance, A9UP.) However we do
1609 * not currently model any of those cores.
1615 static const ARMCPRegInfo mpidr_cp_reginfo
[] = {
1616 { .name
= "MPIDR", .state
= ARM_CP_STATE_BOTH
,
1617 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
1618 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_MIGRATE
},
1622 static uint64_t par64_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1624 return ((uint64_t)env
->cp15
.c7_par_hi
<< 32) | env
->cp15
.c7_par
;
1627 static void par64_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1630 env
->cp15
.c7_par_hi
= value
>> 32;
1631 env
->cp15
.c7_par
= value
;
1634 static void par64_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1636 env
->cp15
.c7_par_hi
= 0;
1637 env
->cp15
.c7_par
= 0;
1640 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
1641 /* NOP AMAIR0/1: the override is because these clash with the rather
1642 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1644 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
1645 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
1646 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
,
1648 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
1649 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
1650 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
,
1652 /* 64 bit access versions of the (dummy) debug registers */
1653 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
1654 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
1655 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
1656 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
1657 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
1658 .access
= PL1_RW
, .type
= ARM_CP_64BIT
,
1659 .readfn
= par64_read
, .writefn
= par64_write
, .resetfn
= par64_reset
},
1660 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
1661 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_NO_MIGRATE
,
1662 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el1
),
1663 .writefn
= vmsa_ttbr_write
, .resetfn
= arm_cp_reset_ignore
},
1664 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
1665 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_NO_MIGRATE
,
1666 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el1
),
1667 .writefn
= vmsa_ttbr_write
, .resetfn
= arm_cp_reset_ignore
},
1671 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1673 return vfp_get_fpcr(env
);
1676 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1679 vfp_set_fpcr(env
, value
);
1682 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1684 return vfp_get_fpsr(env
);
1687 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1690 vfp_set_fpsr(env
, value
);
1693 static CPAccessResult
aa64_cacheop_access(CPUARMState
*env
,
1694 const ARMCPRegInfo
*ri
)
1696 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
1697 * SCTLR_EL1.UCI is set.
1699 if (arm_current_pl(env
) == 0 && !(env
->cp15
.c1_sys
& SCTLR_UCI
)) {
1700 return CP_ACCESS_TRAP
;
1702 return CP_ACCESS_OK
;
1705 static void tlbi_aa64_va_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1708 /* Invalidate by VA (AArch64 version) */
1709 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1710 uint64_t pageaddr
= value
<< 12;
1711 tlb_flush_page(CPU(cpu
), pageaddr
);
1714 static void tlbi_aa64_vaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1717 /* Invalidate by VA, all ASIDs (AArch64 version) */
1718 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1719 uint64_t pageaddr
= value
<< 12;
1720 tlb_flush_page(CPU(cpu
), pageaddr
);
1723 static void tlbi_aa64_asid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1726 /* Invalidate by ASID (AArch64 version) */
1727 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1728 int asid
= extract64(value
, 48, 16);
1729 tlb_flush(CPU(cpu
), asid
== 0);
1732 static const ARMCPRegInfo v8_cp_reginfo
[] = {
1733 /* Minimal set of EL0-visible registers. This will need to be expanded
1734 * significantly for system emulation of AArch64 CPUs.
1736 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
1737 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
1738 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
1739 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
1740 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
1741 .access
= PL0_RW
, .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
1742 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
1743 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
1744 .access
= PL0_RW
, .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
1745 /* Prohibit use of DC ZVA. OPTME: implement DC ZVA and allow its use.
1746 * For system mode the DZP bit here will need to be computed, not constant.
1748 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
1749 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
1750 .access
= PL0_R
, .type
= ARM_CP_CONST
,
1751 .resetvalue
= 0x10 },
1752 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
1753 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
1754 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
1755 /* Cache ops: all NOPs since we don't emulate caches */
1756 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
1757 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
1758 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1759 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
1760 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
1761 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1762 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
1763 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
1764 .access
= PL0_W
, .type
= ARM_CP_NOP
,
1765 .accessfn
= aa64_cacheop_access
},
1766 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
1767 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
1768 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1769 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
1770 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
1771 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1772 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
1773 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
1774 .access
= PL0_W
, .type
= ARM_CP_NOP
,
1775 .accessfn
= aa64_cacheop_access
},
1776 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
1777 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
1778 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1779 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
1780 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
1781 .access
= PL0_W
, .type
= ARM_CP_NOP
,
1782 .accessfn
= aa64_cacheop_access
},
1783 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
1784 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
1785 .access
= PL0_W
, .type
= ARM_CP_NOP
,
1786 .accessfn
= aa64_cacheop_access
},
1787 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
1788 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
1789 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1790 /* TLBI operations */
1791 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
1792 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
1793 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1794 .writefn
= tlbiall_write
},
1795 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
1796 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
1797 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1798 .writefn
= tlbi_aa64_va_write
},
1799 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
1800 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
1801 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1802 .writefn
= tlbi_aa64_asid_write
},
1803 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
1804 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
1805 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1806 .writefn
= tlbi_aa64_vaa_write
},
1807 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
1808 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
1809 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1810 .writefn
= tlbi_aa64_va_write
},
1811 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
1812 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
1813 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1814 .writefn
= tlbi_aa64_vaa_write
},
1815 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
1816 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
1817 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1818 .writefn
= tlbiall_write
},
1819 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
1820 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
1821 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1822 .writefn
= tlbi_aa64_va_write
},
1823 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
1824 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
1825 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1826 .writefn
= tlbi_aa64_asid_write
},
1827 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
1828 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
1829 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1830 .writefn
= tlbi_aa64_vaa_write
},
1831 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
1832 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
1833 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1834 .writefn
= tlbi_aa64_va_write
},
1835 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
1836 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
1837 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1838 .writefn
= tlbi_aa64_vaa_write
},
1839 /* Dummy implementation of monitor debug system control register:
1840 * we don't support debug.
1842 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_AA64
,
1843 .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
1844 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1845 /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
1846 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_AA64
,
1847 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
1848 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1852 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1855 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1857 env
->cp15
.c1_sys
= value
;
1858 /* ??? Lots of these bits are not implemented. */
1859 /* This may enable/disable the MMU, so do a TLB flush. */
1860 tlb_flush(CPU(cpu
), 1);
1863 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1865 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
1866 * but the AArch32 CTR has its own reginfo struct)
1868 if (arm_current_pl(env
) == 0 && !(env
->cp15
.c1_sys
& SCTLR_UCT
)) {
1869 return CP_ACCESS_TRAP
;
1871 return CP_ACCESS_OK
;
1874 static void define_aarch64_debug_regs(ARMCPU
*cpu
)
1876 /* Define breakpoint and watchpoint registers. These do nothing
1877 * but read as written, for now.
1881 for (i
= 0; i
< 16; i
++) {
1882 ARMCPRegInfo dbgregs
[] = {
1883 { .name
= "DBGBVR", .state
= ARM_CP_STATE_AA64
,
1884 .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
1886 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]) },
1887 { .name
= "DBGBCR", .state
= ARM_CP_STATE_AA64
,
1888 .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
1890 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]) },
1891 { .name
= "DBGWVR", .state
= ARM_CP_STATE_AA64
,
1892 .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
1894 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]) },
1895 { .name
= "DBGWCR", .state
= ARM_CP_STATE_AA64
,
1896 .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
1898 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]) },
1901 define_arm_cp_regs(cpu
, dbgregs
);
1905 void register_cp_regs_for_features(ARMCPU
*cpu
)
1907 /* Register all the coprocessor registers based on feature bits */
1908 CPUARMState
*env
= &cpu
->env
;
1909 if (arm_feature(env
, ARM_FEATURE_M
)) {
1910 /* M profile has no coprocessor registers */
1914 define_arm_cp_regs(cpu
, cp_reginfo
);
1915 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1916 /* The ID registers all have impdef reset values */
1917 ARMCPRegInfo v6_idregs
[] = {
1918 { .name
= "ID_PFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1919 .opc1
= 0, .opc2
= 0, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1920 .resetvalue
= cpu
->id_pfr0
},
1921 { .name
= "ID_PFR1", .cp
= 15, .crn
= 0, .crm
= 1,
1922 .opc1
= 0, .opc2
= 1, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1923 .resetvalue
= cpu
->id_pfr1
},
1924 { .name
= "ID_DFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1925 .opc1
= 0, .opc2
= 2, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1926 .resetvalue
= cpu
->id_dfr0
},
1927 { .name
= "ID_AFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1928 .opc1
= 0, .opc2
= 3, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1929 .resetvalue
= cpu
->id_afr0
},
1930 { .name
= "ID_MMFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1931 .opc1
= 0, .opc2
= 4, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1932 .resetvalue
= cpu
->id_mmfr0
},
1933 { .name
= "ID_MMFR1", .cp
= 15, .crn
= 0, .crm
= 1,
1934 .opc1
= 0, .opc2
= 5, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1935 .resetvalue
= cpu
->id_mmfr1
},
1936 { .name
= "ID_MMFR2", .cp
= 15, .crn
= 0, .crm
= 1,
1937 .opc1
= 0, .opc2
= 6, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1938 .resetvalue
= cpu
->id_mmfr2
},
1939 { .name
= "ID_MMFR3", .cp
= 15, .crn
= 0, .crm
= 1,
1940 .opc1
= 0, .opc2
= 7, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1941 .resetvalue
= cpu
->id_mmfr3
},
1942 { .name
= "ID_ISAR0", .cp
= 15, .crn
= 0, .crm
= 2,
1943 .opc1
= 0, .opc2
= 0, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1944 .resetvalue
= cpu
->id_isar0
},
1945 { .name
= "ID_ISAR1", .cp
= 15, .crn
= 0, .crm
= 2,
1946 .opc1
= 0, .opc2
= 1, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1947 .resetvalue
= cpu
->id_isar1
},
1948 { .name
= "ID_ISAR2", .cp
= 15, .crn
= 0, .crm
= 2,
1949 .opc1
= 0, .opc2
= 2, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1950 .resetvalue
= cpu
->id_isar2
},
1951 { .name
= "ID_ISAR3", .cp
= 15, .crn
= 0, .crm
= 2,
1952 .opc1
= 0, .opc2
= 3, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1953 .resetvalue
= cpu
->id_isar3
},
1954 { .name
= "ID_ISAR4", .cp
= 15, .crn
= 0, .crm
= 2,
1955 .opc1
= 0, .opc2
= 4, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1956 .resetvalue
= cpu
->id_isar4
},
1957 { .name
= "ID_ISAR5", .cp
= 15, .crn
= 0, .crm
= 2,
1958 .opc1
= 0, .opc2
= 5, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1959 .resetvalue
= cpu
->id_isar5
},
1960 /* 6..7 are as yet unallocated and must RAZ */
1961 { .name
= "ID_ISAR6", .cp
= 15, .crn
= 0, .crm
= 2,
1962 .opc1
= 0, .opc2
= 6, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1964 { .name
= "ID_ISAR7", .cp
= 15, .crn
= 0, .crm
= 2,
1965 .opc1
= 0, .opc2
= 7, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1969 define_arm_cp_regs(cpu
, v6_idregs
);
1970 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
1972 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
1974 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1975 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
1977 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1978 /* v7 performance monitor control register: same implementor
1979 * field as main ID register, and we implement only the cycle
1982 #ifndef CONFIG_USER_ONLY
1983 ARMCPRegInfo pmcr
= {
1984 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
1985 .access
= PL0_RW
, .resetvalue
= cpu
->midr
& 0xff000000,
1986 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
1987 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
1988 .raw_writefn
= raw_write
,
1990 define_one_arm_cp_reg(cpu
, &pmcr
);
1992 ARMCPRegInfo clidr
= {
1993 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
1994 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
1995 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
1997 define_one_arm_cp_reg(cpu
, &clidr
);
1998 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
2000 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
2002 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2003 /* AArch64 ID registers, which all have impdef reset values */
2004 ARMCPRegInfo v8_idregs
[] = {
2005 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
2006 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
2007 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2008 .resetvalue
= cpu
->id_aa64pfr0
},
2009 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
2010 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
2011 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2012 .resetvalue
= cpu
->id_aa64pfr1
},
2013 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
2014 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
2015 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2016 .resetvalue
= cpu
->id_aa64dfr0
},
2017 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
2018 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
2019 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2020 .resetvalue
= cpu
->id_aa64dfr1
},
2021 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
2022 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
2023 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2024 .resetvalue
= cpu
->id_aa64afr0
},
2025 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
2026 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
2027 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2028 .resetvalue
= cpu
->id_aa64afr1
},
2029 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
2030 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
2031 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2032 .resetvalue
= cpu
->id_aa64isar0
},
2033 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
2034 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
2035 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2036 .resetvalue
= cpu
->id_aa64isar1
},
2037 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
2038 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
2039 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2040 .resetvalue
= cpu
->id_aa64mmfr0
},
2041 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
2042 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
2043 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2044 .resetvalue
= cpu
->id_aa64mmfr1
},
2047 define_arm_cp_regs(cpu
, v8_idregs
);
2048 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
2049 define_aarch64_debug_regs(cpu
);
2051 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
2052 /* These are the MPU registers prior to PMSAv6. Any new
2053 * PMSA core later than the ARM946 will require that we
2054 * implement the PMSAv6 or PMSAv7 registers, which are
2055 * completely different.
2057 assert(!arm_feature(env
, ARM_FEATURE_V6
));
2058 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
2060 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
2062 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
2063 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
2065 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
2066 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
2068 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
2069 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
2071 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
2072 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
2074 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
2075 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
2077 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
2078 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
2080 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
2081 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
2083 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
2084 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
2086 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
2087 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
2089 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
2090 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
2092 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2093 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
2095 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
2096 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
2097 * be read-only (ie write causes UNDEF exception).
2100 ARMCPRegInfo id_cp_reginfo
[] = {
2101 /* Note that the MIDR isn't a simple constant register because
2102 * of the TI925 behaviour where writes to another register can
2103 * cause the MIDR value to change.
2105 * Unimplemented registers in the c15 0 0 0 space default to
2106 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
2107 * and friends override accordingly.
2110 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
2111 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
2112 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
2113 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
2114 .type
= ARM_CP_OVERRIDE
},
2115 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2116 .opc0
= 3, .opc1
= 0, .opc2
= 0, .crn
= 0, .crm
= 0,
2117 .access
= PL1_R
, .resetvalue
= cpu
->midr
, .type
= ARM_CP_CONST
},
2119 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
2120 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
2121 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
2122 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
2123 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
2124 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
2126 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
2127 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2129 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
2130 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2131 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
2133 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
2134 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2136 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
2137 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2139 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
2140 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2142 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
2143 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2145 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
2146 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2149 ARMCPRegInfo crn0_wi_reginfo
= {
2150 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
2151 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
2152 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
2154 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
2155 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
2157 /* Register the blanket "writes ignored" value first to cover the
2158 * whole space. Then update the specific ID registers to allow write
2159 * access, so that they ignore writes rather than causing them to
2162 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
2163 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
2167 define_arm_cp_regs(cpu
, id_cp_reginfo
);
2170 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
2171 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
2174 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
2175 ARMCPRegInfo auxcr
= {
2176 .name
= "AUXCR", .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1,
2177 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
2178 .resetvalue
= cpu
->reset_auxcr
2180 define_one_arm_cp_reg(cpu
, &auxcr
);
2183 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
2184 ARMCPRegInfo cbar
= {
2185 .name
= "CBAR", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
2186 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
2187 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_config_base_address
)
2189 define_one_arm_cp_reg(cpu
, &cbar
);
2192 /* Generic registers whose values depend on the implementation */
2194 ARMCPRegInfo sctlr
= {
2195 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
2196 .opc0
= 3, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
2197 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_sys
),
2198 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
2199 .raw_writefn
= raw_write
,
2201 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
2202 /* Normally we would always end the TB on an SCTLR write, but Linux
2203 * arch/arm/mach-pxa/sleep.S expects two instructions following
2204 * an MMU enable to execute from cache. Imitate this behaviour.
2206 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
2208 define_one_arm_cp_reg(cpu
, &sctlr
);
2212 ARMCPU
*cpu_arm_init(const char *cpu_model
)
2214 return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU
, cpu_model
));
2217 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
2219 CPUState
*cs
= CPU(cpu
);
2220 CPUARMState
*env
= &cpu
->env
;
2222 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
2223 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
2224 aarch64_fpu_gdb_set_reg
,
2225 34, "aarch64-fpu.xml", 0);
2226 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
2227 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
2228 51, "arm-neon.xml", 0);
2229 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
2230 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
2231 35, "arm-vfp3.xml", 0);
2232 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
2233 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
2234 19, "arm-vfp.xml", 0);
2238 /* Sort alphabetically by type name, except for "any". */
2239 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
2241 ObjectClass
*class_a
= (ObjectClass
*)a
;
2242 ObjectClass
*class_b
= (ObjectClass
*)b
;
2243 const char *name_a
, *name_b
;
2245 name_a
= object_class_get_name(class_a
);
2246 name_b
= object_class_get_name(class_b
);
2247 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
2249 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
2252 return strcmp(name_a
, name_b
);
2256 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
2258 ObjectClass
*oc
= data
;
2259 CPUListState
*s
= user_data
;
2260 const char *typename
;
2263 typename
= object_class_get_name(oc
);
2264 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
2265 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
2270 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
2274 .cpu_fprintf
= cpu_fprintf
,
2278 list
= object_class_get_list(TYPE_ARM_CPU
, false);
2279 list
= g_slist_sort(list
, arm_cpu_list_compare
);
2280 (*cpu_fprintf
)(f
, "Available CPUs:\n");
2281 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
2284 /* The 'host' CPU type is dynamically registered only if KVM is
2285 * enabled, so we have to special-case it here:
2287 (*cpu_fprintf
)(f
, " host (only available in KVM mode)\n");
2291 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
2293 ObjectClass
*oc
= data
;
2294 CpuDefinitionInfoList
**cpu_list
= user_data
;
2295 CpuDefinitionInfoList
*entry
;
2296 CpuDefinitionInfo
*info
;
2297 const char *typename
;
2299 typename
= object_class_get_name(oc
);
2300 info
= g_malloc0(sizeof(*info
));
2301 info
->name
= g_strndup(typename
,
2302 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
2304 entry
= g_malloc0(sizeof(*entry
));
2305 entry
->value
= info
;
2306 entry
->next
= *cpu_list
;
2310 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
2312 CpuDefinitionInfoList
*cpu_list
= NULL
;
2315 list
= object_class_get_list(TYPE_ARM_CPU
, false);
2316 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
2322 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
2323 void *opaque
, int state
,
2324 int crm
, int opc1
, int opc2
)
2326 /* Private utility function for define_one_arm_cp_reg_with_opaque():
2327 * add a single reginfo struct to the hash table.
2329 uint32_t *key
= g_new(uint32_t, 1);
2330 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
2331 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
2332 if (r
->state
== ARM_CP_STATE_BOTH
&& state
== ARM_CP_STATE_AA32
) {
2333 /* The AArch32 view of a shared register sees the lower 32 bits
2334 * of a 64 bit backing field. It is not migratable as the AArch64
2335 * view handles that. AArch64 also handles reset.
2336 * We assume it is a cp15 register.
2339 r2
->type
|= ARM_CP_NO_MIGRATE
;
2340 r2
->resetfn
= arm_cp_reset_ignore
;
2341 #ifdef HOST_WORDS_BIGENDIAN
2342 if (r2
->fieldoffset
) {
2343 r2
->fieldoffset
+= sizeof(uint32_t);
2347 if (state
== ARM_CP_STATE_AA64
) {
2348 /* To allow abbreviation of ARMCPRegInfo
2349 * definitions, we treat cp == 0 as equivalent to
2350 * the value for "standard guest-visible sysreg".
2353 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
2355 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
2356 r2
->opc0
, opc1
, opc2
);
2358 *key
= ENCODE_CP_REG(r2
->cp
, is64
, r2
->crn
, crm
, opc1
, opc2
);
2361 r2
->opaque
= opaque
;
2363 /* reginfo passed to helpers is correct for the actual access,
2364 * and is never ARM_CP_STATE_BOTH:
2367 /* Make sure reginfo passed to helpers for wildcarded regs
2368 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
2373 /* By convention, for wildcarded registers only the first
2374 * entry is used for migration; the others are marked as
2375 * NO_MIGRATE so we don't try to transfer the register
2376 * multiple times. Special registers (ie NOP/WFI) are
2379 if ((r
->type
& ARM_CP_SPECIAL
) ||
2380 ((r
->crm
== CP_ANY
) && crm
!= 0) ||
2381 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
2382 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
2383 r2
->type
|= ARM_CP_NO_MIGRATE
;
2386 /* Overriding of an existing definition must be explicitly
2389 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
2390 ARMCPRegInfo
*oldreg
;
2391 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
2392 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
2393 fprintf(stderr
, "Register redefined: cp=%d %d bit "
2394 "crn=%d crm=%d opc1=%d opc2=%d, "
2395 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
2396 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
2397 oldreg
->name
, r2
->name
);
2398 g_assert_not_reached();
2401 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
2405 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
2406 const ARMCPRegInfo
*r
, void *opaque
)
2408 /* Define implementations of coprocessor registers.
2409 * We store these in a hashtable because typically
2410 * there are less than 150 registers in a space which
2411 * is 16*16*16*8*8 = 262144 in size.
2412 * Wildcarding is supported for the crm, opc1 and opc2 fields.
2413 * If a register is defined twice then the second definition is
2414 * used, so this can be used to define some generic registers and
2415 * then override them with implementation specific variations.
2416 * At least one of the original and the second definition should
2417 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
2418 * against accidental use.
2420 * The state field defines whether the register is to be
2421 * visible in the AArch32 or AArch64 execution state. If the
2422 * state is set to ARM_CP_STATE_BOTH then we synthesise a
2423 * reginfo structure for the AArch32 view, which sees the lower
2424 * 32 bits of the 64 bit register.
2426 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
2427 * be wildcarded. AArch64 registers are always considered to be 64
2428 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
2429 * the register, if any.
2431 int crm
, opc1
, opc2
, state
;
2432 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
2433 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
2434 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
2435 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
2436 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
2437 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
2438 /* 64 bit registers have only CRm and Opc1 fields */
2439 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
2440 /* op0 only exists in the AArch64 encodings */
2441 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
2442 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
2443 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
2444 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
2445 * encodes a minimum access level for the register. We roll this
2446 * runtime check into our general permission check code, so check
2447 * here that the reginfo's specified permissions are strict enough
2448 * to encompass the generic architectural permission check.
2450 if (r
->state
!= ARM_CP_STATE_AA32
) {
2453 case 0: case 1: case 2:
2466 /* unallocated encoding, so not possible */
2474 /* min_EL EL1, secure mode only (we don't check the latter) */
2478 /* broken reginfo with out-of-range opc1 */
2482 /* assert our permissions are not too lax (stricter is fine) */
2483 assert((r
->access
& ~mask
) == 0);
2486 /* Check that the register definition has enough info to handle
2487 * reads and writes if they are permitted.
2489 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
2490 if (r
->access
& PL3_R
) {
2491 assert(r
->fieldoffset
|| r
->readfn
);
2493 if (r
->access
& PL3_W
) {
2494 assert(r
->fieldoffset
|| r
->writefn
);
2497 /* Bad type field probably means missing sentinel at end of reg list */
2498 assert(cptype_valid(r
->type
));
2499 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
2500 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
2501 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
2502 for (state
= ARM_CP_STATE_AA32
;
2503 state
<= ARM_CP_STATE_AA64
; state
++) {
2504 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
2507 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
2515 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
2516 const ARMCPRegInfo
*regs
, void *opaque
)
2518 /* Define a whole list of registers */
2519 const ARMCPRegInfo
*r
;
2520 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
2521 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
2525 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
2527 return g_hash_table_lookup(cpregs
, &encoded_cp
);
2530 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2533 /* Helper coprocessor write function for write-ignore registers */
2536 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2538 /* Helper coprocessor write function for read-as-zero registers */
2542 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
2544 /* Helper coprocessor reset function for do-nothing-on-reset registers */
2547 static int bad_mode_switch(CPUARMState
*env
, int mode
)
2549 /* Return true if it is not valid for us to switch to
2550 * this CPU mode (ie all the UNPREDICTABLE cases in
2551 * the ARM ARM CPSRWriteByInstr pseudocode).
2554 case ARM_CPU_MODE_USR
:
2555 case ARM_CPU_MODE_SYS
:
2556 case ARM_CPU_MODE_SVC
:
2557 case ARM_CPU_MODE_ABT
:
2558 case ARM_CPU_MODE_UND
:
2559 case ARM_CPU_MODE_IRQ
:
2560 case ARM_CPU_MODE_FIQ
:
2567 uint32_t cpsr_read(CPUARMState
*env
)
2570 ZF
= (env
->ZF
== 0);
2571 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
2572 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
2573 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
2574 | ((env
->condexec_bits
& 0xfc) << 8)
2575 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
2578 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
2580 if (mask
& CPSR_NZCV
) {
2581 env
->ZF
= (~val
) & CPSR_Z
;
2583 env
->CF
= (val
>> 29) & 1;
2584 env
->VF
= (val
<< 3) & 0x80000000;
2587 env
->QF
= ((val
& CPSR_Q
) != 0);
2589 env
->thumb
= ((val
& CPSR_T
) != 0);
2590 if (mask
& CPSR_IT_0_1
) {
2591 env
->condexec_bits
&= ~3;
2592 env
->condexec_bits
|= (val
>> 25) & 3;
2594 if (mask
& CPSR_IT_2_7
) {
2595 env
->condexec_bits
&= 3;
2596 env
->condexec_bits
|= (val
>> 8) & 0xfc;
2598 if (mask
& CPSR_GE
) {
2599 env
->GE
= (val
>> 16) & 0xf;
2602 env
->daif
&= ~(CPSR_AIF
& mask
);
2603 env
->daif
|= val
& CPSR_AIF
& mask
;
2605 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
2606 if (bad_mode_switch(env
, val
& CPSR_M
)) {
2607 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
2608 * We choose to ignore the attempt and leave the CPSR M field
2613 switch_mode(env
, val
& CPSR_M
);
2616 mask
&= ~CACHED_CPSR_BITS
;
2617 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
2620 /* Sign/zero extend */
2621 uint32_t HELPER(sxtb16
)(uint32_t x
)
2624 res
= (uint16_t)(int8_t)x
;
2625 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
2629 uint32_t HELPER(uxtb16
)(uint32_t x
)
2632 res
= (uint16_t)(uint8_t)x
;
2633 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
2637 uint32_t HELPER(clz
)(uint32_t x
)
2642 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
2646 if (num
== INT_MIN
&& den
== -1)
2651 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
2658 uint32_t HELPER(rbit
)(uint32_t x
)
2660 x
= ((x
& 0xff000000) >> 24)
2661 | ((x
& 0x00ff0000) >> 8)
2662 | ((x
& 0x0000ff00) << 8)
2663 | ((x
& 0x000000ff) << 24);
2664 x
= ((x
& 0xf0f0f0f0) >> 4)
2665 | ((x
& 0x0f0f0f0f) << 4);
2666 x
= ((x
& 0x88888888) >> 3)
2667 | ((x
& 0x44444444) >> 1)
2668 | ((x
& 0x22222222) << 1)
2669 | ((x
& 0x11111111) << 3);
2673 #if defined(CONFIG_USER_ONLY)
2675 void arm_cpu_do_interrupt(CPUState
*cs
)
2677 cs
->exception_index
= -1;
2680 int arm_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int rw
,
2683 ARMCPU
*cpu
= ARM_CPU(cs
);
2684 CPUARMState
*env
= &cpu
->env
;
2687 cs
->exception_index
= EXCP_PREFETCH_ABORT
;
2688 env
->cp15
.c6_insn
= address
;
2690 cs
->exception_index
= EXCP_DATA_ABORT
;
2691 env
->cp15
.c6_data
= address
;
2696 /* These should probably raise undefined insn exceptions. */
2697 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
2699 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2701 cpu_abort(CPU(cpu
), "v7m_msr %d\n", reg
);
2704 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
2706 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2708 cpu_abort(CPU(cpu
), "v7m_mrs %d\n", reg
);
2712 void switch_mode(CPUARMState
*env
, int mode
)
2714 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2716 if (mode
!= ARM_CPU_MODE_USR
) {
2717 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
2721 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
2723 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2725 cpu_abort(CPU(cpu
), "banked r13 write\n");
2728 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
2730 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2732 cpu_abort(CPU(cpu
), "banked r13 read\n");
2738 /* Map CPU modes onto saved register banks. */
2739 int bank_number(int mode
)
2742 case ARM_CPU_MODE_USR
:
2743 case ARM_CPU_MODE_SYS
:
2745 case ARM_CPU_MODE_SVC
:
2747 case ARM_CPU_MODE_ABT
:
2749 case ARM_CPU_MODE_UND
:
2751 case ARM_CPU_MODE_IRQ
:
2753 case ARM_CPU_MODE_FIQ
:
2756 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode
);
2759 void switch_mode(CPUARMState
*env
, int mode
)
2764 old_mode
= env
->uncached_cpsr
& CPSR_M
;
2765 if (mode
== old_mode
)
2768 if (old_mode
== ARM_CPU_MODE_FIQ
) {
2769 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
2770 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
2771 } else if (mode
== ARM_CPU_MODE_FIQ
) {
2772 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
2773 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
2776 i
= bank_number(old_mode
);
2777 env
->banked_r13
[i
] = env
->regs
[13];
2778 env
->banked_r14
[i
] = env
->regs
[14];
2779 env
->banked_spsr
[i
] = env
->spsr
;
2781 i
= bank_number(mode
);
2782 env
->regs
[13] = env
->banked_r13
[i
];
2783 env
->regs
[14] = env
->banked_r14
[i
];
2784 env
->spsr
= env
->banked_spsr
[i
];
2787 static void v7m_push(CPUARMState
*env
, uint32_t val
)
2789 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
2792 stl_phys(cs
->as
, env
->regs
[13], val
);
2795 static uint32_t v7m_pop(CPUARMState
*env
)
2797 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
2800 val
= ldl_phys(cs
->as
, env
->regs
[13]);
2805 /* Switch to V7M main or process stack pointer. */
2806 static void switch_v7m_sp(CPUARMState
*env
, int process
)
2809 if (env
->v7m
.current_sp
!= process
) {
2810 tmp
= env
->v7m
.other_sp
;
2811 env
->v7m
.other_sp
= env
->regs
[13];
2812 env
->regs
[13] = tmp
;
2813 env
->v7m
.current_sp
= process
;
2817 static void do_v7m_exception_exit(CPUARMState
*env
)
2822 type
= env
->regs
[15];
2823 if (env
->v7m
.exception
!= 0)
2824 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
2826 /* Switch to the target stack. */
2827 switch_v7m_sp(env
, (type
& 4) != 0);
2828 /* Pop registers. */
2829 env
->regs
[0] = v7m_pop(env
);
2830 env
->regs
[1] = v7m_pop(env
);
2831 env
->regs
[2] = v7m_pop(env
);
2832 env
->regs
[3] = v7m_pop(env
);
2833 env
->regs
[12] = v7m_pop(env
);
2834 env
->regs
[14] = v7m_pop(env
);
2835 env
->regs
[15] = v7m_pop(env
);
2836 xpsr
= v7m_pop(env
);
2837 xpsr_write(env
, xpsr
, 0xfffffdff);
2838 /* Undo stack alignment. */
2841 /* ??? The exception return type specifies Thread/Handler mode. However
2842 this is also implied by the xPSR value. Not sure what to do
2843 if there is a mismatch. */
2844 /* ??? Likewise for mismatches between the CONTROL register and the stack
2848 /* Exception names for debug logging; note that not all of these
2849 * precisely correspond to architectural exceptions.
2851 static const char * const excnames
[] = {
2852 [EXCP_UDEF
] = "Undefined Instruction",
2854 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
2855 [EXCP_DATA_ABORT
] = "Data Abort",
2858 [EXCP_BKPT
] = "Breakpoint",
2859 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
2860 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
2861 [EXCP_STREX
] = "QEMU intercept of STREX",
2864 static inline void arm_log_exception(int idx
)
2866 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
2867 const char *exc
= NULL
;
2869 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
2870 exc
= excnames
[idx
];
2875 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s]\n", idx
, exc
);
2879 void arm_v7m_cpu_do_interrupt(CPUState
*cs
)
2881 ARMCPU
*cpu
= ARM_CPU(cs
);
2882 CPUARMState
*env
= &cpu
->env
;
2883 uint32_t xpsr
= xpsr_read(env
);
2887 arm_log_exception(cs
->exception_index
);
2890 if (env
->v7m
.current_sp
)
2892 if (env
->v7m
.exception
== 0)
2895 /* For exceptions we just mark as pending on the NVIC, and let that
2897 /* TODO: Need to escalate if the current priority is higher than the
2898 one we're raising. */
2899 switch (cs
->exception_index
) {
2901 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
2904 /* The PC already points to the next instruction. */
2905 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
2907 case EXCP_PREFETCH_ABORT
:
2908 case EXCP_DATA_ABORT
:
2909 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
2912 if (semihosting_enabled
) {
2914 nr
= arm_lduw_code(env
, env
->regs
[15], env
->bswap_code
) & 0xff;
2917 env
->regs
[0] = do_arm_semihosting(env
);
2918 qemu_log_mask(CPU_LOG_INT
, "...handled as semihosting call\n");
2922 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
2925 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
2927 case EXCP_EXCEPTION_EXIT
:
2928 do_v7m_exception_exit(env
);
2931 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
2932 return; /* Never happens. Keep compiler happy. */
2935 /* Align stack pointer. */
2936 /* ??? Should only do this if Configuration Control Register
2937 STACKALIGN bit is set. */
2938 if (env
->regs
[13] & 4) {
2942 /* Switch to the handler mode. */
2943 v7m_push(env
, xpsr
);
2944 v7m_push(env
, env
->regs
[15]);
2945 v7m_push(env
, env
->regs
[14]);
2946 v7m_push(env
, env
->regs
[12]);
2947 v7m_push(env
, env
->regs
[3]);
2948 v7m_push(env
, env
->regs
[2]);
2949 v7m_push(env
, env
->regs
[1]);
2950 v7m_push(env
, env
->regs
[0]);
2951 switch_v7m_sp(env
, 0);
2953 env
->condexec_bits
= 0;
2955 addr
= ldl_phys(cs
->as
, env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
2956 env
->regs
[15] = addr
& 0xfffffffe;
2957 env
->thumb
= addr
& 1;
2960 /* Handle a CPU exception. */
2961 void arm_cpu_do_interrupt(CPUState
*cs
)
2963 ARMCPU
*cpu
= ARM_CPU(cs
);
2964 CPUARMState
*env
= &cpu
->env
;
2972 arm_log_exception(cs
->exception_index
);
2974 /* TODO: Vectored interrupt controller. */
2975 switch (cs
->exception_index
) {
2977 new_mode
= ARM_CPU_MODE_UND
;
2986 if (semihosting_enabled
) {
2987 /* Check for semihosting interrupt. */
2989 mask
= arm_lduw_code(env
, env
->regs
[15] - 2, env
->bswap_code
)
2992 mask
= arm_ldl_code(env
, env
->regs
[15] - 4, env
->bswap_code
)
2995 /* Only intercept calls from privileged modes, to provide some
2996 semblance of security. */
2997 if (((mask
== 0x123456 && !env
->thumb
)
2998 || (mask
== 0xab && env
->thumb
))
2999 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
3000 env
->regs
[0] = do_arm_semihosting(env
);
3001 qemu_log_mask(CPU_LOG_INT
, "...handled as semihosting call\n");
3005 new_mode
= ARM_CPU_MODE_SVC
;
3008 /* The PC already points to the next instruction. */
3012 /* See if this is a semihosting syscall. */
3013 if (env
->thumb
&& semihosting_enabled
) {
3014 mask
= arm_lduw_code(env
, env
->regs
[15], env
->bswap_code
) & 0xff;
3016 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
3018 env
->regs
[0] = do_arm_semihosting(env
);
3019 qemu_log_mask(CPU_LOG_INT
, "...handled as semihosting call\n");
3023 env
->cp15
.c5_insn
= 2;
3024 /* Fall through to prefetch abort. */
3025 case EXCP_PREFETCH_ABORT
:
3026 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
3027 env
->cp15
.c5_insn
, env
->cp15
.c6_insn
);
3028 new_mode
= ARM_CPU_MODE_ABT
;
3030 mask
= CPSR_A
| CPSR_I
;
3033 case EXCP_DATA_ABORT
:
3034 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
3035 env
->cp15
.c5_data
, env
->cp15
.c6_data
);
3036 new_mode
= ARM_CPU_MODE_ABT
;
3038 mask
= CPSR_A
| CPSR_I
;
3042 new_mode
= ARM_CPU_MODE_IRQ
;
3044 /* Disable IRQ and imprecise data aborts. */
3045 mask
= CPSR_A
| CPSR_I
;
3049 new_mode
= ARM_CPU_MODE_FIQ
;
3051 /* Disable FIQ, IRQ and imprecise data aborts. */
3052 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
3056 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
3057 return; /* Never happens. Keep compiler happy. */
3060 if (env
->cp15
.c1_sys
& SCTLR_V
) {
3061 /* when enabled, base address cannot be remapped. */
3064 /* ARM v7 architectures provide a vector base address register to remap
3065 * the interrupt vector table.
3066 * This register is only followed in non-monitor mode, and has a secure
3067 * and un-secure copy. Since the cpu is always in a un-secure operation
3068 * and is never in monitor mode this feature is always active.
3069 * Note: only bits 31:5 are valid.
3071 addr
+= env
->cp15
.c12_vbar
;
3073 switch_mode (env
, new_mode
);
3074 env
->spsr
= cpsr_read(env
);
3075 /* Clear IT bits. */
3076 env
->condexec_bits
= 0;
3077 /* Switch to the new mode, and to the correct instruction set. */
3078 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
3080 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
3081 * and we should just guard the thumb mode on V4 */
3082 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
3083 env
->thumb
= (env
->cp15
.c1_sys
& SCTLR_TE
) != 0;
3085 env
->regs
[14] = env
->regs
[15] + offset
;
3086 env
->regs
[15] = addr
;
3087 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
3090 /* Check section/page access permissions.
3091 Returns the page protection flags, or zero if the access is not
3093 static inline int check_ap(CPUARMState
*env
, int ap
, int domain_prot
,
3094 int access_type
, int is_user
)
3098 if (domain_prot
== 3) {
3099 return PAGE_READ
| PAGE_WRITE
;
3102 if (access_type
== 1)
3105 prot_ro
= PAGE_READ
;
3109 if (arm_feature(env
, ARM_FEATURE_V7
)) {
3112 if (access_type
== 1)
3114 switch (env
->cp15
.c1_sys
& (SCTLR_S
| SCTLR_R
)) {
3116 return is_user
? 0 : PAGE_READ
;
3123 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
3128 return PAGE_READ
| PAGE_WRITE
;
3130 return PAGE_READ
| PAGE_WRITE
;
3131 case 4: /* Reserved. */
3134 return is_user
? 0 : prot_ro
;
3138 if (!arm_feature (env
, ARM_FEATURE_V6K
))
3146 static uint32_t get_level1_table_address(CPUARMState
*env
, uint32_t address
)
3150 if (address
& env
->cp15
.c2_mask
)
3151 table
= env
->cp15
.ttbr1_el1
& 0xffffc000;
3153 table
= env
->cp15
.ttbr0_el1
& env
->cp15
.c2_base_mask
;
3155 table
|= (address
>> 18) & 0x3ffc;
3159 static int get_phys_addr_v5(CPUARMState
*env
, uint32_t address
, int access_type
,
3160 int is_user
, hwaddr
*phys_ptr
,
3161 int *prot
, target_ulong
*page_size
)
3163 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
3173 /* Pagetable walk. */
3174 /* Lookup l1 descriptor. */
3175 table
= get_level1_table_address(env
, address
);
3176 desc
= ldl_phys(cs
->as
, table
);
3178 domain
= (desc
>> 5) & 0x0f;
3179 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
3181 /* Section translation fault. */
3185 if (domain_prot
== 0 || domain_prot
== 2) {
3187 code
= 9; /* Section domain fault. */
3189 code
= 11; /* Page domain fault. */
3194 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
3195 ap
= (desc
>> 10) & 3;
3197 *page_size
= 1024 * 1024;
3199 /* Lookup l2 entry. */
3201 /* Coarse pagetable. */
3202 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
3204 /* Fine pagetable. */
3205 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
3207 desc
= ldl_phys(cs
->as
, table
);
3209 case 0: /* Page translation fault. */
3212 case 1: /* 64k page. */
3213 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
3214 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
3215 *page_size
= 0x10000;
3217 case 2: /* 4k page. */
3218 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
3219 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
3220 *page_size
= 0x1000;
3222 case 3: /* 1k page. */
3224 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
3225 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
3227 /* Page translation fault. */
3232 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
3234 ap
= (desc
>> 4) & 3;
3238 /* Never happens, but compiler isn't smart enough to tell. */
3243 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
3245 /* Access permission fault. */
3249 *phys_ptr
= phys_addr
;
3252 return code
| (domain
<< 4);
3255 static int get_phys_addr_v6(CPUARMState
*env
, uint32_t address
, int access_type
,
3256 int is_user
, hwaddr
*phys_ptr
,
3257 int *prot
, target_ulong
*page_size
)
3259 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
3271 /* Pagetable walk. */
3272 /* Lookup l1 descriptor. */
3273 table
= get_level1_table_address(env
, address
);
3274 desc
= ldl_phys(cs
->as
, table
);
3276 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
3277 /* Section translation fault, or attempt to use the encoding
3278 * which is Reserved on implementations without PXN.
3283 if ((type
== 1) || !(desc
& (1 << 18))) {
3284 /* Page or Section. */
3285 domain
= (desc
>> 5) & 0x0f;
3287 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
3288 if (domain_prot
== 0 || domain_prot
== 2) {
3290 code
= 9; /* Section domain fault. */
3292 code
= 11; /* Page domain fault. */
3297 if (desc
& (1 << 18)) {
3299 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
3300 *page_size
= 0x1000000;
3303 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
3304 *page_size
= 0x100000;
3306 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
3307 xn
= desc
& (1 << 4);
3311 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
3312 pxn
= (desc
>> 2) & 1;
3314 /* Lookup l2 entry. */
3315 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
3316 desc
= ldl_phys(cs
->as
, table
);
3317 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
3319 case 0: /* Page translation fault. */
3322 case 1: /* 64k page. */
3323 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
3324 xn
= desc
& (1 << 15);
3325 *page_size
= 0x10000;
3327 case 2: case 3: /* 4k page. */
3328 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
3330 *page_size
= 0x1000;
3333 /* Never happens, but compiler isn't smart enough to tell. */
3338 if (domain_prot
== 3) {
3339 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
3341 if (pxn
&& !is_user
) {
3344 if (xn
&& access_type
== 2)
3347 /* The simplified model uses AP[0] as an access control bit. */
3348 if ((env
->cp15
.c1_sys
& SCTLR_AFE
) && (ap
& 1) == 0) {
3349 /* Access flag fault. */
3350 code
= (code
== 15) ? 6 : 3;
3353 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
3355 /* Access permission fault. */
3362 *phys_ptr
= phys_addr
;
3365 return code
| (domain
<< 4);
3368 /* Fault type for long-descriptor MMU fault reporting; this corresponds
3369 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
3372 translation_fault
= 1,
3374 permission_fault
= 3,
3377 static int get_phys_addr_lpae(CPUARMState
*env
, uint32_t address
,
3378 int access_type
, int is_user
,
3379 hwaddr
*phys_ptr
, int *prot
,
3380 target_ulong
*page_size_ptr
)
3382 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
3383 /* Read an LPAE long-descriptor translation table. */
3384 MMUFaultType fault_type
= translation_fault
;
3392 uint32_t tableattrs
;
3393 target_ulong page_size
;
3396 /* Determine whether this address is in the region controlled by
3397 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
3398 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
3399 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
3401 uint32_t t0sz
= extract32(env
->cp15
.c2_control
, 0, 3);
3402 uint32_t t1sz
= extract32(env
->cp15
.c2_control
, 16, 3);
3403 if (t0sz
&& !extract32(address
, 32 - t0sz
, t0sz
)) {
3404 /* there is a ttbr0 region and we are in it (high bits all zero) */
3406 } else if (t1sz
&& !extract32(~address
, 32 - t1sz
, t1sz
)) {
3407 /* there is a ttbr1 region and we are in it (high bits all one) */
3410 /* ttbr0 region is "everything not in the ttbr1 region" */
3413 /* ttbr1 region is "everything not in the ttbr0 region" */
3416 /* in the gap between the two regions, this is a Translation fault */
3417 fault_type
= translation_fault
;
3421 /* Note that QEMU ignores shareability and cacheability attributes,
3422 * so we don't need to do anything with the SH, ORGN, IRGN fields
3423 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
3424 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
3425 * implement any ASID-like capability so we can ignore it (instead
3426 * we will always flush the TLB any time the ASID is changed).
3428 if (ttbr_select
== 0) {
3429 ttbr
= env
->cp15
.ttbr0_el1
;
3430 epd
= extract32(env
->cp15
.c2_control
, 7, 1);
3433 ttbr
= env
->cp15
.ttbr1_el1
;
3434 epd
= extract32(env
->cp15
.c2_control
, 23, 1);
3439 /* Translation table walk disabled => Translation fault on TLB miss */
3443 /* If the region is small enough we will skip straight to a 2nd level
3444 * lookup. This affects the number of bits of the address used in
3445 * combination with the TTBR to find the first descriptor. ('n' here
3446 * matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are
3447 * from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero).
3456 /* Clear the vaddr bits which aren't part of the within-region address,
3457 * so that we don't have to special case things when calculating the
3458 * first descriptor address.
3460 address
&= (0xffffffffU
>> tsz
);
3462 /* Now we can extract the actual base address from the TTBR */
3463 descaddr
= extract64(ttbr
, 0, 40);
3464 descaddr
&= ~((1ULL << n
) - 1);
3468 uint64_t descriptor
;
3470 descaddr
|= ((address
>> (9 * (4 - level
))) & 0xff8);
3471 descriptor
= ldq_phys(cs
->as
, descaddr
);
3472 if (!(descriptor
& 1) ||
3473 (!(descriptor
& 2) && (level
== 3))) {
3474 /* Invalid, or the Reserved level 3 encoding */
3477 descaddr
= descriptor
& 0xfffffff000ULL
;
3479 if ((descriptor
& 2) && (level
< 3)) {
3480 /* Table entry. The top five bits are attributes which may
3481 * propagate down through lower levels of the table (and
3482 * which are all arranged so that 0 means "no effect", so
3483 * we can gather them up by ORing in the bits at each level).
3485 tableattrs
|= extract64(descriptor
, 59, 5);
3489 /* Block entry at level 1 or 2, or page entry at level 3.
3490 * These are basically the same thing, although the number
3491 * of bits we pull in from the vaddr varies.
3493 page_size
= (1 << (39 - (9 * level
)));
3494 descaddr
|= (address
& (page_size
- 1));
3495 /* Extract attributes from the descriptor and merge with table attrs */
3496 attrs
= extract64(descriptor
, 2, 10)
3497 | (extract64(descriptor
, 52, 12) << 10);
3498 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
3499 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APTable[1] => AP[2] */
3500 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
3501 * means "force PL1 access only", which means forcing AP[1] to 0.
3503 if (extract32(tableattrs
, 2, 1)) {
3506 /* Since we're always in the Non-secure state, NSTable is ignored. */
3509 /* Here descaddr is the final physical address, and attributes
3512 fault_type
= access_fault
;
3513 if ((attrs
& (1 << 8)) == 0) {
3517 fault_type
= permission_fault
;
3518 if (is_user
&& !(attrs
& (1 << 4))) {
3519 /* Unprivileged access not enabled */
3522 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
3523 if (attrs
& (1 << 12) || (!is_user
&& (attrs
& (1 << 11)))) {
3525 if (access_type
== 2) {
3528 *prot
&= ~PAGE_EXEC
;
3530 if (attrs
& (1 << 5)) {
3531 /* Write access forbidden */
3532 if (access_type
== 1) {
3535 *prot
&= ~PAGE_WRITE
;
3538 *phys_ptr
= descaddr
;
3539 *page_size_ptr
= page_size
;
3543 /* Long-descriptor format IFSR/DFSR value */
3544 return (1 << 9) | (fault_type
<< 2) | level
;
3547 static int get_phys_addr_mpu(CPUARMState
*env
, uint32_t address
,
3548 int access_type
, int is_user
,
3549 hwaddr
*phys_ptr
, int *prot
)
3555 *phys_ptr
= address
;
3556 for (n
= 7; n
>= 0; n
--) {
3557 base
= env
->cp15
.c6_region
[n
];
3558 if ((base
& 1) == 0)
3560 mask
= 1 << ((base
>> 1) & 0x1f);
3561 /* Keep this shift separate from the above to avoid an
3562 (undefined) << 32. */
3563 mask
= (mask
<< 1) - 1;
3564 if (((base
^ address
) & ~mask
) == 0)
3570 if (access_type
== 2) {
3571 mask
= env
->cp15
.c5_insn
;
3573 mask
= env
->cp15
.c5_data
;
3575 mask
= (mask
>> (n
* 4)) & 0xf;
3582 *prot
= PAGE_READ
| PAGE_WRITE
;
3587 *prot
|= PAGE_WRITE
;
3590 *prot
= PAGE_READ
| PAGE_WRITE
;
3601 /* Bad permission. */
3608 /* get_phys_addr - get the physical address for this virtual address
3610 * Find the physical address corresponding to the given virtual address,
3611 * by doing a translation table walk on MMU based systems or using the
3612 * MPU state on MPU based systems.
3614 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
3615 * prot and page_size are not filled in, and the return value provides
3616 * information on why the translation aborted, in the format of a
3617 * DFSR/IFSR fault register, with the following caveats:
3618 * * we honour the short vs long DFSR format differences.
3619 * * the WnR bit is never set (the caller must do this).
3620 * * for MPU based systems we don't bother to return a full FSR format
3624 * @address: virtual address to get physical address for
3625 * @access_type: 0 for read, 1 for write, 2 for execute
3626 * @is_user: 0 for privileged access, 1 for user
3627 * @phys_ptr: set to the physical address corresponding to the virtual address
3628 * @prot: set to the permissions for the page containing phys_ptr
3629 * @page_size: set to the size of the page containing phys_ptr
3631 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
3632 int access_type
, int is_user
,
3633 hwaddr
*phys_ptr
, int *prot
,
3634 target_ulong
*page_size
)
3636 /* Fast Context Switch Extension. */
3637 if (address
< 0x02000000)
3638 address
+= env
->cp15
.c13_fcse
;
3640 if ((env
->cp15
.c1_sys
& SCTLR_M
) == 0) {
3641 /* MMU/MPU disabled. */
3642 *phys_ptr
= address
;
3643 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
3644 *page_size
= TARGET_PAGE_SIZE
;
3646 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
3647 *page_size
= TARGET_PAGE_SIZE
;
3648 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
3650 } else if (extended_addresses_enabled(env
)) {
3651 return get_phys_addr_lpae(env
, address
, access_type
, is_user
, phys_ptr
,
3653 } else if (env
->cp15
.c1_sys
& SCTLR_XP
) {
3654 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
3657 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
3662 int arm_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
,
3663 int access_type
, int mmu_idx
)
3665 ARMCPU
*cpu
= ARM_CPU(cs
);
3666 CPUARMState
*env
= &cpu
->env
;
3668 target_ulong page_size
;
3672 is_user
= mmu_idx
== MMU_USER_IDX
;
3673 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
,
3676 /* Map a single [sub]page. */
3677 phys_addr
&= ~(hwaddr
)0x3ff;
3678 address
&= ~(uint32_t)0x3ff;
3679 tlb_set_page(cs
, address
, phys_addr
, prot
, mmu_idx
, page_size
);
3683 if (access_type
== 2) {
3684 env
->cp15
.c5_insn
= ret
;
3685 env
->cp15
.c6_insn
= address
;
3686 cs
->exception_index
= EXCP_PREFETCH_ABORT
;
3688 env
->cp15
.c5_data
= ret
;
3689 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
3690 env
->cp15
.c5_data
|= (1 << 11);
3691 env
->cp15
.c6_data
= address
;
3692 cs
->exception_index
= EXCP_DATA_ABORT
;
3697 hwaddr
arm_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
3699 ARMCPU
*cpu
= ARM_CPU(cs
);
3701 target_ulong page_size
;
3705 ret
= get_phys_addr(&cpu
->env
, addr
, 0, 0, &phys_addr
, &prot
, &page_size
);
3714 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
3716 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
3717 env
->regs
[13] = val
;
3719 env
->banked_r13
[bank_number(mode
)] = val
;
3723 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
3725 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
3726 return env
->regs
[13];
3728 return env
->banked_r13
[bank_number(mode
)];
3732 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
3734 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3738 return xpsr_read(env
) & 0xf8000000;
3740 return xpsr_read(env
) & 0xf80001ff;
3742 return xpsr_read(env
) & 0xff00fc00;
3744 return xpsr_read(env
) & 0xff00fdff;
3746 return xpsr_read(env
) & 0x000001ff;
3748 return xpsr_read(env
) & 0x0700fc00;
3750 return xpsr_read(env
) & 0x0700edff;
3752 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
3754 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
3755 case 16: /* PRIMASK */
3756 return (env
->daif
& PSTATE_I
) != 0;
3757 case 17: /* BASEPRI */
3758 case 18: /* BASEPRI_MAX */
3759 return env
->v7m
.basepri
;
3760 case 19: /* FAULTMASK */
3761 return (env
->daif
& PSTATE_F
) != 0;
3762 case 20: /* CONTROL */
3763 return env
->v7m
.control
;
3765 /* ??? For debugging only. */
3766 cpu_abort(CPU(cpu
), "Unimplemented system register read (%d)\n", reg
);
3771 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
3773 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3777 xpsr_write(env
, val
, 0xf8000000);
3780 xpsr_write(env
, val
, 0xf8000000);
3783 xpsr_write(env
, val
, 0xfe00fc00);
3786 xpsr_write(env
, val
, 0xfe00fc00);
3789 /* IPSR bits are readonly. */
3792 xpsr_write(env
, val
, 0x0600fc00);
3795 xpsr_write(env
, val
, 0x0600fc00);
3798 if (env
->v7m
.current_sp
)
3799 env
->v7m
.other_sp
= val
;
3801 env
->regs
[13] = val
;
3804 if (env
->v7m
.current_sp
)
3805 env
->regs
[13] = val
;
3807 env
->v7m
.other_sp
= val
;
3809 case 16: /* PRIMASK */
3811 env
->daif
|= PSTATE_I
;
3813 env
->daif
&= ~PSTATE_I
;
3816 case 17: /* BASEPRI */
3817 env
->v7m
.basepri
= val
& 0xff;
3819 case 18: /* BASEPRI_MAX */
3821 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
3822 env
->v7m
.basepri
= val
;
3824 case 19: /* FAULTMASK */
3826 env
->daif
|= PSTATE_F
;
3828 env
->daif
&= ~PSTATE_F
;
3831 case 20: /* CONTROL */
3832 env
->v7m
.control
= val
& 3;
3833 switch_v7m_sp(env
, (val
& 2) != 0);
3836 /* ??? For debugging only. */
3837 cpu_abort(CPU(cpu
), "Unimplemented system register write (%d)\n", reg
);
3844 /* Note that signed overflow is undefined in C. The following routines are
3845 careful to use unsigned types where modulo arithmetic is required.
3846 Failure to do so _will_ break on newer gcc. */
3848 /* Signed saturating arithmetic. */
3850 /* Perform 16-bit signed saturating addition. */
3851 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
3856 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
3865 /* Perform 8-bit signed saturating addition. */
3866 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
3871 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
3880 /* Perform 16-bit signed saturating subtraction. */
3881 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
3886 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
3895 /* Perform 8-bit signed saturating subtraction. */
3896 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
3901 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
3910 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
3911 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
3912 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
3913 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
3916 #include "op_addsub.h"
3918 /* Unsigned saturating arithmetic. */
3919 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
3928 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
3936 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
3945 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
3953 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
3954 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
3955 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
3956 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
3959 #include "op_addsub.h"
3961 /* Signed modulo arithmetic. */
3962 #define SARITH16(a, b, n, op) do { \
3964 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
3965 RESULT(sum, n, 16); \
3967 ge |= 3 << (n * 2); \
3970 #define SARITH8(a, b, n, op) do { \
3972 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
3973 RESULT(sum, n, 8); \
3979 #define ADD16(a, b, n) SARITH16(a, b, n, +)
3980 #define SUB16(a, b, n) SARITH16(a, b, n, -)
3981 #define ADD8(a, b, n) SARITH8(a, b, n, +)
3982 #define SUB8(a, b, n) SARITH8(a, b, n, -)
3986 #include "op_addsub.h"
3988 /* Unsigned modulo arithmetic. */
3989 #define ADD16(a, b, n) do { \
3991 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
3992 RESULT(sum, n, 16); \
3993 if ((sum >> 16) == 1) \
3994 ge |= 3 << (n * 2); \
3997 #define ADD8(a, b, n) do { \
3999 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
4000 RESULT(sum, n, 8); \
4001 if ((sum >> 8) == 1) \
4005 #define SUB16(a, b, n) do { \
4007 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
4008 RESULT(sum, n, 16); \
4009 if ((sum >> 16) == 0) \
4010 ge |= 3 << (n * 2); \
4013 #define SUB8(a, b, n) do { \
4015 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
4016 RESULT(sum, n, 8); \
4017 if ((sum >> 8) == 0) \
4024 #include "op_addsub.h"
4026 /* Halved signed arithmetic. */
4027 #define ADD16(a, b, n) \
4028 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
4029 #define SUB16(a, b, n) \
4030 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
4031 #define ADD8(a, b, n) \
4032 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
4033 #define SUB8(a, b, n) \
4034 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
4037 #include "op_addsub.h"
4039 /* Halved unsigned arithmetic. */
4040 #define ADD16(a, b, n) \
4041 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4042 #define SUB16(a, b, n) \
4043 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4044 #define ADD8(a, b, n) \
4045 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4046 #define SUB8(a, b, n) \
4047 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4050 #include "op_addsub.h"
4052 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
4060 /* Unsigned sum of absolute byte differences. */
4061 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
4064 sum
= do_usad(a
, b
);
4065 sum
+= do_usad(a
>> 8, b
>> 8);
4066 sum
+= do_usad(a
>> 16, b
>>16);
4067 sum
+= do_usad(a
>> 24, b
>> 24);
4071 /* For ARMv6 SEL instruction. */
4072 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
4085 return (a
& mask
) | (b
& ~mask
);
4088 /* VFP support. We follow the convention used for VFP instructions:
4089 Single precision routines have a "s" suffix, double precision a
4092 /* Convert host exception flags to vfp form. */
4093 static inline int vfp_exceptbits_from_host(int host_bits
)
4095 int target_bits
= 0;
4097 if (host_bits
& float_flag_invalid
)
4099 if (host_bits
& float_flag_divbyzero
)
4101 if (host_bits
& float_flag_overflow
)
4103 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
4105 if (host_bits
& float_flag_inexact
)
4106 target_bits
|= 0x10;
4107 if (host_bits
& float_flag_input_denormal
)
4108 target_bits
|= 0x80;
4112 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
4117 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
4118 | (env
->vfp
.vec_len
<< 16)
4119 | (env
->vfp
.vec_stride
<< 20);
4120 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
4121 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
4122 fpscr
|= vfp_exceptbits_from_host(i
);
4126 uint32_t vfp_get_fpscr(CPUARMState
*env
)
4128 return HELPER(vfp_get_fpscr
)(env
);
4131 /* Convert vfp exception flags to target form. */
4132 static inline int vfp_exceptbits_to_host(int target_bits
)
4136 if (target_bits
& 1)
4137 host_bits
|= float_flag_invalid
;
4138 if (target_bits
& 2)
4139 host_bits
|= float_flag_divbyzero
;
4140 if (target_bits
& 4)
4141 host_bits
|= float_flag_overflow
;
4142 if (target_bits
& 8)
4143 host_bits
|= float_flag_underflow
;
4144 if (target_bits
& 0x10)
4145 host_bits
|= float_flag_inexact
;
4146 if (target_bits
& 0x80)
4147 host_bits
|= float_flag_input_denormal
;
4151 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
4156 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
4157 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
4158 env
->vfp
.vec_len
= (val
>> 16) & 7;
4159 env
->vfp
.vec_stride
= (val
>> 20) & 3;
4162 if (changed
& (3 << 22)) {
4163 i
= (val
>> 22) & 3;
4165 case FPROUNDING_TIEEVEN
:
4166 i
= float_round_nearest_even
;
4168 case FPROUNDING_POSINF
:
4171 case FPROUNDING_NEGINF
:
4172 i
= float_round_down
;
4174 case FPROUNDING_ZERO
:
4175 i
= float_round_to_zero
;
4178 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
4180 if (changed
& (1 << 24)) {
4181 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
4182 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
4184 if (changed
& (1 << 25))
4185 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
4187 i
= vfp_exceptbits_to_host(val
);
4188 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
4189 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
4192 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
4194 HELPER(vfp_set_fpscr
)(env
, val
);
4197 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
4199 #define VFP_BINOP(name) \
4200 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4202 float_status *fpst = fpstp; \
4203 return float32_ ## name(a, b, fpst); \
4205 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4207 float_status *fpst = fpstp; \
4208 return float64_ ## name(a, b, fpst); \
4220 float32
VFP_HELPER(neg
, s
)(float32 a
)
4222 return float32_chs(a
);
4225 float64
VFP_HELPER(neg
, d
)(float64 a
)
4227 return float64_chs(a
);
4230 float32
VFP_HELPER(abs
, s
)(float32 a
)
4232 return float32_abs(a
);
4235 float64
VFP_HELPER(abs
, d
)(float64 a
)
4237 return float64_abs(a
);
4240 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
4242 return float32_sqrt(a
, &env
->vfp
.fp_status
);
4245 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
4247 return float64_sqrt(a
, &env
->vfp
.fp_status
);
4250 /* XXX: check quiet/signaling case */
4251 #define DO_VFP_cmp(p, type) \
4252 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
4255 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
4256 case 0: flags = 0x6; break; \
4257 case -1: flags = 0x8; break; \
4258 case 1: flags = 0x2; break; \
4259 default: case 2: flags = 0x3; break; \
4261 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4262 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4264 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4267 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
4268 case 0: flags = 0x6; break; \
4269 case -1: flags = 0x8; break; \
4270 case 1: flags = 0x2; break; \
4271 default: case 2: flags = 0x3; break; \
4273 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4274 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4276 DO_VFP_cmp(s
, float32
)
4277 DO_VFP_cmp(d
, float64
)
4280 /* Integer to float and float to integer conversions */
4282 #define CONV_ITOF(name, fsz, sign) \
4283 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
4285 float_status *fpst = fpstp; \
4286 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4289 #define CONV_FTOI(name, fsz, sign, round) \
4290 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
4292 float_status *fpst = fpstp; \
4293 if (float##fsz##_is_any_nan(x)) { \
4294 float_raise(float_flag_invalid, fpst); \
4297 return float##fsz##_to_##sign##int32##round(x, fpst); \
4300 #define FLOAT_CONVS(name, p, fsz, sign) \
4301 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
4302 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
4303 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4305 FLOAT_CONVS(si
, s
, 32, )
4306 FLOAT_CONVS(si
, d
, 64, )
4307 FLOAT_CONVS(ui
, s
, 32, u
)
4308 FLOAT_CONVS(ui
, d
, 64, u
)
4314 /* floating point conversion */
4315 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
4317 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
4318 /* ARM requires that S<->D conversion of any kind of NaN generates
4319 * a quiet NaN by forcing the most significant frac bit to 1.
4321 return float64_maybe_silence_nan(r
);
4324 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
4326 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
4327 /* ARM requires that S<->D conversion of any kind of NaN generates
4328 * a quiet NaN by forcing the most significant frac bit to 1.
4330 return float32_maybe_silence_nan(r
);
4333 /* VFP3 fixed point conversion. */
4334 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4335 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
4338 float_status *fpst = fpstp; \
4340 tmp = itype##_to_##float##fsz(x, fpst); \
4341 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4344 /* Notice that we want only input-denormal exception flags from the
4345 * scalbn operation: the other possible flags (overflow+inexact if
4346 * we overflow to infinity, output-denormal) aren't correct for the
4347 * complete scale-and-convert operation.
4349 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
4350 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
4354 float_status *fpst = fpstp; \
4355 int old_exc_flags = get_float_exception_flags(fpst); \
4357 if (float##fsz##_is_any_nan(x)) { \
4358 float_raise(float_flag_invalid, fpst); \
4361 tmp = float##fsz##_scalbn(x, shift, fpst); \
4362 old_exc_flags |= get_float_exception_flags(fpst) \
4363 & float_flag_input_denormal; \
4364 set_float_exception_flags(old_exc_flags, fpst); \
4365 return float##fsz##_to_##itype##round(tmp, fpst); \
4368 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
4369 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4370 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
4371 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4373 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
4374 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4375 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4377 VFP_CONV_FIX(sh
, d
, 64, 64, int16
)
4378 VFP_CONV_FIX(sl
, d
, 64, 64, int32
)
4379 VFP_CONV_FIX_A64(sq
, d
, 64, 64, int64
)
4380 VFP_CONV_FIX(uh
, d
, 64, 64, uint16
)
4381 VFP_CONV_FIX(ul
, d
, 64, 64, uint32
)
4382 VFP_CONV_FIX_A64(uq
, d
, 64, 64, uint64
)
4383 VFP_CONV_FIX(sh
, s
, 32, 32, int16
)
4384 VFP_CONV_FIX(sl
, s
, 32, 32, int32
)
4385 VFP_CONV_FIX_A64(sq
, s
, 32, 64, int64
)
4386 VFP_CONV_FIX(uh
, s
, 32, 32, uint16
)
4387 VFP_CONV_FIX(ul
, s
, 32, 32, uint32
)
4388 VFP_CONV_FIX_A64(uq
, s
, 32, 64, uint64
)
4390 #undef VFP_CONV_FIX_FLOAT
4391 #undef VFP_CONV_FLOAT_FIX_ROUND
4393 /* Set the current fp rounding mode and return the old one.
4394 * The argument is a softfloat float_round_ value.
4396 uint32_t HELPER(set_rmode
)(uint32_t rmode
, CPUARMState
*env
)
4398 float_status
*fp_status
= &env
->vfp
.fp_status
;
4400 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
4401 set_float_rounding_mode(rmode
, fp_status
);
4406 /* Set the current fp rounding mode in the standard fp status and return
4407 * the old one. This is for NEON instructions that need to change the
4408 * rounding mode but wish to use the standard FPSCR values for everything
4409 * else. Always set the rounding mode back to the correct value after
4411 * The argument is a softfloat float_round_ value.
4413 uint32_t HELPER(set_neon_rmode
)(uint32_t rmode
, CPUARMState
*env
)
4415 float_status
*fp_status
= &env
->vfp
.standard_fp_status
;
4417 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
4418 set_float_rounding_mode(rmode
, fp_status
);
4423 /* Half precision conversions. */
4424 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
4426 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
4427 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
4429 return float32_maybe_silence_nan(r
);
4434 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
4436 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
4437 float16 r
= float32_to_float16(a
, ieee
, s
);
4439 r
= float16_maybe_silence_nan(r
);
4441 return float16_val(r
);
4444 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
4446 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
4449 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
4451 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
4454 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
4456 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
4459 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
4461 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
4464 float64
HELPER(vfp_fcvt_f16_to_f64
)(uint32_t a
, CPUARMState
*env
)
4466 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
4467 float64 r
= float16_to_float64(make_float16(a
), ieee
, &env
->vfp
.fp_status
);
4469 return float64_maybe_silence_nan(r
);
4474 uint32_t HELPER(vfp_fcvt_f64_to_f16
)(float64 a
, CPUARMState
*env
)
4476 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
4477 float16 r
= float64_to_float16(a
, ieee
, &env
->vfp
.fp_status
);
4479 r
= float16_maybe_silence_nan(r
);
4481 return float16_val(r
);
4484 #define float32_two make_float32(0x40000000)
4485 #define float32_three make_float32(0x40400000)
4486 #define float32_one_point_five make_float32(0x3fc00000)
4488 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
4490 float_status
*s
= &env
->vfp
.standard_fp_status
;
4491 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
4492 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
4493 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
4494 float_raise(float_flag_input_denormal
, s
);
4498 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
4501 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
4503 float_status
*s
= &env
->vfp
.standard_fp_status
;
4505 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
4506 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
4507 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
4508 float_raise(float_flag_input_denormal
, s
);
4510 return float32_one_point_five
;
4512 product
= float32_mul(a
, b
, s
);
4513 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
4518 /* Constants 256 and 512 are used in some helpers; we avoid relying on
4519 * int->float conversions at run-time. */
4520 #define float64_256 make_float64(0x4070000000000000LL)
4521 #define float64_512 make_float64(0x4080000000000000LL)
4523 /* The algorithm that must be used to calculate the estimate
4524 * is specified by the ARM ARM.
4526 static float64
recip_estimate(float64 a
, CPUARMState
*env
)
4528 /* These calculations mustn't set any fp exception flags,
4529 * so we use a local copy of the fp_status.
4531 float_status dummy_status
= env
->vfp
.standard_fp_status
;
4532 float_status
*s
= &dummy_status
;
4533 /* q = (int)(a * 512.0) */
4534 float64 q
= float64_mul(float64_512
, a
, s
);
4535 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
4537 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
4538 q
= int64_to_float64(q_int
, s
);
4539 q
= float64_add(q
, float64_half
, s
);
4540 q
= float64_div(q
, float64_512
, s
);
4541 q
= float64_div(float64_one
, q
, s
);
4543 /* s = (int)(256.0 * r + 0.5) */
4544 q
= float64_mul(q
, float64_256
, s
);
4545 q
= float64_add(q
, float64_half
, s
);
4546 q_int
= float64_to_int64_round_to_zero(q
, s
);
4548 /* return (double)s / 256.0 */
4549 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
4552 float32
HELPER(recpe_f32
)(float32 a
, CPUARMState
*env
)
4554 float_status
*s
= &env
->vfp
.standard_fp_status
;
4556 uint32_t val32
= float32_val(a
);
4559 int a_exp
= (val32
& 0x7f800000) >> 23;
4560 int sign
= val32
& 0x80000000;
4562 if (float32_is_any_nan(a
)) {
4563 if (float32_is_signaling_nan(a
)) {
4564 float_raise(float_flag_invalid
, s
);
4566 return float32_default_nan
;
4567 } else if (float32_is_infinity(a
)) {
4568 return float32_set_sign(float32_zero
, float32_is_neg(a
));
4569 } else if (float32_is_zero_or_denormal(a
)) {
4570 if (!float32_is_zero(a
)) {
4571 float_raise(float_flag_input_denormal
, s
);
4573 float_raise(float_flag_divbyzero
, s
);
4574 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
4575 } else if (a_exp
>= 253) {
4576 float_raise(float_flag_underflow
, s
);
4577 return float32_set_sign(float32_zero
, float32_is_neg(a
));
4580 f64
= make_float64((0x3feULL
<< 52)
4581 | ((int64_t)(val32
& 0x7fffff) << 29));
4583 result_exp
= 253 - a_exp
;
4585 f64
= recip_estimate(f64
, env
);
4588 | ((result_exp
& 0xff) << 23)
4589 | ((float64_val(f64
) >> 29) & 0x7fffff);
4590 return make_float32(val32
);
4593 /* The algorithm that must be used to calculate the estimate
4594 * is specified by the ARM ARM.
4596 static float64
recip_sqrt_estimate(float64 a
, CPUARMState
*env
)
4598 /* These calculations mustn't set any fp exception flags,
4599 * so we use a local copy of the fp_status.
4601 float_status dummy_status
= env
->vfp
.standard_fp_status
;
4602 float_status
*s
= &dummy_status
;
4606 if (float64_lt(a
, float64_half
, s
)) {
4607 /* range 0.25 <= a < 0.5 */
4609 /* a in units of 1/512 rounded down */
4610 /* q0 = (int)(a * 512.0); */
4611 q
= float64_mul(float64_512
, a
, s
);
4612 q_int
= float64_to_int64_round_to_zero(q
, s
);
4614 /* reciprocal root r */
4615 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
4616 q
= int64_to_float64(q_int
, s
);
4617 q
= float64_add(q
, float64_half
, s
);
4618 q
= float64_div(q
, float64_512
, s
);
4619 q
= float64_sqrt(q
, s
);
4620 q
= float64_div(float64_one
, q
, s
);
4622 /* range 0.5 <= a < 1.0 */
4624 /* a in units of 1/256 rounded down */
4625 /* q1 = (int)(a * 256.0); */
4626 q
= float64_mul(float64_256
, a
, s
);
4627 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
4629 /* reciprocal root r */
4630 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
4631 q
= int64_to_float64(q_int
, s
);
4632 q
= float64_add(q
, float64_half
, s
);
4633 q
= float64_div(q
, float64_256
, s
);
4634 q
= float64_sqrt(q
, s
);
4635 q
= float64_div(float64_one
, q
, s
);
4637 /* r in units of 1/256 rounded to nearest */
4638 /* s = (int)(256.0 * r + 0.5); */
4640 q
= float64_mul(q
, float64_256
,s
);
4641 q
= float64_add(q
, float64_half
, s
);
4642 q_int
= float64_to_int64_round_to_zero(q
, s
);
4644 /* return (double)s / 256.0;*/
4645 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
4648 float32
HELPER(rsqrte_f32
)(float32 a
, CPUARMState
*env
)
4650 float_status
*s
= &env
->vfp
.standard_fp_status
;
4656 val
= float32_val(a
);
4658 if (float32_is_any_nan(a
)) {
4659 if (float32_is_signaling_nan(a
)) {
4660 float_raise(float_flag_invalid
, s
);
4662 return float32_default_nan
;
4663 } else if (float32_is_zero_or_denormal(a
)) {
4664 if (!float32_is_zero(a
)) {
4665 float_raise(float_flag_input_denormal
, s
);
4667 float_raise(float_flag_divbyzero
, s
);
4668 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
4669 } else if (float32_is_neg(a
)) {
4670 float_raise(float_flag_invalid
, s
);
4671 return float32_default_nan
;
4672 } else if (float32_is_infinity(a
)) {
4673 return float32_zero
;
4676 /* Normalize to a double-precision value between 0.25 and 1.0,
4677 * preserving the parity of the exponent. */
4678 if ((val
& 0x800000) == 0) {
4679 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
4681 | ((uint64_t)(val
& 0x7fffff) << 29));
4683 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
4685 | ((uint64_t)(val
& 0x7fffff) << 29));
4688 result_exp
= (380 - ((val
& 0x7f800000) >> 23)) / 2;
4690 f64
= recip_sqrt_estimate(f64
, env
);
4692 val64
= float64_val(f64
);
4694 val
= ((result_exp
& 0xff) << 23)
4695 | ((val64
>> 29) & 0x7fffff);
4696 return make_float32(val
);
4699 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUARMState
*env
)
4703 if ((a
& 0x80000000) == 0) {
4707 f64
= make_float64((0x3feULL
<< 52)
4708 | ((int64_t)(a
& 0x7fffffff) << 21));
4710 f64
= recip_estimate (f64
, env
);
4712 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
4715 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUARMState
*env
)
4719 if ((a
& 0xc0000000) == 0) {
4723 if (a
& 0x80000000) {
4724 f64
= make_float64((0x3feULL
<< 52)
4725 | ((uint64_t)(a
& 0x7fffffff) << 21));
4726 } else { /* bits 31-30 == '01' */
4727 f64
= make_float64((0x3fdULL
<< 52)
4728 | ((uint64_t)(a
& 0x3fffffff) << 22));
4731 f64
= recip_sqrt_estimate(f64
, env
);
4733 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
4736 /* VFPv4 fused multiply-accumulate */
4737 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
4739 float_status
*fpst
= fpstp
;
4740 return float32_muladd(a
, b
, c
, 0, fpst
);
4743 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
4745 float_status
*fpst
= fpstp
;
4746 return float64_muladd(a
, b
, c
, 0, fpst
);
4749 /* ARMv8 round to integral */
4750 float32
HELPER(rints_exact
)(float32 x
, void *fp_status
)
4752 return float32_round_to_int(x
, fp_status
);
4755 float64
HELPER(rintd_exact
)(float64 x
, void *fp_status
)
4757 return float64_round_to_int(x
, fp_status
);
4760 float32
HELPER(rints
)(float32 x
, void *fp_status
)
4762 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
4765 ret
= float32_round_to_int(x
, fp_status
);
4767 /* Suppress any inexact exceptions the conversion produced */
4768 if (!(old_flags
& float_flag_inexact
)) {
4769 new_flags
= get_float_exception_flags(fp_status
);
4770 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
4776 float64
HELPER(rintd
)(float64 x
, void *fp_status
)
4778 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
4781 ret
= float64_round_to_int(x
, fp_status
);
4783 new_flags
= get_float_exception_flags(fp_status
);
4785 /* Suppress any inexact exceptions the conversion produced */
4786 if (!(old_flags
& float_flag_inexact
)) {
4787 new_flags
= get_float_exception_flags(fp_status
);
4788 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
4794 /* Convert ARM rounding mode to softfloat */
4795 int arm_rmode_to_sf(int rmode
)
4798 case FPROUNDING_TIEAWAY
:
4799 rmode
= float_round_ties_away
;
4801 case FPROUNDING_ODD
:
4802 /* FIXME: add support for TIEAWAY and ODD */
4803 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
4805 case FPROUNDING_TIEEVEN
:
4807 rmode
= float_round_nearest_even
;
4809 case FPROUNDING_POSINF
:
4810 rmode
= float_round_up
;
4812 case FPROUNDING_NEGINF
:
4813 rmode
= float_round_down
;
4815 case FPROUNDING_ZERO
:
4816 rmode
= float_round_to_zero
;
4822 static void crc_init_buffer(uint8_t *buf
, uint32_t val
, uint32_t bytes
)
4827 buf
[0] = val
& 0xff;
4828 } else if (bytes
== 2) {
4829 buf
[0] = val
& 0xff;
4830 buf
[1] = (val
>> 8) & 0xff;
4832 buf
[0] = val
& 0xff;
4833 buf
[1] = (val
>> 8) & 0xff;
4834 buf
[2] = (val
>> 16) & 0xff;
4835 buf
[3] = (val
>> 24) & 0xff;
4839 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
4843 crc_init_buffer(buf
, val
, bytes
);
4845 /* zlib crc32 converts the accumulator and output to one's complement. */
4846 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
4849 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
4853 crc_init_buffer(buf
, val
, bytes
);
4855 /* Linux crc32c converts the output to one's complement. */
4856 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;