hw/i386/kvmvapic.c

   1 /*
   2  * TPR optimization for 32-bit Windows guests (XP and Server 2003)
   3  *
   4  * Copyright (C) 2007-2008 Qumranet Technologies
   5  * Copyright (C) 2012      Jan Kiszka, Siemens AG
   6  *
   7  * This work is licensed under the terms of the GNU GPL version 2, or
   8  * (at your option) any later version. See the COPYING file in the
   9  * top-level directory.
  10  */
  11 #include "sysemu/sysemu.h"
  12 #include "sysemu/cpus.h"
  13 #include "sysemu/kvm.h"
  14 #include "hw/i386/apic_internal.h"
  15 #include "hw/sysbus.h"
  16
  17 #define VAPIC_IO_PORT           0x7e
  18
  19 #define VAPIC_CPU_SHIFT         7
  20
  21 #define ROM_BLOCK_SIZE          512
  22 #define ROM_BLOCK_MASK          (~(ROM_BLOCK_SIZE - 1))
  23
  24 typedef enum VAPICMode {
  25     VAPIC_INACTIVE = 0,
  26     VAPIC_ACTIVE   = 1,
  27     VAPIC_STANDBY  = 2,
  28 } VAPICMode;
  29
  30 typedef struct VAPICHandlers {
  31     uint32_t set_tpr;
  32     uint32_t set_tpr_eax;
  33     uint32_t get_tpr[8];
  34     uint32_t get_tpr_stack;
  35 } QEMU_PACKED VAPICHandlers;
  36
  37 typedef struct GuestROMState {
  38     char signature[8];
  39     uint32_t vaddr;
  40     uint32_t fixup_start;
  41     uint32_t fixup_end;
  42     uint32_t vapic_vaddr;
  43     uint32_t vapic_size;
  44     uint32_t vcpu_shift;
  45     uint32_t real_tpr_addr;
  46     VAPICHandlers up;
  47     VAPICHandlers mp;
  48 } QEMU_PACKED GuestROMState;
  49
  50 typedef struct VAPICROMState {
  51     SysBusDevice busdev;
  52     MemoryRegion io;
  53     MemoryRegion rom;
  54     uint32_t state;
  55     uint32_t rom_state_paddr;
  56     uint32_t rom_state_vaddr;
  57     uint32_t vapic_paddr;
  58     uint32_t real_tpr_addr;
  59     GuestROMState rom_state;
  60     size_t rom_size;
  61     bool rom_mapped_writable;
  62 } VAPICROMState;
  63
  64 #define TYPE_VAPIC "kvmvapic"
  65 #define VAPIC(obj) OBJECT_CHECK(VAPICROMState, (obj), TYPE_VAPIC)
  66
  67 #define TPR_INSTR_ABS_MODRM             0x1
  68 #define TPR_INSTR_MATCH_MODRM_REG       0x2
  69
  70 typedef struct TPRInstruction {
  71     uint8_t opcode;
  72     uint8_t modrm_reg;
  73     unsigned int flags;
  74     TPRAccess access;
  75     size_t length;
  76     off_t addr_offset;
  77 } TPRInstruction;
  78
  79 /* must be sorted by length, shortest first */
  80 static const TPRInstruction tpr_instr[] = {
  81     { /* mov abs to eax */
  82         .opcode = 0xa1,
  83         .access = TPR_ACCESS_READ,
  84         .length = 5,
  85         .addr_offset = 1,
  86     },
  87     { /* mov eax to abs */
  88         .opcode = 0xa3,
  89         .access = TPR_ACCESS_WRITE,
  90         .length = 5,
  91         .addr_offset = 1,
  92     },
  93     { /* mov r32 to r/m32 */
  94         .opcode = 0x89,
  95         .flags = TPR_INSTR_ABS_MODRM,
  96         .access = TPR_ACCESS_WRITE,
  97         .length = 6,
  98         .addr_offset = 2,
  99     },
 100     { /* mov r/m32 to r32 */
 101         .opcode = 0x8b,
 102         .flags = TPR_INSTR_ABS_MODRM,
 103         .access = TPR_ACCESS_READ,
 104         .length = 6,
 105         .addr_offset = 2,
 106     },
 107     { /* push r/m32 */
 108         .opcode = 0xff,
 109         .modrm_reg = 6,
 110         .flags = TPR_INSTR_ABS_MODRM | TPR_INSTR_MATCH_MODRM_REG,
 111         .access = TPR_ACCESS_READ,
 112         .length = 6,
 113         .addr_offset = 2,
 114     },
 115     { /* mov imm32, r/m32 (c7/0) */
 116         .opcode = 0xc7,
 117         .modrm_reg = 0,
 118         .flags = TPR_INSTR_ABS_MODRM | TPR_INSTR_MATCH_MODRM_REG,
 119         .access = TPR_ACCESS_WRITE,
 120         .length = 10,
 121         .addr_offset = 2,
 122     },
 123 };
 124
 125 static void read_guest_rom_state(VAPICROMState *s)
 126 {
 127     cpu_physical_memory_rw(s->rom_state_paddr, (void *)&s->rom_state,
 128                            sizeof(GuestROMState), 0);
 129 }
 130
 131 static void write_guest_rom_state(VAPICROMState *s)
 132 {
 133     cpu_physical_memory_rw(s->rom_state_paddr, (void *)&s->rom_state,
 134                            sizeof(GuestROMState), 1);
 135 }
 136
 137 static void update_guest_rom_state(VAPICROMState *s)
 138 {
 139     read_guest_rom_state(s);
 140
 141     s->rom_state.real_tpr_addr = cpu_to_le32(s->real_tpr_addr);
 142     s->rom_state.vcpu_shift = cpu_to_le32(VAPIC_CPU_SHIFT);
 143
 144     write_guest_rom_state(s);
 145 }
 146
 147 static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env)
 148 {
 149     hwaddr paddr;
 150     target_ulong addr;
 151
 152     if (s->state == VAPIC_ACTIVE) {
 153         return 0;
 154     }
 155     /*
 156      * If there is no prior TPR access instruction we could analyze (which is
 157      * the case after resume from hibernation), we need to scan the possible
 158      * virtual address space for the APIC mapping.
 159      */
 160     for (addr = 0xfffff000; addr >= 0x80000000; addr -= TARGET_PAGE_SIZE) {
 161         paddr = cpu_get_phys_page_debug(env, addr);
 162         if (paddr != APIC_DEFAULT_ADDRESS) {
 163             continue;
 164         }
 165         s->real_tpr_addr = addr + 0x80;
 166         update_guest_rom_state(s);
 167         return 0;
 168     }
 169     return -1;
 170 }
 171
 172 static uint8_t modrm_reg(uint8_t modrm)
 173 {
 174     return (modrm >> 3) & 7;
 175 }
 176
 177 static bool is_abs_modrm(uint8_t modrm)
 178 {
 179     return (modrm & 0xc7) == 0x05;
 180 }
 181
 182 static bool opcode_matches(uint8_t *opcode, const TPRInstruction *instr)
 183 {
 184     return opcode[0] == instr->opcode &&
 185         (!(instr->flags & TPR_INSTR_ABS_MODRM) || is_abs_modrm(opcode[1])) &&
 186         (!(instr->flags & TPR_INSTR_MATCH_MODRM_REG) ||
 187          modrm_reg(opcode[1]) == instr->modrm_reg);
 188 }
 189
 190 static int evaluate_tpr_instruction(VAPICROMState *s, CPUX86State *env,
 191                                     target_ulong *pip, TPRAccess access)
 192 {
 193     const TPRInstruction *instr;
 194     target_ulong ip = *pip;
 195     uint8_t opcode[2];
 196     uint32_t real_tpr_addr;
 197     int i;
 198
 199     if ((ip & 0xf0000000ULL) != 0x80000000ULL &&
 200         (ip & 0xf0000000ULL) != 0xe0000000ULL) {
 201         return -1;
 202     }
 203
 204     /*
 205      * Early Windows 2003 SMP initialization contains a
 206      *
 207      *   mov imm32, r/m32
 208      *
 209      * instruction that is patched by TPR optimization. The problem is that
 210      * RSP, used by the patched instruction, is zero, so the guest gets a
 211      * double fault and dies.
 212      */
 213     if (env->regs[R_ESP] == 0) {
 214         return -1;
 215     }
 216
 217     if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
 218         /*
 219          * KVM without kernel-based TPR access reporting will pass an IP that
 220          * points after the accessing instruction. So we need to look backward
 221          * to find the reason.
 222          */
 223         for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) {
 224             instr = &tpr_instr[i];
 225             if (instr->access != access) {
 226                 continue;
 227             }
 228             if (cpu_memory_rw_debug(env, ip - instr->length, opcode,
 229                                     sizeof(opcode), 0) < 0) {
 230                 return -1;
 231             }
 232             if (opcode_matches(opcode, instr)) {
 233                 ip -= instr->length;
 234                 goto instruction_ok;
 235             }
 236         }
 237         return -1;
 238     } else {
 239         if (cpu_memory_rw_debug(env, ip, opcode, sizeof(opcode), 0) < 0) {
 240             return -1;
 241         }
 242         for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) {
 243             instr = &tpr_instr[i];
 244             if (opcode_matches(opcode, instr)) {
 245                 goto instruction_ok;
 246             }
 247         }
 248         return -1;
 249     }
 250
 251 instruction_ok:
 252     /*
 253      * Grab the virtual TPR address from the instruction
 254      * and update the cached values.
 255      */
 256     if (cpu_memory_rw_debug(env, ip + instr->addr_offset,
 257                             (void *)&real_tpr_addr,
 258                             sizeof(real_tpr_addr), 0) < 0) {
 259         return -1;
 260     }
 261     real_tpr_addr = le32_to_cpu(real_tpr_addr);
 262     if ((real_tpr_addr & 0xfff) != 0x80) {
 263         return -1;
 264     }
 265     s->real_tpr_addr = real_tpr_addr;
 266     update_guest_rom_state(s);
 267
 268     *pip = ip;
 269     return 0;
 270 }
 271
 272 static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong ip)
 273 {
 274     hwaddr paddr;
 275     uint32_t rom_state_vaddr;
 276     uint32_t pos, patch, offset;
 277
 278     /* nothing to do if already activated */
 279     if (s->state == VAPIC_ACTIVE) {
 280         return 0;
 281     }
 282
 283     /* bail out if ROM init code was not executed (missing ROM?) */
 284     if (s->state == VAPIC_INACTIVE) {
 285         return -1;
 286     }
 287
 288     /* find out virtual address of the ROM */
 289     rom_state_vaddr = s->rom_state_paddr + (ip & 0xf0000000);
 290     paddr = cpu_get_phys_page_debug(env, rom_state_vaddr);
 291     if (paddr == -1) {
 292         return -1;
 293     }
 294     paddr += rom_state_vaddr & ~TARGET_PAGE_MASK;
 295     if (paddr != s->rom_state_paddr) {
 296         return -1;
 297     }
 298     read_guest_rom_state(s);
 299     if (memcmp(s->rom_state.signature, "kvm aPiC", 8) != 0) {
 300         return -1;
 301     }
 302     s->rom_state_vaddr = rom_state_vaddr;
 303
 304     /* fixup addresses in ROM if needed */
 305     if (rom_state_vaddr == le32_to_cpu(s->rom_state.vaddr)) {
 306         return 0;
 307     }
 308     for (pos = le32_to_cpu(s->rom_state.fixup_start);
 309          pos < le32_to_cpu(s->rom_state.fixup_end);
 310          pos += 4) {
 311         cpu_physical_memory_rw(paddr + pos - s->rom_state.vaddr,
 312                                (void *)&offset, sizeof(offset), 0);
 313         offset = le32_to_cpu(offset);
 314         cpu_physical_memory_rw(paddr + offset, (void *)&patch,
 315                                sizeof(patch), 0);
 316         patch = le32_to_cpu(patch);
 317         patch += rom_state_vaddr - le32_to_cpu(s->rom_state.vaddr);
 318         patch = cpu_to_le32(patch);
 319         cpu_physical_memory_rw(paddr + offset, (void *)&patch,
 320                                sizeof(patch), 1);
 321     }
 322     read_guest_rom_state(s);
 323     s->vapic_paddr = paddr + le32_to_cpu(s->rom_state.vapic_vaddr) -
 324         le32_to_cpu(s->rom_state.vaddr);
 325
 326     return 0;
 327 }
 328
 329 /*
 330  * Tries to read the unique processor number from the Kernel Processor Control
 331  * Region (KPCR) of 32-bit Windows XP and Server 2003. Returns -1 if the KPCR
 332  * cannot be accessed or is considered invalid. This also ensures that we are
 333  * not patching the wrong guest.
 334  */
 335 static int get_kpcr_number(CPUX86State *env)
 336 {
 337     struct kpcr {
 338         uint8_t  fill1[0x1c];
 339         uint32_t self;
 340         uint8_t  fill2[0x31];
 341         uint8_t  number;
 342     } QEMU_PACKED kpcr;
 343
 344     if (cpu_memory_rw_debug(env, env->segs[R_FS].base,
 345                             (void *)&kpcr, sizeof(kpcr), 0) < 0 ||
 346         kpcr.self != env->segs[R_FS].base) {
 347         return -1;
 348     }
 349     return kpcr.number;
 350 }
 351
 352 static int vapic_enable(VAPICROMState *s, CPUX86State *env)
 353 {
 354     int cpu_number = get_kpcr_number(env);
 355     hwaddr vapic_paddr;
 356     static const uint8_t enabled = 1;
 357
 358     if (cpu_number < 0) {
 359         return -1;
 360     }
 361     vapic_paddr = s->vapic_paddr +
 362         (((hwaddr)cpu_number) << VAPIC_CPU_SHIFT);
 363     cpu_physical_memory_rw(vapic_paddr + offsetof(VAPICState, enabled),
 364                            (void *)&enabled, sizeof(enabled), 1);
 365     apic_enable_vapic(env->apic_state, vapic_paddr);
 366
 367     s->state = VAPIC_ACTIVE;
 368
 369     return 0;
 370 }
 371
 372 static void patch_byte(CPUX86State *env, target_ulong addr, uint8_t byte)
 373 {
 374     cpu_memory_rw_debug(env, addr, &byte, 1, 1);
 375 }
 376
 377 static void patch_call(VAPICROMState *s, CPUX86State *env, target_ulong ip,
 378                        uint32_t target)
 379 {
 380     uint32_t offset;
 381
 382     offset = cpu_to_le32(target - ip - 5);
 383     patch_byte(env, ip, 0xe8); /* call near */
 384     cpu_memory_rw_debug(env, ip + 1, (void *)&offset, sizeof(offset), 1);
 385 }
 386
 387 static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
 388 {
 389     CPUState *cs = CPU(cpu);
 390     CPUX86State *env = &cpu->env;
 391     VAPICHandlers *handlers;
 392     uint8_t opcode[2];
 393     uint32_t imm32;
 394     target_ulong current_pc = 0;
 395     target_ulong current_cs_base = 0;
 396     int current_flags = 0;
 397
 398     if (smp_cpus == 1) {
 399         handlers = &s->rom_state.up;
 400     } else {
 401         handlers = &s->rom_state.mp;
 402     }
 403
 404     if (!kvm_enabled()) {
 405         cpu_restore_state(env, env->mem_io_pc);
 406         cpu_get_tb_cpu_state(env, &current_pc, &current_cs_base,
 407                              &current_flags);
 408     }
 409
 410     pause_all_vcpus();
 411
 412     cpu_memory_rw_debug(env, ip, opcode, sizeof(opcode), 0);
 413
 414     switch (opcode[0]) {
 415     case 0x89: /* mov r32 to r/m32 */
 416         patch_byte(env, ip, 0x50 + modrm_reg(opcode[1]));  /* push reg */
 417         patch_call(s, env, ip + 1, handlers->set_tpr);
 418         break;
 419     case 0x8b: /* mov r/m32 to r32 */
 420         patch_byte(env, ip, 0x90);
 421         patch_call(s, env, ip + 1, handlers->get_tpr[modrm_reg(opcode[1])]);
 422         break;
 423     case 0xa1: /* mov abs to eax */
 424         patch_call(s, env, ip, handlers->get_tpr[0]);
 425         break;
 426     case 0xa3: /* mov eax to abs */
 427         patch_call(s, env, ip, handlers->set_tpr_eax);
 428         break;
 429     case 0xc7: /* mov imm32, r/m32 (c7/0) */
 430         patch_byte(env, ip, 0x68);  /* push imm32 */
 431         cpu_memory_rw_debug(env, ip + 6, (void *)&imm32, sizeof(imm32), 0);
 432         cpu_memory_rw_debug(env, ip + 1, (void *)&imm32, sizeof(imm32), 1);
 433         patch_call(s, env, ip + 5, handlers->set_tpr);
 434         break;
 435     case 0xff: /* push r/m32 */
 436         patch_byte(env, ip, 0x50); /* push eax */
 437         patch_call(s, env, ip + 1, handlers->get_tpr_stack);
 438         break;
 439     default:
 440         abort();
 441     }
 442
 443     resume_all_vcpus();
 444
 445     if (!kvm_enabled()) {
 446         cs->current_tb = NULL;
 447         tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
 448         cpu_resume_from_signal(env, NULL);
 449     }
 450 }
 451
 452 void vapic_report_tpr_access(DeviceState *dev, CPUState *cs, target_ulong ip,
 453                              TPRAccess access)
 454 {
 455     VAPICROMState *s = DO_UPCAST(VAPICROMState, busdev.qdev, dev);
 456     X86CPU *cpu = X86_CPU(cs);
 457     CPUX86State *env = &cpu->env;
 458
 459     cpu_synchronize_state(env);
 460
 461     if (evaluate_tpr_instruction(s, env, &ip, access) < 0) {
 462         if (s->state == VAPIC_ACTIVE) {
 463             vapic_enable(s, env);
 464         }
 465         return;
 466     }
 467     if (update_rom_mapping(s, env, ip) < 0) {
 468         return;
 469     }
 470     if (vapic_enable(s, env) < 0) {
 471         return;
 472     }
 473     patch_instruction(s, cpu, ip);
 474 }
 475
 476 typedef struct VAPICEnableTPRReporting {
 477     DeviceState *apic;
 478     bool enable;
 479 } VAPICEnableTPRReporting;
 480
 481 static void vapic_do_enable_tpr_reporting(void *data)
 482 {
 483     VAPICEnableTPRReporting *info = data;
 484
 485     apic_enable_tpr_access_reporting(info->apic, info->enable);
 486 }
 487
 488 static void vapic_enable_tpr_reporting(bool enable)
 489 {
 490     VAPICEnableTPRReporting info = {
 491         .enable = enable,
 492     };
 493     X86CPU *cpu;
 494     CPUX86State *env;
 495
 496     for (env = first_cpu; env != NULL; env = env->next_cpu) {
 497         cpu = x86_env_get_cpu(env);
 498         info.apic = env->apic_state;
 499         run_on_cpu(CPU(cpu), vapic_do_enable_tpr_reporting, &info);
 500     }
 501 }
 502
 503 static void vapic_reset(DeviceState *dev)
 504 {
 505     VAPICROMState *s = DO_UPCAST(VAPICROMState, busdev.qdev, dev);
 506
 507     if (s->state == VAPIC_ACTIVE) {
 508         s->state = VAPIC_STANDBY;
 509     }
 510     vapic_enable_tpr_reporting(false);
 511 }
 512
 513 /*
 514  * Set the IRQ polling hypercalls to the supported variant:
 515  *  - vmcall if using KVM in-kernel irqchip
 516  *  - 32-bit VAPIC port write otherwise
 517  */
 518 static int patch_hypercalls(VAPICROMState *s)
 519 {
 520     hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
 521     static const uint8_t vmcall_pattern[] = { /* vmcall */
 522         0xb8, 0x1, 0, 0, 0, 0xf, 0x1, 0xc1
 523     };
 524     static const uint8_t outl_pattern[] = { /* nop; outl %eax,0x7e */
 525         0xb8, 0x1, 0, 0, 0, 0x90, 0xe7, 0x7e
 526     };
 527     uint8_t alternates[2];
 528     const uint8_t *pattern;
 529     const uint8_t *patch;
 530     int patches = 0;
 531     off_t pos;
 532     uint8_t *rom;
 533
 534     rom = g_malloc(s->rom_size);
 535     cpu_physical_memory_rw(rom_paddr, rom, s->rom_size, 0);
 536
 537     for (pos = 0; pos < s->rom_size - sizeof(vmcall_pattern); pos++) {
 538         if (kvm_irqchip_in_kernel()) {
 539             pattern = outl_pattern;
 540             alternates[0] = outl_pattern[7];
 541             alternates[1] = outl_pattern[7];
 542             patch = &vmcall_pattern[5];
 543         } else {
 544             pattern = vmcall_pattern;
 545             alternates[0] = vmcall_pattern[7];
 546             alternates[1] = 0xd9; /* AMD's VMMCALL */
 547             patch = &outl_pattern[5];
 548         }
 549         if (memcmp(rom + pos, pattern, 7) == 0 &&
 550             (rom[pos + 7] == alternates[0] || rom[pos + 7] == alternates[1])) {
 551             cpu_physical_memory_rw(rom_paddr + pos + 5, (uint8_t *)patch,
 552                                    3, 1);
 553             /*
 554              * Don't flush the tb here. Under ordinary conditions, the patched
 555              * calls are miles away from the current IP. Under malicious
 556              * conditions, the guest could trick us to crash.
 557              */
 558         }
 559     }
 560
 561     g_free(rom);
 562
 563     if (patches != 0 && patches != 2) {
 564         return -1;
 565     }
 566
 567     return 0;
 568 }
 569
 570 /*
 571  * For TCG mode or the time KVM honors read-only memory regions, we need to
 572  * enable write access to the option ROM so that variables can be updated by
 573  * the guest.
 574  */
 575 static void vapic_map_rom_writable(VAPICROMState *s)
 576 {
 577     hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
 578     MemoryRegionSection section;
 579     MemoryRegion *as;
 580     size_t rom_size;
 581     uint8_t *ram;
 582
 583     as = sysbus_address_space(&s->busdev);
 584
 585     if (s->rom_mapped_writable) {
 586         memory_region_del_subregion(as, &s->rom);
 587         memory_region_destroy(&s->rom);
 588     }
 589
 590     /* grab RAM memory region (region @rom_paddr may still be pc.rom) */
 591     section = memory_region_find(as, 0, 1);
 592
 593     /* read ROM size from RAM region */
 594     ram = memory_region_get_ram_ptr(section.mr);
 595     rom_size = ram[rom_paddr + 2] * ROM_BLOCK_SIZE;
 596     s->rom_size = rom_size;
 597
 598     /* We need to round to avoid creating subpages
 599      * from which we cannot run code. */
 600     rom_size += rom_paddr & ~TARGET_PAGE_MASK;
 601     rom_paddr &= TARGET_PAGE_MASK;
 602     rom_size = TARGET_PAGE_ALIGN(rom_size);
 603
 604     memory_region_init_alias(&s->rom, "kvmvapic-rom", section.mr, rom_paddr,
 605                              rom_size);
 606     memory_region_add_subregion_overlap(as, rom_paddr, &s->rom, 1000);
 607     s->rom_mapped_writable = true;
 608 }
 609
 610 static int vapic_prepare(VAPICROMState *s)
 611 {
 612     vapic_map_rom_writable(s);
 613
 614     if (patch_hypercalls(s) < 0) {
 615         return -1;
 616     }
 617
 618     vapic_enable_tpr_reporting(true);
 619
 620     return 0;
 621 }
 622
 623 static void vapic_write(void *opaque, hwaddr addr, uint64_t data,
 624                         unsigned int size)
 625 {
 626     CPUX86State *env = cpu_single_env;
 627     hwaddr rom_paddr;
 628     VAPICROMState *s = opaque;
 629
 630     cpu_synchronize_state(env);
 631
 632     /*
 633      * The VAPIC supports two PIO-based hypercalls, both via port 0x7E.
 634      *  o 16-bit write access:
 635      *    Reports the option ROM initialization to the hypervisor. Written
 636      *    value is the offset of the state structure in the ROM.
 637      *  o 8-bit write access:
 638      *    Reactivates the VAPIC after a guest hibernation, i.e. after the
 639      *    option ROM content has been re-initialized by a guest power cycle.
 640      *  o 32-bit write access:
 641      *    Poll for pending IRQs, considering the current VAPIC state.
 642      */
 643     switch (size) {
 644     case 2:
 645         if (s->state == VAPIC_INACTIVE) {
 646             rom_paddr = (env->segs[R_CS].base + env->eip) & ROM_BLOCK_MASK;
 647             s->rom_state_paddr = rom_paddr + data;
 648
 649             s->state = VAPIC_STANDBY;
 650         }
 651         if (vapic_prepare(s) < 0) {
 652             s->state = VAPIC_INACTIVE;
 653             break;
 654         }
 655         break;
 656     case 1:
 657         if (kvm_enabled()) {
 658             /*
 659              * Disable triggering instruction in ROM by writing a NOP.
 660              *
 661              * We cannot do this in TCG mode as the reported IP is not
 662              * accurate.
 663              */
 664             pause_all_vcpus();
 665             patch_byte(env, env->eip - 2, 0x66);
 666             patch_byte(env, env->eip - 1, 0x90);
 667             resume_all_vcpus();
 668         }
 669
 670         if (s->state == VAPIC_ACTIVE) {
 671             break;
 672         }
 673         if (update_rom_mapping(s, env, env->eip) < 0) {
 674             break;
 675         }
 676         if (find_real_tpr_addr(s, env) < 0) {
 677             break;
 678         }
 679         vapic_enable(s, env);
 680         break;
 681     default:
 682     case 4:
 683         if (!kvm_irqchip_in_kernel()) {
 684             apic_poll_irq(env->apic_state);
 685         }
 686         break;
 687     }
 688 }
 689
 690 static uint64_t vapic_read(void *opaque, hwaddr addr, unsigned size)
 691 {
 692     return 0xffffffff;
 693 }
 694
 695 static const MemoryRegionOps vapic_ops = {
 696     .write = vapic_write,
 697     .read = vapic_read,
 698     .endianness = DEVICE_NATIVE_ENDIAN,
 699 };
 700
 701 static int vapic_init(SysBusDevice *dev)
 702 {
 703     VAPICROMState *s = VAPIC(dev);
 704
 705     memory_region_init_io(&s->io, &vapic_ops, s, "kvmvapic", 2);
 706     sysbus_add_io(dev, VAPIC_IO_PORT, &s->io);
 707     sysbus_init_ioports(dev, VAPIC_IO_PORT, 2);
 708
 709     option_rom[nb_option_roms].name = "kvmvapic.bin";
 710     option_rom[nb_option_roms].bootindex = -1;
 711     nb_option_roms++;
 712
 713     return 0;
 714 }
 715
 716 static void do_vapic_enable(void *data)
 717 {
 718     VAPICROMState *s = data;
 719
 720     vapic_enable(s, first_cpu);
 721 }
 722
 723 static int vapic_post_load(void *opaque, int version_id)
 724 {
 725     VAPICROMState *s = opaque;
 726     uint8_t *zero;
 727
 728     /*
 729      * The old implementation of qemu-kvm did not provide the state
 730      * VAPIC_STANDBY. Reconstruct it.
 731      */
 732     if (s->state == VAPIC_INACTIVE && s->rom_state_paddr != 0) {
 733         s->state = VAPIC_STANDBY;
 734     }
 735
 736     if (s->state != VAPIC_INACTIVE) {
 737         if (vapic_prepare(s) < 0) {
 738             return -1;
 739         }
 740     }
 741     if (s->state == VAPIC_ACTIVE) {
 742         if (smp_cpus == 1) {
 743             run_on_cpu(ENV_GET_CPU(first_cpu), do_vapic_enable, s);
 744         } else {
 745             zero = g_malloc0(s->rom_state.vapic_size);
 746             cpu_physical_memory_rw(s->vapic_paddr, zero,
 747                                    s->rom_state.vapic_size, 1);
 748             g_free(zero);
 749         }
 750     }
 751
 752     return 0;
 753 }
 754
 755 static const VMStateDescription vmstate_handlers = {
 756     .name = "kvmvapic-handlers",
 757     .version_id = 1,
 758     .minimum_version_id = 1,
 759     .minimum_version_id_old = 1,
 760     .fields = (VMStateField[]) {
 761         VMSTATE_UINT32(set_tpr, VAPICHandlers),
 762         VMSTATE_UINT32(set_tpr_eax, VAPICHandlers),
 763         VMSTATE_UINT32_ARRAY(get_tpr, VAPICHandlers, 8),
 764         VMSTATE_UINT32(get_tpr_stack, VAPICHandlers),
 765         VMSTATE_END_OF_LIST()
 766     }
 767 };
 768
 769 static const VMStateDescription vmstate_guest_rom = {
 770     .name = "kvmvapic-guest-rom",
 771     .version_id = 1,
 772     .minimum_version_id = 1,
 773     .minimum_version_id_old = 1,
 774     .fields = (VMStateField[]) {
 775         VMSTATE_UNUSED(8),     /* signature */
 776         VMSTATE_UINT32(vaddr, GuestROMState),
 777         VMSTATE_UINT32(fixup_start, GuestROMState),
 778         VMSTATE_UINT32(fixup_end, GuestROMState),
 779         VMSTATE_UINT32(vapic_vaddr, GuestROMState),
 780         VMSTATE_UINT32(vapic_size, GuestROMState),
 781         VMSTATE_UINT32(vcpu_shift, GuestROMState),
 782         VMSTATE_UINT32(real_tpr_addr, GuestROMState),
 783         VMSTATE_STRUCT(up, GuestROMState, 0, vmstate_handlers, VAPICHandlers),
 784         VMSTATE_STRUCT(mp, GuestROMState, 0, vmstate_handlers, VAPICHandlers),
 785         VMSTATE_END_OF_LIST()
 786     }
 787 };
 788
 789 static const VMStateDescription vmstate_vapic = {
 790     .name = "kvm-tpr-opt",      /* compatible with qemu-kvm VAPIC */
 791     .version_id = 1,
 792     .minimum_version_id = 1,
 793     .minimum_version_id_old = 1,
 794     .post_load = vapic_post_load,
 795     .fields = (VMStateField[]) {
 796         VMSTATE_STRUCT(rom_state, VAPICROMState, 0, vmstate_guest_rom,
 797                        GuestROMState),
 798         VMSTATE_UINT32(state, VAPICROMState),
 799         VMSTATE_UINT32(real_tpr_addr, VAPICROMState),
 800         VMSTATE_UINT32(rom_state_vaddr, VAPICROMState),
 801         VMSTATE_UINT32(vapic_paddr, VAPICROMState),
 802         VMSTATE_UINT32(rom_state_paddr, VAPICROMState),
 803         VMSTATE_END_OF_LIST()
 804     }
 805 };
 806
 807 static void vapic_class_init(ObjectClass *klass, void *data)
 808 {
 809     SysBusDeviceClass *sc = SYS_BUS_DEVICE_CLASS(klass);
 810     DeviceClass *dc = DEVICE_CLASS(klass);
 811
 812     dc->no_user = 1;
 813     dc->reset   = vapic_reset;
 814     dc->vmsd    = &vmstate_vapic;
 815     sc->init    = vapic_init;
 816 }
 817
 818 static const TypeInfo vapic_type = {
 819     .name          = TYPE_VAPIC,
 820     .parent        = TYPE_SYS_BUS_DEVICE,
 821     .instance_size = sizeof(VAPICROMState),
 822     .class_init    = vapic_class_init,
 823 };
 824
 825 static void vapic_register(void)
 826 {
 827     type_register_static(&vapic_type);
 828 }
 829
 830 type_init(vapic_register);