include/exec/cpu-defs.h

   1 /*
   2  * common defines for all CPUs
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_DEFS_H
  20 #define CPU_DEFS_H
  21
  22 #ifndef NEED_CPU_H
  23 #error cpu.h included from common code
  24 #endif
  25
  26 #include "qemu/host-utils.h"
  27 #include "qemu/queue.h"
  28 #include "tcg-target.h"
  29 #ifndef CONFIG_USER_ONLY
  30 #include "exec/hwaddr.h"
  31 #endif
  32 #include "exec/memattrs.h"
  33
  34 #ifndef TARGET_LONG_BITS
  35 #error TARGET_LONG_BITS must be defined before including this header
  36 #endif
  37
  38 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
  39
  40 /* target_ulong is the type of a virtual address */
  41 #if TARGET_LONG_SIZE == 4
  42 typedef int32_t target_long;
  43 typedef uint32_t target_ulong;
  44 #define TARGET_FMT_lx "%08x"
  45 #define TARGET_FMT_ld "%d"
  46 #define TARGET_FMT_lu "%u"
  47 #elif TARGET_LONG_SIZE == 8
  48 typedef int64_t target_long;
  49 typedef uint64_t target_ulong;
  50 #define TARGET_FMT_lx "%016" PRIx64
  51 #define TARGET_FMT_ld "%" PRId64
  52 #define TARGET_FMT_lu "%" PRIu64
  53 #else
  54 #error TARGET_LONG_SIZE undefined
  55 #endif
  56
  57 #if !defined(CONFIG_USER_ONLY)
  58 /* use a fully associative victim tlb of 8 entries */
  59 #define CPU_VTLB_SIZE 8
  60
  61 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
  62 #define CPU_TLB_ENTRY_BITS 4
  63 #else
  64 #define CPU_TLB_ENTRY_BITS 5
  65 #endif
  66
  67 /* TCG_TARGET_TLB_DISPLACEMENT_BITS is used in CPU_TLB_BITS to ensure that
  68  * the TLB is not unnecessarily small, but still small enough for the
  69  * TLB lookup instruction sequence used by the TCG target.
  70  *
  71  * TCG will have to generate an operand as large as the distance between
  72  * env and the tlb_table[NB_MMU_MODES - 1][0].addend.  For simplicity,
  73  * the TCG targets just round everything up to the next power of two, and
  74  * count bits.  This works because: 1) the size of each TLB is a largish
  75  * power of two, 2) and because the limit of the displacement is really close
  76  * to a power of two, 3) the offset of tlb_table[0][0] inside env is smaller
  77  * than the size of a TLB.
  78  *
  79  * For example, the maximum displacement 0xFFF0 on PPC and MIPS, but TCG
  80  * just says "the displacement is 16 bits".  TCG_TARGET_TLB_DISPLACEMENT_BITS
  81  * then ensures that tlb_table at least 0x8000 bytes large ("not unnecessarily
  82  * small": 2^15).  The operand then will come up smaller than 0xFFF0 without
  83  * any particular care, because the TLB for a single MMU mode is larger than
  84  * 0x10000-0xFFF0=16 bytes.  In the end, the maximum value of the operand
  85  * could be something like 0xC000 (the offset of the last TLB table) plus
  86  * 0x18 (the offset of the addend field in each TLB entry) plus the offset
  87  * of tlb_table inside env (which is non-trivial but not huge).
  88  */
  89 #define CPU_TLB_BITS                                             \
  90     MIN(8,                                                       \
  91         TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS -  \
  92         (NB_MMU_MODES <= 1 ? 0 :                                 \
  93          NB_MMU_MODES <= 2 ? 1 :                                 \
  94          NB_MMU_MODES <= 4 ? 2 :                                 \
  95          NB_MMU_MODES <= 8 ? 3 : 4))
  96
  97 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
  98
  99 typedef struct CPUTLBEntry {
 100     /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
 101        bit TARGET_PAGE_BITS-1..4  : Nonzero for accesses that should not
 102                                     go directly to ram.
 103        bit 3                      : indicates that the entry is invalid
 104        bit 2..0                   : zero
 105     */
 106     union {
 107         struct {
 108             target_ulong addr_read;
 109             target_ulong addr_write;
 110             target_ulong addr_code;
 111             /* Addend to virtual address to get host address.  IO accesses
 112                use the corresponding iotlb value.  */
 113             uintptr_t addend;
 114         };
 115         /* padding to get a power of two size */
 116         uint8_t dummy[1 << CPU_TLB_ENTRY_BITS];
 117     };
 118 } CPUTLBEntry;
 119
 120 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
 121
 122 /* The IOTLB is not accessed directly inline by generated TCG code,
 123  * so the CPUIOTLBEntry layout is not as critical as that of the
 124  * CPUTLBEntry. (This is also why we don't want to combine the two
 125  * structs into one.)
 126  */
 127 typedef struct CPUIOTLBEntry {
 128     hwaddr addr;
 129     MemTxAttrs attrs;
 130 } CPUIOTLBEntry;
 131
 132 #define CPU_COMMON_TLB \
 133     /* The meaning of the MMU modes is defined in the target code. */   \
 134     CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                  \
 135     CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE];               \
 136     CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE];                    \
 137     CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE];                 \
 138     target_ulong tlb_flush_addr;                                        \
 139     target_ulong tlb_flush_mask;                                        \
 140     target_ulong vtlb_index;                                            \
 141
 142 #else
 143
 144 #define CPU_COMMON_TLB
 145
 146 #endif
 147
 148
 149 #define CPU_COMMON                                                      \
 150     /* soft mmu support */                                              \
 151     CPU_COMMON_TLB                                                      \
 152
 153 #endif