2 * RISC-V Emulation Helpers for QEMU.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
23 #include "qemu/main-loop.h"
24 #include "exec/exec-all.h"
25 #include "exec/helper-proto.h"
27 /* Exceptions processing helpers */
28 void QEMU_NORETURN
do_raise_exception_err(CPURISCVState
*env
,
29 uint32_t exception
, uintptr_t pc
)
31 CPUState
*cs
= CPU(riscv_env_get_cpu(env
));
32 qemu_log_mask(CPU_LOG_INT
, "%s: %d\n", __func__
, exception
);
33 cs
->exception_index
= exception
;
34 cpu_loop_exit_restore(cs
, pc
);
37 void helper_raise_exception(CPURISCVState
*env
, uint32_t exception
)
39 do_raise_exception_err(env
, exception
, 0);
42 target_ulong
helper_csrrw(CPURISCVState
*env
, target_ulong src
,
46 if (riscv_csrrw(env
, csr
, &val
, src
, -1) < 0) {
47 do_raise_exception_err(env
, RISCV_EXCP_ILLEGAL_INST
, GETPC());
52 target_ulong
helper_csrrs(CPURISCVState
*env
, target_ulong src
,
53 target_ulong csr
, target_ulong rs1_pass
)
56 if (riscv_csrrw(env
, csr
, &val
, -1, rs1_pass
? src
: 0) < 0) {
57 do_raise_exception_err(env
, RISCV_EXCP_ILLEGAL_INST
, GETPC());
62 target_ulong
helper_csrrc(CPURISCVState
*env
, target_ulong src
,
63 target_ulong csr
, target_ulong rs1_pass
)
66 if (riscv_csrrw(env
, csr
, &val
, 0, rs1_pass
? src
: 0) < 0) {
67 do_raise_exception_err(env
, RISCV_EXCP_ILLEGAL_INST
, GETPC());
72 #ifndef CONFIG_USER_ONLY
74 target_ulong
helper_sret(CPURISCVState
*env
, target_ulong cpu_pc_deb
)
76 if (!(env
->priv
>= PRV_S
)) {
77 do_raise_exception_err(env
, RISCV_EXCP_ILLEGAL_INST
, GETPC());
80 target_ulong retpc
= env
->sepc
;
81 if (!riscv_has_ext(env
, RVC
) && (retpc
& 0x3)) {
82 do_raise_exception_err(env
, RISCV_EXCP_INST_ADDR_MIS
, GETPC());
85 target_ulong mstatus
= env
->mstatus
;
86 target_ulong prev_priv
= get_field(mstatus
, MSTATUS_SPP
);
87 mstatus
= set_field(mstatus
,
88 env
->priv_ver
>= PRIV_VERSION_1_10_0
?
89 MSTATUS_SIE
: MSTATUS_UIE
<< prev_priv
,
90 get_field(mstatus
, MSTATUS_SPIE
));
91 mstatus
= set_field(mstatus
, MSTATUS_SPIE
, 0);
92 mstatus
= set_field(mstatus
, MSTATUS_SPP
, PRV_U
);
93 riscv_set_mode(env
, prev_priv
);
94 env
->mstatus
= mstatus
;
99 target_ulong
helper_mret(CPURISCVState
*env
, target_ulong cpu_pc_deb
)
101 if (!(env
->priv
>= PRV_M
)) {
102 do_raise_exception_err(env
, RISCV_EXCP_ILLEGAL_INST
, GETPC());
105 target_ulong retpc
= env
->mepc
;
106 if (!riscv_has_ext(env
, RVC
) && (retpc
& 0x3)) {
107 do_raise_exception_err(env
, RISCV_EXCP_INST_ADDR_MIS
, GETPC());
110 target_ulong mstatus
= env
->mstatus
;
111 target_ulong prev_priv
= get_field(mstatus
, MSTATUS_MPP
);
112 mstatus
= set_field(mstatus
,
113 env
->priv_ver
>= PRIV_VERSION_1_10_0
?
114 MSTATUS_MIE
: MSTATUS_UIE
<< prev_priv
,
115 get_field(mstatus
, MSTATUS_MPIE
));
116 mstatus
= set_field(mstatus
, MSTATUS_MPIE
, 0);
117 mstatus
= set_field(mstatus
, MSTATUS_MPP
, PRV_U
);
118 riscv_set_mode(env
, prev_priv
);
119 env
->mstatus
= mstatus
;
124 void helper_wfi(CPURISCVState
*env
)
126 CPUState
*cs
= CPU(riscv_env_get_cpu(env
));
129 cs
->exception_index
= EXCP_HLT
;
133 void helper_tlb_flush(CPURISCVState
*env
)
135 RISCVCPU
*cpu
= riscv_env_get_cpu(env
);
136 CPUState
*cs
= CPU(cpu
);
140 #endif /* !CONFIG_USER_ONLY */