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chardev: ensure qemu_chr_parse_compat reports missing driver error
[qemu/ar7.git] / target / mips / helper.c
blob8988452dbd79504aac89bab37357d1a29be85e43
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20
21 #include "cpu.h"
22 #include "internal.h"
23 #include "exec/exec-all.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/log.h"
26 #include "hw/mips/cpudevs.h"
27
28 enum {
29 TLBRET_XI = -6,
30 TLBRET_RI = -5,
31 TLBRET_DIRTY = -4,
32 TLBRET_INVALID = -3,
33 TLBRET_NOMATCH = -2,
34 TLBRET_BADADDR = -1,
35 TLBRET_MATCH = 0
36 };
37
38 #if !defined(CONFIG_USER_ONLY)
39
40 /* no MMU emulation */
41 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
42 target_ulong address, int rw, int access_type)
43 {
44 *physical = address;
45 *prot = PAGE_READ | PAGE_WRITE;
46 return TLBRET_MATCH;
47 }
48
49 /* fixed mapping MMU emulation */
50 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
51 target_ulong address, int rw, int access_type)
52 {
53 if (address <= (int32_t)0x7FFFFFFFUL) {
54 if (!(env->CP0_Status & (1 << CP0St_ERL)))
55 *physical = address + 0x40000000UL;
56 else
57 *physical = address;
58 } else if (address <= (int32_t)0xBFFFFFFFUL)
59 *physical = address & 0x1FFFFFFF;
60 else
61 *physical = address;
62
63 *prot = PAGE_READ | PAGE_WRITE;
64 return TLBRET_MATCH;
65 }
66
67 /* MIPS32/MIPS64 R4000-style MMU emulation */
68 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
69 target_ulong address, int rw, int access_type)
70 {
71 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
72 int i;
73
74 for (i = 0; i < env->tlb->tlb_in_use; i++) {
75 r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
76 /* 1k pages are not supported. */
77 target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
78 target_ulong tag = address & ~mask;
79 target_ulong VPN = tlb->VPN & ~mask;
80 #if defined(TARGET_MIPS64)
81 tag &= env->SEGMask;
82 #endif
83
84 /* Check ASID, virtual page number & size */
85 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
86 /* TLB match */
87 int n = !!(address & mask & ~(mask >> 1));
88 /* Check access rights */
89 if (!(n ? tlb->V1 : tlb->V0)) {
90 return TLBRET_INVALID;
91 }
92 if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
93 return TLBRET_XI;
94 }
95 if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
96 return TLBRET_RI;
97 }
98 if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
99 *physical = tlb->PFN[n] | (address & (mask >> 1));
100 *prot = PAGE_READ;
101 if (n ? tlb->D1 : tlb->D0)
102 *prot |= PAGE_WRITE;
103 return TLBRET_MATCH;
104 }
105 return TLBRET_DIRTY;
106 }
107 }
108 return TLBRET_NOMATCH;
109 }
110
111 static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
112 {
113 /*
114 * Interpret access control mode and mmu_idx.
115 * AdE? TLB?
116 * AM K S U E K S U E
117 * UK 0 0 1 1 0 0 - - 0
118 * MK 1 0 1 1 0 1 - - !eu
119 * MSK 2 0 0 1 0 1 1 - !eu
120 * MUSK 3 0 0 0 0 1 1 1 !eu
121 * MUSUK 4 0 0 0 0 0 1 1 0
122 * USK 5 0 0 1 0 0 0 - 0
123 * - 6 - - - - - - - -
124 * UUSK 7 0 0 0 0 0 0 0 0
125 */
126 int32_t adetlb_mask;
127
128 switch (mmu_idx) {
129 case 3 /* ERL */:
130 /* If EU is set, always unmapped */
131 if (eu) {
132 return 0;
133 }
134 /* fall through */
135 case MIPS_HFLAG_KM:
136 /* Never AdE, TLB mapped if AM={1,2,3} */
137 adetlb_mask = 0x70000000;
138 goto check_tlb;
139
140 case MIPS_HFLAG_SM:
141 /* AdE if AM={0,1}, TLB mapped if AM={2,3,4} */
142 adetlb_mask = 0xc0380000;
143 goto check_ade;
144
145 case MIPS_HFLAG_UM:
146 /* AdE if AM={0,1,2,5}, TLB mapped if AM={3,4} */
147 adetlb_mask = 0xe4180000;
148 /* fall through */
149 check_ade:
150 /* does this AM cause AdE in current execution mode */
151 if ((adetlb_mask << am) < 0) {
152 return TLBRET_BADADDR;
153 }
154 adetlb_mask <<= 8;
155 /* fall through */
156 check_tlb:
157 /* is this AM mapped in current execution mode */
158 return ((adetlb_mask << am) < 0);
159 default:
160 assert(0);
161 return TLBRET_BADADDR;
162 };
163 }
164
165 static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical,
166 int *prot, target_ulong real_address,
167 int rw, int access_type, int mmu_idx,
168 unsigned int am, bool eu,
169 target_ulong segmask,
170 hwaddr physical_base)
171 {
172 int mapped = is_seg_am_mapped(am, eu, mmu_idx);
173
174 if (mapped < 0) {
175 /* is_seg_am_mapped can report TLBRET_BADADDR */
176 return mapped;
177 } else if (mapped) {
178 /* The segment is TLB mapped */
179 return env->tlb->map_address(env, physical, prot, real_address, rw,
180 access_type);
181 } else {
182 /* The segment is unmapped */
183 *physical = physical_base | (real_address & segmask);
184 *prot = PAGE_READ | PAGE_WRITE;
185 return TLBRET_MATCH;
186 }
187 }
188
189 static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical,
190 int *prot, target_ulong real_address,
191 int rw, int access_type, int mmu_idx,
192 uint16_t segctl, target_ulong segmask)
193 {
194 unsigned int am = (segctl & CP0SC_AM_MASK) >> CP0SC_AM;
195 bool eu = (segctl >> CP0SC_EU) & 1;
196 hwaddr pa = ((hwaddr)segctl & CP0SC_PA_MASK) << 20;
197
198 return get_seg_physical_address(env, physical, prot, real_address, rw,
199 access_type, mmu_idx, am, eu, segmask,
200 pa & ~(hwaddr)segmask);
201 }
202
203 static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
204 int *prot, target_ulong real_address,
205 int rw, int access_type, int mmu_idx)
206 {
207 /* User mode can only access useg/xuseg */
208 #if defined(TARGET_MIPS64)
209 int user_mode = mmu_idx == MIPS_HFLAG_UM;
210 int supervisor_mode = mmu_idx == MIPS_HFLAG_SM;
211 int kernel_mode = !user_mode && !supervisor_mode;
212 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
213 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
214 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
215 #endif
216 int ret = TLBRET_MATCH;
217 /* effective address (modified for KVM T&E kernel segments) */
218 target_ulong address = real_address;
219
220 #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL)
221 #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL)
222 #define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL)
223 #define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL)
224 #define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL)
225
226 #define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL)
227 #define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL)
228
229 if (mips_um_ksegs_enabled()) {
230 /* KVM T&E adds guest kernel segments in useg */
231 if (real_address >= KVM_KSEG0_BASE) {
232 if (real_address < KVM_KSEG2_BASE) {
233 /* kseg0 */
234 address += KSEG0_BASE - KVM_KSEG0_BASE;
235 } else if (real_address <= USEG_LIMIT) {
236 /* kseg2/3 */
237 address += KSEG2_BASE - KVM_KSEG2_BASE;
238 }
239 }
240 }
241
242 if (address <= USEG_LIMIT) {
243 /* useg */
244 uint16_t segctl;
245
246 if (address >= 0x40000000UL) {
247 segctl = env->CP0_SegCtl2;
248 } else {
249 segctl = env->CP0_SegCtl2 >> 16;
250 }
251 ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
252 access_type, mmu_idx, segctl,
253 0x3FFFFFFF);
254 #if defined(TARGET_MIPS64)
255 } else if (address < 0x4000000000000000ULL) {
256 /* xuseg */
257 if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
258 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
259 } else {
260 ret = TLBRET_BADADDR;
261 }
262 } else if (address < 0x8000000000000000ULL) {
263 /* xsseg */
264 if ((supervisor_mode || kernel_mode) &&
265 SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
266 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
267 } else {
268 ret = TLBRET_BADADDR;
269 }
270 } else if (address < 0xC000000000000000ULL) {
271 /* xkphys */
272 if ((address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
273 /* KX/SX/UX bit to check for each xkphys EVA access mode */
274 static const uint8_t am_ksux[8] = {
275 [CP0SC_AM_UK] = (1u << CP0St_KX),
276 [CP0SC_AM_MK] = (1u << CP0St_KX),
277 [CP0SC_AM_MSK] = (1u << CP0St_SX),
278 [CP0SC_AM_MUSK] = (1u << CP0St_UX),
279 [CP0SC_AM_MUSUK] = (1u << CP0St_UX),
280 [CP0SC_AM_USK] = (1u << CP0St_SX),
281 [6] = (1u << CP0St_KX),
282 [CP0SC_AM_UUSK] = (1u << CP0St_UX),
283 };
284 unsigned int am = CP0SC_AM_UK;
285 unsigned int xr = (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0SC2_XR;
286
287 if (xr & (1 << ((address >> 59) & 0x7))) {
288 am = (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM;
289 }
290 /* Does CP0_Status.KX/SX/UX permit the access mode (am) */
291 if (env->CP0_Status & am_ksux[am]) {
292 ret = get_seg_physical_address(env, physical, prot,
293 real_address, rw, access_type,
294 mmu_idx, am, false, env->PAMask,
295 0);
296 } else {
297 ret = TLBRET_BADADDR;
298 }
299 } else {
300 ret = TLBRET_BADADDR;
301 }
302 } else if (address < 0xFFFFFFFF80000000ULL) {
303 /* xkseg */
304 if (kernel_mode && KX &&
305 address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
306 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
307 } else {
308 ret = TLBRET_BADADDR;
309 }
310 #endif
311 } else if (address < KSEG1_BASE) {
312 /* kseg0 */
313 ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
314 access_type, mmu_idx,
315 env->CP0_SegCtl1 >> 16, 0x1FFFFFFF);
316 } else if (address < KSEG2_BASE) {
317 /* kseg1 */
318 ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
319 access_type, mmu_idx,
320 env->CP0_SegCtl1, 0x1FFFFFFF);
321 } else if (address < KSEG3_BASE) {
322 /* sseg (kseg2) */
323 ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
324 access_type, mmu_idx,
325 env->CP0_SegCtl0 >> 16, 0x1FFFFFFF);
326 } else {
327 /* kseg3 */
328 /* XXX: debug segment is not emulated */
329 ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
330 access_type, mmu_idx,
331 env->CP0_SegCtl0, 0x1FFFFFFF);
332 }
333 return ret;
334 }
335
336 void cpu_mips_tlb_flush(CPUMIPSState *env)
337 {
338 MIPSCPU *cpu = mips_env_get_cpu(env);
339
340 /* Flush qemu's TLB and discard all shadowed entries. */
341 tlb_flush(CPU(cpu));
342 env->tlb->tlb_in_use = env->tlb->nb_tlb;
343 }
344
345 /* Called for updates to CP0_Status. */
346 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
347 {
348 int32_t tcstatus, *tcst;
349 uint32_t v = cpu->CP0_Status;
350 uint32_t cu, mx, asid, ksu;
351 uint32_t mask = ((1 << CP0TCSt_TCU3)
352 | (1 << CP0TCSt_TCU2)
353 | (1 << CP0TCSt_TCU1)
354 | (1 << CP0TCSt_TCU0)
355 | (1 << CP0TCSt_TMX)
356 | (3 << CP0TCSt_TKSU)
357 | (0xff << CP0TCSt_TASID));
358
359 cu = (v >> CP0St_CU0) & 0xf;
360 mx = (v >> CP0St_MX) & 0x1;
361 ksu = (v >> CP0St_KSU) & 0x3;
362 asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
363
364 tcstatus = cu << CP0TCSt_TCU0;
365 tcstatus |= mx << CP0TCSt_TMX;
366 tcstatus |= ksu << CP0TCSt_TKSU;
367 tcstatus |= asid;
368
369 if (tc == cpu->current_tc) {
370 tcst = &cpu->active_tc.CP0_TCStatus;
371 } else {
372 tcst = &cpu->tcs[tc].CP0_TCStatus;
373 }
374
375 *tcst &= ~mask;
376 *tcst |= tcstatus;
377 compute_hflags(cpu);
378 }
379
380 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
381 {
382 uint32_t mask = env->CP0_Status_rw_bitmask;
383 target_ulong old = env->CP0_Status;
384
385 if (env->insn_flags & ISA_MIPS32R6) {
386 bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
387 #if defined(TARGET_MIPS64)
388 uint32_t ksux = (1 << CP0St_KX) & val;
389 ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
390 ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
391 val = (val & ~(7 << CP0St_UX)) | ksux;
392 #endif
393 if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
394 mask &= ~(3 << CP0St_KSU);
395 }
396 mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
397 }
398
399 env->CP0_Status = (old & ~mask) | (val & mask);
400 #if defined(TARGET_MIPS64)
401 if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
402 /* Access to at least one of the 64-bit segments has been disabled */
403 tlb_flush(CPU(mips_env_get_cpu(env)));
404 }
405 #endif
406 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
407 sync_c0_status(env, env, env->current_tc);
408 } else {
409 compute_hflags(env);
410 }
411 }
412
413 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
414 {
415 uint32_t mask = 0x00C00300;
416 uint32_t old = env->CP0_Cause;
417 int i;
418
419 if (env->insn_flags & ISA_MIPS32R2) {
420 mask |= 1 << CP0Ca_DC;
421 }
422 if (env->insn_flags & ISA_MIPS32R6) {
423 mask &= ~((1 << CP0Ca_WP) & val);
424 }
425
426 env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
427
428 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
429 if (env->CP0_Cause & (1 << CP0Ca_DC)) {
430 cpu_mips_stop_count(env);
431 } else {
432 cpu_mips_start_count(env);
433 }
434 }
435
436 /* Set/reset software interrupts */
437 for (i = 0 ; i < 2 ; i++) {
438 if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
439 cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
440 }
441 }
442 }
443 #endif
444
445 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
446 int rw, int tlb_error)
447 {
448 CPUState *cs = CPU(mips_env_get_cpu(env));
449 int exception = 0, error_code = 0;
450
451 if (rw == MMU_INST_FETCH) {
452 error_code |= EXCP_INST_NOTAVAIL;
453 }
454
455 switch (tlb_error) {
456 default:
457 case TLBRET_BADADDR:
458 /* Reference to kernel address from user mode or supervisor mode */
459 /* Reference to supervisor address from user mode */
460 if (rw == MMU_DATA_STORE) {
461 exception = EXCP_AdES;
462 } else {
463 exception = EXCP_AdEL;
464 }
465 break;
466 case TLBRET_NOMATCH:
467 /* No TLB match for a mapped address */
468 if (rw == MMU_DATA_STORE) {
469 exception = EXCP_TLBS;
470 } else {
471 exception = EXCP_TLBL;
472 }
473 error_code |= EXCP_TLB_NOMATCH;
474 break;
475 case TLBRET_INVALID:
476 /* TLB match with no valid bit */
477 if (rw == MMU_DATA_STORE) {
478 exception = EXCP_TLBS;
479 } else {
480 exception = EXCP_TLBL;
481 }
482 break;
483 case TLBRET_DIRTY:
484 /* TLB match but 'D' bit is cleared */
485 exception = EXCP_LTLBL;
486 break;
487 case TLBRET_XI:
488 /* Execute-Inhibit Exception */
489 if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
490 exception = EXCP_TLBXI;
491 } else {
492 exception = EXCP_TLBL;
493 }
494 break;
495 case TLBRET_RI:
496 /* Read-Inhibit Exception */
497 if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
498 exception = EXCP_TLBRI;
499 } else {
500 exception = EXCP_TLBL;
501 }
502 break;
503 }
504 /* Raise exception */
505 if (!(env->hflags & MIPS_HFLAG_DM)) {
506 env->CP0_BadVAddr = address;
507 }
508 env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
509 ((address >> 9) & 0x007ffff0);
510 env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
511 (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) |
512 (address & (TARGET_PAGE_MASK << 1));
513 #if defined(TARGET_MIPS64)
514 env->CP0_EntryHi &= env->SEGMask;
515 env->CP0_XContext =
516 /* PTEBase */ (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
517 /* R */ (extract64(address, 62, 2) << (env->SEGBITS - 9)) |
518 /* BadVPN2 */ (extract64(address, 13, env->SEGBITS - 13) << 4);
519 #endif
520 cs->exception_index = exception;
521 env->error_code = error_code;
522 }
523
524 #if !defined(CONFIG_USER_ONLY)
525 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
526 {
527 MIPSCPU *cpu = MIPS_CPU(cs);
528 CPUMIPSState *env = &cpu->env;
529 hwaddr phys_addr;
530 int prot;
531
532 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT,
533 cpu_mmu_index(env, false)) != 0) {
534 return -1;
535 }
536 return phys_addr;
537 }
538 #endif
539
540 #if !defined(CONFIG_USER_ONLY)
541 #if !defined(TARGET_MIPS64)
542
543 /*
544 * Perform hardware page table walk
545 *
546 * Memory accesses are performed using the KERNEL privilege level.
547 * Synchronous exceptions detected on memory accesses cause a silent exit
548 * from page table walking, resulting in a TLB or XTLB Refill exception.
549 *
550 * Implementations are not required to support page table walk memory
551 * accesses from mapped memory regions. When an unsupported access is
552 * attempted, a silent exit is taken, resulting in a TLB or XTLB Refill
553 * exception.
554 *
555 * Note that if an exception is caused by AddressTranslation or LoadMemory
556 * functions, the exception is not taken, a silent exit is taken,
557 * resulting in a TLB or XTLB Refill exception.
558 */
559
560 static bool get_pte(CPUMIPSState *env, uint64_t vaddr, int entry_size,
561 uint64_t *pte)
562 {
563 if ((vaddr & ((entry_size >> 3) - 1)) != 0) {
564 return false;
565 }
566 if (entry_size == 64) {
567 *pte = cpu_ldq_code(env, vaddr);
568 } else {
569 *pte = cpu_ldl_code(env, vaddr);
570 }
571 return true;
572 }
573
574 static uint64_t get_tlb_entry_layout(CPUMIPSState *env, uint64_t entry,
575 int entry_size, int ptei)
576 {
577 uint64_t result = entry;
578 uint64_t rixi;
579 if (ptei > entry_size) {
580 ptei -= 32;
581 }
582 result >>= (ptei - 2);
583 rixi = result & 3;
584 result >>= 2;
585 result |= rixi << CP0EnLo_XI;
586 return result;
587 }
588
589 static int walk_directory(CPUMIPSState *env, uint64_t *vaddr,
590 int directory_index, bool *huge_page, bool *hgpg_directory_hit,
591 uint64_t *pw_entrylo0, uint64_t *pw_entrylo1)
592 {
593 int dph = (env->CP0_PWCtl >> CP0PC_DPH) & 0x1;
594 int psn = (env->CP0_PWCtl >> CP0PC_PSN) & 0x3F;
595 int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1;
596 int pf_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
597 int ptew = (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F;
598 int native_shift = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? 2 : 3;
599 int directory_shift = (ptew > 1) ? -1 :
600 (hugepg && (ptew == 1)) ? native_shift + 1 : native_shift;
601 int leaf_shift = (ptew > 1) ? -1 :
602 (ptew == 1) ? native_shift + 1 : native_shift;
603 uint32_t direntry_size = 1 << (directory_shift + 3);
604 uint32_t leafentry_size = 1 << (leaf_shift + 3);
605 uint64_t entry;
606 uint64_t paddr;
607 int prot;
608 uint64_t lsb = 0;
609 uint64_t w = 0;
610
611 if (get_physical_address(env, &paddr, &prot, *vaddr, MMU_DATA_LOAD,
612 ACCESS_INT, cpu_mmu_index(env, false)) !=
613 TLBRET_MATCH) {
614 /* wrong base address */
615 return 0;
616 }
617 if (!get_pte(env, *vaddr, direntry_size, &entry)) {
618 return 0;
619 }
620
621 if ((entry & (1 << psn)) && hugepg) {
622 *huge_page = true;
623 *hgpg_directory_hit = true;
624 entry = get_tlb_entry_layout(env, entry, leafentry_size, pf_ptew);
625 w = directory_index - 1;
626 if (directory_index & 0x1) {
627 /* Generate adjacent page from same PTE for odd TLB page */
628 lsb = (1 << w) >> 6;
629 *pw_entrylo0 = entry & ~lsb; /* even page */
630 *pw_entrylo1 = entry | lsb; /* odd page */
631 } else if (dph) {
632 int oddpagebit = 1 << leaf_shift;
633 uint64_t vaddr2 = *vaddr ^ oddpagebit;
634 if (*vaddr & oddpagebit) {
635 *pw_entrylo1 = entry;
636 } else {
637 *pw_entrylo0 = entry;
638 }
639 if (get_physical_address(env, &paddr, &prot, vaddr2, MMU_DATA_LOAD,
640 ACCESS_INT, cpu_mmu_index(env, false)) !=
641 TLBRET_MATCH) {
642 return 0;
643 }
644 if (!get_pte(env, vaddr2, leafentry_size, &entry)) {
645 return 0;
646 }
647 entry = get_tlb_entry_layout(env, entry, leafentry_size, pf_ptew);
648 if (*vaddr & oddpagebit) {
649 *pw_entrylo0 = entry;
650 } else {
651 *pw_entrylo1 = entry;
652 }
653 } else {
654 return 0;
655 }
656 return 1;
657 } else {
658 *vaddr = entry;
659 return 2;
660 }
661 }
662
663 static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, int rw,
664 int mmu_idx)
665 {
666 int gdw = (env->CP0_PWSize >> CP0PS_GDW) & 0x3F;
667 int udw = (env->CP0_PWSize >> CP0PS_UDW) & 0x3F;
668 int mdw = (env->CP0_PWSize >> CP0PS_MDW) & 0x3F;
669 int ptw = (env->CP0_PWSize >> CP0PS_PTW) & 0x3F;
670 int ptew = (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F;
671
672 /* Initial values */
673 bool huge_page = false;
674 bool hgpg_bdhit = false;
675 bool hgpg_gdhit = false;
676 bool hgpg_udhit = false;
677 bool hgpg_mdhit = false;
678
679 int32_t pw_pagemask = 0;
680 target_ulong pw_entryhi = 0;
681 uint64_t pw_entrylo0 = 0;
682 uint64_t pw_entrylo1 = 0;
683
684 /* Native pointer size */
685 /*For the 32-bit architectures, this bit is fixed to 0.*/
686 int native_shift = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? 2 : 3;
687
688 /* Indices from PWField */
689 int pf_gdw = (env->CP0_PWField >> CP0PF_GDW) & 0x3F;
690 int pf_udw = (env->CP0_PWField >> CP0PF_UDW) & 0x3F;
691 int pf_mdw = (env->CP0_PWField >> CP0PF_MDW) & 0x3F;
692 int pf_ptw = (env->CP0_PWField >> CP0PF_PTW) & 0x3F;
693 int pf_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
694
695 /* Indices computed from faulting address */
696 int gindex = (address >> pf_gdw) & ((1 << gdw) - 1);
697 int uindex = (address >> pf_udw) & ((1 << udw) - 1);
698 int mindex = (address >> pf_mdw) & ((1 << mdw) - 1);
699 int ptindex = (address >> pf_ptw) & ((1 << ptw) - 1);
700
701 /* Other HTW configs */
702 int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1;
703
704 /* HTW Shift values (depend on entry size) */
705 int directory_shift = (ptew > 1) ? -1 :
706 (hugepg && (ptew == 1)) ? native_shift + 1 : native_shift;
707 int leaf_shift = (ptew > 1) ? -1 :
708 (ptew == 1) ? native_shift + 1 : native_shift;
709
710 /* Offsets into tables */
711 int goffset = gindex << directory_shift;
712 int uoffset = uindex << directory_shift;
713 int moffset = mindex << directory_shift;
714 int ptoffset0 = (ptindex >> 1) << (leaf_shift + 1);
715 int ptoffset1 = ptoffset0 | (1 << (leaf_shift));
716
717 uint32_t leafentry_size = 1 << (leaf_shift + 3);
718
719 /* Starting address - Page Table Base */
720 uint64_t vaddr = env->CP0_PWBase;
721
722 uint64_t dir_entry;
723 uint64_t paddr;
724 int prot;
725 int m;
726
727 if (!(env->CP0_Config3 & (1 << CP0C3_PW))) {
728 /* walker is unimplemented */
729 return false;
730 }
731 if (!(env->CP0_PWCtl & (1 << CP0PC_PWEN))) {
732 /* walker is disabled */
733 return false;
734 }
735 if (!(gdw > 0 || udw > 0 || mdw > 0)) {
736 /* no structure to walk */
737 return false;
738 }
739 if ((directory_shift == -1) || (leaf_shift == -1)) {
740 return false;
741 }
742
743 /* Global Directory */
744 if (gdw > 0) {
745 vaddr |= goffset;
746 switch (walk_directory(env, &vaddr, pf_gdw, &huge_page, &hgpg_gdhit,
747 &pw_entrylo0, &pw_entrylo1))
748 {
749 case 0:
750 return false;
751 case 1:
752 goto refill;
753 case 2:
754 default:
755 break;
756 }
757 }
758
759 /* Upper directory */
760 if (udw > 0) {
761 vaddr |= uoffset;
762 switch (walk_directory(env, &vaddr, pf_udw, &huge_page, &hgpg_udhit,
763 &pw_entrylo0, &pw_entrylo1))
764 {
765 case 0:
766 return false;
767 case 1:
768 goto refill;
769 case 2:
770 default:
771 break;
772 }
773 }
774
775 /* Middle directory */
776 if (mdw > 0) {
777 vaddr |= moffset;
778 switch (walk_directory(env, &vaddr, pf_mdw, &huge_page, &hgpg_mdhit,
779 &pw_entrylo0, &pw_entrylo1))
780 {
781 case 0:
782 return false;
783 case 1:
784 goto refill;
785 case 2:
786 default:
787 break;
788 }
789 }
790
791 /* Leaf Level Page Table - First half of PTE pair */
792 vaddr |= ptoffset0;
793 if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD,
794 ACCESS_INT, cpu_mmu_index(env, false)) !=
795 TLBRET_MATCH) {
796 return false;
797 }
798 if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) {
799 return false;
800 }
801 dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, pf_ptew);
802 pw_entrylo0 = dir_entry;
803
804 /* Leaf Level Page Table - Second half of PTE pair */
805 vaddr |= ptoffset1;
806 if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD,
807 ACCESS_INT, cpu_mmu_index(env, false)) !=
808 TLBRET_MATCH) {
809 return false;
810 }
811 if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) {
812 return false;
813 }
814 dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, pf_ptew);
815 pw_entrylo1 = dir_entry;
816
817 refill:
818
819 m = (1 << pf_ptw) - 1;
820
821 if (huge_page) {
822 switch (hgpg_bdhit << 3 | hgpg_gdhit << 2 | hgpg_udhit << 1 |
823 hgpg_mdhit)
824 {
825 case 4:
826 m = (1 << pf_gdw) - 1;
827 if (pf_gdw & 1) {
828 m >>= 1;
829 }
830 break;
831 case 2:
832 m = (1 << pf_udw) - 1;
833 if (pf_udw & 1) {
834 m >>= 1;
835 }
836 break;
837 case 1:
838 m = (1 << pf_mdw) - 1;
839 if (pf_mdw & 1) {
840 m >>= 1;
841 }
842 break;
843 }
844 }
845 pw_pagemask = m >> 12;
846 update_pagemask(env, pw_pagemask << 13, &pw_pagemask);
847 pw_entryhi = (address & ~0x1fff) | (env->CP0_EntryHi & 0xFF);
848 {
849 target_ulong tmp_entryhi = env->CP0_EntryHi;
850 int32_t tmp_pagemask = env->CP0_PageMask;
851 uint64_t tmp_entrylo0 = env->CP0_EntryLo0;
852 uint64_t tmp_entrylo1 = env->CP0_EntryLo1;
853
854 env->CP0_EntryHi = pw_entryhi;
855 env->CP0_PageMask = pw_pagemask;
856 env->CP0_EntryLo0 = pw_entrylo0;
857 env->CP0_EntryLo1 = pw_entrylo1;
858
859 /*
860 * The hardware page walker inserts a page into the TLB in a manner
861 * identical to a TLBWR instruction as executed by the software refill
862 * handler.
863 */
864 r4k_helper_tlbwr(env);
865
866 env->CP0_EntryHi = tmp_entryhi;
867 env->CP0_PageMask = tmp_pagemask;
868 env->CP0_EntryLo0 = tmp_entrylo0;
869 env->CP0_EntryLo1 = tmp_entrylo1;
870 }
871 return true;
872 }
873 #endif
874 #endif
875
876 int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
877 int mmu_idx)
878 {
879 MIPSCPU *cpu = MIPS_CPU(cs);
880 CPUMIPSState *env = &cpu->env;
881 #if !defined(CONFIG_USER_ONLY)
882 hwaddr physical;
883 int prot;
884 int access_type;
885 #endif
886 int ret = 0;
887
888 #if 0
889 log_cpu_state(cs, 0);
890 #endif
891 qemu_log_mask(CPU_LOG_MMU,
892 "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
893 __func__, env->active_tc.PC, address, rw, mmu_idx);
894
895 /* data access */
896 #if !defined(CONFIG_USER_ONLY)
897 /* XXX: put correct access by using cpu_restore_state() correctly */
898 access_type = ACCESS_INT;
899 ret = get_physical_address(env, &physical, &prot,
900 address, rw, access_type, mmu_idx);
901 switch (ret) {
902 case TLBRET_MATCH:
903 qemu_log_mask(CPU_LOG_MMU,
904 "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx
905 " prot %d\n", __func__, address, physical, prot);
906 break;
907 default:
908 qemu_log_mask(CPU_LOG_MMU,
909 "%s address=%" VADDR_PRIx " ret %d\n", __func__, address,
910 ret);
911 break;
912 }
913 if (ret == TLBRET_MATCH) {
914 tlb_set_page(cs, address & TARGET_PAGE_MASK,
915 physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
916 mmu_idx, TARGET_PAGE_SIZE);
917 ret = 0;
918 } else if (ret < 0)
919 #endif
920 {
921 #if !defined(CONFIG_USER_ONLY)
922 #if !defined(TARGET_MIPS64)
923 if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) {
924 /*
925 * Memory reads during hardware page table walking are performed
926 * as if they were kernel-mode load instructions.
927 */
928 int mode = (env->hflags & MIPS_HFLAG_KSU);
929 bool ret_walker;
930 env->hflags &= ~MIPS_HFLAG_KSU;
931 ret_walker = page_table_walk_refill(env, address, rw, mmu_idx);
932 env->hflags |= mode;
933 if (ret_walker) {
934 ret = get_physical_address(env, &physical, &prot,
935 address, rw, access_type, mmu_idx);
936 if (ret == TLBRET_MATCH) {
937 tlb_set_page(cs, address & TARGET_PAGE_MASK,
938 physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
939 mmu_idx, TARGET_PAGE_SIZE);
940 ret = 0;
941 return ret;
942 }
943 }
944 }
945 #endif
946 #endif
947 raise_mmu_exception(env, address, rw, ret);
948 ret = 1;
949 }
950
951 return ret;
952 }
953
954 #if !defined(CONFIG_USER_ONLY)
955 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
956 {
957 hwaddr physical;
958 int prot;
959 int access_type;
960 int ret = 0;
961
962 /* data access */
963 access_type = ACCESS_INT;
964 ret = get_physical_address(env, &physical, &prot, address, rw, access_type,
965 cpu_mmu_index(env, false));
966 if (ret != TLBRET_MATCH) {
967 raise_mmu_exception(env, address, rw, ret);
968 return -1LL;
969 } else {
970 return physical;
971 }
972 }
973
974 static const char * const excp_names[EXCP_LAST + 1] = {
975 [EXCP_RESET] = "reset",
976 [EXCP_SRESET] = "soft reset",
977 [EXCP_DSS] = "debug single step",
978 [EXCP_DINT] = "debug interrupt",
979 [EXCP_NMI] = "non-maskable interrupt",
980 [EXCP_MCHECK] = "machine check",
981 [EXCP_EXT_INTERRUPT] = "interrupt",
982 [EXCP_DFWATCH] = "deferred watchpoint",
983 [EXCP_DIB] = "debug instruction breakpoint",
984 [EXCP_IWATCH] = "instruction fetch watchpoint",
985 [EXCP_AdEL] = "address error load",
986 [EXCP_AdES] = "address error store",
987 [EXCP_TLBF] = "TLB refill",
988 [EXCP_IBE] = "instruction bus error",
989 [EXCP_DBp] = "debug breakpoint",
990 [EXCP_SYSCALL] = "syscall",
991 [EXCP_BREAK] = "break",
992 [EXCP_CpU] = "coprocessor unusable",
993 [EXCP_RI] = "reserved instruction",
994 [EXCP_OVERFLOW] = "arithmetic overflow",
995 [EXCP_TRAP] = "trap",
996 [EXCP_FPE] = "floating point",
997 [EXCP_DDBS] = "debug data break store",
998 [EXCP_DWATCH] = "data watchpoint",
999 [EXCP_LTLBL] = "TLB modify",
1000 [EXCP_TLBL] = "TLB load",
1001 [EXCP_TLBS] = "TLB store",
1002 [EXCP_DBE] = "data bus error",
1003 [EXCP_DDBL] = "debug data break load",
1004 [EXCP_THREAD] = "thread",
1005 [EXCP_MDMX] = "MDMX",
1006 [EXCP_C2E] = "precise coprocessor 2",
1007 [EXCP_CACHE] = "cache error",
1008 [EXCP_TLBXI] = "TLB execute-inhibit",
1009 [EXCP_TLBRI] = "TLB read-inhibit",
1010 [EXCP_MSADIS] = "MSA disabled",
1011 [EXCP_MSAFPE] = "MSA floating point",
1012 };
1013 #endif
1014
1015 target_ulong exception_resume_pc (CPUMIPSState *env)
1016 {
1017 target_ulong bad_pc;
1018 target_ulong isa_mode;
1019
1020 isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
1021 bad_pc = env->active_tc.PC | isa_mode;
1022 if (env->hflags & MIPS_HFLAG_BMASK) {
1023 /* If the exception was raised from a delay slot, come back to
1024 the jump. */
1025 bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
1026 }
1027
1028 return bad_pc;
1029 }
1030
1031 #if !defined(CONFIG_USER_ONLY)
1032 static void set_hflags_for_handler (CPUMIPSState *env)
1033 {
1034 /* Exception handlers are entered in 32-bit mode. */
1035 env->hflags &= ~(MIPS_HFLAG_M16);
1036 /* ...except that microMIPS lets you choose. */
1037 if (env->insn_flags & ASE_MICROMIPS) {
1038 env->hflags |= (!!(env->CP0_Config3
1039 & (1 << CP0C3_ISA_ON_EXC))
1040 << MIPS_HFLAG_M16_SHIFT);
1041 }
1042 }
1043
1044 static inline void set_badinstr_registers(CPUMIPSState *env)
1045 {
1046 if (env->insn_flags & ISA_NANOMIPS32) {
1047 if (env->CP0_Config3 & (1 << CP0C3_BI)) {
1048 uint32_t instr = (cpu_lduw_code(env, env->active_tc.PC)) << 16;
1049 if ((instr & 0x10000000) == 0) {
1050 instr |= cpu_lduw_code(env, env->active_tc.PC + 2);
1051 }
1052 env->CP0_BadInstr = instr;
1053
1054 if ((instr & 0xFC000000) == 0x60000000) {
1055 instr = cpu_lduw_code(env, env->active_tc.PC + 4) << 16;
1056 env->CP0_BadInstrX = instr;
1057 }
1058 }
1059 return;
1060 }
1061
1062 if (env->hflags & MIPS_HFLAG_M16) {
1063 /* TODO: add BadInstr support for microMIPS */
1064 return;
1065 }
1066 if (env->CP0_Config3 & (1 << CP0C3_BI)) {
1067 env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC);
1068 }
1069 if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
1070 (env->hflags & MIPS_HFLAG_BMASK)) {
1071 env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
1072 }
1073 }
1074 #endif
1075
1076 void mips_cpu_do_interrupt(CPUState *cs)
1077 {
1078 #if !defined(CONFIG_USER_ONLY)
1079 MIPSCPU *cpu = MIPS_CPU(cs);
1080 CPUMIPSState *env = &cpu->env;
1081 bool update_badinstr = 0;
1082 target_ulong offset;
1083 int cause = -1;
1084 const char *name;
1085
1086 if (qemu_loglevel_mask(CPU_LOG_INT)
1087 && cs->exception_index != EXCP_EXT_INTERRUPT) {
1088 if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {
1089 name = "unknown";
1090 } else {
1091 name = excp_names[cs->exception_index];
1092 }
1093
1094 qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx
1095 " %s exception\n",
1096 __func__, env->active_tc.PC, env->CP0_EPC, name);
1097 }
1098 if (cs->exception_index == EXCP_EXT_INTERRUPT &&
1099 (env->hflags & MIPS_HFLAG_DM)) {
1100 cs->exception_index = EXCP_DINT;
1101 }
1102 offset = 0x180;
1103 switch (cs->exception_index) {
1104 case EXCP_DSS:
1105 env->CP0_Debug |= 1 << CP0DB_DSS;
1106 /* Debug single step cannot be raised inside a delay slot and
1107 resume will always occur on the next instruction
1108 (but we assume the pc has always been updated during
1109 code translation). */
1110 env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
1111 goto enter_debug_mode;
1112 case EXCP_DINT:
1113 env->CP0_Debug |= 1 << CP0DB_DINT;
1114 goto set_DEPC;
1115 case EXCP_DIB:
1116 env->CP0_Debug |= 1 << CP0DB_DIB;
1117 goto set_DEPC;
1118 case EXCP_DBp:
1119 env->CP0_Debug |= 1 << CP0DB_DBp;
1120 /* Setup DExcCode - SDBBP instruction */
1121 env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | 9 << CP0DB_DEC;
1122 goto set_DEPC;
1123 case EXCP_DDBS:
1124 env->CP0_Debug |= 1 << CP0DB_DDBS;
1125 goto set_DEPC;
1126 case EXCP_DDBL:
1127 env->CP0_Debug |= 1 << CP0DB_DDBL;
1128 set_DEPC:
1129 env->CP0_DEPC = exception_resume_pc(env);
1130 env->hflags &= ~MIPS_HFLAG_BMASK;
1131 enter_debug_mode:
1132 if (env->insn_flags & ISA_MIPS3) {
1133 env->hflags |= MIPS_HFLAG_64;
1134 if (!(env->insn_flags & ISA_MIPS64R6) ||
1135 env->CP0_Status & (1 << CP0St_KX)) {
1136 env->hflags &= ~MIPS_HFLAG_AWRAP;
1137 }
1138 }
1139 env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;
1140 env->hflags &= ~(MIPS_HFLAG_KSU);
1141 /* EJTAG probe trap enable is not implemented... */
1142 if (!(env->CP0_Status & (1 << CP0St_EXL)))
1143 env->CP0_Cause &= ~(1U << CP0Ca_BD);
1144 env->active_tc.PC = env->exception_base + 0x480;
1145 set_hflags_for_handler(env);
1146 break;
1147 case EXCP_RESET:
1148 cpu_reset(CPU(cpu));
1149 break;
1150 case EXCP_SRESET:
1151 env->CP0_Status |= (1 << CP0St_SR);
1152 memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo));
1153 goto set_error_EPC;
1154 case EXCP_NMI:
1155 env->CP0_Status |= (1 << CP0St_NMI);
1156 set_error_EPC:
1157 env->CP0_ErrorEPC = exception_resume_pc(env);
1158 env->hflags &= ~MIPS_HFLAG_BMASK;
1159 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
1160 if (env->insn_flags & ISA_MIPS3) {
1161 env->hflags |= MIPS_HFLAG_64;
1162 if (!(env->insn_flags & ISA_MIPS64R6) ||
1163 env->CP0_Status & (1 << CP0St_KX)) {
1164 env->hflags &= ~MIPS_HFLAG_AWRAP;
1165 }
1166 }
1167 env->hflags |= MIPS_HFLAG_CP0;
1168 env->hflags &= ~(MIPS_HFLAG_KSU);
1169 if (!(env->CP0_Status & (1 << CP0St_EXL)))
1170 env->CP0_Cause &= ~(1U << CP0Ca_BD);
1171 env->active_tc.PC = env->exception_base;
1172 set_hflags_for_handler(env);
1173 break;
1174 case EXCP_EXT_INTERRUPT:
1175 cause = 0;
1176 if (env->CP0_Cause & (1 << CP0Ca_IV)) {
1177 uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f;
1178
1179 if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) {
1180 offset = 0x200;
1181 } else {
1182 uint32_t vector = 0;
1183 uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP;
1184
1185 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
1186 /* For VEIC mode, the external interrupt controller feeds
1187 * the vector through the CP0Cause IP lines. */
1188 vector = pending;
1189 } else {
1190 /* Vectored Interrupts
1191 * Mask with Status.IM7-IM0 to get enabled interrupts. */
1192 pending &= (env->CP0_Status >> CP0St_IM) & 0xff;
1193 /* Find the highest-priority interrupt. */
1194 while (pending >>= 1) {
1195 vector++;
1196 }
1197 }
1198 offset = 0x200 + (vector * (spacing << 5));
1199 }
1200 }
1201 goto set_EPC;
1202 case EXCP_LTLBL:
1203 cause = 1;
1204 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
1205 goto set_EPC;
1206 case EXCP_TLBL:
1207 cause = 2;
1208 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
1209 if ((env->error_code & EXCP_TLB_NOMATCH) &&
1210 !(env->CP0_Status & (1 << CP0St_EXL))) {
1211 #if defined(TARGET_MIPS64)
1212 int R = env->CP0_BadVAddr >> 62;
1213 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
1214 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
1215
1216 if ((R != 0 || UX) && (R != 3 || KX) &&
1217 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) {
1218 offset = 0x080;
1219 } else {
1220 #endif
1221 offset = 0x000;
1222 #if defined(TARGET_MIPS64)
1223 }
1224 #endif
1225 }
1226 goto set_EPC;
1227 case EXCP_TLBS:
1228 cause = 3;
1229 update_badinstr = 1;
1230 if ((env->error_code & EXCP_TLB_NOMATCH) &&
1231 !(env->CP0_Status & (1 << CP0St_EXL))) {
1232 #if defined(TARGET_MIPS64)
1233 int R = env->CP0_BadVAddr >> 62;
1234 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
1235 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
1236
1237 if ((R != 0 || UX) && (R != 3 || KX) &&
1238 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) {
1239 offset = 0x080;
1240 } else {
1241 #endif
1242 offset = 0x000;
1243 #if defined(TARGET_MIPS64)
1244 }
1245 #endif
1246 }
1247 goto set_EPC;
1248 case EXCP_AdEL:
1249 cause = 4;
1250 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
1251 goto set_EPC;
1252 case EXCP_AdES:
1253 cause = 5;
1254 update_badinstr = 1;
1255 goto set_EPC;
1256 case EXCP_IBE:
1257 cause = 6;
1258 goto set_EPC;
1259 case EXCP_DBE:
1260 cause = 7;
1261 goto set_EPC;
1262 case EXCP_SYSCALL:
1263 cause = 8;
1264 update_badinstr = 1;
1265 goto set_EPC;
1266 case EXCP_BREAK:
1267 cause = 9;
1268 update_badinstr = 1;
1269 goto set_EPC;
1270 case EXCP_RI:
1271 cause = 10;
1272 update_badinstr = 1;
1273 goto set_EPC;
1274 case EXCP_CpU:
1275 cause = 11;
1276 update_badinstr = 1;
1277 env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
1278 (env->error_code << CP0Ca_CE);
1279 goto set_EPC;
1280 case EXCP_OVERFLOW:
1281 cause = 12;
1282 update_badinstr = 1;
1283 goto set_EPC;
1284 case EXCP_TRAP:
1285 cause = 13;
1286 update_badinstr = 1;
1287 goto set_EPC;
1288 case EXCP_MSAFPE:
1289 cause = 14;
1290 update_badinstr = 1;
1291 goto set_EPC;
1292 case EXCP_FPE:
1293 cause = 15;
1294 update_badinstr = 1;
1295 goto set_EPC;
1296 case EXCP_C2E:
1297 cause = 18;
1298 goto set_EPC;
1299 case EXCP_TLBRI:
1300 cause = 19;
1301 update_badinstr = 1;
1302 goto set_EPC;
1303 case EXCP_TLBXI:
1304 cause = 20;
1305 goto set_EPC;
1306 case EXCP_MSADIS:
1307 cause = 21;
1308 update_badinstr = 1;
1309 goto set_EPC;
1310 case EXCP_MDMX:
1311 cause = 22;
1312 goto set_EPC;
1313 case EXCP_DWATCH:
1314 cause = 23;
1315 /* XXX: TODO: manage deferred watch exceptions */
1316 goto set_EPC;
1317 case EXCP_MCHECK:
1318 cause = 24;
1319 goto set_EPC;
1320 case EXCP_THREAD:
1321 cause = 25;
1322 goto set_EPC;
1323 case EXCP_DSPDIS:
1324 cause = 26;
1325 goto set_EPC;
1326 case EXCP_CACHE:
1327 cause = 30;
1328 offset = 0x100;
1329 set_EPC:
1330 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
1331 env->CP0_EPC = exception_resume_pc(env);
1332 if (update_badinstr) {
1333 set_badinstr_registers(env);
1334 }
1335 if (env->hflags & MIPS_HFLAG_BMASK) {
1336 env->CP0_Cause |= (1U << CP0Ca_BD);
1337 } else {
1338 env->CP0_Cause &= ~(1U << CP0Ca_BD);
1339 }
1340 env->CP0_Status |= (1 << CP0St_EXL);
1341 if (env->insn_flags & ISA_MIPS3) {
1342 env->hflags |= MIPS_HFLAG_64;
1343 if (!(env->insn_flags & ISA_MIPS64R6) ||
1344 env->CP0_Status & (1 << CP0St_KX)) {
1345 env->hflags &= ~MIPS_HFLAG_AWRAP;
1346 }
1347 }
1348 env->hflags |= MIPS_HFLAG_CP0;
1349 env->hflags &= ~(MIPS_HFLAG_KSU);
1350 }
1351 env->hflags &= ~MIPS_HFLAG_BMASK;
1352 if (env->CP0_Status & (1 << CP0St_BEV)) {
1353 env->active_tc.PC = env->exception_base + 0x200;
1354 } else if (cause == 30 && !(env->CP0_Config3 & (1 << CP0C3_SC) &&
1355 env->CP0_Config5 & (1 << CP0C5_CV))) {
1356 /* Force KSeg1 for cache errors */
1357 env->active_tc.PC = KSEG1_BASE | (env->CP0_EBase & 0x1FFFF000);
1358 } else {
1359 env->active_tc.PC = env->CP0_EBase & ~0xfff;
1360 }
1361
1362 env->active_tc.PC += offset;
1363 set_hflags_for_handler(env);
1364 env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
1365 break;
1366 default:
1367 abort();
1368 }
1369 if (qemu_loglevel_mask(CPU_LOG_INT)
1370 && cs->exception_index != EXCP_EXT_INTERRUPT) {
1371 qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
1372 " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
1373 __func__, env->active_tc.PC, env->CP0_EPC, cause,
1374 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
1375 env->CP0_DEPC);
1376 }
1377 #endif
1378 cs->exception_index = EXCP_NONE;
1379 }
1380
1381 bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
1382 {
1383 if (interrupt_request & CPU_INTERRUPT_HARD) {
1384 MIPSCPU *cpu = MIPS_CPU(cs);
1385 CPUMIPSState *env = &cpu->env;
1386
1387 if (cpu_mips_hw_interrupts_enabled(env) &&
1388 cpu_mips_hw_interrupts_pending(env)) {
1389 /* Raise it */
1390 cs->exception_index = EXCP_EXT_INTERRUPT;
1391 env->error_code = 0;
1392 mips_cpu_do_interrupt(cs);
1393 return true;
1394 }
1395 }
1396 return false;
1397 }
1398
1399 #if !defined(CONFIG_USER_ONLY)
1400 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
1401 {
1402 MIPSCPU *cpu = mips_env_get_cpu(env);
1403 CPUState *cs;
1404 r4k_tlb_t *tlb;
1405 target_ulong addr;
1406 target_ulong end;
1407 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
1408 target_ulong mask;
1409
1410 tlb = &env->tlb->mmu.r4k.tlb[idx];
1411 /* The qemu TLB is flushed when the ASID changes, so no need to
1412 flush these entries again. */
1413 if (tlb->G == 0 && tlb->ASID != ASID) {
1414 return;
1415 }
1416
1417 if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
1418 /* For tlbwr, we can shadow the discarded entry into
1419 a new (fake) TLB entry, as long as the guest can not
1420 tell that it's there. */
1421 env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
1422 env->tlb->tlb_in_use++;
1423 return;
1424 }
1425
1426 /* 1k pages are not supported. */
1427 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1428 if (tlb->V0) {
1429 cs = CPU(cpu);
1430 addr = tlb->VPN & ~mask;
1431 #if defined(TARGET_MIPS64)
1432 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
1433 addr |= 0x3FFFFF0000000000ULL;
1434 }
1435 #endif
1436 end = addr | (mask >> 1);
1437 while (addr < end) {
1438 tlb_flush_page(cs, addr);
1439 addr += TARGET_PAGE_SIZE;
1440 }
1441 }
1442 if (tlb->V1) {
1443 cs = CPU(cpu);
1444 addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
1445 #if defined(TARGET_MIPS64)
1446 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
1447 addr |= 0x3FFFFF0000000000ULL;
1448 }
1449 #endif
1450 end = addr | mask;
1451 while (addr - 1 < end) {
1452 tlb_flush_page(cs, addr);
1453 addr += TARGET_PAGE_SIZE;
1454 }
1455 }
1456 }
1457 #endif
1458
1459 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
1460 uint32_t exception,
1461 int error_code,
1462 uintptr_t pc)
1463 {
1464 CPUState *cs = CPU(mips_env_get_cpu(env));
1465
1466 if (exception < EXCP_SC) {
1467 qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n",
1468 __func__, exception, error_code);
1469 }
1470 cs->exception_index = exception;
1471 env->error_code = error_code;
1472
1473 cpu_loop_exit_restore(cs, pc);
1474 }
AR7 emulation for QEMU