target-cris/helper.c

   1 /*
   2  *  CRIS helper routines.
   3  *
   4  *  Copyright (c) 2007 AXIS Communications AB
   5  *  Written by Edgar E. Iglesias.
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "cpu.h"
  22 #include "mmu.h"
  23 #include "qemu/host-utils.h"
  24
  25
  26 //#define CRIS_HELPER_DEBUG
  27
  28
  29 #ifdef CRIS_HELPER_DEBUG
  30 #define D(x) x
  31 #define D_LOG(...) qemu_log(__VA_ARGS__)
  32 #else
  33 #define D(x)
  34 #define D_LOG(...) do { } while (0)
  35 #endif
  36
  37 #if defined(CONFIG_USER_ONLY)
  38
  39 void cris_cpu_do_interrupt(CPUState *cs)
  40 {
  41     CRISCPU *cpu = CRIS_CPU(cs);
  42     CPUCRISState *env = &cpu->env;
  43
  44     env->exception_index = -1;
  45     env->pregs[PR_ERP] = env->pc;
  46 }
  47
  48 int cpu_cris_handle_mmu_fault(CPUCRISState * env, target_ulong address, int rw,
  49                               int mmu_idx)
  50 {
  51     env->exception_index = 0xaa;
  52     env->pregs[PR_EDA] = address;
  53     cpu_dump_state(env, stderr, fprintf, 0);
  54     return 1;
  55 }
  56
  57 #else /* !CONFIG_USER_ONLY */
  58
  59
  60 static void cris_shift_ccs(CPUCRISState *env)
  61 {
  62     uint32_t ccs;
  63     /* Apply the ccs shift.  */
  64     ccs = env->pregs[PR_CCS];
  65     ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff;
  66     env->pregs[PR_CCS] = ccs;
  67 }
  68
  69 int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
  70                               int mmu_idx)
  71 {
  72     D(CPUState *cpu = CPU(cris_env_get_cpu(env)));
  73     struct cris_mmu_result res;
  74     int prot, miss;
  75     int r = -1;
  76     target_ulong phy;
  77
  78     D(printf("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));
  79     miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
  80                               rw, mmu_idx, 0);
  81     if (miss) {
  82         if (env->exception_index == EXCP_BUSFAULT) {
  83             cpu_abort(env,
  84                       "CRIS: Illegal recursive bus fault."
  85                       "addr=%x rw=%d\n",
  86                       address, rw);
  87         }
  88
  89         env->pregs[PR_EDA] = address;
  90         env->exception_index = EXCP_BUSFAULT;
  91         env->fault_vector = res.bf_vec;
  92         r = 1;
  93     } else {
  94         /*
  95          * Mask off the cache selection bit. The ETRAX busses do not
  96          * see the top bit.
  97          */
  98         phy = res.phy & ~0x80000000;
  99         prot = res.prot;
 100         tlb_set_page(env, address & TARGET_PAGE_MASK, phy,
 101                      prot, mmu_idx, TARGET_PAGE_SIZE);
 102         r = 0;
 103     }
 104     if (r > 0) {
 105         D_LOG("%s returns %d irqreq=%x addr=%x phy=%x vec=%x pc=%x\n",
 106               __func__, r, cpu->interrupt_request, address, res.phy,
 107               res.bf_vec, env->pc);
 108     }
 109     return r;
 110 }
 111
 112 static void do_interruptv10(CPUCRISState *env)
 113 {
 114     D(CPUState *cs = CPU(cris_env_get_cpu(env)));
 115     int ex_vec = -1;
 116
 117     D_LOG("exception index=%d interrupt_req=%d\n",
 118           env->exception_index,
 119           cs->interrupt_request);
 120
 121     assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
 122     switch (env->exception_index) {
 123     case EXCP_BREAK:
 124         /* These exceptions are genereated by the core itself.
 125            ERP should point to the insn following the brk.  */
 126         ex_vec = env->trap_vector;
 127         env->pregs[PRV10_BRP] = env->pc;
 128         break;
 129
 130     case EXCP_NMI:
 131         /* NMI is hardwired to vector zero.  */
 132         ex_vec = 0;
 133         env->pregs[PR_CCS] &= ~M_FLAG_V10;
 134         env->pregs[PRV10_BRP] = env->pc;
 135         break;
 136
 137     case EXCP_BUSFAULT:
 138         cpu_abort(env, "Unhandled busfault");
 139         break;
 140
 141     default:
 142         /* The interrupt controller gives us the vector.  */
 143         ex_vec = env->interrupt_vector;
 144         /* Normal interrupts are taken between
 145            TB's.  env->pc is valid here.  */
 146         env->pregs[PR_ERP] = env->pc;
 147         break;
 148     }
 149
 150     if (env->pregs[PR_CCS] & U_FLAG) {
 151         /* Swap stack pointers.  */
 152         env->pregs[PR_USP] = env->regs[R_SP];
 153         env->regs[R_SP] = env->ksp;
 154     }
 155
 156     /* Now that we are in kernel mode, load the handlers address.  */
 157     env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
 158     env->locked_irq = 1;
 159     env->pregs[PR_CCS] |= F_FLAG_V10; /* set F.  */
 160
 161     qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
 162                   __func__, env->pc, ex_vec,
 163                   env->pregs[PR_CCS],
 164                   env->pregs[PR_PID],
 165                   env->pregs[PR_ERP]);
 166 }
 167
 168 void cris_cpu_do_interrupt(CPUState *cs)
 169 {
 170     CRISCPU *cpu = CRIS_CPU(cs);
 171     CPUCRISState *env = &cpu->env;
 172     int ex_vec = -1;
 173
 174     if (env->pregs[PR_VR] < 32) {
 175         return do_interruptv10(env);
 176     }
 177
 178     D_LOG("exception index=%d interrupt_req=%d\n",
 179           env->exception_index,
 180           cs->interrupt_request);
 181
 182     switch (env->exception_index) {
 183     case EXCP_BREAK:
 184         /* These exceptions are genereated by the core itself.
 185            ERP should point to the insn following the brk.  */
 186         ex_vec = env->trap_vector;
 187         env->pregs[PR_ERP] = env->pc;
 188         break;
 189
 190     case EXCP_NMI:
 191         /* NMI is hardwired to vector zero.  */
 192         ex_vec = 0;
 193         env->pregs[PR_CCS] &= ~M_FLAG_V32;
 194         env->pregs[PR_NRP] = env->pc;
 195         break;
 196
 197     case EXCP_BUSFAULT:
 198         ex_vec = env->fault_vector;
 199         env->pregs[PR_ERP] = env->pc;
 200         break;
 201
 202     default:
 203         /* The interrupt controller gives us the vector.  */
 204         ex_vec = env->interrupt_vector;
 205         /* Normal interrupts are taken between
 206            TB's.  env->pc is valid here.  */
 207         env->pregs[PR_ERP] = env->pc;
 208         break;
 209     }
 210
 211     /* Fill in the IDX field.  */
 212     env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;
 213
 214     if (env->dslot) {
 215         D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
 216               " ERP=%x pid=%x ccs=%x cc=%d %x\n",
 217               ex_vec, env->pc, env->dslot,
 218               env->regs[R_SP],
 219               env->pregs[PR_ERP], env->pregs[PR_PID],
 220               env->pregs[PR_CCS],
 221               env->cc_op, env->cc_mask);
 222         /* We loose the btarget, btaken state here so rexec the
 223            branch.  */
 224         env->pregs[PR_ERP] -= env->dslot;
 225         /* Exception starts with dslot cleared.  */
 226         env->dslot = 0;
 227     }
 228
 229     if (env->pregs[PR_CCS] & U_FLAG) {
 230         /* Swap stack pointers.  */
 231         env->pregs[PR_USP] = env->regs[R_SP];
 232         env->regs[R_SP] = env->ksp;
 233     }
 234
 235     /* Apply the CRIS CCS shift. Clears U if set.  */
 236     cris_shift_ccs(env);
 237
 238     /* Now that we are in kernel mode, load the handlers address.
 239        This load may not fault, real hw leaves that behaviour as
 240        undefined.  */
 241     env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
 242
 243     /* Clear the excption_index to avoid spurios hw_aborts for recursive
 244        bus faults.  */
 245     env->exception_index = -1;
 246
 247     D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
 248           __func__, env->pc, ex_vec,
 249           env->pregs[PR_CCS],
 250           env->pregs[PR_PID],
 251           env->pregs[PR_ERP]);
 252 }
 253
 254 hwaddr cpu_get_phys_page_debug(CPUCRISState * env, target_ulong addr)
 255 {
 256     uint32_t phy = addr;
 257     struct cris_mmu_result res;
 258     int miss;
 259
 260     miss = cris_mmu_translate(&res, env, addr, 0, 0, 1);
 261     /* If D TLB misses, try I TLB.  */
 262     if (miss) {
 263         miss = cris_mmu_translate(&res, env, addr, 2, 0, 1);
 264     }
 265
 266     if (!miss) {
 267         phy = res.phy;
 268     }
 269     D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
 270     return phy;
 271 }
 272 #endif