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target/mips: fpu: Demacro CLASS.<D|S>
[qemu/ar7.git] / target / mips / fpu_helper.c
blobb3903f5357422fbb43349cb4f9d5391e3a0f4998
1 /*
2 * Helpers for emulation of FPU-related MIPS instructions.
3 *
4 * Copyright (C) 2004-2005 Jocelyn Mayer
5 * Copyright (C) 2020 Wave Computing, Inc.
6 * Copyright (C) 2020 Aleksandar Markovic <amarkovic@wavecomp.com>
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 *
21 */
22
23 #include "qemu/osdep.h"
24 #include "qemu/main-loop.h"
25 #include "cpu.h"
26 #include "internal.h"
27 #include "qemu/host-utils.h"
28 #include "exec/helper-proto.h"
29 #include "exec/exec-all.h"
30 #include "exec/cpu_ldst.h"
31 #include "exec/memop.h"
32 #include "sysemu/kvm.h"
33 #include "fpu/softfloat.h"
34
35
36 /* Complex FPU operations which may need stack space. */
37
38 #define FLOAT_TWO32 make_float32(1 << 30)
39 #define FLOAT_TWO64 make_float64(1ULL << 62)
40
41 #define FP_TO_INT32_OVERFLOW 0x7fffffff
42 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
43
44 /* convert MIPS rounding mode in FCR31 to IEEE library */
45 unsigned int ieee_rm[] = {
46 float_round_nearest_even,
47 float_round_to_zero,
48 float_round_up,
49 float_round_down
50 };
51
52 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
53 {
54 target_ulong arg1 = 0;
55
56 switch (reg) {
57 case 0:
58 arg1 = (int32_t)env->active_fpu.fcr0;
59 break;
60 case 1:
61 /* UFR Support - Read Status FR */
62 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
63 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
64 arg1 = (int32_t)
65 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR);
66 } else {
67 do_raise_exception(env, EXCP_RI, GETPC());
68 }
69 }
70 break;
71 case 5:
72 /* FRE Support - read Config5.FRE bit */
73 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
74 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
75 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
76 } else {
77 helper_raise_exception(env, EXCP_RI);
78 }
79 }
80 break;
81 case 25:
82 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) |
83 ((env->active_fpu.fcr31 >> 23) & 0x1);
84 break;
85 case 26:
86 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
87 break;
88 case 28:
89 arg1 = (env->active_fpu.fcr31 & 0x00000f83) |
90 ((env->active_fpu.fcr31 >> 22) & 0x4);
91 break;
92 default:
93 arg1 = (int32_t)env->active_fpu.fcr31;
94 break;
95 }
96
97 return arg1;
98 }
99
100 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
101 {
102 switch (fs) {
103 case 1:
104 /* UFR Alias - Reset Status FR */
105 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
106 return;
107 }
108 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
109 env->CP0_Status &= ~(1 << CP0St_FR);
110 compute_hflags(env);
111 } else {
112 do_raise_exception(env, EXCP_RI, GETPC());
113 }
114 break;
115 case 4:
116 /* UNFR Alias - Set Status FR */
117 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
118 return;
119 }
120 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
121 env->CP0_Status |= (1 << CP0St_FR);
122 compute_hflags(env);
123 } else {
124 do_raise_exception(env, EXCP_RI, GETPC());
125 }
126 break;
127 case 5:
128 /* FRE Support - clear Config5.FRE bit */
129 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
130 return;
131 }
132 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
133 env->CP0_Config5 &= ~(1 << CP0C5_FRE);
134 compute_hflags(env);
135 } else {
136 helper_raise_exception(env, EXCP_RI);
137 }
138 break;
139 case 6:
140 /* FRE Support - set Config5.FRE bit */
141 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
142 return;
143 }
144 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
145 env->CP0_Config5 |= (1 << CP0C5_FRE);
146 compute_hflags(env);
147 } else {
148 helper_raise_exception(env, EXCP_RI);
149 }
150 break;
151 case 25:
152 if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
153 return;
154 }
155 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) |
156 ((arg1 & 0xfe) << 24) |
157 ((arg1 & 0x1) << 23);
158 break;
159 case 26:
160 if (arg1 & 0x007c0000) {
161 return;
162 }
163 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) |
164 (arg1 & 0x0003f07c);
165 break;
166 case 28:
167 if (arg1 & 0x007c0000) {
168 return;
169 }
170 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) |
171 (arg1 & 0x00000f83) |
172 ((arg1 & 0x4) << 22);
173 break;
174 case 31:
175 env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) |
176 (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
177 break;
178 default:
179 if (env->insn_flags & ISA_MIPS32R6) {
180 do_raise_exception(env, EXCP_RI, GETPC());
181 }
182 return;
183 }
184 restore_fp_status(env);
185 set_float_exception_flags(0, &env->active_fpu.fp_status);
186 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) &
187 GET_FP_CAUSE(env->active_fpu.fcr31)) {
188 do_raise_exception(env, EXCP_FPE, GETPC());
189 }
190 }
191
192 int ieee_ex_to_mips(int xcpt)
193 {
194 int ret = 0;
195 if (xcpt) {
196 if (xcpt & float_flag_invalid) {
197 ret |= FP_INVALID;
198 }
199 if (xcpt & float_flag_overflow) {
200 ret |= FP_OVERFLOW;
201 }
202 if (xcpt & float_flag_underflow) {
203 ret |= FP_UNDERFLOW;
204 }
205 if (xcpt & float_flag_divbyzero) {
206 ret |= FP_DIV0;
207 }
208 if (xcpt & float_flag_inexact) {
209 ret |= FP_INEXACT;
210 }
211 }
212 return ret;
213 }
214
215 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
216 {
217 int tmp = ieee_ex_to_mips(get_float_exception_flags(
218 &env->active_fpu.fp_status));
219
220 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
221
222 if (tmp) {
223 set_float_exception_flags(0, &env->active_fpu.fp_status);
224
225 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
226 do_raise_exception(env, EXCP_FPE, pc);
227 } else {
228 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
229 }
230 }
231 }
232
233 /*
234 * Float support.
235 * Single precition routines have a "s" suffix, double precision a
236 * "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
237 * paired single lower "pl", paired single upper "pu".
238 */
239
240 /* unary operations, modifying fp status */
241 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
242 {
243 fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
244 update_fcr31(env, GETPC());
245 return fdt0;
246 }
247
248 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
249 {
250 fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
251 update_fcr31(env, GETPC());
252 return fst0;
253 }
254
255 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
256 {
257 uint64_t fdt2;
258
259 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
260 update_fcr31(env, GETPC());
261 return fdt2;
262 }
263
264 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
265 {
266 uint64_t fdt2;
267
268 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
269 update_fcr31(env, GETPC());
270 return fdt2;
271 }
272
273 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
274 {
275 uint64_t fdt2;
276
277 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
278 update_fcr31(env, GETPC());
279 return fdt2;
280 }
281
282 uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
283 {
284 uint64_t dt2;
285
286 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
287 if (get_float_exception_flags(&env->active_fpu.fp_status)
288 & (float_flag_invalid | float_flag_overflow)) {
289 dt2 = FP_TO_INT64_OVERFLOW;
290 }
291 update_fcr31(env, GETPC());
292 return dt2;
293 }
294
295 uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
296 {
297 uint64_t dt2;
298
299 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
300 if (get_float_exception_flags(&env->active_fpu.fp_status)
301 & (float_flag_invalid | float_flag_overflow)) {
302 dt2 = FP_TO_INT64_OVERFLOW;
303 }
304 update_fcr31(env, GETPC());
305 return dt2;
306 }
307
308 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
309 {
310 uint32_t fst2;
311 uint32_t fsth2;
312
313 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
314 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
315 update_fcr31(env, GETPC());
316 return ((uint64_t)fsth2 << 32) | fst2;
317 }
318
319 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
320 {
321 uint32_t wt2;
322 uint32_t wth2;
323 int excp, excph;
324
325 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
326 excp = get_float_exception_flags(&env->active_fpu.fp_status);
327 if (excp & (float_flag_overflow | float_flag_invalid)) {
328 wt2 = FP_TO_INT32_OVERFLOW;
329 }
330
331 set_float_exception_flags(0, &env->active_fpu.fp_status);
332 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
333 excph = get_float_exception_flags(&env->active_fpu.fp_status);
334 if (excph & (float_flag_overflow | float_flag_invalid)) {
335 wth2 = FP_TO_INT32_OVERFLOW;
336 }
337
338 set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
339 update_fcr31(env, GETPC());
340
341 return ((uint64_t)wth2 << 32) | wt2;
342 }
343
344 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
345 {
346 uint32_t fst2;
347
348 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
349 update_fcr31(env, GETPC());
350 return fst2;
351 }
352
353 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
354 {
355 uint32_t fst2;
356
357 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
358 update_fcr31(env, GETPC());
359 return fst2;
360 }
361
362 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
363 {
364 uint32_t fst2;
365
366 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
367 update_fcr31(env, GETPC());
368 return fst2;
369 }
370
371 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
372 {
373 uint32_t wt2;
374
375 wt2 = wt0;
376 update_fcr31(env, GETPC());
377 return wt2;
378 }
379
380 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
381 {
382 uint32_t wt2;
383
384 wt2 = wth0;
385 update_fcr31(env, GETPC());
386 return wt2;
387 }
388
389 uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
390 {
391 uint32_t wt2;
392
393 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
394 if (get_float_exception_flags(&env->active_fpu.fp_status)
395 & (float_flag_invalid | float_flag_overflow)) {
396 wt2 = FP_TO_INT32_OVERFLOW;
397 }
398 update_fcr31(env, GETPC());
399 return wt2;
400 }
401
402 uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
403 {
404 uint32_t wt2;
405
406 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
407 if (get_float_exception_flags(&env->active_fpu.fp_status)
408 & (float_flag_invalid | float_flag_overflow)) {
409 wt2 = FP_TO_INT32_OVERFLOW;
410 }
411 update_fcr31(env, GETPC());
412 return wt2;
413 }
414
415 uint64_t helper_float_round_l_d(CPUMIPSState *env, uint64_t fdt0)
416 {
417 uint64_t dt2;
418
419 set_float_rounding_mode(float_round_nearest_even,
420 &env->active_fpu.fp_status);
421 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
422 restore_rounding_mode(env);
423 if (get_float_exception_flags(&env->active_fpu.fp_status)
424 & (float_flag_invalid | float_flag_overflow)) {
425 dt2 = FP_TO_INT64_OVERFLOW;
426 }
427 update_fcr31(env, GETPC());
428 return dt2;
429 }
430
431 uint64_t helper_float_round_l_s(CPUMIPSState *env, uint32_t fst0)
432 {
433 uint64_t dt2;
434
435 set_float_rounding_mode(float_round_nearest_even,
436 &env->active_fpu.fp_status);
437 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
438 restore_rounding_mode(env);
439 if (get_float_exception_flags(&env->active_fpu.fp_status)
440 & (float_flag_invalid | float_flag_overflow)) {
441 dt2 = FP_TO_INT64_OVERFLOW;
442 }
443 update_fcr31(env, GETPC());
444 return dt2;
445 }
446
447 uint32_t helper_float_round_w_d(CPUMIPSState *env, uint64_t fdt0)
448 {
449 uint32_t wt2;
450
451 set_float_rounding_mode(float_round_nearest_even,
452 &env->active_fpu.fp_status);
453 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
454 restore_rounding_mode(env);
455 if (get_float_exception_flags(&env->active_fpu.fp_status)
456 & (float_flag_invalid | float_flag_overflow)) {
457 wt2 = FP_TO_INT32_OVERFLOW;
458 }
459 update_fcr31(env, GETPC());
460 return wt2;
461 }
462
463 uint32_t helper_float_round_w_s(CPUMIPSState *env, uint32_t fst0)
464 {
465 uint32_t wt2;
466
467 set_float_rounding_mode(float_round_nearest_even,
468 &env->active_fpu.fp_status);
469 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
470 restore_rounding_mode(env);
471 if (get_float_exception_flags(&env->active_fpu.fp_status)
472 & (float_flag_invalid | float_flag_overflow)) {
473 wt2 = FP_TO_INT32_OVERFLOW;
474 }
475 update_fcr31(env, GETPC());
476 return wt2;
477 }
478
479 uint64_t helper_float_trunc_l_d(CPUMIPSState *env, uint64_t fdt0)
480 {
481 uint64_t dt2;
482
483 dt2 = float64_to_int64_round_to_zero(fdt0,
484 &env->active_fpu.fp_status);
485 if (get_float_exception_flags(&env->active_fpu.fp_status)
486 & (float_flag_invalid | float_flag_overflow)) {
487 dt2 = FP_TO_INT64_OVERFLOW;
488 }
489 update_fcr31(env, GETPC());
490 return dt2;
491 }
492
493 uint64_t helper_float_trunc_l_s(CPUMIPSState *env, uint32_t fst0)
494 {
495 uint64_t dt2;
496
497 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
498 if (get_float_exception_flags(&env->active_fpu.fp_status)
499 & (float_flag_invalid | float_flag_overflow)) {
500 dt2 = FP_TO_INT64_OVERFLOW;
501 }
502 update_fcr31(env, GETPC());
503 return dt2;
504 }
505
506 uint32_t helper_float_trunc_w_d(CPUMIPSState *env, uint64_t fdt0)
507 {
508 uint32_t wt2;
509
510 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
511 if (get_float_exception_flags(&env->active_fpu.fp_status)
512 & (float_flag_invalid | float_flag_overflow)) {
513 wt2 = FP_TO_INT32_OVERFLOW;
514 }
515 update_fcr31(env, GETPC());
516 return wt2;
517 }
518
519 uint32_t helper_float_trunc_w_s(CPUMIPSState *env, uint32_t fst0)
520 {
521 uint32_t wt2;
522
523 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
524 if (get_float_exception_flags(&env->active_fpu.fp_status)
525 & (float_flag_invalid | float_flag_overflow)) {
526 wt2 = FP_TO_INT32_OVERFLOW;
527 }
528 update_fcr31(env, GETPC());
529 return wt2;
530 }
531
532 uint64_t helper_float_ceil_l_d(CPUMIPSState *env, uint64_t fdt0)
533 {
534 uint64_t dt2;
535
536 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
537 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
538 restore_rounding_mode(env);
539 if (get_float_exception_flags(&env->active_fpu.fp_status)
540 & (float_flag_invalid | float_flag_overflow)) {
541 dt2 = FP_TO_INT64_OVERFLOW;
542 }
543 update_fcr31(env, GETPC());
544 return dt2;
545 }
546
547 uint64_t helper_float_ceil_l_s(CPUMIPSState *env, uint32_t fst0)
548 {
549 uint64_t dt2;
550
551 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
552 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
553 restore_rounding_mode(env);
554 if (get_float_exception_flags(&env->active_fpu.fp_status)
555 & (float_flag_invalid | float_flag_overflow)) {
556 dt2 = FP_TO_INT64_OVERFLOW;
557 }
558 update_fcr31(env, GETPC());
559 return dt2;
560 }
561
562 uint32_t helper_float_ceil_w_d(CPUMIPSState *env, uint64_t fdt0)
563 {
564 uint32_t wt2;
565
566 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
567 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
568 restore_rounding_mode(env);
569 if (get_float_exception_flags(&env->active_fpu.fp_status)
570 & (float_flag_invalid | float_flag_overflow)) {
571 wt2 = FP_TO_INT32_OVERFLOW;
572 }
573 update_fcr31(env, GETPC());
574 return wt2;
575 }
576
577 uint32_t helper_float_ceil_w_s(CPUMIPSState *env, uint32_t fst0)
578 {
579 uint32_t wt2;
580
581 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
582 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
583 restore_rounding_mode(env);
584 if (get_float_exception_flags(&env->active_fpu.fp_status)
585 & (float_flag_invalid | float_flag_overflow)) {
586 wt2 = FP_TO_INT32_OVERFLOW;
587 }
588 update_fcr31(env, GETPC());
589 return wt2;
590 }
591
592 uint64_t helper_float_floor_l_d(CPUMIPSState *env, uint64_t fdt0)
593 {
594 uint64_t dt2;
595
596 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
597 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
598 restore_rounding_mode(env);
599 if (get_float_exception_flags(&env->active_fpu.fp_status)
600 & (float_flag_invalid | float_flag_overflow)) {
601 dt2 = FP_TO_INT64_OVERFLOW;
602 }
603 update_fcr31(env, GETPC());
604 return dt2;
605 }
606
607 uint64_t helper_float_floor_l_s(CPUMIPSState *env, uint32_t fst0)
608 {
609 uint64_t dt2;
610
611 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
612 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
613 restore_rounding_mode(env);
614 if (get_float_exception_flags(&env->active_fpu.fp_status)
615 & (float_flag_invalid | float_flag_overflow)) {
616 dt2 = FP_TO_INT64_OVERFLOW;
617 }
618 update_fcr31(env, GETPC());
619 return dt2;
620 }
621
622 uint32_t helper_float_floor_w_d(CPUMIPSState *env, uint64_t fdt0)
623 {
624 uint32_t wt2;
625
626 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
627 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
628 restore_rounding_mode(env);
629 if (get_float_exception_flags(&env->active_fpu.fp_status)
630 & (float_flag_invalid | float_flag_overflow)) {
631 wt2 = FP_TO_INT32_OVERFLOW;
632 }
633 update_fcr31(env, GETPC());
634 return wt2;
635 }
636
637 uint32_t helper_float_floor_w_s(CPUMIPSState *env, uint32_t fst0)
638 {
639 uint32_t wt2;
640
641 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
642 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
643 restore_rounding_mode(env);
644 if (get_float_exception_flags(&env->active_fpu.fp_status)
645 & (float_flag_invalid | float_flag_overflow)) {
646 wt2 = FP_TO_INT32_OVERFLOW;
647 }
648 update_fcr31(env, GETPC());
649 return wt2;
650 }
651
652 uint64_t helper_float_cvt_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
653 {
654 uint64_t dt2;
655
656 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
657 if (get_float_exception_flags(&env->active_fpu.fp_status)
658 & float_flag_invalid) {
659 if (float64_is_any_nan(fdt0)) {
660 dt2 = 0;
661 }
662 }
663 update_fcr31(env, GETPC());
664 return dt2;
665 }
666
667 uint64_t helper_float_cvt_2008_l_s(CPUMIPSState *env, uint32_t fst0)
668 {
669 uint64_t dt2;
670
671 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
672 if (get_float_exception_flags(&env->active_fpu.fp_status)
673 & float_flag_invalid) {
674 if (float32_is_any_nan(fst0)) {
675 dt2 = 0;
676 }
677 }
678 update_fcr31(env, GETPC());
679 return dt2;
680 }
681
682 uint32_t helper_float_cvt_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
683 {
684 uint32_t wt2;
685
686 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
687 if (get_float_exception_flags(&env->active_fpu.fp_status)
688 & float_flag_invalid) {
689 if (float64_is_any_nan(fdt0)) {
690 wt2 = 0;
691 }
692 }
693 update_fcr31(env, GETPC());
694 return wt2;
695 }
696
697 uint32_t helper_float_cvt_2008_w_s(CPUMIPSState *env, uint32_t fst0)
698 {
699 uint32_t wt2;
700
701 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
702 if (get_float_exception_flags(&env->active_fpu.fp_status)
703 & float_flag_invalid) {
704 if (float32_is_any_nan(fst0)) {
705 wt2 = 0;
706 }
707 }
708 update_fcr31(env, GETPC());
709 return wt2;
710 }
711
712 uint64_t helper_float_round_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
713 {
714 uint64_t dt2;
715
716 set_float_rounding_mode(float_round_nearest_even,
717 &env->active_fpu.fp_status);
718 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
719 restore_rounding_mode(env);
720 if (get_float_exception_flags(&env->active_fpu.fp_status)
721 & float_flag_invalid) {
722 if (float64_is_any_nan(fdt0)) {
723 dt2 = 0;
724 }
725 }
726 update_fcr31(env, GETPC());
727 return dt2;
728 }
729
730 uint64_t helper_float_round_2008_l_s(CPUMIPSState *env, uint32_t fst0)
731 {
732 uint64_t dt2;
733
734 set_float_rounding_mode(float_round_nearest_even,
735 &env->active_fpu.fp_status);
736 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
737 restore_rounding_mode(env);
738 if (get_float_exception_flags(&env->active_fpu.fp_status)
739 & float_flag_invalid) {
740 if (float32_is_any_nan(fst0)) {
741 dt2 = 0;
742 }
743 }
744 update_fcr31(env, GETPC());
745 return dt2;
746 }
747
748 uint32_t helper_float_round_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
749 {
750 uint32_t wt2;
751
752 set_float_rounding_mode(float_round_nearest_even,
753 &env->active_fpu.fp_status);
754 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
755 restore_rounding_mode(env);
756 if (get_float_exception_flags(&env->active_fpu.fp_status)
757 & float_flag_invalid) {
758 if (float64_is_any_nan(fdt0)) {
759 wt2 = 0;
760 }
761 }
762 update_fcr31(env, GETPC());
763 return wt2;
764 }
765
766 uint32_t helper_float_round_2008_w_s(CPUMIPSState *env, uint32_t fst0)
767 {
768 uint32_t wt2;
769
770 set_float_rounding_mode(float_round_nearest_even,
771 &env->active_fpu.fp_status);
772 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
773 restore_rounding_mode(env);
774 if (get_float_exception_flags(&env->active_fpu.fp_status)
775 & float_flag_invalid) {
776 if (float32_is_any_nan(fst0)) {
777 wt2 = 0;
778 }
779 }
780 update_fcr31(env, GETPC());
781 return wt2;
782 }
783
784 uint64_t helper_float_trunc_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
785 {
786 uint64_t dt2;
787
788 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
789 if (get_float_exception_flags(&env->active_fpu.fp_status)
790 & float_flag_invalid) {
791 if (float64_is_any_nan(fdt0)) {
792 dt2 = 0;
793 }
794 }
795 update_fcr31(env, GETPC());
796 return dt2;
797 }
798
799 uint64_t helper_float_trunc_2008_l_s(CPUMIPSState *env, uint32_t fst0)
800 {
801 uint64_t dt2;
802
803 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
804 if (get_float_exception_flags(&env->active_fpu.fp_status)
805 & float_flag_invalid) {
806 if (float32_is_any_nan(fst0)) {
807 dt2 = 0;
808 }
809 }
810 update_fcr31(env, GETPC());
811 return dt2;
812 }
813
814 uint32_t helper_float_trunc_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
815 {
816 uint32_t wt2;
817
818 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
819 if (get_float_exception_flags(&env->active_fpu.fp_status)
820 & float_flag_invalid) {
821 if (float64_is_any_nan(fdt0)) {
822 wt2 = 0;
823 }
824 }
825 update_fcr31(env, GETPC());
826 return wt2;
827 }
828
829 uint32_t helper_float_trunc_2008_w_s(CPUMIPSState *env, uint32_t fst0)
830 {
831 uint32_t wt2;
832
833 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
834 if (get_float_exception_flags(&env->active_fpu.fp_status)
835 & float_flag_invalid) {
836 if (float32_is_any_nan(fst0)) {
837 wt2 = 0;
838 }
839 }
840 update_fcr31(env, GETPC());
841 return wt2;
842 }
843
844 uint64_t helper_float_ceil_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
845 {
846 uint64_t dt2;
847
848 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
849 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
850 restore_rounding_mode(env);
851 if (get_float_exception_flags(&env->active_fpu.fp_status)
852 & float_flag_invalid) {
853 if (float64_is_any_nan(fdt0)) {
854 dt2 = 0;
855 }
856 }
857 update_fcr31(env, GETPC());
858 return dt2;
859 }
860
861 uint64_t helper_float_ceil_2008_l_s(CPUMIPSState *env, uint32_t fst0)
862 {
863 uint64_t dt2;
864
865 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
866 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
867 restore_rounding_mode(env);
868 if (get_float_exception_flags(&env->active_fpu.fp_status)
869 & float_flag_invalid) {
870 if (float32_is_any_nan(fst0)) {
871 dt2 = 0;
872 }
873 }
874 update_fcr31(env, GETPC());
875 return dt2;
876 }
877
878 uint32_t helper_float_ceil_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
879 {
880 uint32_t wt2;
881
882 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
883 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
884 restore_rounding_mode(env);
885 if (get_float_exception_flags(&env->active_fpu.fp_status)
886 & float_flag_invalid) {
887 if (float64_is_any_nan(fdt0)) {
888 wt2 = 0;
889 }
890 }
891 update_fcr31(env, GETPC());
892 return wt2;
893 }
894
895 uint32_t helper_float_ceil_2008_w_s(CPUMIPSState *env, uint32_t fst0)
896 {
897 uint32_t wt2;
898
899 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
900 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
901 restore_rounding_mode(env);
902 if (get_float_exception_flags(&env->active_fpu.fp_status)
903 & float_flag_invalid) {
904 if (float32_is_any_nan(fst0)) {
905 wt2 = 0;
906 }
907 }
908 update_fcr31(env, GETPC());
909 return wt2;
910 }
911
912 uint64_t helper_float_floor_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
913 {
914 uint64_t dt2;
915
916 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
917 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
918 restore_rounding_mode(env);
919 if (get_float_exception_flags(&env->active_fpu.fp_status)
920 & float_flag_invalid) {
921 if (float64_is_any_nan(fdt0)) {
922 dt2 = 0;
923 }
924 }
925 update_fcr31(env, GETPC());
926 return dt2;
927 }
928
929 uint64_t helper_float_floor_2008_l_s(CPUMIPSState *env, uint32_t fst0)
930 {
931 uint64_t dt2;
932
933 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
934 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
935 restore_rounding_mode(env);
936 if (get_float_exception_flags(&env->active_fpu.fp_status)
937 & float_flag_invalid) {
938 if (float32_is_any_nan(fst0)) {
939 dt2 = 0;
940 }
941 }
942 update_fcr31(env, GETPC());
943 return dt2;
944 }
945
946 uint32_t helper_float_floor_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
947 {
948 uint32_t wt2;
949
950 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
951 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
952 restore_rounding_mode(env);
953 if (get_float_exception_flags(&env->active_fpu.fp_status)
954 & float_flag_invalid) {
955 if (float64_is_any_nan(fdt0)) {
956 wt2 = 0;
957 }
958 }
959 update_fcr31(env, GETPC());
960 return wt2;
961 }
962
963 uint32_t helper_float_floor_2008_w_s(CPUMIPSState *env, uint32_t fst0)
964 {
965 uint32_t wt2;
966
967 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
968 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
969 restore_rounding_mode(env);
970 if (get_float_exception_flags(&env->active_fpu.fp_status)
971 & float_flag_invalid) {
972 if (float32_is_any_nan(fst0)) {
973 wt2 = 0;
974 }
975 }
976 update_fcr31(env, GETPC());
977 return wt2;
978 }
979
980 /* unary operations, not modifying fp status */
981 #define FLOAT_UNOP(name) \
982 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
983 { \
984 return float64_ ## name(fdt0); \
985 } \
986 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
987 { \
988 return float32_ ## name(fst0); \
989 } \
990 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
991 { \
992 uint32_t wt0; \
993 uint32_t wth0; \
994 \
995 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
996 wth0 = float32_ ## name(fdt0 >> 32); \
997 return ((uint64_t)wth0 << 32) | wt0; \
998 }
999 FLOAT_UNOP(abs)
1000 FLOAT_UNOP(chs)
1001 #undef FLOAT_UNOP
1002
1003 /* MIPS specific unary operations */
1004 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
1005 {
1006 uint64_t fdt2;
1007
1008 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
1009 update_fcr31(env, GETPC());
1010 return fdt2;
1011 }
1012
1013 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
1014 {
1015 uint32_t fst2;
1016
1017 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
1018 update_fcr31(env, GETPC());
1019 return fst2;
1020 }
1021
1022 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
1023 {
1024 uint64_t fdt2;
1025
1026 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
1027 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
1028 update_fcr31(env, GETPC());
1029 return fdt2;
1030 }
1031
1032 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
1033 {
1034 uint32_t fst2;
1035
1036 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
1037 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
1038 update_fcr31(env, GETPC());
1039 return fst2;
1040 }
1041
1042 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
1043 {
1044 uint64_t fdt2;
1045
1046 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
1047 update_fcr31(env, GETPC());
1048 return fdt2;
1049 }
1050
1051 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
1052 {
1053 uint32_t fst2;
1054
1055 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
1056 update_fcr31(env, GETPC());
1057 return fst2;
1058 }
1059
1060 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
1061 {
1062 uint32_t fst2;
1063 uint32_t fsth2;
1064
1065 fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF,
1066 &env->active_fpu.fp_status);
1067 fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
1068 update_fcr31(env, GETPC());
1069 return ((uint64_t)fsth2 << 32) | fst2;
1070 }
1071
1072 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
1073 {
1074 uint64_t fdt2;
1075
1076 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
1077 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
1078 update_fcr31(env, GETPC());
1079 return fdt2;
1080 }
1081
1082 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
1083 {
1084 uint32_t fst2;
1085
1086 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
1087 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
1088 update_fcr31(env, GETPC());
1089 return fst2;
1090 }
1091
1092 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
1093 {
1094 uint32_t fst2;
1095 uint32_t fsth2;
1096
1097 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
1098 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
1099 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
1100 fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
1101 update_fcr31(env, GETPC());
1102 return ((uint64_t)fsth2 << 32) | fst2;
1103 }
1104
1105 #define FLOAT_RINT(name, bits) \
1106 uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
1107 uint ## bits ## _t fs) \
1108 { \
1109 uint ## bits ## _t fdret; \
1110 \
1111 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
1112 update_fcr31(env, GETPC()); \
1113 return fdret; \
1114 }
1115
1116 FLOAT_RINT(rint_s, 32)
1117 FLOAT_RINT(rint_d, 64)
1118 #undef FLOAT_RINT
1119
1120 #define FLOAT_CLASS_SIGNALING_NAN 0x001
1121 #define FLOAT_CLASS_QUIET_NAN 0x002
1122 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
1123 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
1124 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
1125 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
1126 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
1127 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
1128 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
1129 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
1130
1131 #define FLOAT_CLASS(name, bits) \
1132 uint ## bits ## _t float_ ## name(uint ## bits ## _t arg, \
1133 float_status *status) \
1134 { \
1135 if (float ## bits ## _is_signaling_nan(arg, status)) { \
1136 return FLOAT_CLASS_SIGNALING_NAN; \
1137 } else if (float ## bits ## _is_quiet_nan(arg, status)) { \
1138 return FLOAT_CLASS_QUIET_NAN; \
1139 } else if (float ## bits ## _is_neg(arg)) { \
1140 if (float ## bits ## _is_infinity(arg)) { \
1141 return FLOAT_CLASS_NEGATIVE_INFINITY; \
1142 } else if (float ## bits ## _is_zero(arg)) { \
1143 return FLOAT_CLASS_NEGATIVE_ZERO; \
1144 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
1145 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
1146 } else { \
1147 return FLOAT_CLASS_NEGATIVE_NORMAL; \
1148 } \
1149 } else { \
1150 if (float ## bits ## _is_infinity(arg)) { \
1151 return FLOAT_CLASS_POSITIVE_INFINITY; \
1152 } else if (float ## bits ## _is_zero(arg)) { \
1153 return FLOAT_CLASS_POSITIVE_ZERO; \
1154 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
1155 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
1156 } else { \
1157 return FLOAT_CLASS_POSITIVE_NORMAL; \
1158 } \
1159 } \
1160 } \
1161 \
1162 uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
1163 uint ## bits ## _t arg) \
1164 { \
1165 return float_ ## name(arg, &env->active_fpu.fp_status); \
1166 }
1167
1168 #undef FLOAT_CLASS
1169
1170 uint64_t float_class_d(uint64_t arg, float_status *status)
1171 {
1172 if (float64_is_signaling_nan(arg, status)) {
1173 return FLOAT_CLASS_SIGNALING_NAN;
1174 } else if (float64_is_quiet_nan(arg, status)) {
1175 return FLOAT_CLASS_QUIET_NAN;
1176 } else if (float64_is_neg(arg)) {
1177 if (float64_is_infinity(arg)) {
1178 return FLOAT_CLASS_NEGATIVE_INFINITY;
1179 } else if (float64_is_zero(arg)) {
1180 return FLOAT_CLASS_NEGATIVE_ZERO;
1181 } else if (float64_is_zero_or_denormal(arg)) {
1182 return FLOAT_CLASS_NEGATIVE_SUBNORMAL;
1183 } else {
1184 return FLOAT_CLASS_NEGATIVE_NORMAL;
1185 }
1186 } else {
1187 if (float64_is_infinity(arg)) {
1188 return FLOAT_CLASS_POSITIVE_INFINITY;
1189 } else if (float64_is_zero(arg)) {
1190 return FLOAT_CLASS_POSITIVE_ZERO;
1191 } else if (float64_is_zero_or_denormal(arg)) {
1192 return FLOAT_CLASS_POSITIVE_SUBNORMAL;
1193 } else {
1194 return FLOAT_CLASS_POSITIVE_NORMAL;
1195 }
1196 }
1197 }
1198
1199 uint64_t helper_float_class_d(CPUMIPSState *env, uint64_t arg)
1200 {
1201 return float_class_d(arg, &env->active_fpu.fp_status);
1202 }
1203
1204 uint32_t float_class_s(uint32_t arg, float_status *status)
1205 {
1206 if (float32_is_signaling_nan(arg, status)) {
1207 return FLOAT_CLASS_SIGNALING_NAN;
1208 } else if (float32_is_quiet_nan(arg, status)) {
1209 return FLOAT_CLASS_QUIET_NAN;
1210 } else if (float32_is_neg(arg)) {
1211 if (float32_is_infinity(arg)) {
1212 return FLOAT_CLASS_NEGATIVE_INFINITY;
1213 } else if (float32_is_zero(arg)) {
1214 return FLOAT_CLASS_NEGATIVE_ZERO;
1215 } else if (float32_is_zero_or_denormal(arg)) {
1216 return FLOAT_CLASS_NEGATIVE_SUBNORMAL;
1217 } else {
1218 return FLOAT_CLASS_NEGATIVE_NORMAL;
1219 }
1220 } else {
1221 if (float32_is_infinity(arg)) {
1222 return FLOAT_CLASS_POSITIVE_INFINITY;
1223 } else if (float32_is_zero(arg)) {
1224 return FLOAT_CLASS_POSITIVE_ZERO;
1225 } else if (float32_is_zero_or_denormal(arg)) {
1226 return FLOAT_CLASS_POSITIVE_SUBNORMAL;
1227 } else {
1228 return FLOAT_CLASS_POSITIVE_NORMAL;
1229 }
1230 }
1231 }
1232
1233 uint32_t helper_float_class_s(CPUMIPSState *env, uint32_t arg)
1234 {
1235 return float_class_s(arg, &env->active_fpu.fp_status);
1236 }
1237
1238 /* binary operations */
1239
1240 uint64_t helper_float_add_d(CPUMIPSState *env,
1241 uint64_t fdt0, uint64_t fdt1)
1242 {
1243 uint64_t dt2;
1244
1245 dt2 = float64_add(fdt0, fdt1, &env->active_fpu.fp_status);
1246 update_fcr31(env, GETPC());
1247 return dt2;
1248 }
1249
1250 uint32_t helper_float_add_s(CPUMIPSState *env,
1251 uint32_t fst0, uint32_t fst1)
1252 {
1253 uint32_t wt2;
1254
1255 wt2 = float32_sub(fst0, fst1, &env->active_fpu.fp_status);
1256 update_fcr31(env, GETPC());
1257 return wt2;
1258 }
1259
1260 uint64_t helper_float_add_ps(CPUMIPSState *env,
1261 uint64_t fdt0, uint64_t fdt1)
1262 {
1263 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1264 uint32_t fsth0 = fdt0 >> 32;
1265 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1266 uint32_t fsth1 = fdt1 >> 32;
1267 uint32_t wtl2;
1268 uint32_t wth2;
1269
1270 wtl2 = float32_add(fstl0, fstl1, &env->active_fpu.fp_status);
1271 wth2 = float32_add(fsth0, fsth1, &env->active_fpu.fp_status);
1272 update_fcr31(env, GETPC());
1273 return ((uint64_t)wth2 << 32) | wtl2;
1274 }
1275
1276 uint64_t helper_float_sub_d(CPUMIPSState *env,
1277 uint64_t fdt0, uint64_t fdt1)
1278 {
1279 uint64_t dt2;
1280
1281 dt2 = float64_sub(fdt0, fdt1, &env->active_fpu.fp_status);
1282 update_fcr31(env, GETPC());
1283 return dt2;
1284 }
1285
1286 uint32_t helper_float_sub_s(CPUMIPSState *env,
1287 uint32_t fst0, uint32_t fst1)
1288 {
1289 uint32_t wt2;
1290
1291 wt2 = float32_sub(fst0, fst1, &env->active_fpu.fp_status);
1292 update_fcr31(env, GETPC());
1293 return wt2;
1294 }
1295
1296 uint64_t helper_float_sub_ps(CPUMIPSState *env,
1297 uint64_t fdt0, uint64_t fdt1)
1298 {
1299 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1300 uint32_t fsth0 = fdt0 >> 32;
1301 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1302 uint32_t fsth1 = fdt1 >> 32;
1303 uint32_t wtl2;
1304 uint32_t wth2;
1305
1306 wtl2 = float32_sub(fstl0, fstl1, &env->active_fpu.fp_status);
1307 wth2 = float32_sub(fsth0, fsth1, &env->active_fpu.fp_status);
1308 update_fcr31(env, GETPC());
1309 return ((uint64_t)wth2 << 32) | wtl2;
1310 }
1311
1312 uint64_t helper_float_mul_d(CPUMIPSState *env,
1313 uint64_t fdt0, uint64_t fdt1)
1314 {
1315 uint64_t dt2;
1316
1317 dt2 = float64_mul(fdt0, fdt1, &env->active_fpu.fp_status);
1318 update_fcr31(env, GETPC());
1319 return dt2;
1320 }
1321
1322 uint32_t helper_float_mul_s(CPUMIPSState *env,
1323 uint32_t fst0, uint32_t fst1)
1324 {
1325 uint32_t wt2;
1326
1327 wt2 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
1328 update_fcr31(env, GETPC());
1329 return wt2;
1330 }
1331
1332 uint64_t helper_float_mul_ps(CPUMIPSState *env,
1333 uint64_t fdt0, uint64_t fdt1)
1334 {
1335 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1336 uint32_t fsth0 = fdt0 >> 32;
1337 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1338 uint32_t fsth1 = fdt1 >> 32;
1339 uint32_t wtl2;
1340 uint32_t wth2;
1341
1342 wtl2 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
1343 wth2 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
1344 update_fcr31(env, GETPC());
1345 return ((uint64_t)wth2 << 32) | wtl2;
1346 }
1347
1348 uint64_t helper_float_div_d(CPUMIPSState *env,
1349 uint64_t fdt0, uint64_t fdt1)
1350 {
1351 uint64_t dt2;
1352
1353 dt2 = float64_div(fdt0, fdt1, &env->active_fpu.fp_status);
1354 update_fcr31(env, GETPC());
1355 return dt2;
1356 }
1357
1358 uint32_t helper_float_div_s(CPUMIPSState *env,
1359 uint32_t fst0, uint32_t fst1)
1360 {
1361 uint32_t wt2;
1362
1363 wt2 = float32_div(fst0, fst1, &env->active_fpu.fp_status);
1364 update_fcr31(env, GETPC());
1365 return wt2;
1366 }
1367
1368 uint64_t helper_float_div_ps(CPUMIPSState *env,
1369 uint64_t fdt0, uint64_t fdt1)
1370 {
1371 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1372 uint32_t fsth0 = fdt0 >> 32;
1373 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1374 uint32_t fsth1 = fdt1 >> 32;
1375 uint32_t wtl2;
1376 uint32_t wth2;
1377
1378 wtl2 = float32_div(fstl0, fstl1, &env->active_fpu.fp_status);
1379 wth2 = float32_div(fsth0, fsth1, &env->active_fpu.fp_status);
1380 update_fcr31(env, GETPC());
1381 return ((uint64_t)wth2 << 32) | wtl2;
1382 }
1383
1384
1385 /* MIPS specific binary operations */
1386 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
1387 {
1388 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
1389 fdt2 = float64_chs(float64_sub(fdt2, float64_one,
1390 &env->active_fpu.fp_status));
1391 update_fcr31(env, GETPC());
1392 return fdt2;
1393 }
1394
1395 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
1396 {
1397 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
1398 fst2 = float32_chs(float32_sub(fst2, float32_one,
1399 &env->active_fpu.fp_status));
1400 update_fcr31(env, GETPC());
1401 return fst2;
1402 }
1403
1404 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
1405 {
1406 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
1407 uint32_t fsth0 = fdt0 >> 32;
1408 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
1409 uint32_t fsth2 = fdt2 >> 32;
1410
1411 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
1412 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
1413 fst2 = float32_chs(float32_sub(fst2, float32_one,
1414 &env->active_fpu.fp_status));
1415 fsth2 = float32_chs(float32_sub(fsth2, float32_one,
1416 &env->active_fpu.fp_status));
1417 update_fcr31(env, GETPC());
1418 return ((uint64_t)fsth2 << 32) | fst2;
1419 }
1420
1421 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
1422 {
1423 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
1424 fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
1425 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64,
1426 &env->active_fpu.fp_status));
1427 update_fcr31(env, GETPC());
1428 return fdt2;
1429 }
1430
1431 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
1432 {
1433 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
1434 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
1435 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32,
1436 &env->active_fpu.fp_status));
1437 update_fcr31(env, GETPC());
1438 return fst2;
1439 }
1440
1441 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
1442 {
1443 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
1444 uint32_t fsth0 = fdt0 >> 32;
1445 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
1446 uint32_t fsth2 = fdt2 >> 32;
1447
1448 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
1449 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
1450 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
1451 fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
1452 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32,
1453 &env->active_fpu.fp_status));
1454 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32,
1455 &env->active_fpu.fp_status));
1456 update_fcr31(env, GETPC());
1457 return ((uint64_t)fsth2 << 32) | fst2;
1458 }
1459
1460 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
1461 {
1462 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
1463 uint32_t fsth0 = fdt0 >> 32;
1464 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
1465 uint32_t fsth1 = fdt1 >> 32;
1466 uint32_t fst2;
1467 uint32_t fsth2;
1468
1469 fst2 = float32_add(fst0, fsth0, &env->active_fpu.fp_status);
1470 fsth2 = float32_add(fst1, fsth1, &env->active_fpu.fp_status);
1471 update_fcr31(env, GETPC());
1472 return ((uint64_t)fsth2 << 32) | fst2;
1473 }
1474
1475 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
1476 {
1477 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
1478 uint32_t fsth0 = fdt0 >> 32;
1479 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
1480 uint32_t fsth1 = fdt1 >> 32;
1481 uint32_t fst2;
1482 uint32_t fsth2;
1483
1484 fst2 = float32_mul(fst0, fsth0, &env->active_fpu.fp_status);
1485 fsth2 = float32_mul(fst1, fsth1, &env->active_fpu.fp_status);
1486 update_fcr31(env, GETPC());
1487 return ((uint64_t)fsth2 << 32) | fst2;
1488 }
1489
1490 #define FLOAT_MINMAX(name, bits, minmaxfunc) \
1491 uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
1492 uint ## bits ## _t fs, \
1493 uint ## bits ## _t ft) \
1494 { \
1495 uint ## bits ## _t fdret; \
1496 \
1497 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
1498 &env->active_fpu.fp_status); \
1499 update_fcr31(env, GETPC()); \
1500 return fdret; \
1501 }
1502
1503 FLOAT_MINMAX(max_s, 32, maxnum)
1504 FLOAT_MINMAX(max_d, 64, maxnum)
1505 FLOAT_MINMAX(maxa_s, 32, maxnummag)
1506 FLOAT_MINMAX(maxa_d, 64, maxnummag)
1507
1508 FLOAT_MINMAX(min_s, 32, minnum)
1509 FLOAT_MINMAX(min_d, 64, minnum)
1510 FLOAT_MINMAX(mina_s, 32, minnummag)
1511 FLOAT_MINMAX(mina_d, 64, minnummag)
1512 #undef FLOAT_MINMAX
1513
1514 /* ternary operations */
1515
1516 uint64_t helper_float_madd_d(CPUMIPSState *env, uint64_t fst0,
1517 uint64_t fst1, uint64_t fst2)
1518 {
1519 fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status);
1520 fst0 = float64_add(fst0, fst2, &env->active_fpu.fp_status);
1521
1522 update_fcr31(env, GETPC());
1523 return fst0;
1524 }
1525
1526 uint32_t helper_float_madd_s(CPUMIPSState *env, uint32_t fst0,
1527 uint32_t fst1, uint32_t fst2)
1528 {
1529 fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
1530 fst0 = float32_add(fst0, fst2, &env->active_fpu.fp_status);
1531
1532 update_fcr31(env, GETPC());
1533 return fst0;
1534 }
1535
1536 uint64_t helper_float_madd_ps(CPUMIPSState *env, uint64_t fdt0,
1537 uint64_t fdt1, uint64_t fdt2)
1538 {
1539 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1540 uint32_t fsth0 = fdt0 >> 32;
1541 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1542 uint32_t fsth1 = fdt1 >> 32;
1543 uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
1544 uint32_t fsth2 = fdt2 >> 32;
1545
1546 fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
1547 fstl0 = float32_add(fstl0, fstl2, &env->active_fpu.fp_status);
1548 fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
1549 fsth0 = float32_add(fsth0, fsth2, &env->active_fpu.fp_status);
1550
1551 update_fcr31(env, GETPC());
1552 return ((uint64_t)fsth0 << 32) | fstl0;
1553 }
1554
1555 uint64_t helper_float_msub_d(CPUMIPSState *env, uint64_t fst0,
1556 uint64_t fst1, uint64_t fst2)
1557 {
1558 fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status);
1559 fst0 = float64_sub(fst0, fst2, &env->active_fpu.fp_status);
1560
1561 update_fcr31(env, GETPC());
1562 return fst0;
1563 }
1564
1565 uint32_t helper_float_msub_s(CPUMIPSState *env, uint32_t fst0,
1566 uint32_t fst1, uint32_t fst2)
1567 {
1568 fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
1569 fst0 = float32_sub(fst0, fst2, &env->active_fpu.fp_status);
1570
1571 update_fcr31(env, GETPC());
1572 return fst0;
1573 }
1574
1575 uint64_t helper_float_msub_ps(CPUMIPSState *env, uint64_t fdt0,
1576 uint64_t fdt1, uint64_t fdt2)
1577 {
1578 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1579 uint32_t fsth0 = fdt0 >> 32;
1580 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1581 uint32_t fsth1 = fdt1 >> 32;
1582 uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
1583 uint32_t fsth2 = fdt2 >> 32;
1584
1585 fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
1586 fstl0 = float32_sub(fstl0, fstl2, &env->active_fpu.fp_status);
1587 fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
1588 fsth0 = float32_sub(fsth0, fsth2, &env->active_fpu.fp_status);
1589
1590 update_fcr31(env, GETPC());
1591 return ((uint64_t)fsth0 << 32) | fstl0;
1592 }
1593
1594 uint64_t helper_float_nmadd_d(CPUMIPSState *env, uint64_t fst0,
1595 uint64_t fst1, uint64_t fst2)
1596 {
1597 fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status);
1598 fst0 = float64_add(fst0, fst2, &env->active_fpu.fp_status);
1599 fst0 = float64_chs(fst0);
1600
1601 update_fcr31(env, GETPC());
1602 return fst0;
1603 }
1604
1605 uint32_t helper_float_nmadd_s(CPUMIPSState *env, uint32_t fst0,
1606 uint32_t fst1, uint32_t fst2)
1607 {
1608 fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
1609 fst0 = float32_add(fst0, fst2, &env->active_fpu.fp_status);
1610 fst0 = float32_chs(fst0);
1611
1612 update_fcr31(env, GETPC());
1613 return fst0;
1614 }
1615
1616 uint64_t helper_float_nmadd_ps(CPUMIPSState *env, uint64_t fdt0,
1617 uint64_t fdt1, uint64_t fdt2)
1618 {
1619 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1620 uint32_t fsth0 = fdt0 >> 32;
1621 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1622 uint32_t fsth1 = fdt1 >> 32;
1623 uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
1624 uint32_t fsth2 = fdt2 >> 32;
1625
1626 fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
1627 fstl0 = float32_add(fstl0, fstl2, &env->active_fpu.fp_status);
1628 fstl0 = float32_chs(fstl0);
1629 fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
1630 fsth0 = float32_add(fsth0, fsth2, &env->active_fpu.fp_status);
1631 fsth0 = float32_chs(fsth0);
1632
1633 update_fcr31(env, GETPC());
1634 return ((uint64_t)fsth0 << 32) | fstl0;
1635 }
1636
1637 uint64_t helper_float_nmsub_d(CPUMIPSState *env, uint64_t fst0,
1638 uint64_t fst1, uint64_t fst2)
1639 {
1640 fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status);
1641 fst0 = float64_sub(fst0, fst2, &env->active_fpu.fp_status);
1642 fst0 = float64_chs(fst0);
1643
1644 update_fcr31(env, GETPC());
1645 return fst0;
1646 }
1647
1648 uint32_t helper_float_nmsub_s(CPUMIPSState *env, uint32_t fst0,
1649 uint32_t fst1, uint32_t fst2)
1650 {
1651 fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
1652 fst0 = float32_sub(fst0, fst2, &env->active_fpu.fp_status);
1653 fst0 = float32_chs(fst0);
1654
1655 update_fcr31(env, GETPC());
1656 return fst0;
1657 }
1658
1659 uint64_t helper_float_nmsub_ps(CPUMIPSState *env, uint64_t fdt0,
1660 uint64_t fdt1, uint64_t fdt2)
1661 {
1662 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1663 uint32_t fsth0 = fdt0 >> 32;
1664 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1665 uint32_t fsth1 = fdt1 >> 32;
1666 uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
1667 uint32_t fsth2 = fdt2 >> 32;
1668
1669 fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
1670 fstl0 = float32_sub(fstl0, fstl2, &env->active_fpu.fp_status);
1671 fstl0 = float32_chs(fstl0);
1672 fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
1673 fsth0 = float32_sub(fsth0, fsth2, &env->active_fpu.fp_status);
1674 fsth0 = float32_chs(fsth0);
1675
1676 update_fcr31(env, GETPC());
1677 return ((uint64_t)fsth0 << 32) | fstl0;
1678 }
1679
1680
1681 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \
1682 uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
1683 uint ## bits ## _t fs, \
1684 uint ## bits ## _t ft, \
1685 uint ## bits ## _t fd) \
1686 { \
1687 uint ## bits ## _t fdret; \
1688 \
1689 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
1690 &env->active_fpu.fp_status); \
1691 update_fcr31(env, GETPC()); \
1692 return fdret; \
1693 }
1694
1695 FLOAT_FMADDSUB(maddf_s, 32, 0)
1696 FLOAT_FMADDSUB(maddf_d, 64, 0)
1697 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
1698 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
1699 #undef FLOAT_FMADDSUB
1700
1701 /* compare operations */
1702 #define FOP_COND_D(op, cond) \
1703 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
1704 uint64_t fdt1, int cc) \
1705 { \
1706 int c; \
1707 c = cond; \
1708 update_fcr31(env, GETPC()); \
1709 if (c) \
1710 SET_FP_COND(cc, env->active_fpu); \
1711 else \
1712 CLEAR_FP_COND(cc, env->active_fpu); \
1713 } \
1714 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
1715 uint64_t fdt1, int cc) \
1716 { \
1717 int c; \
1718 fdt0 = float64_abs(fdt0); \
1719 fdt1 = float64_abs(fdt1); \
1720 c = cond; \
1721 update_fcr31(env, GETPC()); \
1722 if (c) \
1723 SET_FP_COND(cc, env->active_fpu); \
1724 else \
1725 CLEAR_FP_COND(cc, env->active_fpu); \
1726 }
1727
1728 /*
1729 * NOTE: the comma operator will make "cond" to eval to false,
1730 * but float64_unordered_quiet() is still called.
1731 */
1732 FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0,
1733 &env->active_fpu.fp_status), 0))
1734 FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0,
1735 &env->active_fpu.fp_status))
1736 FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1,
1737 &env->active_fpu.fp_status))
1738 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0,
1739 &env->active_fpu.fp_status)
1740 || float64_eq_quiet(fdt0, fdt1,
1741 &env->active_fpu.fp_status))
1742 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1,
1743 &env->active_fpu.fp_status))
1744 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0,
1745 &env->active_fpu.fp_status)
1746 || float64_lt_quiet(fdt0, fdt1,
1747 &env->active_fpu.fp_status))
1748 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1,
1749 &env->active_fpu.fp_status))
1750 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0,
1751 &env->active_fpu.fp_status)
1752 || float64_le_quiet(fdt0, fdt1,
1753 &env->active_fpu.fp_status))
1754 /*
1755 * NOTE: the comma operator will make "cond" to eval to false,
1756 * but float64_unordered() is still called.
1757 */
1758 FOP_COND_D(sf, (float64_unordered(fdt1, fdt0,
1759 &env->active_fpu.fp_status), 0))
1760 FOP_COND_D(ngle, float64_unordered(fdt1, fdt0,
1761 &env->active_fpu.fp_status))
1762 FOP_COND_D(seq, float64_eq(fdt0, fdt1,
1763 &env->active_fpu.fp_status))
1764 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0,
1765 &env->active_fpu.fp_status)
1766 || float64_eq(fdt0, fdt1,
1767 &env->active_fpu.fp_status))
1768 FOP_COND_D(lt, float64_lt(fdt0, fdt1,
1769 &env->active_fpu.fp_status))
1770 FOP_COND_D(nge, float64_unordered(fdt1, fdt0,
1771 &env->active_fpu.fp_status)
1772 || float64_lt(fdt0, fdt1,
1773 &env->active_fpu.fp_status))
1774 FOP_COND_D(le, float64_le(fdt0, fdt1,
1775 &env->active_fpu.fp_status))
1776 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0,
1777 &env->active_fpu.fp_status)
1778 || float64_le(fdt0, fdt1,
1779 &env->active_fpu.fp_status))
1780
1781 #define FOP_COND_S(op, cond) \
1782 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
1783 uint32_t fst1, int cc) \
1784 { \
1785 int c; \
1786 c = cond; \
1787 update_fcr31(env, GETPC()); \
1788 if (c) \
1789 SET_FP_COND(cc, env->active_fpu); \
1790 else \
1791 CLEAR_FP_COND(cc, env->active_fpu); \
1792 } \
1793 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
1794 uint32_t fst1, int cc) \
1795 { \
1796 int c; \
1797 fst0 = float32_abs(fst0); \
1798 fst1 = float32_abs(fst1); \
1799 c = cond; \
1800 update_fcr31(env, GETPC()); \
1801 if (c) \
1802 SET_FP_COND(cc, env->active_fpu); \
1803 else \
1804 CLEAR_FP_COND(cc, env->active_fpu); \
1805 }
1806
1807 /*
1808 * NOTE: the comma operator will make "cond" to eval to false,
1809 * but float32_unordered_quiet() is still called.
1810 */
1811 FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0,
1812 &env->active_fpu.fp_status), 0))
1813 FOP_COND_S(un, float32_unordered_quiet(fst1, fst0,
1814 &env->active_fpu.fp_status))
1815 FOP_COND_S(eq, float32_eq_quiet(fst0, fst1,
1816 &env->active_fpu.fp_status))
1817 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0,
1818 &env->active_fpu.fp_status)
1819 || float32_eq_quiet(fst0, fst1,
1820 &env->active_fpu.fp_status))
1821 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1,
1822 &env->active_fpu.fp_status))
1823 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0,
1824 &env->active_fpu.fp_status)
1825 || float32_lt_quiet(fst0, fst1,
1826 &env->active_fpu.fp_status))
1827 FOP_COND_S(ole, float32_le_quiet(fst0, fst1,
1828 &env->active_fpu.fp_status))
1829 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0,
1830 &env->active_fpu.fp_status)
1831 || float32_le_quiet(fst0, fst1,
1832 &env->active_fpu.fp_status))
1833 /*
1834 * NOTE: the comma operator will make "cond" to eval to false,
1835 * but float32_unordered() is still called.
1836 */
1837 FOP_COND_S(sf, (float32_unordered(fst1, fst0,
1838 &env->active_fpu.fp_status), 0))
1839 FOP_COND_S(ngle, float32_unordered(fst1, fst0,
1840 &env->active_fpu.fp_status))
1841 FOP_COND_S(seq, float32_eq(fst0, fst1,
1842 &env->active_fpu.fp_status))
1843 FOP_COND_S(ngl, float32_unordered(fst1, fst0,
1844 &env->active_fpu.fp_status)
1845 || float32_eq(fst0, fst1,
1846 &env->active_fpu.fp_status))
1847 FOP_COND_S(lt, float32_lt(fst0, fst1,
1848 &env->active_fpu.fp_status))
1849 FOP_COND_S(nge, float32_unordered(fst1, fst0,
1850 &env->active_fpu.fp_status)
1851 || float32_lt(fst0, fst1,
1852 &env->active_fpu.fp_status))
1853 FOP_COND_S(le, float32_le(fst0, fst1,
1854 &env->active_fpu.fp_status))
1855 FOP_COND_S(ngt, float32_unordered(fst1, fst0,
1856 &env->active_fpu.fp_status)
1857 || float32_le(fst0, fst1,
1858 &env->active_fpu.fp_status))
1859
1860 #define FOP_COND_PS(op, condl, condh) \
1861 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
1862 uint64_t fdt1, int cc) \
1863 { \
1864 uint32_t fst0, fsth0, fst1, fsth1; \
1865 int ch, cl; \
1866 fst0 = fdt0 & 0XFFFFFFFF; \
1867 fsth0 = fdt0 >> 32; \
1868 fst1 = fdt1 & 0XFFFFFFFF; \
1869 fsth1 = fdt1 >> 32; \
1870 cl = condl; \
1871 ch = condh; \
1872 update_fcr31(env, GETPC()); \
1873 if (cl) \
1874 SET_FP_COND(cc, env->active_fpu); \
1875 else \
1876 CLEAR_FP_COND(cc, env->active_fpu); \
1877 if (ch) \
1878 SET_FP_COND(cc + 1, env->active_fpu); \
1879 else \
1880 CLEAR_FP_COND(cc + 1, env->active_fpu); \
1881 } \
1882 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
1883 uint64_t fdt1, int cc) \
1884 { \
1885 uint32_t fst0, fsth0, fst1, fsth1; \
1886 int ch, cl; \
1887 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
1888 fsth0 = float32_abs(fdt0 >> 32); \
1889 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
1890 fsth1 = float32_abs(fdt1 >> 32); \
1891 cl = condl; \
1892 ch = condh; \
1893 update_fcr31(env, GETPC()); \
1894 if (cl) \
1895 SET_FP_COND(cc, env->active_fpu); \
1896 else \
1897 CLEAR_FP_COND(cc, env->active_fpu); \
1898 if (ch) \
1899 SET_FP_COND(cc + 1, env->active_fpu); \
1900 else \
1901 CLEAR_FP_COND(cc + 1, env->active_fpu); \
1902 }
1903
1904 /*
1905 * NOTE: the comma operator will make "cond" to eval to false,
1906 * but float32_unordered_quiet() is still called.
1907 */
1908 FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0,
1909 &env->active_fpu.fp_status), 0),
1910 (float32_unordered_quiet(fsth1, fsth0,
1911 &env->active_fpu.fp_status), 0))
1912 FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0,
1913 &env->active_fpu.fp_status),
1914 float32_unordered_quiet(fsth1, fsth0,
1915 &env->active_fpu.fp_status))
1916 FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1,
1917 &env->active_fpu.fp_status),
1918 float32_eq_quiet(fsth0, fsth1,
1919 &env->active_fpu.fp_status))
1920 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0,
1921 &env->active_fpu.fp_status)
1922 || float32_eq_quiet(fst0, fst1,
1923 &env->active_fpu.fp_status),
1924 float32_unordered_quiet(fsth1, fsth0,
1925 &env->active_fpu.fp_status)
1926 || float32_eq_quiet(fsth0, fsth1,
1927 &env->active_fpu.fp_status))
1928 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1,
1929 &env->active_fpu.fp_status),
1930 float32_lt_quiet(fsth0, fsth1,
1931 &env->active_fpu.fp_status))
1932 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0,
1933 &env->active_fpu.fp_status)
1934 || float32_lt_quiet(fst0, fst1,
1935 &env->active_fpu.fp_status),
1936 float32_unordered_quiet(fsth1, fsth0,
1937 &env->active_fpu.fp_status)
1938 || float32_lt_quiet(fsth0, fsth1,
1939 &env->active_fpu.fp_status))
1940 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1,
1941 &env->active_fpu.fp_status),
1942 float32_le_quiet(fsth0, fsth1,
1943 &env->active_fpu.fp_status))
1944 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0,
1945 &env->active_fpu.fp_status)
1946 || float32_le_quiet(fst0, fst1,
1947 &env->active_fpu.fp_status),
1948 float32_unordered_quiet(fsth1, fsth0,
1949 &env->active_fpu.fp_status)
1950 || float32_le_quiet(fsth0, fsth1,
1951 &env->active_fpu.fp_status))
1952 /*
1953 * NOTE: the comma operator will make "cond" to eval to false,
1954 * but float32_unordered() is still called.
1955 */
1956 FOP_COND_PS(sf, (float32_unordered(fst1, fst0,
1957 &env->active_fpu.fp_status), 0),
1958 (float32_unordered(fsth1, fsth0,
1959 &env->active_fpu.fp_status), 0))
1960 FOP_COND_PS(ngle, float32_unordered(fst1, fst0,
1961 &env->active_fpu.fp_status),
1962 float32_unordered(fsth1, fsth0,
1963 &env->active_fpu.fp_status))
1964 FOP_COND_PS(seq, float32_eq(fst0, fst1,
1965 &env->active_fpu.fp_status),
1966 float32_eq(fsth0, fsth1,
1967 &env->active_fpu.fp_status))
1968 FOP_COND_PS(ngl, float32_unordered(fst1, fst0,
1969 &env->active_fpu.fp_status)
1970 || float32_eq(fst0, fst1,
1971 &env->active_fpu.fp_status),
1972 float32_unordered(fsth1, fsth0,
1973 &env->active_fpu.fp_status)
1974 || float32_eq(fsth0, fsth1,
1975 &env->active_fpu.fp_status))
1976 FOP_COND_PS(lt, float32_lt(fst0, fst1,
1977 &env->active_fpu.fp_status),
1978 float32_lt(fsth0, fsth1,
1979 &env->active_fpu.fp_status))
1980 FOP_COND_PS(nge, float32_unordered(fst1, fst0,
1981 &env->active_fpu.fp_status)
1982 || float32_lt(fst0, fst1,
1983 &env->active_fpu.fp_status),
1984 float32_unordered(fsth1, fsth0,
1985 &env->active_fpu.fp_status)
1986 || float32_lt(fsth0, fsth1,
1987 &env->active_fpu.fp_status))
1988 FOP_COND_PS(le, float32_le(fst0, fst1,
1989 &env->active_fpu.fp_status),
1990 float32_le(fsth0, fsth1,
1991 &env->active_fpu.fp_status))
1992 FOP_COND_PS(ngt, float32_unordered(fst1, fst0,
1993 &env->active_fpu.fp_status)
1994 || float32_le(fst0, fst1,
1995 &env->active_fpu.fp_status),
1996 float32_unordered(fsth1, fsth0,
1997 &env->active_fpu.fp_status)
1998 || float32_le(fsth0, fsth1,
1999 &env->active_fpu.fp_status))
2000
2001 /* R6 compare operations */
2002 #define FOP_CONDN_D(op, cond) \
2003 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
2004 uint64_t fdt1) \
2005 { \
2006 uint64_t c; \
2007 c = cond; \
2008 update_fcr31(env, GETPC()); \
2009 if (c) { \
2010 return -1; \
2011 } else { \
2012 return 0; \
2013 } \
2014 }
2015
2016 /*
2017 * NOTE: the comma operator will make "cond" to eval to false,
2018 * but float64_unordered_quiet() is still called.
2019 */
2020 FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0,
2021 &env->active_fpu.fp_status), 0))
2022 FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0,
2023 &env->active_fpu.fp_status)))
2024 FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1,
2025 &env->active_fpu.fp_status)))
2026 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0,
2027 &env->active_fpu.fp_status)
2028 || float64_eq_quiet(fdt0, fdt1,
2029 &env->active_fpu.fp_status)))
2030 FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1,
2031 &env->active_fpu.fp_status)))
2032 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0,
2033 &env->active_fpu.fp_status)
2034 || float64_lt_quiet(fdt0, fdt1,
2035 &env->active_fpu.fp_status)))
2036 FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1,
2037 &env->active_fpu.fp_status)))
2038 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0,
2039 &env->active_fpu.fp_status)
2040 || float64_le_quiet(fdt0, fdt1,
2041 &env->active_fpu.fp_status)))
2042 /*
2043 * NOTE: the comma operator will make "cond" to eval to false,
2044 * but float64_unordered() is still called.\
2045 */
2046 FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0,
2047 &env->active_fpu.fp_status), 0))
2048 FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0,
2049 &env->active_fpu.fp_status)))
2050 FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1,
2051 &env->active_fpu.fp_status)))
2052 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0,
2053 &env->active_fpu.fp_status)
2054 || float64_eq(fdt0, fdt1,
2055 &env->active_fpu.fp_status)))
2056 FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1,
2057 &env->active_fpu.fp_status)))
2058 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0,
2059 &env->active_fpu.fp_status)
2060 || float64_lt(fdt0, fdt1,
2061 &env->active_fpu.fp_status)))
2062 FOP_CONDN_D(sle, (float64_le(fdt0, fdt1,
2063 &env->active_fpu.fp_status)))
2064 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0,
2065 &env->active_fpu.fp_status)
2066 || float64_le(fdt0, fdt1,
2067 &env->active_fpu.fp_status)))
2068 FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0,
2069 &env->active_fpu.fp_status)
2070 || float64_le_quiet(fdt0, fdt1,
2071 &env->active_fpu.fp_status)))
2072 FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0,
2073 &env->active_fpu.fp_status)
2074 || float64_lt_quiet(fdt1, fdt0,
2075 &env->active_fpu.fp_status)
2076 || float64_lt_quiet(fdt0, fdt1,
2077 &env->active_fpu.fp_status)))
2078 FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0,
2079 &env->active_fpu.fp_status)
2080 || float64_lt_quiet(fdt0, fdt1,
2081 &env->active_fpu.fp_status)))
2082 FOP_CONDN_D(sor, (float64_le(fdt1, fdt0,
2083 &env->active_fpu.fp_status)
2084 || float64_le(fdt0, fdt1,
2085 &env->active_fpu.fp_status)))
2086 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0,
2087 &env->active_fpu.fp_status)
2088 || float64_lt(fdt1, fdt0,
2089 &env->active_fpu.fp_status)
2090 || float64_lt(fdt0, fdt1,
2091 &env->active_fpu.fp_status)))
2092 FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0,
2093 &env->active_fpu.fp_status)
2094 || float64_lt(fdt0, fdt1,
2095 &env->active_fpu.fp_status)))
2096
2097 #define FOP_CONDN_S(op, cond) \
2098 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
2099 uint32_t fst1) \
2100 { \
2101 uint64_t c; \
2102 c = cond; \
2103 update_fcr31(env, GETPC()); \
2104 if (c) { \
2105 return -1; \
2106 } else { \
2107 return 0; \
2108 } \
2109 }
2110
2111 /*
2112 * NOTE: the comma operator will make "cond" to eval to false,
2113 * but float32_unordered_quiet() is still called.
2114 */
2115 FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0,
2116 &env->active_fpu.fp_status), 0))
2117 FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0,
2118 &env->active_fpu.fp_status)))
2119 FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1,
2120 &env->active_fpu.fp_status)))
2121 FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0,
2122 &env->active_fpu.fp_status)
2123 || float32_eq_quiet(fst0, fst1,
2124 &env->active_fpu.fp_status)))
2125 FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1,
2126 &env->active_fpu.fp_status)))
2127 FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0,
2128 &env->active_fpu.fp_status)
2129 || float32_lt_quiet(fst0, fst1,
2130 &env->active_fpu.fp_status)))
2131 FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1,
2132 &env->active_fpu.fp_status)))
2133 FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0,
2134 &env->active_fpu.fp_status)
2135 || float32_le_quiet(fst0, fst1,
2136 &env->active_fpu.fp_status)))
2137 /*
2138 * NOTE: the comma operator will make "cond" to eval to false,
2139 * but float32_unordered() is still called.
2140 */
2141 FOP_CONDN_S(saf, (float32_unordered(fst1, fst0,
2142 &env->active_fpu.fp_status), 0))
2143 FOP_CONDN_S(sun, (float32_unordered(fst1, fst0,
2144 &env->active_fpu.fp_status)))
2145 FOP_CONDN_S(seq, (float32_eq(fst0, fst1,
2146 &env->active_fpu.fp_status)))
2147 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0,
2148 &env->active_fpu.fp_status)
2149 || float32_eq(fst0, fst1,
2150 &env->active_fpu.fp_status)))
2151 FOP_CONDN_S(slt, (float32_lt(fst0, fst1,
2152 &env->active_fpu.fp_status)))
2153 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0,
2154 &env->active_fpu.fp_status)
2155 || float32_lt(fst0, fst1,
2156 &env->active_fpu.fp_status)))
2157 FOP_CONDN_S(sle, (float32_le(fst0, fst1,
2158 &env->active_fpu.fp_status)))
2159 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0,
2160 &env->active_fpu.fp_status)
2161 || float32_le(fst0, fst1,
2162 &env->active_fpu.fp_status)))
2163 FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0,
2164 &env->active_fpu.fp_status)
2165 || float32_le_quiet(fst0, fst1,
2166 &env->active_fpu.fp_status)))
2167 FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0,
2168 &env->active_fpu.fp_status)
2169 || float32_lt_quiet(fst1, fst0,
2170 &env->active_fpu.fp_status)
2171 || float32_lt_quiet(fst0, fst1,
2172 &env->active_fpu.fp_status)))
2173 FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0,
2174 &env->active_fpu.fp_status)
2175 || float32_lt_quiet(fst0, fst1,
2176 &env->active_fpu.fp_status)))
2177 FOP_CONDN_S(sor, (float32_le(fst1, fst0,
2178 &env->active_fpu.fp_status)
2179 || float32_le(fst0, fst1,
2180 &env->active_fpu.fp_status)))
2181 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0,
2182 &env->active_fpu.fp_status)
2183 || float32_lt(fst1, fst0,
2184 &env->active_fpu.fp_status)
2185 || float32_lt(fst0, fst1,
2186 &env->active_fpu.fp_status)))
2187 FOP_CONDN_S(sne, (float32_lt(fst1, fst0,
2188 &env->active_fpu.fp_status)
2189 || float32_lt(fst0, fst1,
2190 &env->active_fpu.fp_status)))
AR7 emulation for QEMU