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s390x/kvm: Fix coding style in handle_sigp()
[qemu/ar7.git] / target-ppc / translate.c
blob66c777174c3bbef6d60f08568ba626945e520f1d
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55 static TCGv cpu_gpr[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh[32];
58 #endif
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i32 cpu_crf[8];
62 static TCGv cpu_nip;
63 static TCGv cpu_msr;
64 static TCGv cpu_ctr;
65 static TCGv cpu_lr;
66 #if defined(TARGET_PPC64)
67 static TCGv cpu_cfar;
68 #endif
69 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
70 static TCGv cpu_reserve;
71 static TCGv cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 #include "exec/gen-icount.h"
75
76 void ppc_translate_init(void)
77 {
78 int i;
79 char* p;
80 size_t cpu_reg_names_size;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111 #endif
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123 #else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126 #endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134 #else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137 #endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUPPCState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUPPCState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUPPCState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUPPCState, lr), "lr");
153
154 #if defined(TARGET_PPC64)
155 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, cfar), "cfar");
157 #endif
158
159 cpu_xer = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, xer), "xer");
161 cpu_so = tcg_global_mem_new(TCG_AREG0,
162 offsetof(CPUPPCState, so), "SO");
163 cpu_ov = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, ov), "OV");
165 cpu_ca = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, ca), "CA");
167
168 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, reserve_addr),
170 "reserve_addr");
171
172 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, fpscr), "fpscr");
174
175 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
176 offsetof(CPUPPCState, access_type), "access_type");
177
178 done_init = 1;
179 }
180
181 /* internal defines */
182 typedef struct DisasContext {
183 struct TranslationBlock *tb;
184 target_ulong nip;
185 uint32_t opcode;
186 uint32_t exception;
187 /* Routine used to access memory */
188 int mem_idx;
189 int access_type;
190 /* Translation flags */
191 int le_mode;
192 #if defined(TARGET_PPC64)
193 int sf_mode;
194 int has_cfar;
195 #endif
196 int fpu_enabled;
197 int altivec_enabled;
198 int spe_enabled;
199 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
200 int singlestep_enabled;
201 uint64_t insns_flags;
202 uint64_t insns_flags2;
203 } DisasContext;
204
205 /* True when active word size < size of target_long. */
206 #ifdef TARGET_PPC64
207 # define NARROW_MODE(C) (!(C)->sf_mode)
208 #else
209 # define NARROW_MODE(C) 0
210 #endif
211
212 struct opc_handler_t {
213 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
214 uint32_t inval1;
215 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
216 uint32_t inval2;
217 /* instruction type */
218 uint64_t type;
219 /* extended instruction type */
220 uint64_t type2;
221 /* handler */
222 void (*handler)(DisasContext *ctx);
223 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
224 const char *oname;
225 #endif
226 #if defined(DO_PPC_STATISTICS)
227 uint64_t count;
228 #endif
229 };
230
231 static inline void gen_reset_fpstatus(void)
232 {
233 gen_helper_reset_fpstatus(cpu_env);
234 }
235
236 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
237 {
238 TCGv_i32 t0 = tcg_temp_new_i32();
239
240 if (set_fprf != 0) {
241 /* This case might be optimized later */
242 tcg_gen_movi_i32(t0, 1);
243 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
244 if (unlikely(set_rc)) {
245 tcg_gen_mov_i32(cpu_crf[1], t0);
246 }
247 gen_helper_float_check_status(cpu_env);
248 } else if (unlikely(set_rc)) {
249 /* We always need to compute fpcc */
250 tcg_gen_movi_i32(t0, 0);
251 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
252 tcg_gen_mov_i32(cpu_crf[1], t0);
253 }
254
255 tcg_temp_free_i32(t0);
256 }
257
258 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
259 {
260 if (ctx->access_type != access_type) {
261 tcg_gen_movi_i32(cpu_access_type, access_type);
262 ctx->access_type = access_type;
263 }
264 }
265
266 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
267 {
268 if (NARROW_MODE(ctx)) {
269 nip = (uint32_t)nip;
270 }
271 tcg_gen_movi_tl(cpu_nip, nip);
272 }
273
274 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
275 {
276 TCGv_i32 t0, t1;
277 if (ctx->exception == POWERPC_EXCP_NONE) {
278 gen_update_nip(ctx, ctx->nip);
279 }
280 t0 = tcg_const_i32(excp);
281 t1 = tcg_const_i32(error);
282 gen_helper_raise_exception_err(cpu_env, t0, t1);
283 tcg_temp_free_i32(t0);
284 tcg_temp_free_i32(t1);
285 ctx->exception = (excp);
286 }
287
288 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
289 {
290 TCGv_i32 t0;
291 if (ctx->exception == POWERPC_EXCP_NONE) {
292 gen_update_nip(ctx, ctx->nip);
293 }
294 t0 = tcg_const_i32(excp);
295 gen_helper_raise_exception(cpu_env, t0);
296 tcg_temp_free_i32(t0);
297 ctx->exception = (excp);
298 }
299
300 static inline void gen_debug_exception(DisasContext *ctx)
301 {
302 TCGv_i32 t0;
303
304 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
305 (ctx->exception != POWERPC_EXCP_SYNC)) {
306 gen_update_nip(ctx, ctx->nip);
307 }
308 t0 = tcg_const_i32(EXCP_DEBUG);
309 gen_helper_raise_exception(cpu_env, t0);
310 tcg_temp_free_i32(t0);
311 }
312
313 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
314 {
315 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
316 }
317
318 /* Stop translation */
319 static inline void gen_stop_exception(DisasContext *ctx)
320 {
321 gen_update_nip(ctx, ctx->nip);
322 ctx->exception = POWERPC_EXCP_STOP;
323 }
324
325 /* No need to update nip here, as execution flow will change */
326 static inline void gen_sync_exception(DisasContext *ctx)
327 {
328 ctx->exception = POWERPC_EXCP_SYNC;
329 }
330
331 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
332 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
333
334 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
335 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
336
337 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
338 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
339
340 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
341 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
342
343 typedef struct opcode_t {
344 unsigned char opc1, opc2, opc3;
345 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
346 unsigned char pad[5];
347 #else
348 unsigned char pad[1];
349 #endif
350 opc_handler_t handler;
351 const char *oname;
352 } opcode_t;
353
354 /*****************************************************************************/
355 /*** Instruction decoding ***/
356 #define EXTRACT_HELPER(name, shift, nb) \
357 static inline uint32_t name(uint32_t opcode) \
358 { \
359 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
360 }
361
362 #define EXTRACT_SHELPER(name, shift, nb) \
363 static inline int32_t name(uint32_t opcode) \
364 { \
365 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
366 }
367
368 /* Opcode part 1 */
369 EXTRACT_HELPER(opc1, 26, 6);
370 /* Opcode part 2 */
371 EXTRACT_HELPER(opc2, 1, 5);
372 /* Opcode part 3 */
373 EXTRACT_HELPER(opc3, 6, 5);
374 /* Update Cr0 flags */
375 EXTRACT_HELPER(Rc, 0, 1);
376 /* Destination */
377 EXTRACT_HELPER(rD, 21, 5);
378 /* Source */
379 EXTRACT_HELPER(rS, 21, 5);
380 /* First operand */
381 EXTRACT_HELPER(rA, 16, 5);
382 /* Second operand */
383 EXTRACT_HELPER(rB, 11, 5);
384 /* Third operand */
385 EXTRACT_HELPER(rC, 6, 5);
386 /*** Get CRn ***/
387 EXTRACT_HELPER(crfD, 23, 3);
388 EXTRACT_HELPER(crfS, 18, 3);
389 EXTRACT_HELPER(crbD, 21, 5);
390 EXTRACT_HELPER(crbA, 16, 5);
391 EXTRACT_HELPER(crbB, 11, 5);
392 /* SPR / TBL */
393 EXTRACT_HELPER(_SPR, 11, 10);
394 static inline uint32_t SPR(uint32_t opcode)
395 {
396 uint32_t sprn = _SPR(opcode);
397
398 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
399 }
400 /*** Get constants ***/
401 EXTRACT_HELPER(IMM, 12, 8);
402 /* 16 bits signed immediate value */
403 EXTRACT_SHELPER(SIMM, 0, 16);
404 /* 16 bits unsigned immediate value */
405 EXTRACT_HELPER(UIMM, 0, 16);
406 /* 5 bits signed immediate value */
407 EXTRACT_HELPER(SIMM5, 16, 5);
408 /* 5 bits signed immediate value */
409 EXTRACT_HELPER(UIMM5, 16, 5);
410 /* Bit count */
411 EXTRACT_HELPER(NB, 11, 5);
412 /* Shift count */
413 EXTRACT_HELPER(SH, 11, 5);
414 /* Vector shift count */
415 EXTRACT_HELPER(VSH, 6, 4);
416 /* Mask start */
417 EXTRACT_HELPER(MB, 6, 5);
418 /* Mask end */
419 EXTRACT_HELPER(ME, 1, 5);
420 /* Trap operand */
421 EXTRACT_HELPER(TO, 21, 5);
422
423 EXTRACT_HELPER(CRM, 12, 8);
424 EXTRACT_HELPER(SR, 16, 4);
425
426 /* mtfsf/mtfsfi */
427 EXTRACT_HELPER(FPBF, 23, 3);
428 EXTRACT_HELPER(FPIMM, 12, 4);
429 EXTRACT_HELPER(FPL, 25, 1);
430 EXTRACT_HELPER(FPFLM, 17, 8);
431 EXTRACT_HELPER(FPW, 16, 1);
432
433 /*** Jump target decoding ***/
434 /* Displacement */
435 EXTRACT_SHELPER(d, 0, 16);
436 /* Immediate address */
437 static inline target_ulong LI(uint32_t opcode)
438 {
439 return (opcode >> 0) & 0x03FFFFFC;
440 }
441
442 static inline uint32_t BD(uint32_t opcode)
443 {
444 return (opcode >> 0) & 0xFFFC;
445 }
446
447 EXTRACT_HELPER(BO, 21, 5);
448 EXTRACT_HELPER(BI, 16, 5);
449 /* Absolute/relative address */
450 EXTRACT_HELPER(AA, 1, 1);
451 /* Link */
452 EXTRACT_HELPER(LK, 0, 1);
453
454 /* Create a mask between <start> and <end> bits */
455 static inline target_ulong MASK(uint32_t start, uint32_t end)
456 {
457 target_ulong ret;
458
459 #if defined(TARGET_PPC64)
460 if (likely(start == 0)) {
461 ret = UINT64_MAX << (63 - end);
462 } else if (likely(end == 63)) {
463 ret = UINT64_MAX >> start;
464 }
465 #else
466 if (likely(start == 0)) {
467 ret = UINT32_MAX << (31 - end);
468 } else if (likely(end == 31)) {
469 ret = UINT32_MAX >> start;
470 }
471 #endif
472 else {
473 ret = (((target_ulong)(-1ULL)) >> (start)) ^
474 (((target_ulong)(-1ULL) >> (end)) >> 1);
475 if (unlikely(start > end))
476 return ~ret;
477 }
478
479 return ret;
480 }
481
482 /*****************************************************************************/
483 /* PowerPC instructions table */
484
485 #if defined(DO_PPC_STATISTICS)
486 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
487 { \
488 .opc1 = op1, \
489 .opc2 = op2, \
490 .opc3 = op3, \
491 .pad = { 0, }, \
492 .handler = { \
493 .inval1 = invl, \
494 .type = _typ, \
495 .type2 = _typ2, \
496 .handler = &gen_##name, \
497 .oname = stringify(name), \
498 }, \
499 .oname = stringify(name), \
500 }
501 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
502 { \
503 .opc1 = op1, \
504 .opc2 = op2, \
505 .opc3 = op3, \
506 .pad = { 0, }, \
507 .handler = { \
508 .inval1 = invl1, \
509 .inval2 = invl2, \
510 .type = _typ, \
511 .type2 = _typ2, \
512 .handler = &gen_##name, \
513 .oname = stringify(name), \
514 }, \
515 .oname = stringify(name), \
516 }
517 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
518 { \
519 .opc1 = op1, \
520 .opc2 = op2, \
521 .opc3 = op3, \
522 .pad = { 0, }, \
523 .handler = { \
524 .inval1 = invl, \
525 .type = _typ, \
526 .type2 = _typ2, \
527 .handler = &gen_##name, \
528 .oname = onam, \
529 }, \
530 .oname = onam, \
531 }
532 #else
533 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
534 { \
535 .opc1 = op1, \
536 .opc2 = op2, \
537 .opc3 = op3, \
538 .pad = { 0, }, \
539 .handler = { \
540 .inval1 = invl, \
541 .type = _typ, \
542 .type2 = _typ2, \
543 .handler = &gen_##name, \
544 }, \
545 .oname = stringify(name), \
546 }
547 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
548 { \
549 .opc1 = op1, \
550 .opc2 = op2, \
551 .opc3 = op3, \
552 .pad = { 0, }, \
553 .handler = { \
554 .inval1 = invl1, \
555 .inval2 = invl2, \
556 .type = _typ, \
557 .type2 = _typ2, \
558 .handler = &gen_##name, \
559 }, \
560 .oname = stringify(name), \
561 }
562 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
563 { \
564 .opc1 = op1, \
565 .opc2 = op2, \
566 .opc3 = op3, \
567 .pad = { 0, }, \
568 .handler = { \
569 .inval1 = invl, \
570 .type = _typ, \
571 .type2 = _typ2, \
572 .handler = &gen_##name, \
573 }, \
574 .oname = onam, \
575 }
576 #endif
577
578 /* SPR load/store helpers */
579 static inline void gen_load_spr(TCGv t, int reg)
580 {
581 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
582 }
583
584 static inline void gen_store_spr(int reg, TCGv t)
585 {
586 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
587 }
588
589 /* Invalid instruction */
590 static void gen_invalid(DisasContext *ctx)
591 {
592 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
593 }
594
595 static opc_handler_t invalid_handler = {
596 .inval1 = 0xFFFFFFFF,
597 .inval2 = 0xFFFFFFFF,
598 .type = PPC_NONE,
599 .type2 = PPC_NONE,
600 .handler = gen_invalid,
601 };
602
603 /*** Integer comparison ***/
604
605 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
606 {
607 TCGv t0 = tcg_temp_new();
608 TCGv_i32 t1 = tcg_temp_new_i32();
609
610 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
611
612 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
613 tcg_gen_trunc_tl_i32(t1, t0);
614 tcg_gen_shli_i32(t1, t1, CRF_LT);
615 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
616
617 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
618 tcg_gen_trunc_tl_i32(t1, t0);
619 tcg_gen_shli_i32(t1, t1, CRF_GT);
620 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
621
622 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
623 tcg_gen_trunc_tl_i32(t1, t0);
624 tcg_gen_shli_i32(t1, t1, CRF_EQ);
625 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
626
627 tcg_temp_free(t0);
628 tcg_temp_free_i32(t1);
629 }
630
631 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
632 {
633 TCGv t0 = tcg_const_tl(arg1);
634 gen_op_cmp(arg0, t0, s, crf);
635 tcg_temp_free(t0);
636 }
637
638 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
639 {
640 TCGv t0, t1;
641 t0 = tcg_temp_new();
642 t1 = tcg_temp_new();
643 if (s) {
644 tcg_gen_ext32s_tl(t0, arg0);
645 tcg_gen_ext32s_tl(t1, arg1);
646 } else {
647 tcg_gen_ext32u_tl(t0, arg0);
648 tcg_gen_ext32u_tl(t1, arg1);
649 }
650 gen_op_cmp(t0, t1, s, crf);
651 tcg_temp_free(t1);
652 tcg_temp_free(t0);
653 }
654
655 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
656 {
657 TCGv t0 = tcg_const_tl(arg1);
658 gen_op_cmp32(arg0, t0, s, crf);
659 tcg_temp_free(t0);
660 }
661
662 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
663 {
664 if (NARROW_MODE(ctx)) {
665 gen_op_cmpi32(reg, 0, 1, 0);
666 } else {
667 gen_op_cmpi(reg, 0, 1, 0);
668 }
669 }
670
671 /* cmp */
672 static void gen_cmp(DisasContext *ctx)
673 {
674 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
675 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
676 1, crfD(ctx->opcode));
677 } else {
678 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
679 1, crfD(ctx->opcode));
680 }
681 }
682
683 /* cmpi */
684 static void gen_cmpi(DisasContext *ctx)
685 {
686 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
687 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
688 1, crfD(ctx->opcode));
689 } else {
690 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
691 1, crfD(ctx->opcode));
692 }
693 }
694
695 /* cmpl */
696 static void gen_cmpl(DisasContext *ctx)
697 {
698 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
699 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
700 0, crfD(ctx->opcode));
701 } else {
702 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
703 0, crfD(ctx->opcode));
704 }
705 }
706
707 /* cmpli */
708 static void gen_cmpli(DisasContext *ctx)
709 {
710 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
711 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
712 0, crfD(ctx->opcode));
713 } else {
714 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
715 0, crfD(ctx->opcode));
716 }
717 }
718
719 /* isel (PowerPC 2.03 specification) */
720 static void gen_isel(DisasContext *ctx)
721 {
722 int l1, l2;
723 uint32_t bi = rC(ctx->opcode);
724 uint32_t mask;
725 TCGv_i32 t0;
726
727 l1 = gen_new_label();
728 l2 = gen_new_label();
729
730 mask = 1 << (3 - (bi & 0x03));
731 t0 = tcg_temp_new_i32();
732 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
733 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
734 if (rA(ctx->opcode) == 0)
735 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
736 else
737 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
738 tcg_gen_br(l2);
739 gen_set_label(l1);
740 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
741 gen_set_label(l2);
742 tcg_temp_free_i32(t0);
743 }
744
745 /* cmpb: PowerPC 2.05 specification */
746 static void gen_cmpb(DisasContext *ctx)
747 {
748 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
749 cpu_gpr[rB(ctx->opcode)]);
750 }
751
752 /*** Integer arithmetic ***/
753
754 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
755 TCGv arg1, TCGv arg2, int sub)
756 {
757 TCGv t0 = tcg_temp_new();
758
759 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
760 tcg_gen_xor_tl(t0, arg1, arg2);
761 if (sub) {
762 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
763 } else {
764 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
765 }
766 tcg_temp_free(t0);
767 if (NARROW_MODE(ctx)) {
768 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
769 }
770 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
771 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
772 }
773
774 /* Common add function */
775 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
776 TCGv arg2, bool add_ca, bool compute_ca,
777 bool compute_ov, bool compute_rc0)
778 {
779 TCGv t0 = ret;
780
781 if (compute_ca || compute_ov) {
782 t0 = tcg_temp_new();
783 }
784
785 if (compute_ca) {
786 if (NARROW_MODE(ctx)) {
787 /* Caution: a non-obvious corner case of the spec is that we
788 must produce the *entire* 64-bit addition, but produce the
789 carry into bit 32. */
790 TCGv t1 = tcg_temp_new();
791 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
792 tcg_gen_add_tl(t0, arg1, arg2);
793 if (add_ca) {
794 tcg_gen_add_tl(t0, t0, cpu_ca);
795 }
796 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
797 tcg_temp_free(t1);
798 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
799 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
800 } else {
801 TCGv zero = tcg_const_tl(0);
802 if (add_ca) {
803 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
804 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
805 } else {
806 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
807 }
808 tcg_temp_free(zero);
809 }
810 } else {
811 tcg_gen_add_tl(t0, arg1, arg2);
812 if (add_ca) {
813 tcg_gen_add_tl(t0, t0, cpu_ca);
814 }
815 }
816
817 if (compute_ov) {
818 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
819 }
820 if (unlikely(compute_rc0)) {
821 gen_set_Rc0(ctx, t0);
822 }
823
824 if (!TCGV_EQUAL(t0, ret)) {
825 tcg_gen_mov_tl(ret, t0);
826 tcg_temp_free(t0);
827 }
828 }
829 /* Add functions with two operands */
830 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
831 static void glue(gen_, name)(DisasContext *ctx) \
832 { \
833 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
834 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
835 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
836 }
837 /* Add functions with one operand and one immediate */
838 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
839 add_ca, compute_ca, compute_ov) \
840 static void glue(gen_, name)(DisasContext *ctx) \
841 { \
842 TCGv t0 = tcg_const_tl(const_val); \
843 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
844 cpu_gpr[rA(ctx->opcode)], t0, \
845 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
846 tcg_temp_free(t0); \
847 }
848
849 /* add add. addo addo. */
850 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
851 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
852 /* addc addc. addco addco. */
853 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
854 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
855 /* adde adde. addeo addeo. */
856 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
857 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
858 /* addme addme. addmeo addmeo. */
859 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
860 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
861 /* addze addze. addzeo addzeo.*/
862 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
863 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
864 /* addi */
865 static void gen_addi(DisasContext *ctx)
866 {
867 target_long simm = SIMM(ctx->opcode);
868
869 if (rA(ctx->opcode) == 0) {
870 /* li case */
871 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
872 } else {
873 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
874 cpu_gpr[rA(ctx->opcode)], simm);
875 }
876 }
877 /* addic addic.*/
878 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
879 {
880 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
881 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
882 c, 0, 1, 0, compute_rc0);
883 tcg_temp_free(c);
884 }
885
886 static void gen_addic(DisasContext *ctx)
887 {
888 gen_op_addic(ctx, 0);
889 }
890
891 static void gen_addic_(DisasContext *ctx)
892 {
893 gen_op_addic(ctx, 1);
894 }
895
896 /* addis */
897 static void gen_addis(DisasContext *ctx)
898 {
899 target_long simm = SIMM(ctx->opcode);
900
901 if (rA(ctx->opcode) == 0) {
902 /* lis case */
903 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
904 } else {
905 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
906 cpu_gpr[rA(ctx->opcode)], simm << 16);
907 }
908 }
909
910 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
911 TCGv arg2, int sign, int compute_ov)
912 {
913 int l1 = gen_new_label();
914 int l2 = gen_new_label();
915 TCGv_i32 t0 = tcg_temp_local_new_i32();
916 TCGv_i32 t1 = tcg_temp_local_new_i32();
917
918 tcg_gen_trunc_tl_i32(t0, arg1);
919 tcg_gen_trunc_tl_i32(t1, arg2);
920 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
921 if (sign) {
922 int l3 = gen_new_label();
923 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
924 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
925 gen_set_label(l3);
926 tcg_gen_div_i32(t0, t0, t1);
927 } else {
928 tcg_gen_divu_i32(t0, t0, t1);
929 }
930 if (compute_ov) {
931 tcg_gen_movi_tl(cpu_ov, 0);
932 }
933 tcg_gen_br(l2);
934 gen_set_label(l1);
935 if (sign) {
936 tcg_gen_sari_i32(t0, t0, 31);
937 } else {
938 tcg_gen_movi_i32(t0, 0);
939 }
940 if (compute_ov) {
941 tcg_gen_movi_tl(cpu_ov, 1);
942 tcg_gen_movi_tl(cpu_so, 1);
943 }
944 gen_set_label(l2);
945 tcg_gen_extu_i32_tl(ret, t0);
946 tcg_temp_free_i32(t0);
947 tcg_temp_free_i32(t1);
948 if (unlikely(Rc(ctx->opcode) != 0))
949 gen_set_Rc0(ctx, ret);
950 }
951 /* Div functions */
952 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
953 static void glue(gen_, name)(DisasContext *ctx) \
954 { \
955 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
956 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
957 sign, compute_ov); \
958 }
959 /* divwu divwu. divwuo divwuo. */
960 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
961 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
962 /* divw divw. divwo divwo. */
963 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
964 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
965 #if defined(TARGET_PPC64)
966 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
967 TCGv arg2, int sign, int compute_ov)
968 {
969 int l1 = gen_new_label();
970 int l2 = gen_new_label();
971
972 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
973 if (sign) {
974 int l3 = gen_new_label();
975 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
976 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
977 gen_set_label(l3);
978 tcg_gen_div_i64(ret, arg1, arg2);
979 } else {
980 tcg_gen_divu_i64(ret, arg1, arg2);
981 }
982 if (compute_ov) {
983 tcg_gen_movi_tl(cpu_ov, 0);
984 }
985 tcg_gen_br(l2);
986 gen_set_label(l1);
987 if (sign) {
988 tcg_gen_sari_i64(ret, arg1, 63);
989 } else {
990 tcg_gen_movi_i64(ret, 0);
991 }
992 if (compute_ov) {
993 tcg_gen_movi_tl(cpu_ov, 1);
994 tcg_gen_movi_tl(cpu_so, 1);
995 }
996 gen_set_label(l2);
997 if (unlikely(Rc(ctx->opcode) != 0))
998 gen_set_Rc0(ctx, ret);
999 }
1000 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1001 static void glue(gen_, name)(DisasContext *ctx) \
1002 { \
1003 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1004 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1005 sign, compute_ov); \
1006 }
1007 /* divwu divwu. divwuo divwuo. */
1008 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1009 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1010 /* divw divw. divwo divwo. */
1011 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1012 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1013 #endif
1014
1015 /* mulhw mulhw. */
1016 static void gen_mulhw(DisasContext *ctx)
1017 {
1018 TCGv_i32 t0 = tcg_temp_new_i32();
1019 TCGv_i32 t1 = tcg_temp_new_i32();
1020
1021 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1022 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1023 tcg_gen_muls2_i32(t0, t1, t0, t1);
1024 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1025 tcg_temp_free_i32(t0);
1026 tcg_temp_free_i32(t1);
1027 if (unlikely(Rc(ctx->opcode) != 0))
1028 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1029 }
1030
1031 /* mulhwu mulhwu. */
1032 static void gen_mulhwu(DisasContext *ctx)
1033 {
1034 TCGv_i32 t0 = tcg_temp_new_i32();
1035 TCGv_i32 t1 = tcg_temp_new_i32();
1036
1037 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1038 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1039 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1040 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1041 tcg_temp_free_i32(t0);
1042 tcg_temp_free_i32(t1);
1043 if (unlikely(Rc(ctx->opcode) != 0))
1044 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1045 }
1046
1047 /* mullw mullw. */
1048 static void gen_mullw(DisasContext *ctx)
1049 {
1050 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1051 cpu_gpr[rB(ctx->opcode)]);
1052 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1053 if (unlikely(Rc(ctx->opcode) != 0))
1054 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1055 }
1056
1057 /* mullwo mullwo. */
1058 static void gen_mullwo(DisasContext *ctx)
1059 {
1060 TCGv_i32 t0 = tcg_temp_new_i32();
1061 TCGv_i32 t1 = tcg_temp_new_i32();
1062
1063 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1064 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1065 tcg_gen_muls2_i32(t0, t1, t0, t1);
1066 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1067
1068 tcg_gen_sari_i32(t0, t0, 31);
1069 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1070 tcg_gen_extu_i32_tl(cpu_ov, t0);
1071 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1072
1073 tcg_temp_free_i32(t0);
1074 tcg_temp_free_i32(t1);
1075 if (unlikely(Rc(ctx->opcode) != 0))
1076 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1077 }
1078
1079 /* mulli */
1080 static void gen_mulli(DisasContext *ctx)
1081 {
1082 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1083 SIMM(ctx->opcode));
1084 }
1085
1086 #if defined(TARGET_PPC64)
1087 /* mulhd mulhd. */
1088 static void gen_mulhd(DisasContext *ctx)
1089 {
1090 TCGv lo = tcg_temp_new();
1091 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1092 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1093 tcg_temp_free(lo);
1094 if (unlikely(Rc(ctx->opcode) != 0)) {
1095 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1096 }
1097 }
1098
1099 /* mulhdu mulhdu. */
1100 static void gen_mulhdu(DisasContext *ctx)
1101 {
1102 TCGv lo = tcg_temp_new();
1103 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1104 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1105 tcg_temp_free(lo);
1106 if (unlikely(Rc(ctx->opcode) != 0)) {
1107 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1108 }
1109 }
1110
1111 /* mulld mulld. */
1112 static void gen_mulld(DisasContext *ctx)
1113 {
1114 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1115 cpu_gpr[rB(ctx->opcode)]);
1116 if (unlikely(Rc(ctx->opcode) != 0))
1117 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1118 }
1119
1120 /* mulldo mulldo. */
1121 static void gen_mulldo(DisasContext *ctx)
1122 {
1123 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1124 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1125 if (unlikely(Rc(ctx->opcode) != 0)) {
1126 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1127 }
1128 }
1129 #endif
1130
1131 /* Common subf function */
1132 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1133 TCGv arg2, bool add_ca, bool compute_ca,
1134 bool compute_ov, bool compute_rc0)
1135 {
1136 TCGv t0 = ret;
1137
1138 if (compute_ca || compute_ov) {
1139 t0 = tcg_temp_new();
1140 }
1141
1142 if (compute_ca) {
1143 /* dest = ~arg1 + arg2 [+ ca]. */
1144 if (NARROW_MODE(ctx)) {
1145 /* Caution: a non-obvious corner case of the spec is that we
1146 must produce the *entire* 64-bit addition, but produce the
1147 carry into bit 32. */
1148 TCGv inv1 = tcg_temp_new();
1149 TCGv t1 = tcg_temp_new();
1150 tcg_gen_not_tl(inv1, arg1);
1151 if (add_ca) {
1152 tcg_gen_add_tl(t0, arg2, cpu_ca);
1153 } else {
1154 tcg_gen_addi_tl(t0, arg2, 1);
1155 }
1156 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1157 tcg_gen_add_tl(t0, t0, inv1);
1158 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1159 tcg_temp_free(t1);
1160 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1161 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1162 } else if (add_ca) {
1163 TCGv zero, inv1 = tcg_temp_new();
1164 tcg_gen_not_tl(inv1, arg1);
1165 zero = tcg_const_tl(0);
1166 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1167 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1168 tcg_temp_free(zero);
1169 tcg_temp_free(inv1);
1170 } else {
1171 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1172 tcg_gen_sub_tl(t0, arg2, arg1);
1173 }
1174 } else if (add_ca) {
1175 /* Since we're ignoring carry-out, we can simplify the
1176 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1177 tcg_gen_sub_tl(t0, arg2, arg1);
1178 tcg_gen_add_tl(t0, t0, cpu_ca);
1179 tcg_gen_subi_tl(t0, t0, 1);
1180 } else {
1181 tcg_gen_sub_tl(t0, arg2, arg1);
1182 }
1183
1184 if (compute_ov) {
1185 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1186 }
1187 if (unlikely(compute_rc0)) {
1188 gen_set_Rc0(ctx, t0);
1189 }
1190
1191 if (!TCGV_EQUAL(t0, ret)) {
1192 tcg_gen_mov_tl(ret, t0);
1193 tcg_temp_free(t0);
1194 }
1195 }
1196 /* Sub functions with Two operands functions */
1197 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1198 static void glue(gen_, name)(DisasContext *ctx) \
1199 { \
1200 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1201 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1202 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1203 }
1204 /* Sub functions with one operand and one immediate */
1205 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1206 add_ca, compute_ca, compute_ov) \
1207 static void glue(gen_, name)(DisasContext *ctx) \
1208 { \
1209 TCGv t0 = tcg_const_tl(const_val); \
1210 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1211 cpu_gpr[rA(ctx->opcode)], t0, \
1212 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1213 tcg_temp_free(t0); \
1214 }
1215 /* subf subf. subfo subfo. */
1216 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1217 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1218 /* subfc subfc. subfco subfco. */
1219 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1220 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1221 /* subfe subfe. subfeo subfo. */
1222 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1223 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1224 /* subfme subfme. subfmeo subfmeo. */
1225 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1226 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1227 /* subfze subfze. subfzeo subfzeo.*/
1228 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1229 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1230
1231 /* subfic */
1232 static void gen_subfic(DisasContext *ctx)
1233 {
1234 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1235 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1236 c, 0, 1, 0, 0);
1237 tcg_temp_free(c);
1238 }
1239
1240 /* neg neg. nego nego. */
1241 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1242 {
1243 TCGv zero = tcg_const_tl(0);
1244 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1245 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1246 tcg_temp_free(zero);
1247 }
1248
1249 static void gen_neg(DisasContext *ctx)
1250 {
1251 gen_op_arith_neg(ctx, 0);
1252 }
1253
1254 static void gen_nego(DisasContext *ctx)
1255 {
1256 gen_op_arith_neg(ctx, 1);
1257 }
1258
1259 /*** Integer logical ***/
1260 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1261 static void glue(gen_, name)(DisasContext *ctx) \
1262 { \
1263 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1264 cpu_gpr[rB(ctx->opcode)]); \
1265 if (unlikely(Rc(ctx->opcode) != 0)) \
1266 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1267 }
1268
1269 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1270 static void glue(gen_, name)(DisasContext *ctx) \
1271 { \
1272 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1273 if (unlikely(Rc(ctx->opcode) != 0)) \
1274 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1275 }
1276
1277 /* and & and. */
1278 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1279 /* andc & andc. */
1280 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1281
1282 /* andi. */
1283 static void gen_andi_(DisasContext *ctx)
1284 {
1285 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1286 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1287 }
1288
1289 /* andis. */
1290 static void gen_andis_(DisasContext *ctx)
1291 {
1292 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1293 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1294 }
1295
1296 /* cntlzw */
1297 static void gen_cntlzw(DisasContext *ctx)
1298 {
1299 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1300 if (unlikely(Rc(ctx->opcode) != 0))
1301 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1302 }
1303 /* eqv & eqv. */
1304 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1305 /* extsb & extsb. */
1306 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1307 /* extsh & extsh. */
1308 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1309 /* nand & nand. */
1310 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1311 /* nor & nor. */
1312 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1313
1314 /* or & or. */
1315 static void gen_or(DisasContext *ctx)
1316 {
1317 int rs, ra, rb;
1318
1319 rs = rS(ctx->opcode);
1320 ra = rA(ctx->opcode);
1321 rb = rB(ctx->opcode);
1322 /* Optimisation for mr. ri case */
1323 if (rs != ra || rs != rb) {
1324 if (rs != rb)
1325 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1326 else
1327 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1328 if (unlikely(Rc(ctx->opcode) != 0))
1329 gen_set_Rc0(ctx, cpu_gpr[ra]);
1330 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1331 gen_set_Rc0(ctx, cpu_gpr[rs]);
1332 #if defined(TARGET_PPC64)
1333 } else {
1334 int prio = 0;
1335
1336 switch (rs) {
1337 case 1:
1338 /* Set process priority to low */
1339 prio = 2;
1340 break;
1341 case 6:
1342 /* Set process priority to medium-low */
1343 prio = 3;
1344 break;
1345 case 2:
1346 /* Set process priority to normal */
1347 prio = 4;
1348 break;
1349 #if !defined(CONFIG_USER_ONLY)
1350 case 31:
1351 if (ctx->mem_idx > 0) {
1352 /* Set process priority to very low */
1353 prio = 1;
1354 }
1355 break;
1356 case 5:
1357 if (ctx->mem_idx > 0) {
1358 /* Set process priority to medium-hight */
1359 prio = 5;
1360 }
1361 break;
1362 case 3:
1363 if (ctx->mem_idx > 0) {
1364 /* Set process priority to high */
1365 prio = 6;
1366 }
1367 break;
1368 case 7:
1369 if (ctx->mem_idx > 1) {
1370 /* Set process priority to very high */
1371 prio = 7;
1372 }
1373 break;
1374 #endif
1375 default:
1376 /* nop */
1377 break;
1378 }
1379 if (prio) {
1380 TCGv t0 = tcg_temp_new();
1381 gen_load_spr(t0, SPR_PPR);
1382 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1383 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1384 gen_store_spr(SPR_PPR, t0);
1385 tcg_temp_free(t0);
1386 }
1387 #endif
1388 }
1389 }
1390 /* orc & orc. */
1391 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1392
1393 /* xor & xor. */
1394 static void gen_xor(DisasContext *ctx)
1395 {
1396 /* Optimisation for "set to zero" case */
1397 if (rS(ctx->opcode) != rB(ctx->opcode))
1398 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1399 else
1400 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1401 if (unlikely(Rc(ctx->opcode) != 0))
1402 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1403 }
1404
1405 /* ori */
1406 static void gen_ori(DisasContext *ctx)
1407 {
1408 target_ulong uimm = UIMM(ctx->opcode);
1409
1410 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1411 /* NOP */
1412 /* XXX: should handle special NOPs for POWER series */
1413 return;
1414 }
1415 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1416 }
1417
1418 /* oris */
1419 static void gen_oris(DisasContext *ctx)
1420 {
1421 target_ulong uimm = UIMM(ctx->opcode);
1422
1423 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1424 /* NOP */
1425 return;
1426 }
1427 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1428 }
1429
1430 /* xori */
1431 static void gen_xori(DisasContext *ctx)
1432 {
1433 target_ulong uimm = UIMM(ctx->opcode);
1434
1435 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1436 /* NOP */
1437 return;
1438 }
1439 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1440 }
1441
1442 /* xoris */
1443 static void gen_xoris(DisasContext *ctx)
1444 {
1445 target_ulong uimm = UIMM(ctx->opcode);
1446
1447 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1448 /* NOP */
1449 return;
1450 }
1451 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1452 }
1453
1454 /* popcntb : PowerPC 2.03 specification */
1455 static void gen_popcntb(DisasContext *ctx)
1456 {
1457 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1458 }
1459
1460 static void gen_popcntw(DisasContext *ctx)
1461 {
1462 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1463 }
1464
1465 #if defined(TARGET_PPC64)
1466 /* popcntd: PowerPC 2.06 specification */
1467 static void gen_popcntd(DisasContext *ctx)
1468 {
1469 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1470 }
1471 #endif
1472
1473 /* prtyw: PowerPC 2.05 specification */
1474 static void gen_prtyw(DisasContext *ctx)
1475 {
1476 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1477 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1478 TCGv t0 = tcg_temp_new();
1479 tcg_gen_shri_tl(t0, rs, 16);
1480 tcg_gen_xor_tl(ra, rs, t0);
1481 tcg_gen_shri_tl(t0, ra, 8);
1482 tcg_gen_xor_tl(ra, ra, t0);
1483 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1484 tcg_temp_free(t0);
1485 }
1486
1487 #if defined(TARGET_PPC64)
1488 /* prtyd: PowerPC 2.05 specification */
1489 static void gen_prtyd(DisasContext *ctx)
1490 {
1491 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1492 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1493 TCGv t0 = tcg_temp_new();
1494 tcg_gen_shri_tl(t0, rs, 32);
1495 tcg_gen_xor_tl(ra, rs, t0);
1496 tcg_gen_shri_tl(t0, ra, 16);
1497 tcg_gen_xor_tl(ra, ra, t0);
1498 tcg_gen_shri_tl(t0, ra, 8);
1499 tcg_gen_xor_tl(ra, ra, t0);
1500 tcg_gen_andi_tl(ra, ra, 1);
1501 tcg_temp_free(t0);
1502 }
1503 #endif
1504
1505 #if defined(TARGET_PPC64)
1506 /* extsw & extsw. */
1507 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1508
1509 /* cntlzd */
1510 static void gen_cntlzd(DisasContext *ctx)
1511 {
1512 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1513 if (unlikely(Rc(ctx->opcode) != 0))
1514 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1515 }
1516 #endif
1517
1518 /*** Integer rotate ***/
1519
1520 /* rlwimi & rlwimi. */
1521 static void gen_rlwimi(DisasContext *ctx)
1522 {
1523 uint32_t mb, me, sh;
1524
1525 mb = MB(ctx->opcode);
1526 me = ME(ctx->opcode);
1527 sh = SH(ctx->opcode);
1528 if (likely(sh == 0 && mb == 0 && me == 31)) {
1529 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1530 } else {
1531 target_ulong mask;
1532 TCGv t1;
1533 TCGv t0 = tcg_temp_new();
1534 #if defined(TARGET_PPC64)
1535 TCGv_i32 t2 = tcg_temp_new_i32();
1536 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1537 tcg_gen_rotli_i32(t2, t2, sh);
1538 tcg_gen_extu_i32_i64(t0, t2);
1539 tcg_temp_free_i32(t2);
1540 #else
1541 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1542 #endif
1543 #if defined(TARGET_PPC64)
1544 mb += 32;
1545 me += 32;
1546 #endif
1547 mask = MASK(mb, me);
1548 t1 = tcg_temp_new();
1549 tcg_gen_andi_tl(t0, t0, mask);
1550 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1551 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1552 tcg_temp_free(t0);
1553 tcg_temp_free(t1);
1554 }
1555 if (unlikely(Rc(ctx->opcode) != 0))
1556 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1557 }
1558
1559 /* rlwinm & rlwinm. */
1560 static void gen_rlwinm(DisasContext *ctx)
1561 {
1562 uint32_t mb, me, sh;
1563
1564 sh = SH(ctx->opcode);
1565 mb = MB(ctx->opcode);
1566 me = ME(ctx->opcode);
1567
1568 if (likely(mb == 0 && me == (31 - sh))) {
1569 if (likely(sh == 0)) {
1570 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1571 } else {
1572 TCGv t0 = tcg_temp_new();
1573 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1574 tcg_gen_shli_tl(t0, t0, sh);
1575 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1576 tcg_temp_free(t0);
1577 }
1578 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1579 TCGv t0 = tcg_temp_new();
1580 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1581 tcg_gen_shri_tl(t0, t0, mb);
1582 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1583 tcg_temp_free(t0);
1584 } else {
1585 TCGv t0 = tcg_temp_new();
1586 #if defined(TARGET_PPC64)
1587 TCGv_i32 t1 = tcg_temp_new_i32();
1588 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1589 tcg_gen_rotli_i32(t1, t1, sh);
1590 tcg_gen_extu_i32_i64(t0, t1);
1591 tcg_temp_free_i32(t1);
1592 #else
1593 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1594 #endif
1595 #if defined(TARGET_PPC64)
1596 mb += 32;
1597 me += 32;
1598 #endif
1599 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1600 tcg_temp_free(t0);
1601 }
1602 if (unlikely(Rc(ctx->opcode) != 0))
1603 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1604 }
1605
1606 /* rlwnm & rlwnm. */
1607 static void gen_rlwnm(DisasContext *ctx)
1608 {
1609 uint32_t mb, me;
1610 TCGv t0;
1611 #if defined(TARGET_PPC64)
1612 TCGv_i32 t1, t2;
1613 #endif
1614
1615 mb = MB(ctx->opcode);
1616 me = ME(ctx->opcode);
1617 t0 = tcg_temp_new();
1618 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1619 #if defined(TARGET_PPC64)
1620 t1 = tcg_temp_new_i32();
1621 t2 = tcg_temp_new_i32();
1622 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1623 tcg_gen_trunc_i64_i32(t2, t0);
1624 tcg_gen_rotl_i32(t1, t1, t2);
1625 tcg_gen_extu_i32_i64(t0, t1);
1626 tcg_temp_free_i32(t1);
1627 tcg_temp_free_i32(t2);
1628 #else
1629 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1630 #endif
1631 if (unlikely(mb != 0 || me != 31)) {
1632 #if defined(TARGET_PPC64)
1633 mb += 32;
1634 me += 32;
1635 #endif
1636 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1637 } else {
1638 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1639 }
1640 tcg_temp_free(t0);
1641 if (unlikely(Rc(ctx->opcode) != 0))
1642 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1643 }
1644
1645 #if defined(TARGET_PPC64)
1646 #define GEN_PPC64_R2(name, opc1, opc2) \
1647 static void glue(gen_, name##0)(DisasContext *ctx) \
1648 { \
1649 gen_##name(ctx, 0); \
1650 } \
1651 \
1652 static void glue(gen_, name##1)(DisasContext *ctx) \
1653 { \
1654 gen_##name(ctx, 1); \
1655 }
1656 #define GEN_PPC64_R4(name, opc1, opc2) \
1657 static void glue(gen_, name##0)(DisasContext *ctx) \
1658 { \
1659 gen_##name(ctx, 0, 0); \
1660 } \
1661 \
1662 static void glue(gen_, name##1)(DisasContext *ctx) \
1663 { \
1664 gen_##name(ctx, 0, 1); \
1665 } \
1666 \
1667 static void glue(gen_, name##2)(DisasContext *ctx) \
1668 { \
1669 gen_##name(ctx, 1, 0); \
1670 } \
1671 \
1672 static void glue(gen_, name##3)(DisasContext *ctx) \
1673 { \
1674 gen_##name(ctx, 1, 1); \
1675 }
1676
1677 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1678 uint32_t sh)
1679 {
1680 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1681 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1682 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1683 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1684 } else {
1685 TCGv t0 = tcg_temp_new();
1686 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1687 if (likely(mb == 0 && me == 63)) {
1688 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1689 } else {
1690 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1691 }
1692 tcg_temp_free(t0);
1693 }
1694 if (unlikely(Rc(ctx->opcode) != 0))
1695 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1696 }
1697 /* rldicl - rldicl. */
1698 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1699 {
1700 uint32_t sh, mb;
1701
1702 sh = SH(ctx->opcode) | (shn << 5);
1703 mb = MB(ctx->opcode) | (mbn << 5);
1704 gen_rldinm(ctx, mb, 63, sh);
1705 }
1706 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1707 /* rldicr - rldicr. */
1708 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1709 {
1710 uint32_t sh, me;
1711
1712 sh = SH(ctx->opcode) | (shn << 5);
1713 me = MB(ctx->opcode) | (men << 5);
1714 gen_rldinm(ctx, 0, me, sh);
1715 }
1716 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1717 /* rldic - rldic. */
1718 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1719 {
1720 uint32_t sh, mb;
1721
1722 sh = SH(ctx->opcode) | (shn << 5);
1723 mb = MB(ctx->opcode) | (mbn << 5);
1724 gen_rldinm(ctx, mb, 63 - sh, sh);
1725 }
1726 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1727
1728 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1729 {
1730 TCGv t0;
1731
1732 t0 = tcg_temp_new();
1733 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1734 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1735 if (unlikely(mb != 0 || me != 63)) {
1736 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1737 } else {
1738 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1739 }
1740 tcg_temp_free(t0);
1741 if (unlikely(Rc(ctx->opcode) != 0))
1742 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1743 }
1744
1745 /* rldcl - rldcl. */
1746 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1747 {
1748 uint32_t mb;
1749
1750 mb = MB(ctx->opcode) | (mbn << 5);
1751 gen_rldnm(ctx, mb, 63);
1752 }
1753 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1754 /* rldcr - rldcr. */
1755 static inline void gen_rldcr(DisasContext *ctx, int men)
1756 {
1757 uint32_t me;
1758
1759 me = MB(ctx->opcode) | (men << 5);
1760 gen_rldnm(ctx, 0, me);
1761 }
1762 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1763 /* rldimi - rldimi. */
1764 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1765 {
1766 uint32_t sh, mb, me;
1767
1768 sh = SH(ctx->opcode) | (shn << 5);
1769 mb = MB(ctx->opcode) | (mbn << 5);
1770 me = 63 - sh;
1771 if (unlikely(sh == 0 && mb == 0)) {
1772 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1773 } else {
1774 TCGv t0, t1;
1775 target_ulong mask;
1776
1777 t0 = tcg_temp_new();
1778 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1779 t1 = tcg_temp_new();
1780 mask = MASK(mb, me);
1781 tcg_gen_andi_tl(t0, t0, mask);
1782 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1783 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1784 tcg_temp_free(t0);
1785 tcg_temp_free(t1);
1786 }
1787 if (unlikely(Rc(ctx->opcode) != 0))
1788 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1789 }
1790 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1791 #endif
1792
1793 /*** Integer shift ***/
1794
1795 /* slw & slw. */
1796 static void gen_slw(DisasContext *ctx)
1797 {
1798 TCGv t0, t1;
1799
1800 t0 = tcg_temp_new();
1801 /* AND rS with a mask that is 0 when rB >= 0x20 */
1802 #if defined(TARGET_PPC64)
1803 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1804 tcg_gen_sari_tl(t0, t0, 0x3f);
1805 #else
1806 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1807 tcg_gen_sari_tl(t0, t0, 0x1f);
1808 #endif
1809 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1810 t1 = tcg_temp_new();
1811 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1812 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1813 tcg_temp_free(t1);
1814 tcg_temp_free(t0);
1815 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1816 if (unlikely(Rc(ctx->opcode) != 0))
1817 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1818 }
1819
1820 /* sraw & sraw. */
1821 static void gen_sraw(DisasContext *ctx)
1822 {
1823 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1824 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1825 if (unlikely(Rc(ctx->opcode) != 0))
1826 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1827 }
1828
1829 /* srawi & srawi. */
1830 static void gen_srawi(DisasContext *ctx)
1831 {
1832 int sh = SH(ctx->opcode);
1833 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1834 TCGv src = cpu_gpr[rS(ctx->opcode)];
1835 if (sh == 0) {
1836 tcg_gen_mov_tl(dst, src);
1837 tcg_gen_movi_tl(cpu_ca, 0);
1838 } else {
1839 TCGv t0;
1840 tcg_gen_ext32s_tl(dst, src);
1841 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1842 t0 = tcg_temp_new();
1843 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1844 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1845 tcg_temp_free(t0);
1846 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1847 tcg_gen_sari_tl(dst, dst, sh);
1848 }
1849 if (unlikely(Rc(ctx->opcode) != 0)) {
1850 gen_set_Rc0(ctx, dst);
1851 }
1852 }
1853
1854 /* srw & srw. */
1855 static void gen_srw(DisasContext *ctx)
1856 {
1857 TCGv t0, t1;
1858
1859 t0 = tcg_temp_new();
1860 /* AND rS with a mask that is 0 when rB >= 0x20 */
1861 #if defined(TARGET_PPC64)
1862 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1863 tcg_gen_sari_tl(t0, t0, 0x3f);
1864 #else
1865 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1866 tcg_gen_sari_tl(t0, t0, 0x1f);
1867 #endif
1868 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1869 tcg_gen_ext32u_tl(t0, t0);
1870 t1 = tcg_temp_new();
1871 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1872 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1873 tcg_temp_free(t1);
1874 tcg_temp_free(t0);
1875 if (unlikely(Rc(ctx->opcode) != 0))
1876 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1877 }
1878
1879 #if defined(TARGET_PPC64)
1880 /* sld & sld. */
1881 static void gen_sld(DisasContext *ctx)
1882 {
1883 TCGv t0, t1;
1884
1885 t0 = tcg_temp_new();
1886 /* AND rS with a mask that is 0 when rB >= 0x40 */
1887 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1888 tcg_gen_sari_tl(t0, t0, 0x3f);
1889 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1890 t1 = tcg_temp_new();
1891 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1892 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1893 tcg_temp_free(t1);
1894 tcg_temp_free(t0);
1895 if (unlikely(Rc(ctx->opcode) != 0))
1896 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1897 }
1898
1899 /* srad & srad. */
1900 static void gen_srad(DisasContext *ctx)
1901 {
1902 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1903 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1904 if (unlikely(Rc(ctx->opcode) != 0))
1905 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1906 }
1907 /* sradi & sradi. */
1908 static inline void gen_sradi(DisasContext *ctx, int n)
1909 {
1910 int sh = SH(ctx->opcode) + (n << 5);
1911 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1912 TCGv src = cpu_gpr[rS(ctx->opcode)];
1913 if (sh == 0) {
1914 tcg_gen_mov_tl(dst, src);
1915 tcg_gen_movi_tl(cpu_ca, 0);
1916 } else {
1917 TCGv t0;
1918 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1919 t0 = tcg_temp_new();
1920 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1921 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1922 tcg_temp_free(t0);
1923 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1924 tcg_gen_sari_tl(dst, src, sh);
1925 }
1926 if (unlikely(Rc(ctx->opcode) != 0)) {
1927 gen_set_Rc0(ctx, dst);
1928 }
1929 }
1930
1931 static void gen_sradi0(DisasContext *ctx)
1932 {
1933 gen_sradi(ctx, 0);
1934 }
1935
1936 static void gen_sradi1(DisasContext *ctx)
1937 {
1938 gen_sradi(ctx, 1);
1939 }
1940
1941 /* srd & srd. */
1942 static void gen_srd(DisasContext *ctx)
1943 {
1944 TCGv t0, t1;
1945
1946 t0 = tcg_temp_new();
1947 /* AND rS with a mask that is 0 when rB >= 0x40 */
1948 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1949 tcg_gen_sari_tl(t0, t0, 0x3f);
1950 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1951 t1 = tcg_temp_new();
1952 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1953 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1954 tcg_temp_free(t1);
1955 tcg_temp_free(t0);
1956 if (unlikely(Rc(ctx->opcode) != 0))
1957 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1958 }
1959 #endif
1960
1961 /*** Floating-Point arithmetic ***/
1962 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1963 static void gen_f##name(DisasContext *ctx) \
1964 { \
1965 if (unlikely(!ctx->fpu_enabled)) { \
1966 gen_exception(ctx, POWERPC_EXCP_FPU); \
1967 return; \
1968 } \
1969 /* NIP cannot be restored if the memory exception comes from an helper */ \
1970 gen_update_nip(ctx, ctx->nip - 4); \
1971 gen_reset_fpstatus(); \
1972 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1973 cpu_fpr[rA(ctx->opcode)], \
1974 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
1975 if (isfloat) { \
1976 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1977 cpu_fpr[rD(ctx->opcode)]); \
1978 } \
1979 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
1980 Rc(ctx->opcode) != 0); \
1981 }
1982
1983 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1984 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1985 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1986
1987 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1988 static void gen_f##name(DisasContext *ctx) \
1989 { \
1990 if (unlikely(!ctx->fpu_enabled)) { \
1991 gen_exception(ctx, POWERPC_EXCP_FPU); \
1992 return; \
1993 } \
1994 /* NIP cannot be restored if the memory exception comes from an helper */ \
1995 gen_update_nip(ctx, ctx->nip - 4); \
1996 gen_reset_fpstatus(); \
1997 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1998 cpu_fpr[rA(ctx->opcode)], \
1999 cpu_fpr[rB(ctx->opcode)]); \
2000 if (isfloat) { \
2001 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2002 cpu_fpr[rD(ctx->opcode)]); \
2003 } \
2004 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2005 set_fprf, Rc(ctx->opcode) != 0); \
2006 }
2007 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2008 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2009 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2010
2011 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2012 static void gen_f##name(DisasContext *ctx) \
2013 { \
2014 if (unlikely(!ctx->fpu_enabled)) { \
2015 gen_exception(ctx, POWERPC_EXCP_FPU); \
2016 return; \
2017 } \
2018 /* NIP cannot be restored if the memory exception comes from an helper */ \
2019 gen_update_nip(ctx, ctx->nip - 4); \
2020 gen_reset_fpstatus(); \
2021 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2022 cpu_fpr[rA(ctx->opcode)], \
2023 cpu_fpr[rC(ctx->opcode)]); \
2024 if (isfloat) { \
2025 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2026 cpu_fpr[rD(ctx->opcode)]); \
2027 } \
2028 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2029 set_fprf, Rc(ctx->opcode) != 0); \
2030 }
2031 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2032 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2033 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2034
2035 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2036 static void gen_f##name(DisasContext *ctx) \
2037 { \
2038 if (unlikely(!ctx->fpu_enabled)) { \
2039 gen_exception(ctx, POWERPC_EXCP_FPU); \
2040 return; \
2041 } \
2042 /* NIP cannot be restored if the memory exception comes from an helper */ \
2043 gen_update_nip(ctx, ctx->nip - 4); \
2044 gen_reset_fpstatus(); \
2045 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2046 cpu_fpr[rB(ctx->opcode)]); \
2047 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2048 set_fprf, Rc(ctx->opcode) != 0); \
2049 }
2050
2051 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2052 static void gen_f##name(DisasContext *ctx) \
2053 { \
2054 if (unlikely(!ctx->fpu_enabled)) { \
2055 gen_exception(ctx, POWERPC_EXCP_FPU); \
2056 return; \
2057 } \
2058 /* NIP cannot be restored if the memory exception comes from an helper */ \
2059 gen_update_nip(ctx, ctx->nip - 4); \
2060 gen_reset_fpstatus(); \
2061 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2062 cpu_fpr[rB(ctx->opcode)]); \
2063 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2064 set_fprf, Rc(ctx->opcode) != 0); \
2065 }
2066
2067 /* fadd - fadds */
2068 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2069 /* fdiv - fdivs */
2070 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2071 /* fmul - fmuls */
2072 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2073
2074 /* fre */
2075 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2076
2077 /* fres */
2078 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2079
2080 /* frsqrte */
2081 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2082
2083 /* frsqrtes */
2084 static void gen_frsqrtes(DisasContext *ctx)
2085 {
2086 if (unlikely(!ctx->fpu_enabled)) {
2087 gen_exception(ctx, POWERPC_EXCP_FPU);
2088 return;
2089 }
2090 /* NIP cannot be restored if the memory exception comes from an helper */
2091 gen_update_nip(ctx, ctx->nip - 4);
2092 gen_reset_fpstatus();
2093 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2094 cpu_fpr[rB(ctx->opcode)]);
2095 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2096 cpu_fpr[rD(ctx->opcode)]);
2097 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2098 }
2099
2100 /* fsel */
2101 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2102 /* fsub - fsubs */
2103 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2104 /* Optional: */
2105
2106 /* fsqrt */
2107 static void gen_fsqrt(DisasContext *ctx)
2108 {
2109 if (unlikely(!ctx->fpu_enabled)) {
2110 gen_exception(ctx, POWERPC_EXCP_FPU);
2111 return;
2112 }
2113 /* NIP cannot be restored if the memory exception comes from an helper */
2114 gen_update_nip(ctx, ctx->nip - 4);
2115 gen_reset_fpstatus();
2116 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2117 cpu_fpr[rB(ctx->opcode)]);
2118 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2119 }
2120
2121 static void gen_fsqrts(DisasContext *ctx)
2122 {
2123 if (unlikely(!ctx->fpu_enabled)) {
2124 gen_exception(ctx, POWERPC_EXCP_FPU);
2125 return;
2126 }
2127 /* NIP cannot be restored if the memory exception comes from an helper */
2128 gen_update_nip(ctx, ctx->nip - 4);
2129 gen_reset_fpstatus();
2130 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2131 cpu_fpr[rB(ctx->opcode)]);
2132 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2133 cpu_fpr[rD(ctx->opcode)]);
2134 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2135 }
2136
2137 /*** Floating-Point multiply-and-add ***/
2138 /* fmadd - fmadds */
2139 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2140 /* fmsub - fmsubs */
2141 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2142 /* fnmadd - fnmadds */
2143 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2144 /* fnmsub - fnmsubs */
2145 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2146
2147 /*** Floating-Point round & convert ***/
2148 /* fctiw */
2149 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2150 /* fctiwz */
2151 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2152 /* frsp */
2153 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2154 #if defined(TARGET_PPC64)
2155 /* fcfid */
2156 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2157 /* fctid */
2158 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2159 /* fctidz */
2160 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2161 #endif
2162
2163 /* frin */
2164 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2165 /* friz */
2166 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2167 /* frip */
2168 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2169 /* frim */
2170 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2171
2172 /*** Floating-Point compare ***/
2173
2174 /* fcmpo */
2175 static void gen_fcmpo(DisasContext *ctx)
2176 {
2177 TCGv_i32 crf;
2178 if (unlikely(!ctx->fpu_enabled)) {
2179 gen_exception(ctx, POWERPC_EXCP_FPU);
2180 return;
2181 }
2182 /* NIP cannot be restored if the memory exception comes from an helper */
2183 gen_update_nip(ctx, ctx->nip - 4);
2184 gen_reset_fpstatus();
2185 crf = tcg_const_i32(crfD(ctx->opcode));
2186 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2187 cpu_fpr[rB(ctx->opcode)], crf);
2188 tcg_temp_free_i32(crf);
2189 gen_helper_float_check_status(cpu_env);
2190 }
2191
2192 /* fcmpu */
2193 static void gen_fcmpu(DisasContext *ctx)
2194 {
2195 TCGv_i32 crf;
2196 if (unlikely(!ctx->fpu_enabled)) {
2197 gen_exception(ctx, POWERPC_EXCP_FPU);
2198 return;
2199 }
2200 /* NIP cannot be restored if the memory exception comes from an helper */
2201 gen_update_nip(ctx, ctx->nip - 4);
2202 gen_reset_fpstatus();
2203 crf = tcg_const_i32(crfD(ctx->opcode));
2204 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2205 cpu_fpr[rB(ctx->opcode)], crf);
2206 tcg_temp_free_i32(crf);
2207 gen_helper_float_check_status(cpu_env);
2208 }
2209
2210 /*** Floating-point move ***/
2211 /* fabs */
2212 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2213 static void gen_fabs(DisasContext *ctx)
2214 {
2215 if (unlikely(!ctx->fpu_enabled)) {
2216 gen_exception(ctx, POWERPC_EXCP_FPU);
2217 return;
2218 }
2219 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2220 ~(1ULL << 63));
2221 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2222 }
2223
2224 /* fmr - fmr. */
2225 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2226 static void gen_fmr(DisasContext *ctx)
2227 {
2228 if (unlikely(!ctx->fpu_enabled)) {
2229 gen_exception(ctx, POWERPC_EXCP_FPU);
2230 return;
2231 }
2232 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2233 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2234 }
2235
2236 /* fnabs */
2237 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2238 static void gen_fnabs(DisasContext *ctx)
2239 {
2240 if (unlikely(!ctx->fpu_enabled)) {
2241 gen_exception(ctx, POWERPC_EXCP_FPU);
2242 return;
2243 }
2244 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2245 1ULL << 63);
2246 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2247 }
2248
2249 /* fneg */
2250 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2251 static void gen_fneg(DisasContext *ctx)
2252 {
2253 if (unlikely(!ctx->fpu_enabled)) {
2254 gen_exception(ctx, POWERPC_EXCP_FPU);
2255 return;
2256 }
2257 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2258 1ULL << 63);
2259 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2260 }
2261
2262 /* fcpsgn: PowerPC 2.05 specification */
2263 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2264 static void gen_fcpsgn(DisasContext *ctx)
2265 {
2266 if (unlikely(!ctx->fpu_enabled)) {
2267 gen_exception(ctx, POWERPC_EXCP_FPU);
2268 return;
2269 }
2270 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2271 cpu_fpr[rB(ctx->opcode)], 0, 63);
2272 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2273 }
2274
2275 /*** Floating-Point status & ctrl register ***/
2276
2277 /* mcrfs */
2278 static void gen_mcrfs(DisasContext *ctx)
2279 {
2280 TCGv tmp = tcg_temp_new();
2281 int bfa;
2282
2283 if (unlikely(!ctx->fpu_enabled)) {
2284 gen_exception(ctx, POWERPC_EXCP_FPU);
2285 return;
2286 }
2287 bfa = 4 * (7 - crfS(ctx->opcode));
2288 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2289 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2290 tcg_temp_free(tmp);
2291 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2292 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2293 }
2294
2295 /* mffs */
2296 static void gen_mffs(DisasContext *ctx)
2297 {
2298 if (unlikely(!ctx->fpu_enabled)) {
2299 gen_exception(ctx, POWERPC_EXCP_FPU);
2300 return;
2301 }
2302 gen_reset_fpstatus();
2303 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2304 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2305 }
2306
2307 /* mtfsb0 */
2308 static void gen_mtfsb0(DisasContext *ctx)
2309 {
2310 uint8_t crb;
2311
2312 if (unlikely(!ctx->fpu_enabled)) {
2313 gen_exception(ctx, POWERPC_EXCP_FPU);
2314 return;
2315 }
2316 crb = 31 - crbD(ctx->opcode);
2317 gen_reset_fpstatus();
2318 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2319 TCGv_i32 t0;
2320 /* NIP cannot be restored if the memory exception comes from an helper */
2321 gen_update_nip(ctx, ctx->nip - 4);
2322 t0 = tcg_const_i32(crb);
2323 gen_helper_fpscr_clrbit(cpu_env, t0);
2324 tcg_temp_free_i32(t0);
2325 }
2326 if (unlikely(Rc(ctx->opcode) != 0)) {
2327 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2328 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2329 }
2330 }
2331
2332 /* mtfsb1 */
2333 static void gen_mtfsb1(DisasContext *ctx)
2334 {
2335 uint8_t crb;
2336
2337 if (unlikely(!ctx->fpu_enabled)) {
2338 gen_exception(ctx, POWERPC_EXCP_FPU);
2339 return;
2340 }
2341 crb = 31 - crbD(ctx->opcode);
2342 gen_reset_fpstatus();
2343 /* XXX: we pretend we can only do IEEE floating-point computations */
2344 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2345 TCGv_i32 t0;
2346 /* NIP cannot be restored if the memory exception comes from an helper */
2347 gen_update_nip(ctx, ctx->nip - 4);
2348 t0 = tcg_const_i32(crb);
2349 gen_helper_fpscr_setbit(cpu_env, t0);
2350 tcg_temp_free_i32(t0);
2351 }
2352 if (unlikely(Rc(ctx->opcode) != 0)) {
2353 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2354 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2355 }
2356 /* We can raise a differed exception */
2357 gen_helper_float_check_status(cpu_env);
2358 }
2359
2360 /* mtfsf */
2361 static void gen_mtfsf(DisasContext *ctx)
2362 {
2363 TCGv_i32 t0;
2364 int flm, l, w;
2365
2366 if (unlikely(!ctx->fpu_enabled)) {
2367 gen_exception(ctx, POWERPC_EXCP_FPU);
2368 return;
2369 }
2370 flm = FPFLM(ctx->opcode);
2371 l = FPL(ctx->opcode);
2372 w = FPW(ctx->opcode);
2373 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2374 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2375 return;
2376 }
2377 /* NIP cannot be restored if the memory exception comes from an helper */
2378 gen_update_nip(ctx, ctx->nip - 4);
2379 gen_reset_fpstatus();
2380 if (l) {
2381 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2382 } else {
2383 t0 = tcg_const_i32(flm << (w * 8));
2384 }
2385 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2386 tcg_temp_free_i32(t0);
2387 if (unlikely(Rc(ctx->opcode) != 0)) {
2388 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2389 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2390 }
2391 /* We can raise a differed exception */
2392 gen_helper_float_check_status(cpu_env);
2393 }
2394
2395 /* mtfsfi */
2396 static void gen_mtfsfi(DisasContext *ctx)
2397 {
2398 int bf, sh, w;
2399 TCGv_i64 t0;
2400 TCGv_i32 t1;
2401
2402 if (unlikely(!ctx->fpu_enabled)) {
2403 gen_exception(ctx, POWERPC_EXCP_FPU);
2404 return;
2405 }
2406 w = FPW(ctx->opcode);
2407 bf = FPBF(ctx->opcode);
2408 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2409 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2410 return;
2411 }
2412 sh = (8 * w) + 7 - bf;
2413 /* NIP cannot be restored if the memory exception comes from an helper */
2414 gen_update_nip(ctx, ctx->nip - 4);
2415 gen_reset_fpstatus();
2416 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2417 t1 = tcg_const_i32(1 << sh);
2418 gen_helper_store_fpscr(cpu_env, t0, t1);
2419 tcg_temp_free_i64(t0);
2420 tcg_temp_free_i32(t1);
2421 if (unlikely(Rc(ctx->opcode) != 0)) {
2422 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2423 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2424 }
2425 /* We can raise a differed exception */
2426 gen_helper_float_check_status(cpu_env);
2427 }
2428
2429 /*** Addressing modes ***/
2430 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2431 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2432 target_long maskl)
2433 {
2434 target_long simm = SIMM(ctx->opcode);
2435
2436 simm &= ~maskl;
2437 if (rA(ctx->opcode) == 0) {
2438 if (NARROW_MODE(ctx)) {
2439 simm = (uint32_t)simm;
2440 }
2441 tcg_gen_movi_tl(EA, simm);
2442 } else if (likely(simm != 0)) {
2443 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2444 if (NARROW_MODE(ctx)) {
2445 tcg_gen_ext32u_tl(EA, EA);
2446 }
2447 } else {
2448 if (NARROW_MODE(ctx)) {
2449 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2450 } else {
2451 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2452 }
2453 }
2454 }
2455
2456 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2457 {
2458 if (rA(ctx->opcode) == 0) {
2459 if (NARROW_MODE(ctx)) {
2460 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2461 } else {
2462 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2463 }
2464 } else {
2465 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2466 if (NARROW_MODE(ctx)) {
2467 tcg_gen_ext32u_tl(EA, EA);
2468 }
2469 }
2470 }
2471
2472 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2473 {
2474 if (rA(ctx->opcode) == 0) {
2475 tcg_gen_movi_tl(EA, 0);
2476 } else if (NARROW_MODE(ctx)) {
2477 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2478 } else {
2479 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2480 }
2481 }
2482
2483 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2484 target_long val)
2485 {
2486 tcg_gen_addi_tl(ret, arg1, val);
2487 if (NARROW_MODE(ctx)) {
2488 tcg_gen_ext32u_tl(ret, ret);
2489 }
2490 }
2491
2492 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2493 {
2494 int l1 = gen_new_label();
2495 TCGv t0 = tcg_temp_new();
2496 TCGv_i32 t1, t2;
2497 /* NIP cannot be restored if the memory exception comes from an helper */
2498 gen_update_nip(ctx, ctx->nip - 4);
2499 tcg_gen_andi_tl(t0, EA, mask);
2500 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2501 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2502 t2 = tcg_const_i32(0);
2503 gen_helper_raise_exception_err(cpu_env, t1, t2);
2504 tcg_temp_free_i32(t1);
2505 tcg_temp_free_i32(t2);
2506 gen_set_label(l1);
2507 tcg_temp_free(t0);
2508 }
2509
2510 /*** Integer load ***/
2511 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2512 {
2513 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2514 }
2515
2516 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2517 {
2518 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2519 }
2520
2521 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2522 {
2523 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2524 if (unlikely(ctx->le_mode)) {
2525 tcg_gen_bswap16_tl(arg1, arg1);
2526 }
2527 }
2528
2529 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2530 {
2531 if (unlikely(ctx->le_mode)) {
2532 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2533 tcg_gen_bswap16_tl(arg1, arg1);
2534 tcg_gen_ext16s_tl(arg1, arg1);
2535 } else {
2536 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2537 }
2538 }
2539
2540 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2541 {
2542 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2543 if (unlikely(ctx->le_mode)) {
2544 tcg_gen_bswap32_tl(arg1, arg1);
2545 }
2546 }
2547
2548 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2549 {
2550 if (unlikely(ctx->le_mode)) {
2551 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2552 tcg_gen_bswap32_tl(arg1, arg1);
2553 tcg_gen_ext32s_tl(arg1, arg1);
2554 } else
2555 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2556 }
2557
2558 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2559 {
2560 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2561 if (unlikely(ctx->le_mode)) {
2562 tcg_gen_bswap64_i64(arg1, arg1);
2563 }
2564 }
2565
2566 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2567 {
2568 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2569 }
2570
2571 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2572 {
2573 if (unlikely(ctx->le_mode)) {
2574 TCGv t0 = tcg_temp_new();
2575 tcg_gen_ext16u_tl(t0, arg1);
2576 tcg_gen_bswap16_tl(t0, t0);
2577 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2578 tcg_temp_free(t0);
2579 } else {
2580 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2581 }
2582 }
2583
2584 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2585 {
2586 if (unlikely(ctx->le_mode)) {
2587 TCGv t0 = tcg_temp_new();
2588 tcg_gen_ext32u_tl(t0, arg1);
2589 tcg_gen_bswap32_tl(t0, t0);
2590 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2591 tcg_temp_free(t0);
2592 } else {
2593 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2594 }
2595 }
2596
2597 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2598 {
2599 if (unlikely(ctx->le_mode)) {
2600 TCGv_i64 t0 = tcg_temp_new_i64();
2601 tcg_gen_bswap64_i64(t0, arg1);
2602 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2603 tcg_temp_free_i64(t0);
2604 } else
2605 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2606 }
2607
2608 #define GEN_LD(name, ldop, opc, type) \
2609 static void glue(gen_, name)(DisasContext *ctx) \
2610 { \
2611 TCGv EA; \
2612 gen_set_access_type(ctx, ACCESS_INT); \
2613 EA = tcg_temp_new(); \
2614 gen_addr_imm_index(ctx, EA, 0); \
2615 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2616 tcg_temp_free(EA); \
2617 }
2618
2619 #define GEN_LDU(name, ldop, opc, type) \
2620 static void glue(gen_, name##u)(DisasContext *ctx) \
2621 { \
2622 TCGv EA; \
2623 if (unlikely(rA(ctx->opcode) == 0 || \
2624 rA(ctx->opcode) == rD(ctx->opcode))) { \
2625 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2626 return; \
2627 } \
2628 gen_set_access_type(ctx, ACCESS_INT); \
2629 EA = tcg_temp_new(); \
2630 if (type == PPC_64B) \
2631 gen_addr_imm_index(ctx, EA, 0x03); \
2632 else \
2633 gen_addr_imm_index(ctx, EA, 0); \
2634 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2635 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2636 tcg_temp_free(EA); \
2637 }
2638
2639 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2640 static void glue(gen_, name##ux)(DisasContext *ctx) \
2641 { \
2642 TCGv EA; \
2643 if (unlikely(rA(ctx->opcode) == 0 || \
2644 rA(ctx->opcode) == rD(ctx->opcode))) { \
2645 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2646 return; \
2647 } \
2648 gen_set_access_type(ctx, ACCESS_INT); \
2649 EA = tcg_temp_new(); \
2650 gen_addr_reg_index(ctx, EA); \
2651 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2652 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2653 tcg_temp_free(EA); \
2654 }
2655
2656 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2657 static void glue(gen_, name##x)(DisasContext *ctx) \
2658 { \
2659 TCGv EA; \
2660 gen_set_access_type(ctx, ACCESS_INT); \
2661 EA = tcg_temp_new(); \
2662 gen_addr_reg_index(ctx, EA); \
2663 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2664 tcg_temp_free(EA); \
2665 }
2666 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2667 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2668
2669 #define GEN_LDS(name, ldop, op, type) \
2670 GEN_LD(name, ldop, op | 0x20, type); \
2671 GEN_LDU(name, ldop, op | 0x21, type); \
2672 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2673 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2674
2675 /* lbz lbzu lbzux lbzx */
2676 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2677 /* lha lhau lhaux lhax */
2678 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2679 /* lhz lhzu lhzux lhzx */
2680 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2681 /* lwz lwzu lwzux lwzx */
2682 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2683 #if defined(TARGET_PPC64)
2684 /* lwaux */
2685 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2686 /* lwax */
2687 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2688 /* ldux */
2689 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2690 /* ldx */
2691 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2692
2693 static void gen_ld(DisasContext *ctx)
2694 {
2695 TCGv EA;
2696 if (Rc(ctx->opcode)) {
2697 if (unlikely(rA(ctx->opcode) == 0 ||
2698 rA(ctx->opcode) == rD(ctx->opcode))) {
2699 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2700 return;
2701 }
2702 }
2703 gen_set_access_type(ctx, ACCESS_INT);
2704 EA = tcg_temp_new();
2705 gen_addr_imm_index(ctx, EA, 0x03);
2706 if (ctx->opcode & 0x02) {
2707 /* lwa (lwau is undefined) */
2708 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2709 } else {
2710 /* ld - ldu */
2711 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2712 }
2713 if (Rc(ctx->opcode))
2714 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2715 tcg_temp_free(EA);
2716 }
2717
2718 /* lq */
2719 static void gen_lq(DisasContext *ctx)
2720 {
2721 #if defined(CONFIG_USER_ONLY)
2722 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2723 #else
2724 int ra, rd;
2725 TCGv EA;
2726
2727 /* Restore CPU state */
2728 if (unlikely(ctx->mem_idx == 0)) {
2729 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2730 return;
2731 }
2732 ra = rA(ctx->opcode);
2733 rd = rD(ctx->opcode);
2734 if (unlikely((rd & 1) || rd == ra)) {
2735 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2736 return;
2737 }
2738 if (unlikely(ctx->le_mode)) {
2739 /* Little-endian mode is not handled */
2740 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2741 return;
2742 }
2743 gen_set_access_type(ctx, ACCESS_INT);
2744 EA = tcg_temp_new();
2745 gen_addr_imm_index(ctx, EA, 0x0F);
2746 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2747 gen_addr_add(ctx, EA, EA, 8);
2748 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2749 tcg_temp_free(EA);
2750 #endif
2751 }
2752 #endif
2753
2754 /*** Integer store ***/
2755 #define GEN_ST(name, stop, opc, type) \
2756 static void glue(gen_, name)(DisasContext *ctx) \
2757 { \
2758 TCGv EA; \
2759 gen_set_access_type(ctx, ACCESS_INT); \
2760 EA = tcg_temp_new(); \
2761 gen_addr_imm_index(ctx, EA, 0); \
2762 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2763 tcg_temp_free(EA); \
2764 }
2765
2766 #define GEN_STU(name, stop, opc, type) \
2767 static void glue(gen_, stop##u)(DisasContext *ctx) \
2768 { \
2769 TCGv EA; \
2770 if (unlikely(rA(ctx->opcode) == 0)) { \
2771 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2772 return; \
2773 } \
2774 gen_set_access_type(ctx, ACCESS_INT); \
2775 EA = tcg_temp_new(); \
2776 if (type == PPC_64B) \
2777 gen_addr_imm_index(ctx, EA, 0x03); \
2778 else \
2779 gen_addr_imm_index(ctx, EA, 0); \
2780 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2781 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2782 tcg_temp_free(EA); \
2783 }
2784
2785 #define GEN_STUX(name, stop, opc2, opc3, type) \
2786 static void glue(gen_, name##ux)(DisasContext *ctx) \
2787 { \
2788 TCGv EA; \
2789 if (unlikely(rA(ctx->opcode) == 0)) { \
2790 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2791 return; \
2792 } \
2793 gen_set_access_type(ctx, ACCESS_INT); \
2794 EA = tcg_temp_new(); \
2795 gen_addr_reg_index(ctx, EA); \
2796 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2797 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2798 tcg_temp_free(EA); \
2799 }
2800
2801 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2802 static void glue(gen_, name##x)(DisasContext *ctx) \
2803 { \
2804 TCGv EA; \
2805 gen_set_access_type(ctx, ACCESS_INT); \
2806 EA = tcg_temp_new(); \
2807 gen_addr_reg_index(ctx, EA); \
2808 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2809 tcg_temp_free(EA); \
2810 }
2811 #define GEN_STX(name, stop, opc2, opc3, type) \
2812 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2813
2814 #define GEN_STS(name, stop, op, type) \
2815 GEN_ST(name, stop, op | 0x20, type); \
2816 GEN_STU(name, stop, op | 0x21, type); \
2817 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2818 GEN_STX(name, stop, 0x17, op | 0x00, type)
2819
2820 /* stb stbu stbux stbx */
2821 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2822 /* sth sthu sthux sthx */
2823 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2824 /* stw stwu stwux stwx */
2825 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2826 #if defined(TARGET_PPC64)
2827 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2828 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2829
2830 static void gen_std(DisasContext *ctx)
2831 {
2832 int rs;
2833 TCGv EA;
2834
2835 rs = rS(ctx->opcode);
2836 if ((ctx->opcode & 0x3) == 0x2) {
2837 #if defined(CONFIG_USER_ONLY)
2838 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2839 #else
2840 /* stq */
2841 if (unlikely(ctx->mem_idx == 0)) {
2842 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2843 return;
2844 }
2845 if (unlikely(rs & 1)) {
2846 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2847 return;
2848 }
2849 if (unlikely(ctx->le_mode)) {
2850 /* Little-endian mode is not handled */
2851 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2852 return;
2853 }
2854 gen_set_access_type(ctx, ACCESS_INT);
2855 EA = tcg_temp_new();
2856 gen_addr_imm_index(ctx, EA, 0x03);
2857 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2858 gen_addr_add(ctx, EA, EA, 8);
2859 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2860 tcg_temp_free(EA);
2861 #endif
2862 } else {
2863 /* std / stdu */
2864 if (Rc(ctx->opcode)) {
2865 if (unlikely(rA(ctx->opcode) == 0)) {
2866 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2867 return;
2868 }
2869 }
2870 gen_set_access_type(ctx, ACCESS_INT);
2871 EA = tcg_temp_new();
2872 gen_addr_imm_index(ctx, EA, 0x03);
2873 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2874 if (Rc(ctx->opcode))
2875 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2876 tcg_temp_free(EA);
2877 }
2878 }
2879 #endif
2880 /*** Integer load and store with byte reverse ***/
2881 /* lhbrx */
2882 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2883 {
2884 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2885 if (likely(!ctx->le_mode)) {
2886 tcg_gen_bswap16_tl(arg1, arg1);
2887 }
2888 }
2889 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2890
2891 /* lwbrx */
2892 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2893 {
2894 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2895 if (likely(!ctx->le_mode)) {
2896 tcg_gen_bswap32_tl(arg1, arg1);
2897 }
2898 }
2899 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2900
2901 #if defined(TARGET_PPC64)
2902 /* ldbrx */
2903 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2904 {
2905 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2906 if (likely(!ctx->le_mode)) {
2907 tcg_gen_bswap64_tl(arg1, arg1);
2908 }
2909 }
2910 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2911 #endif /* TARGET_PPC64 */
2912
2913 /* sthbrx */
2914 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2915 {
2916 if (likely(!ctx->le_mode)) {
2917 TCGv t0 = tcg_temp_new();
2918 tcg_gen_ext16u_tl(t0, arg1);
2919 tcg_gen_bswap16_tl(t0, t0);
2920 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2921 tcg_temp_free(t0);
2922 } else {
2923 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2924 }
2925 }
2926 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2927
2928 /* stwbrx */
2929 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2930 {
2931 if (likely(!ctx->le_mode)) {
2932 TCGv t0 = tcg_temp_new();
2933 tcg_gen_ext32u_tl(t0, arg1);
2934 tcg_gen_bswap32_tl(t0, t0);
2935 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2936 tcg_temp_free(t0);
2937 } else {
2938 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2939 }
2940 }
2941 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2942
2943 #if defined(TARGET_PPC64)
2944 /* stdbrx */
2945 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2946 {
2947 if (likely(!ctx->le_mode)) {
2948 TCGv t0 = tcg_temp_new();
2949 tcg_gen_bswap64_tl(t0, arg1);
2950 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2951 tcg_temp_free(t0);
2952 } else {
2953 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2954 }
2955 }
2956 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
2957 #endif /* TARGET_PPC64 */
2958
2959 /*** Integer load and store multiple ***/
2960
2961 /* lmw */
2962 static void gen_lmw(DisasContext *ctx)
2963 {
2964 TCGv t0;
2965 TCGv_i32 t1;
2966 gen_set_access_type(ctx, ACCESS_INT);
2967 /* NIP cannot be restored if the memory exception comes from an helper */
2968 gen_update_nip(ctx, ctx->nip - 4);
2969 t0 = tcg_temp_new();
2970 t1 = tcg_const_i32(rD(ctx->opcode));
2971 gen_addr_imm_index(ctx, t0, 0);
2972 gen_helper_lmw(cpu_env, t0, t1);
2973 tcg_temp_free(t0);
2974 tcg_temp_free_i32(t1);
2975 }
2976
2977 /* stmw */
2978 static void gen_stmw(DisasContext *ctx)
2979 {
2980 TCGv t0;
2981 TCGv_i32 t1;
2982 gen_set_access_type(ctx, ACCESS_INT);
2983 /* NIP cannot be restored if the memory exception comes from an helper */
2984 gen_update_nip(ctx, ctx->nip - 4);
2985 t0 = tcg_temp_new();
2986 t1 = tcg_const_i32(rS(ctx->opcode));
2987 gen_addr_imm_index(ctx, t0, 0);
2988 gen_helper_stmw(cpu_env, t0, t1);
2989 tcg_temp_free(t0);
2990 tcg_temp_free_i32(t1);
2991 }
2992
2993 /*** Integer load and store strings ***/
2994
2995 /* lswi */
2996 /* PowerPC32 specification says we must generate an exception if
2997 * rA is in the range of registers to be loaded.
2998 * In an other hand, IBM says this is valid, but rA won't be loaded.
2999 * For now, I'll follow the spec...
3000 */
3001 static void gen_lswi(DisasContext *ctx)
3002 {
3003 TCGv t0;
3004 TCGv_i32 t1, t2;
3005 int nb = NB(ctx->opcode);
3006 int start = rD(ctx->opcode);
3007 int ra = rA(ctx->opcode);
3008 int nr;
3009
3010 if (nb == 0)
3011 nb = 32;
3012 nr = nb / 4;
3013 if (unlikely(((start + nr) > 32 &&
3014 start <= ra && (start + nr - 32) > ra) ||
3015 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3016 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3017 return;
3018 }
3019 gen_set_access_type(ctx, ACCESS_INT);
3020 /* NIP cannot be restored if the memory exception comes from an helper */
3021 gen_update_nip(ctx, ctx->nip - 4);
3022 t0 = tcg_temp_new();
3023 gen_addr_register(ctx, t0);
3024 t1 = tcg_const_i32(nb);
3025 t2 = tcg_const_i32(start);
3026 gen_helper_lsw(cpu_env, t0, t1, t2);
3027 tcg_temp_free(t0);
3028 tcg_temp_free_i32(t1);
3029 tcg_temp_free_i32(t2);
3030 }
3031
3032 /* lswx */
3033 static void gen_lswx(DisasContext *ctx)
3034 {
3035 TCGv t0;
3036 TCGv_i32 t1, t2, t3;
3037 gen_set_access_type(ctx, ACCESS_INT);
3038 /* NIP cannot be restored if the memory exception comes from an helper */
3039 gen_update_nip(ctx, ctx->nip - 4);
3040 t0 = tcg_temp_new();
3041 gen_addr_reg_index(ctx, t0);
3042 t1 = tcg_const_i32(rD(ctx->opcode));
3043 t2 = tcg_const_i32(rA(ctx->opcode));
3044 t3 = tcg_const_i32(rB(ctx->opcode));
3045 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3046 tcg_temp_free(t0);
3047 tcg_temp_free_i32(t1);
3048 tcg_temp_free_i32(t2);
3049 tcg_temp_free_i32(t3);
3050 }
3051
3052 /* stswi */
3053 static void gen_stswi(DisasContext *ctx)
3054 {
3055 TCGv t0;
3056 TCGv_i32 t1, t2;
3057 int nb = NB(ctx->opcode);
3058 gen_set_access_type(ctx, ACCESS_INT);
3059 /* NIP cannot be restored if the memory exception comes from an helper */
3060 gen_update_nip(ctx, ctx->nip - 4);
3061 t0 = tcg_temp_new();
3062 gen_addr_register(ctx, t0);
3063 if (nb == 0)
3064 nb = 32;
3065 t1 = tcg_const_i32(nb);
3066 t2 = tcg_const_i32(rS(ctx->opcode));
3067 gen_helper_stsw(cpu_env, t0, t1, t2);
3068 tcg_temp_free(t0);
3069 tcg_temp_free_i32(t1);
3070 tcg_temp_free_i32(t2);
3071 }
3072
3073 /* stswx */
3074 static void gen_stswx(DisasContext *ctx)
3075 {
3076 TCGv t0;
3077 TCGv_i32 t1, t2;
3078 gen_set_access_type(ctx, ACCESS_INT);
3079 /* NIP cannot be restored if the memory exception comes from an helper */
3080 gen_update_nip(ctx, ctx->nip - 4);
3081 t0 = tcg_temp_new();
3082 gen_addr_reg_index(ctx, t0);
3083 t1 = tcg_temp_new_i32();
3084 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3085 tcg_gen_andi_i32(t1, t1, 0x7F);
3086 t2 = tcg_const_i32(rS(ctx->opcode));
3087 gen_helper_stsw(cpu_env, t0, t1, t2);
3088 tcg_temp_free(t0);
3089 tcg_temp_free_i32(t1);
3090 tcg_temp_free_i32(t2);
3091 }
3092
3093 /*** Memory synchronisation ***/
3094 /* eieio */
3095 static void gen_eieio(DisasContext *ctx)
3096 {
3097 }
3098
3099 /* isync */
3100 static void gen_isync(DisasContext *ctx)
3101 {
3102 gen_stop_exception(ctx);
3103 }
3104
3105 /* lwarx */
3106 static void gen_lwarx(DisasContext *ctx)
3107 {
3108 TCGv t0;
3109 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3110 gen_set_access_type(ctx, ACCESS_RES);
3111 t0 = tcg_temp_local_new();
3112 gen_addr_reg_index(ctx, t0);
3113 gen_check_align(ctx, t0, 0x03);
3114 gen_qemu_ld32u(ctx, gpr, t0);
3115 tcg_gen_mov_tl(cpu_reserve, t0);
3116 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3117 tcg_temp_free(t0);
3118 }
3119
3120 #if defined(CONFIG_USER_ONLY)
3121 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3122 int reg, int size)
3123 {
3124 TCGv t0 = tcg_temp_new();
3125 uint32_t save_exception = ctx->exception;
3126
3127 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3128 tcg_gen_movi_tl(t0, (size << 5) | reg);
3129 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3130 tcg_temp_free(t0);
3131 gen_update_nip(ctx, ctx->nip-4);
3132 ctx->exception = POWERPC_EXCP_BRANCH;
3133 gen_exception(ctx, POWERPC_EXCP_STCX);
3134 ctx->exception = save_exception;
3135 }
3136 #endif
3137
3138 /* stwcx. */
3139 static void gen_stwcx_(DisasContext *ctx)
3140 {
3141 TCGv t0;
3142 gen_set_access_type(ctx, ACCESS_RES);
3143 t0 = tcg_temp_local_new();
3144 gen_addr_reg_index(ctx, t0);
3145 gen_check_align(ctx, t0, 0x03);
3146 #if defined(CONFIG_USER_ONLY)
3147 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3148 #else
3149 {
3150 int l1;
3151
3152 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3153 l1 = gen_new_label();
3154 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3155 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3156 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3157 gen_set_label(l1);
3158 tcg_gen_movi_tl(cpu_reserve, -1);
3159 }
3160 #endif
3161 tcg_temp_free(t0);
3162 }
3163
3164 #if defined(TARGET_PPC64)
3165 /* ldarx */
3166 static void gen_ldarx(DisasContext *ctx)
3167 {
3168 TCGv t0;
3169 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3170 gen_set_access_type(ctx, ACCESS_RES);
3171 t0 = tcg_temp_local_new();
3172 gen_addr_reg_index(ctx, t0);
3173 gen_check_align(ctx, t0, 0x07);
3174 gen_qemu_ld64(ctx, gpr, t0);
3175 tcg_gen_mov_tl(cpu_reserve, t0);
3176 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3177 tcg_temp_free(t0);
3178 }
3179
3180 /* stdcx. */
3181 static void gen_stdcx_(DisasContext *ctx)
3182 {
3183 TCGv t0;
3184 gen_set_access_type(ctx, ACCESS_RES);
3185 t0 = tcg_temp_local_new();
3186 gen_addr_reg_index(ctx, t0);
3187 gen_check_align(ctx, t0, 0x07);
3188 #if defined(CONFIG_USER_ONLY)
3189 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3190 #else
3191 {
3192 int l1;
3193 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3194 l1 = gen_new_label();
3195 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3196 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3197 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3198 gen_set_label(l1);
3199 tcg_gen_movi_tl(cpu_reserve, -1);
3200 }
3201 #endif
3202 tcg_temp_free(t0);
3203 }
3204 #endif /* defined(TARGET_PPC64) */
3205
3206 /* sync */
3207 static void gen_sync(DisasContext *ctx)
3208 {
3209 }
3210
3211 /* wait */
3212 static void gen_wait(DisasContext *ctx)
3213 {
3214 TCGv_i32 t0 = tcg_temp_new_i32();
3215 tcg_gen_st_i32(t0, cpu_env,
3216 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3217 tcg_temp_free_i32(t0);
3218 /* Stop translation, as the CPU is supposed to sleep from now */
3219 gen_exception_err(ctx, EXCP_HLT, 1);
3220 }
3221
3222 /*** Floating-point load ***/
3223 #define GEN_LDF(name, ldop, opc, type) \
3224 static void glue(gen_, name)(DisasContext *ctx) \
3225 { \
3226 TCGv EA; \
3227 if (unlikely(!ctx->fpu_enabled)) { \
3228 gen_exception(ctx, POWERPC_EXCP_FPU); \
3229 return; \
3230 } \
3231 gen_set_access_type(ctx, ACCESS_FLOAT); \
3232 EA = tcg_temp_new(); \
3233 gen_addr_imm_index(ctx, EA, 0); \
3234 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3235 tcg_temp_free(EA); \
3236 }
3237
3238 #define GEN_LDUF(name, ldop, opc, type) \
3239 static void glue(gen_, name##u)(DisasContext *ctx) \
3240 { \
3241 TCGv EA; \
3242 if (unlikely(!ctx->fpu_enabled)) { \
3243 gen_exception(ctx, POWERPC_EXCP_FPU); \
3244 return; \
3245 } \
3246 if (unlikely(rA(ctx->opcode) == 0)) { \
3247 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3248 return; \
3249 } \
3250 gen_set_access_type(ctx, ACCESS_FLOAT); \
3251 EA = tcg_temp_new(); \
3252 gen_addr_imm_index(ctx, EA, 0); \
3253 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3254 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3255 tcg_temp_free(EA); \
3256 }
3257
3258 #define GEN_LDUXF(name, ldop, opc, type) \
3259 static void glue(gen_, name##ux)(DisasContext *ctx) \
3260 { \
3261 TCGv EA; \
3262 if (unlikely(!ctx->fpu_enabled)) { \
3263 gen_exception(ctx, POWERPC_EXCP_FPU); \
3264 return; \
3265 } \
3266 if (unlikely(rA(ctx->opcode) == 0)) { \
3267 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3268 return; \
3269 } \
3270 gen_set_access_type(ctx, ACCESS_FLOAT); \
3271 EA = tcg_temp_new(); \
3272 gen_addr_reg_index(ctx, EA); \
3273 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3274 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3275 tcg_temp_free(EA); \
3276 }
3277
3278 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3279 static void glue(gen_, name##x)(DisasContext *ctx) \
3280 { \
3281 TCGv EA; \
3282 if (unlikely(!ctx->fpu_enabled)) { \
3283 gen_exception(ctx, POWERPC_EXCP_FPU); \
3284 return; \
3285 } \
3286 gen_set_access_type(ctx, ACCESS_FLOAT); \
3287 EA = tcg_temp_new(); \
3288 gen_addr_reg_index(ctx, EA); \
3289 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3290 tcg_temp_free(EA); \
3291 }
3292
3293 #define GEN_LDFS(name, ldop, op, type) \
3294 GEN_LDF(name, ldop, op | 0x20, type); \
3295 GEN_LDUF(name, ldop, op | 0x21, type); \
3296 GEN_LDUXF(name, ldop, op | 0x01, type); \
3297 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3298
3299 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3300 {
3301 TCGv t0 = tcg_temp_new();
3302 TCGv_i32 t1 = tcg_temp_new_i32();
3303 gen_qemu_ld32u(ctx, t0, arg2);
3304 tcg_gen_trunc_tl_i32(t1, t0);
3305 tcg_temp_free(t0);
3306 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3307 tcg_temp_free_i32(t1);
3308 }
3309
3310 /* lfd lfdu lfdux lfdx */
3311 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3312 /* lfs lfsu lfsux lfsx */
3313 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3314
3315 /* lfdp */
3316 static void gen_lfdp(DisasContext *ctx)
3317 {
3318 TCGv EA;
3319 if (unlikely(!ctx->fpu_enabled)) {
3320 gen_exception(ctx, POWERPC_EXCP_FPU);
3321 return;
3322 }
3323 gen_set_access_type(ctx, ACCESS_FLOAT);
3324 EA = tcg_temp_new();
3325 gen_addr_imm_index(ctx, EA, 0); \
3326 if (unlikely(ctx->le_mode)) {
3327 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3328 tcg_gen_addi_tl(EA, EA, 8);
3329 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3330 } else {
3331 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3332 tcg_gen_addi_tl(EA, EA, 8);
3333 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3334 }
3335 tcg_temp_free(EA);
3336 }
3337
3338 /* lfdpx */
3339 static void gen_lfdpx(DisasContext *ctx)
3340 {
3341 TCGv EA;
3342 if (unlikely(!ctx->fpu_enabled)) {
3343 gen_exception(ctx, POWERPC_EXCP_FPU);
3344 return;
3345 }
3346 gen_set_access_type(ctx, ACCESS_FLOAT);
3347 EA = tcg_temp_new();
3348 gen_addr_reg_index(ctx, EA);
3349 if (unlikely(ctx->le_mode)) {
3350 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3351 tcg_gen_addi_tl(EA, EA, 8);
3352 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3353 } else {
3354 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3355 tcg_gen_addi_tl(EA, EA, 8);
3356 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3357 }
3358 tcg_temp_free(EA);
3359 }
3360
3361 /* lfiwax */
3362 static void gen_lfiwax(DisasContext *ctx)
3363 {
3364 TCGv EA;
3365 TCGv t0;
3366 if (unlikely(!ctx->fpu_enabled)) {
3367 gen_exception(ctx, POWERPC_EXCP_FPU);
3368 return;
3369 }
3370 gen_set_access_type(ctx, ACCESS_FLOAT);
3371 EA = tcg_temp_new();
3372 t0 = tcg_temp_new();
3373 gen_addr_reg_index(ctx, EA);
3374 gen_qemu_ld32s(ctx, t0, EA);
3375 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3376 tcg_temp_free(EA);
3377 tcg_temp_free(t0);
3378 }
3379
3380 /*** Floating-point store ***/
3381 #define GEN_STF(name, stop, opc, type) \
3382 static void glue(gen_, name)(DisasContext *ctx) \
3383 { \
3384 TCGv EA; \
3385 if (unlikely(!ctx->fpu_enabled)) { \
3386 gen_exception(ctx, POWERPC_EXCP_FPU); \
3387 return; \
3388 } \
3389 gen_set_access_type(ctx, ACCESS_FLOAT); \
3390 EA = tcg_temp_new(); \
3391 gen_addr_imm_index(ctx, EA, 0); \
3392 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3393 tcg_temp_free(EA); \
3394 }
3395
3396 #define GEN_STUF(name, stop, opc, type) \
3397 static void glue(gen_, name##u)(DisasContext *ctx) \
3398 { \
3399 TCGv EA; \
3400 if (unlikely(!ctx->fpu_enabled)) { \
3401 gen_exception(ctx, POWERPC_EXCP_FPU); \
3402 return; \
3403 } \
3404 if (unlikely(rA(ctx->opcode) == 0)) { \
3405 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3406 return; \
3407 } \
3408 gen_set_access_type(ctx, ACCESS_FLOAT); \
3409 EA = tcg_temp_new(); \
3410 gen_addr_imm_index(ctx, EA, 0); \
3411 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3412 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3413 tcg_temp_free(EA); \
3414 }
3415
3416 #define GEN_STUXF(name, stop, opc, type) \
3417 static void glue(gen_, name##ux)(DisasContext *ctx) \
3418 { \
3419 TCGv EA; \
3420 if (unlikely(!ctx->fpu_enabled)) { \
3421 gen_exception(ctx, POWERPC_EXCP_FPU); \
3422 return; \
3423 } \
3424 if (unlikely(rA(ctx->opcode) == 0)) { \
3425 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3426 return; \
3427 } \
3428 gen_set_access_type(ctx, ACCESS_FLOAT); \
3429 EA = tcg_temp_new(); \
3430 gen_addr_reg_index(ctx, EA); \
3431 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3432 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3433 tcg_temp_free(EA); \
3434 }
3435
3436 #define GEN_STXF(name, stop, opc2, opc3, type) \
3437 static void glue(gen_, name##x)(DisasContext *ctx) \
3438 { \
3439 TCGv EA; \
3440 if (unlikely(!ctx->fpu_enabled)) { \
3441 gen_exception(ctx, POWERPC_EXCP_FPU); \
3442 return; \
3443 } \
3444 gen_set_access_type(ctx, ACCESS_FLOAT); \
3445 EA = tcg_temp_new(); \
3446 gen_addr_reg_index(ctx, EA); \
3447 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3448 tcg_temp_free(EA); \
3449 }
3450
3451 #define GEN_STFS(name, stop, op, type) \
3452 GEN_STF(name, stop, op | 0x20, type); \
3453 GEN_STUF(name, stop, op | 0x21, type); \
3454 GEN_STUXF(name, stop, op | 0x01, type); \
3455 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3456
3457 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3458 {
3459 TCGv_i32 t0 = tcg_temp_new_i32();
3460 TCGv t1 = tcg_temp_new();
3461 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3462 tcg_gen_extu_i32_tl(t1, t0);
3463 tcg_temp_free_i32(t0);
3464 gen_qemu_st32(ctx, t1, arg2);
3465 tcg_temp_free(t1);
3466 }
3467
3468 /* stfd stfdu stfdux stfdx */
3469 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3470 /* stfs stfsu stfsux stfsx */
3471 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3472
3473 /* stfdp */
3474 static void gen_stfdp(DisasContext *ctx)
3475 {
3476 TCGv EA;
3477 if (unlikely(!ctx->fpu_enabled)) {
3478 gen_exception(ctx, POWERPC_EXCP_FPU);
3479 return;
3480 }
3481 gen_set_access_type(ctx, ACCESS_FLOAT);
3482 EA = tcg_temp_new();
3483 gen_addr_imm_index(ctx, EA, 0); \
3484 if (unlikely(ctx->le_mode)) {
3485 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3486 tcg_gen_addi_tl(EA, EA, 8);
3487 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3488 } else {
3489 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3490 tcg_gen_addi_tl(EA, EA, 8);
3491 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3492 }
3493 tcg_temp_free(EA);
3494 }
3495
3496 /* stfdpx */
3497 static void gen_stfdpx(DisasContext *ctx)
3498 {
3499 TCGv EA;
3500 if (unlikely(!ctx->fpu_enabled)) {
3501 gen_exception(ctx, POWERPC_EXCP_FPU);
3502 return;
3503 }
3504 gen_set_access_type(ctx, ACCESS_FLOAT);
3505 EA = tcg_temp_new();
3506 gen_addr_reg_index(ctx, EA);
3507 if (unlikely(ctx->le_mode)) {
3508 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3509 tcg_gen_addi_tl(EA, EA, 8);
3510 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3511 } else {
3512 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3513 tcg_gen_addi_tl(EA, EA, 8);
3514 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3515 }
3516 tcg_temp_free(EA);
3517 }
3518
3519 /* Optional: */
3520 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3521 {
3522 TCGv t0 = tcg_temp_new();
3523 tcg_gen_trunc_i64_tl(t0, arg1),
3524 gen_qemu_st32(ctx, t0, arg2);
3525 tcg_temp_free(t0);
3526 }
3527 /* stfiwx */
3528 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3529
3530 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3531 {
3532 #if defined(TARGET_PPC64)
3533 if (ctx->has_cfar)
3534 tcg_gen_movi_tl(cpu_cfar, nip);
3535 #endif
3536 }
3537
3538 /*** Branch ***/
3539 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3540 {
3541 TranslationBlock *tb;
3542 tb = ctx->tb;
3543 if (NARROW_MODE(ctx)) {
3544 dest = (uint32_t) dest;
3545 }
3546 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3547 likely(!ctx->singlestep_enabled)) {
3548 tcg_gen_goto_tb(n);
3549 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3550 tcg_gen_exit_tb((uintptr_t)tb + n);
3551 } else {
3552 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3553 if (unlikely(ctx->singlestep_enabled)) {
3554 if ((ctx->singlestep_enabled &
3555 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3556 (ctx->exception == POWERPC_EXCP_BRANCH ||
3557 ctx->exception == POWERPC_EXCP_TRACE)) {
3558 target_ulong tmp = ctx->nip;
3559 ctx->nip = dest;
3560 gen_exception(ctx, POWERPC_EXCP_TRACE);
3561 ctx->nip = tmp;
3562 }
3563 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3564 gen_debug_exception(ctx);
3565 }
3566 }
3567 tcg_gen_exit_tb(0);
3568 }
3569 }
3570
3571 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3572 {
3573 if (NARROW_MODE(ctx)) {
3574 nip = (uint32_t)nip;
3575 }
3576 tcg_gen_movi_tl(cpu_lr, nip);
3577 }
3578
3579 /* b ba bl bla */
3580 static void gen_b(DisasContext *ctx)
3581 {
3582 target_ulong li, target;
3583
3584 ctx->exception = POWERPC_EXCP_BRANCH;
3585 /* sign extend LI */
3586 li = LI(ctx->opcode);
3587 li = (li ^ 0x02000000) - 0x02000000;
3588 if (likely(AA(ctx->opcode) == 0)) {
3589 target = ctx->nip + li - 4;
3590 } else {
3591 target = li;
3592 }
3593 if (LK(ctx->opcode)) {
3594 gen_setlr(ctx, ctx->nip);
3595 }
3596 gen_update_cfar(ctx, ctx->nip);
3597 gen_goto_tb(ctx, 0, target);
3598 }
3599
3600 #define BCOND_IM 0
3601 #define BCOND_LR 1
3602 #define BCOND_CTR 2
3603
3604 static inline void gen_bcond(DisasContext *ctx, int type)
3605 {
3606 uint32_t bo = BO(ctx->opcode);
3607 int l1;
3608 TCGv target;
3609
3610 ctx->exception = POWERPC_EXCP_BRANCH;
3611 if (type == BCOND_LR || type == BCOND_CTR) {
3612 target = tcg_temp_local_new();
3613 if (type == BCOND_CTR)
3614 tcg_gen_mov_tl(target, cpu_ctr);
3615 else
3616 tcg_gen_mov_tl(target, cpu_lr);
3617 } else {
3618 TCGV_UNUSED(target);
3619 }
3620 if (LK(ctx->opcode))
3621 gen_setlr(ctx, ctx->nip);
3622 l1 = gen_new_label();
3623 if ((bo & 0x4) == 0) {
3624 /* Decrement and test CTR */
3625 TCGv temp = tcg_temp_new();
3626 if (unlikely(type == BCOND_CTR)) {
3627 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3628 return;
3629 }
3630 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3631 if (NARROW_MODE(ctx)) {
3632 tcg_gen_ext32u_tl(temp, cpu_ctr);
3633 } else {
3634 tcg_gen_mov_tl(temp, cpu_ctr);
3635 }
3636 if (bo & 0x2) {
3637 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3638 } else {
3639 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3640 }
3641 tcg_temp_free(temp);
3642 }
3643 if ((bo & 0x10) == 0) {
3644 /* Test CR */
3645 uint32_t bi = BI(ctx->opcode);
3646 uint32_t mask = 1 << (3 - (bi & 0x03));
3647 TCGv_i32 temp = tcg_temp_new_i32();
3648
3649 if (bo & 0x8) {
3650 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3651 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3652 } else {
3653 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3654 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3655 }
3656 tcg_temp_free_i32(temp);
3657 }
3658 gen_update_cfar(ctx, ctx->nip);
3659 if (type == BCOND_IM) {
3660 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3661 if (likely(AA(ctx->opcode) == 0)) {
3662 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3663 } else {
3664 gen_goto_tb(ctx, 0, li);
3665 }
3666 gen_set_label(l1);
3667 gen_goto_tb(ctx, 1, ctx->nip);
3668 } else {
3669 if (NARROW_MODE(ctx)) {
3670 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3671 } else {
3672 tcg_gen_andi_tl(cpu_nip, target, ~3);
3673 }
3674 tcg_gen_exit_tb(0);
3675 gen_set_label(l1);
3676 gen_update_nip(ctx, ctx->nip);
3677 tcg_gen_exit_tb(0);
3678 }
3679 }
3680
3681 static void gen_bc(DisasContext *ctx)
3682 {
3683 gen_bcond(ctx, BCOND_IM);
3684 }
3685
3686 static void gen_bcctr(DisasContext *ctx)
3687 {
3688 gen_bcond(ctx, BCOND_CTR);
3689 }
3690
3691 static void gen_bclr(DisasContext *ctx)
3692 {
3693 gen_bcond(ctx, BCOND_LR);
3694 }
3695
3696 /*** Condition register logical ***/
3697 #define GEN_CRLOGIC(name, tcg_op, opc) \
3698 static void glue(gen_, name)(DisasContext *ctx) \
3699 { \
3700 uint8_t bitmask; \
3701 int sh; \
3702 TCGv_i32 t0, t1; \
3703 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3704 t0 = tcg_temp_new_i32(); \
3705 if (sh > 0) \
3706 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3707 else if (sh < 0) \
3708 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3709 else \
3710 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3711 t1 = tcg_temp_new_i32(); \
3712 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3713 if (sh > 0) \
3714 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3715 else if (sh < 0) \
3716 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3717 else \
3718 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3719 tcg_op(t0, t0, t1); \
3720 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3721 tcg_gen_andi_i32(t0, t0, bitmask); \
3722 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3723 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3724 tcg_temp_free_i32(t0); \
3725 tcg_temp_free_i32(t1); \
3726 }
3727
3728 /* crand */
3729 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3730 /* crandc */
3731 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3732 /* creqv */
3733 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3734 /* crnand */
3735 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3736 /* crnor */
3737 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3738 /* cror */
3739 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3740 /* crorc */
3741 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3742 /* crxor */
3743 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3744
3745 /* mcrf */
3746 static void gen_mcrf(DisasContext *ctx)
3747 {
3748 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3749 }
3750
3751 /*** System linkage ***/
3752
3753 /* rfi (mem_idx only) */
3754 static void gen_rfi(DisasContext *ctx)
3755 {
3756 #if defined(CONFIG_USER_ONLY)
3757 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3758 #else
3759 /* Restore CPU state */
3760 if (unlikely(!ctx->mem_idx)) {
3761 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3762 return;
3763 }
3764 gen_update_cfar(ctx, ctx->nip);
3765 gen_helper_rfi(cpu_env);
3766 gen_sync_exception(ctx);
3767 #endif
3768 }
3769
3770 #if defined(TARGET_PPC64)
3771 static void gen_rfid(DisasContext *ctx)
3772 {
3773 #if defined(CONFIG_USER_ONLY)
3774 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3775 #else
3776 /* Restore CPU state */
3777 if (unlikely(!ctx->mem_idx)) {
3778 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3779 return;
3780 }
3781 gen_update_cfar(ctx, ctx->nip);
3782 gen_helper_rfid(cpu_env);
3783 gen_sync_exception(ctx);
3784 #endif
3785 }
3786
3787 static void gen_hrfid(DisasContext *ctx)
3788 {
3789 #if defined(CONFIG_USER_ONLY)
3790 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3791 #else
3792 /* Restore CPU state */
3793 if (unlikely(ctx->mem_idx <= 1)) {
3794 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3795 return;
3796 }
3797 gen_helper_hrfid(cpu_env);
3798 gen_sync_exception(ctx);
3799 #endif
3800 }
3801 #endif
3802
3803 /* sc */
3804 #if defined(CONFIG_USER_ONLY)
3805 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3806 #else
3807 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3808 #endif
3809 static void gen_sc(DisasContext *ctx)
3810 {
3811 uint32_t lev;
3812
3813 lev = (ctx->opcode >> 5) & 0x7F;
3814 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3815 }
3816
3817 /*** Trap ***/
3818
3819 /* tw */
3820 static void gen_tw(DisasContext *ctx)
3821 {
3822 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3823 /* Update the nip since this might generate a trap exception */
3824 gen_update_nip(ctx, ctx->nip);
3825 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3826 t0);
3827 tcg_temp_free_i32(t0);
3828 }
3829
3830 /* twi */
3831 static void gen_twi(DisasContext *ctx)
3832 {
3833 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3834 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3835 /* Update the nip since this might generate a trap exception */
3836 gen_update_nip(ctx, ctx->nip);
3837 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3838 tcg_temp_free(t0);
3839 tcg_temp_free_i32(t1);
3840 }
3841
3842 #if defined(TARGET_PPC64)
3843 /* td */
3844 static void gen_td(DisasContext *ctx)
3845 {
3846 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3847 /* Update the nip since this might generate a trap exception */
3848 gen_update_nip(ctx, ctx->nip);
3849 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3850 t0);
3851 tcg_temp_free_i32(t0);
3852 }
3853
3854 /* tdi */
3855 static void gen_tdi(DisasContext *ctx)
3856 {
3857 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3858 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3859 /* Update the nip since this might generate a trap exception */
3860 gen_update_nip(ctx, ctx->nip);
3861 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3862 tcg_temp_free(t0);
3863 tcg_temp_free_i32(t1);
3864 }
3865 #endif
3866
3867 /*** Processor control ***/
3868
3869 static void gen_read_xer(TCGv dst)
3870 {
3871 TCGv t0 = tcg_temp_new();
3872 TCGv t1 = tcg_temp_new();
3873 TCGv t2 = tcg_temp_new();
3874 tcg_gen_mov_tl(dst, cpu_xer);
3875 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3876 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3877 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3878 tcg_gen_or_tl(t0, t0, t1);
3879 tcg_gen_or_tl(dst, dst, t2);
3880 tcg_gen_or_tl(dst, dst, t0);
3881 tcg_temp_free(t0);
3882 tcg_temp_free(t1);
3883 tcg_temp_free(t2);
3884 }
3885
3886 static void gen_write_xer(TCGv src)
3887 {
3888 tcg_gen_andi_tl(cpu_xer, src,
3889 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3890 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3891 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3892 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3893 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3894 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3895 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3896 }
3897
3898 /* mcrxr */
3899 static void gen_mcrxr(DisasContext *ctx)
3900 {
3901 TCGv_i32 t0 = tcg_temp_new_i32();
3902 TCGv_i32 t1 = tcg_temp_new_i32();
3903 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3904
3905 tcg_gen_trunc_tl_i32(t0, cpu_so);
3906 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3907 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3908 tcg_gen_shri_i32(t0, t0, 2);
3909 tcg_gen_shri_i32(t1, t1, 1);
3910 tcg_gen_or_i32(dst, dst, t0);
3911 tcg_gen_or_i32(dst, dst, t1);
3912 tcg_temp_free_i32(t0);
3913 tcg_temp_free_i32(t1);
3914
3915 tcg_gen_movi_tl(cpu_so, 0);
3916 tcg_gen_movi_tl(cpu_ov, 0);
3917 tcg_gen_movi_tl(cpu_ca, 0);
3918 }
3919
3920 /* mfcr mfocrf */
3921 static void gen_mfcr(DisasContext *ctx)
3922 {
3923 uint32_t crm, crn;
3924
3925 if (likely(ctx->opcode & 0x00100000)) {
3926 crm = CRM(ctx->opcode);
3927 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3928 crn = ctz32 (crm);
3929 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3930 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3931 cpu_gpr[rD(ctx->opcode)], crn * 4);
3932 }
3933 } else {
3934 TCGv_i32 t0 = tcg_temp_new_i32();
3935 tcg_gen_mov_i32(t0, cpu_crf[0]);
3936 tcg_gen_shli_i32(t0, t0, 4);
3937 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3938 tcg_gen_shli_i32(t0, t0, 4);
3939 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3940 tcg_gen_shli_i32(t0, t0, 4);
3941 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3942 tcg_gen_shli_i32(t0, t0, 4);
3943 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3944 tcg_gen_shli_i32(t0, t0, 4);
3945 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3946 tcg_gen_shli_i32(t0, t0, 4);
3947 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3948 tcg_gen_shli_i32(t0, t0, 4);
3949 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3950 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3951 tcg_temp_free_i32(t0);
3952 }
3953 }
3954
3955 /* mfmsr */
3956 static void gen_mfmsr(DisasContext *ctx)
3957 {
3958 #if defined(CONFIG_USER_ONLY)
3959 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3960 #else
3961 if (unlikely(!ctx->mem_idx)) {
3962 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3963 return;
3964 }
3965 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3966 #endif
3967 }
3968
3969 static void spr_noaccess(void *opaque, int gprn, int sprn)
3970 {
3971 #if 0
3972 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3973 printf("ERROR: try to access SPR %d !\n", sprn);
3974 #endif
3975 }
3976 #define SPR_NOACCESS (&spr_noaccess)
3977
3978 /* mfspr */
3979 static inline void gen_op_mfspr(DisasContext *ctx)
3980 {
3981 void (*read_cb)(void *opaque, int gprn, int sprn);
3982 uint32_t sprn = SPR(ctx->opcode);
3983
3984 #if !defined(CONFIG_USER_ONLY)
3985 if (ctx->mem_idx == 2)
3986 read_cb = ctx->spr_cb[sprn].hea_read;
3987 else if (ctx->mem_idx)
3988 read_cb = ctx->spr_cb[sprn].oea_read;
3989 else
3990 #endif
3991 read_cb = ctx->spr_cb[sprn].uea_read;
3992 if (likely(read_cb != NULL)) {
3993 if (likely(read_cb != SPR_NOACCESS)) {
3994 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3995 } else {
3996 /* Privilege exception */
3997 /* This is a hack to avoid warnings when running Linux:
3998 * this OS breaks the PowerPC virtualisation model,
3999 * allowing userland application to read the PVR
4000 */
4001 if (sprn != SPR_PVR) {
4002 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4003 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4004 printf("Trying to read privileged spr %d (0x%03x) at "
4005 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4006 }
4007 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4008 }
4009 } else {
4010 /* Not defined */
4011 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4012 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4013 printf("Trying to read invalid spr %d (0x%03x) at "
4014 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4015 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4016 }
4017 }
4018
4019 static void gen_mfspr(DisasContext *ctx)
4020 {
4021 gen_op_mfspr(ctx);
4022 }
4023
4024 /* mftb */
4025 static void gen_mftb(DisasContext *ctx)
4026 {
4027 gen_op_mfspr(ctx);
4028 }
4029
4030 /* mtcrf mtocrf*/
4031 static void gen_mtcrf(DisasContext *ctx)
4032 {
4033 uint32_t crm, crn;
4034
4035 crm = CRM(ctx->opcode);
4036 if (likely((ctx->opcode & 0x00100000))) {
4037 if (crm && ((crm & (crm - 1)) == 0)) {
4038 TCGv_i32 temp = tcg_temp_new_i32();
4039 crn = ctz32 (crm);
4040 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4041 tcg_gen_shri_i32(temp, temp, crn * 4);
4042 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4043 tcg_temp_free_i32(temp);
4044 }
4045 } else {
4046 TCGv_i32 temp = tcg_temp_new_i32();
4047 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4048 for (crn = 0 ; crn < 8 ; crn++) {
4049 if (crm & (1 << crn)) {
4050 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4051 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4052 }
4053 }
4054 tcg_temp_free_i32(temp);
4055 }
4056 }
4057
4058 /* mtmsr */
4059 #if defined(TARGET_PPC64)
4060 static void gen_mtmsrd(DisasContext *ctx)
4061 {
4062 #if defined(CONFIG_USER_ONLY)
4063 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4064 #else
4065 if (unlikely(!ctx->mem_idx)) {
4066 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4067 return;
4068 }
4069 if (ctx->opcode & 0x00010000) {
4070 /* Special form that does not need any synchronisation */
4071 TCGv t0 = tcg_temp_new();
4072 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4073 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4074 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4075 tcg_temp_free(t0);
4076 } else {
4077 /* XXX: we need to update nip before the store
4078 * if we enter power saving mode, we will exit the loop
4079 * directly from ppc_store_msr
4080 */
4081 gen_update_nip(ctx, ctx->nip);
4082 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4083 /* Must stop the translation as machine state (may have) changed */
4084 /* Note that mtmsr is not always defined as context-synchronizing */
4085 gen_stop_exception(ctx);
4086 }
4087 #endif
4088 }
4089 #endif
4090
4091 static void gen_mtmsr(DisasContext *ctx)
4092 {
4093 #if defined(CONFIG_USER_ONLY)
4094 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4095 #else
4096 if (unlikely(!ctx->mem_idx)) {
4097 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4098 return;
4099 }
4100 if (ctx->opcode & 0x00010000) {
4101 /* Special form that does not need any synchronisation */
4102 TCGv t0 = tcg_temp_new();
4103 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4104 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4105 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4106 tcg_temp_free(t0);
4107 } else {
4108 TCGv msr = tcg_temp_new();
4109
4110 /* XXX: we need to update nip before the store
4111 * if we enter power saving mode, we will exit the loop
4112 * directly from ppc_store_msr
4113 */
4114 gen_update_nip(ctx, ctx->nip);
4115 #if defined(TARGET_PPC64)
4116 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4117 #else
4118 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4119 #endif
4120 gen_helper_store_msr(cpu_env, msr);
4121 /* Must stop the translation as machine state (may have) changed */
4122 /* Note that mtmsr is not always defined as context-synchronizing */
4123 gen_stop_exception(ctx);
4124 }
4125 #endif
4126 }
4127
4128 /* mtspr */
4129 static void gen_mtspr(DisasContext *ctx)
4130 {
4131 void (*write_cb)(void *opaque, int sprn, int gprn);
4132 uint32_t sprn = SPR(ctx->opcode);
4133
4134 #if !defined(CONFIG_USER_ONLY)
4135 if (ctx->mem_idx == 2)
4136 write_cb = ctx->spr_cb[sprn].hea_write;
4137 else if (ctx->mem_idx)
4138 write_cb = ctx->spr_cb[sprn].oea_write;
4139 else
4140 #endif
4141 write_cb = ctx->spr_cb[sprn].uea_write;
4142 if (likely(write_cb != NULL)) {
4143 if (likely(write_cb != SPR_NOACCESS)) {
4144 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4145 } else {
4146 /* Privilege exception */
4147 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4148 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4149 printf("Trying to write privileged spr %d (0x%03x) at "
4150 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4151 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4152 }
4153 } else {
4154 /* Not defined */
4155 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4156 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4157 printf("Trying to write invalid spr %d (0x%03x) at "
4158 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4159 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4160 }
4161 }
4162
4163 /*** Cache management ***/
4164
4165 /* dcbf */
4166 static void gen_dcbf(DisasContext *ctx)
4167 {
4168 /* XXX: specification says this is treated as a load by the MMU */
4169 TCGv t0;
4170 gen_set_access_type(ctx, ACCESS_CACHE);
4171 t0 = tcg_temp_new();
4172 gen_addr_reg_index(ctx, t0);
4173 gen_qemu_ld8u(ctx, t0, t0);
4174 tcg_temp_free(t0);
4175 }
4176
4177 /* dcbi (Supervisor only) */
4178 static void gen_dcbi(DisasContext *ctx)
4179 {
4180 #if defined(CONFIG_USER_ONLY)
4181 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4182 #else
4183 TCGv EA, val;
4184 if (unlikely(!ctx->mem_idx)) {
4185 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4186 return;
4187 }
4188 EA = tcg_temp_new();
4189 gen_set_access_type(ctx, ACCESS_CACHE);
4190 gen_addr_reg_index(ctx, EA);
4191 val = tcg_temp_new();
4192 /* XXX: specification says this should be treated as a store by the MMU */
4193 gen_qemu_ld8u(ctx, val, EA);
4194 gen_qemu_st8(ctx, val, EA);
4195 tcg_temp_free(val);
4196 tcg_temp_free(EA);
4197 #endif
4198 }
4199
4200 /* dcdst */
4201 static void gen_dcbst(DisasContext *ctx)
4202 {
4203 /* XXX: specification say this is treated as a load by the MMU */
4204 TCGv t0;
4205 gen_set_access_type(ctx, ACCESS_CACHE);
4206 t0 = tcg_temp_new();
4207 gen_addr_reg_index(ctx, t0);
4208 gen_qemu_ld8u(ctx, t0, t0);
4209 tcg_temp_free(t0);
4210 }
4211
4212 /* dcbt */
4213 static void gen_dcbt(DisasContext *ctx)
4214 {
4215 /* interpreted as no-op */
4216 /* XXX: specification say this is treated as a load by the MMU
4217 * but does not generate any exception
4218 */
4219 }
4220
4221 /* dcbtst */
4222 static void gen_dcbtst(DisasContext *ctx)
4223 {
4224 /* interpreted as no-op */
4225 /* XXX: specification say this is treated as a load by the MMU
4226 * but does not generate any exception
4227 */
4228 }
4229
4230 /* dcbz */
4231 static void gen_dcbz(DisasContext *ctx)
4232 {
4233 TCGv tcgv_addr;
4234 TCGv_i32 tcgv_is_dcbzl;
4235 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4236
4237 gen_set_access_type(ctx, ACCESS_CACHE);
4238 /* NIP cannot be restored if the memory exception comes from an helper */
4239 gen_update_nip(ctx, ctx->nip - 4);
4240 tcgv_addr = tcg_temp_new();
4241 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4242
4243 gen_addr_reg_index(ctx, tcgv_addr);
4244 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4245
4246 tcg_temp_free(tcgv_addr);
4247 tcg_temp_free_i32(tcgv_is_dcbzl);
4248 }
4249
4250 /* dst / dstt */
4251 static void gen_dst(DisasContext *ctx)
4252 {
4253 if (rA(ctx->opcode) == 0) {
4254 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4255 } else {
4256 /* interpreted as no-op */
4257 }
4258 }
4259
4260 /* dstst /dststt */
4261 static void gen_dstst(DisasContext *ctx)
4262 {
4263 if (rA(ctx->opcode) == 0) {
4264 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4265 } else {
4266 /* interpreted as no-op */
4267 }
4268
4269 }
4270
4271 /* dss / dssall */
4272 static void gen_dss(DisasContext *ctx)
4273 {
4274 /* interpreted as no-op */
4275 }
4276
4277 /* icbi */
4278 static void gen_icbi(DisasContext *ctx)
4279 {
4280 TCGv t0;
4281 gen_set_access_type(ctx, ACCESS_CACHE);
4282 /* NIP cannot be restored if the memory exception comes from an helper */
4283 gen_update_nip(ctx, ctx->nip - 4);
4284 t0 = tcg_temp_new();
4285 gen_addr_reg_index(ctx, t0);
4286 gen_helper_icbi(cpu_env, t0);
4287 tcg_temp_free(t0);
4288 }
4289
4290 /* Optional: */
4291 /* dcba */
4292 static void gen_dcba(DisasContext *ctx)
4293 {
4294 /* interpreted as no-op */
4295 /* XXX: specification say this is treated as a store by the MMU
4296 * but does not generate any exception
4297 */
4298 }
4299
4300 /*** Segment register manipulation ***/
4301 /* Supervisor only: */
4302
4303 /* mfsr */
4304 static void gen_mfsr(DisasContext *ctx)
4305 {
4306 #if defined(CONFIG_USER_ONLY)
4307 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4308 #else
4309 TCGv t0;
4310 if (unlikely(!ctx->mem_idx)) {
4311 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4312 return;
4313 }
4314 t0 = tcg_const_tl(SR(ctx->opcode));
4315 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4316 tcg_temp_free(t0);
4317 #endif
4318 }
4319
4320 /* mfsrin */
4321 static void gen_mfsrin(DisasContext *ctx)
4322 {
4323 #if defined(CONFIG_USER_ONLY)
4324 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4325 #else
4326 TCGv t0;
4327 if (unlikely(!ctx->mem_idx)) {
4328 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4329 return;
4330 }
4331 t0 = tcg_temp_new();
4332 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4333 tcg_gen_andi_tl(t0, t0, 0xF);
4334 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4335 tcg_temp_free(t0);
4336 #endif
4337 }
4338
4339 /* mtsr */
4340 static void gen_mtsr(DisasContext *ctx)
4341 {
4342 #if defined(CONFIG_USER_ONLY)
4343 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4344 #else
4345 TCGv t0;
4346 if (unlikely(!ctx->mem_idx)) {
4347 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4348 return;
4349 }
4350 t0 = tcg_const_tl(SR(ctx->opcode));
4351 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4352 tcg_temp_free(t0);
4353 #endif
4354 }
4355
4356 /* mtsrin */
4357 static void gen_mtsrin(DisasContext *ctx)
4358 {
4359 #if defined(CONFIG_USER_ONLY)
4360 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4361 #else
4362 TCGv t0;
4363 if (unlikely(!ctx->mem_idx)) {
4364 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4365 return;
4366 }
4367 t0 = tcg_temp_new();
4368 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4369 tcg_gen_andi_tl(t0, t0, 0xF);
4370 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4371 tcg_temp_free(t0);
4372 #endif
4373 }
4374
4375 #if defined(TARGET_PPC64)
4376 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4377
4378 /* mfsr */
4379 static void gen_mfsr_64b(DisasContext *ctx)
4380 {
4381 #if defined(CONFIG_USER_ONLY)
4382 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4383 #else
4384 TCGv t0;
4385 if (unlikely(!ctx->mem_idx)) {
4386 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4387 return;
4388 }
4389 t0 = tcg_const_tl(SR(ctx->opcode));
4390 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4391 tcg_temp_free(t0);
4392 #endif
4393 }
4394
4395 /* mfsrin */
4396 static void gen_mfsrin_64b(DisasContext *ctx)
4397 {
4398 #if defined(CONFIG_USER_ONLY)
4399 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4400 #else
4401 TCGv t0;
4402 if (unlikely(!ctx->mem_idx)) {
4403 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4404 return;
4405 }
4406 t0 = tcg_temp_new();
4407 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4408 tcg_gen_andi_tl(t0, t0, 0xF);
4409 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4410 tcg_temp_free(t0);
4411 #endif
4412 }
4413
4414 /* mtsr */
4415 static void gen_mtsr_64b(DisasContext *ctx)
4416 {
4417 #if defined(CONFIG_USER_ONLY)
4418 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4419 #else
4420 TCGv t0;
4421 if (unlikely(!ctx->mem_idx)) {
4422 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4423 return;
4424 }
4425 t0 = tcg_const_tl(SR(ctx->opcode));
4426 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4427 tcg_temp_free(t0);
4428 #endif
4429 }
4430
4431 /* mtsrin */
4432 static void gen_mtsrin_64b(DisasContext *ctx)
4433 {
4434 #if defined(CONFIG_USER_ONLY)
4435 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4436 #else
4437 TCGv t0;
4438 if (unlikely(!ctx->mem_idx)) {
4439 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4440 return;
4441 }
4442 t0 = tcg_temp_new();
4443 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4444 tcg_gen_andi_tl(t0, t0, 0xF);
4445 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4446 tcg_temp_free(t0);
4447 #endif
4448 }
4449
4450 /* slbmte */
4451 static void gen_slbmte(DisasContext *ctx)
4452 {
4453 #if defined(CONFIG_USER_ONLY)
4454 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4455 #else
4456 if (unlikely(!ctx->mem_idx)) {
4457 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4458 return;
4459 }
4460 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4461 cpu_gpr[rS(ctx->opcode)]);
4462 #endif
4463 }
4464
4465 static void gen_slbmfee(DisasContext *ctx)
4466 {
4467 #if defined(CONFIG_USER_ONLY)
4468 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4469 #else
4470 if (unlikely(!ctx->mem_idx)) {
4471 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4472 return;
4473 }
4474 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4475 cpu_gpr[rB(ctx->opcode)]);
4476 #endif
4477 }
4478
4479 static void gen_slbmfev(DisasContext *ctx)
4480 {
4481 #if defined(CONFIG_USER_ONLY)
4482 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4483 #else
4484 if (unlikely(!ctx->mem_idx)) {
4485 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4486 return;
4487 }
4488 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4489 cpu_gpr[rB(ctx->opcode)]);
4490 #endif
4491 }
4492 #endif /* defined(TARGET_PPC64) */
4493
4494 /*** Lookaside buffer management ***/
4495 /* Optional & mem_idx only: */
4496
4497 /* tlbia */
4498 static void gen_tlbia(DisasContext *ctx)
4499 {
4500 #if defined(CONFIG_USER_ONLY)
4501 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4502 #else
4503 if (unlikely(!ctx->mem_idx)) {
4504 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4505 return;
4506 }
4507 gen_helper_tlbia(cpu_env);
4508 #endif
4509 }
4510
4511 /* tlbiel */
4512 static void gen_tlbiel(DisasContext *ctx)
4513 {
4514 #if defined(CONFIG_USER_ONLY)
4515 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4516 #else
4517 if (unlikely(!ctx->mem_idx)) {
4518 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4519 return;
4520 }
4521 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4522 #endif
4523 }
4524
4525 /* tlbie */
4526 static void gen_tlbie(DisasContext *ctx)
4527 {
4528 #if defined(CONFIG_USER_ONLY)
4529 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4530 #else
4531 if (unlikely(!ctx->mem_idx)) {
4532 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4533 return;
4534 }
4535 if (NARROW_MODE(ctx)) {
4536 TCGv t0 = tcg_temp_new();
4537 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4538 gen_helper_tlbie(cpu_env, t0);
4539 tcg_temp_free(t0);
4540 } else {
4541 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4542 }
4543 #endif
4544 }
4545
4546 /* tlbsync */
4547 static void gen_tlbsync(DisasContext *ctx)
4548 {
4549 #if defined(CONFIG_USER_ONLY)
4550 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4551 #else
4552 if (unlikely(!ctx->mem_idx)) {
4553 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4554 return;
4555 }
4556 /* This has no effect: it should ensure that all previous
4557 * tlbie have completed
4558 */
4559 gen_stop_exception(ctx);
4560 #endif
4561 }
4562
4563 #if defined(TARGET_PPC64)
4564 /* slbia */
4565 static void gen_slbia(DisasContext *ctx)
4566 {
4567 #if defined(CONFIG_USER_ONLY)
4568 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4569 #else
4570 if (unlikely(!ctx->mem_idx)) {
4571 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4572 return;
4573 }
4574 gen_helper_slbia(cpu_env);
4575 #endif
4576 }
4577
4578 /* slbie */
4579 static void gen_slbie(DisasContext *ctx)
4580 {
4581 #if defined(CONFIG_USER_ONLY)
4582 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4583 #else
4584 if (unlikely(!ctx->mem_idx)) {
4585 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4586 return;
4587 }
4588 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4589 #endif
4590 }
4591 #endif
4592
4593 /*** External control ***/
4594 /* Optional: */
4595
4596 /* eciwx */
4597 static void gen_eciwx(DisasContext *ctx)
4598 {
4599 TCGv t0;
4600 /* Should check EAR[E] ! */
4601 gen_set_access_type(ctx, ACCESS_EXT);
4602 t0 = tcg_temp_new();
4603 gen_addr_reg_index(ctx, t0);
4604 gen_check_align(ctx, t0, 0x03);
4605 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4606 tcg_temp_free(t0);
4607 }
4608
4609 /* ecowx */
4610 static void gen_ecowx(DisasContext *ctx)
4611 {
4612 TCGv t0;
4613 /* Should check EAR[E] ! */
4614 gen_set_access_type(ctx, ACCESS_EXT);
4615 t0 = tcg_temp_new();
4616 gen_addr_reg_index(ctx, t0);
4617 gen_check_align(ctx, t0, 0x03);
4618 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4619 tcg_temp_free(t0);
4620 }
4621
4622 /* PowerPC 601 specific instructions */
4623
4624 /* abs - abs. */
4625 static void gen_abs(DisasContext *ctx)
4626 {
4627 int l1 = gen_new_label();
4628 int l2 = gen_new_label();
4629 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4630 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4631 tcg_gen_br(l2);
4632 gen_set_label(l1);
4633 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4634 gen_set_label(l2);
4635 if (unlikely(Rc(ctx->opcode) != 0))
4636 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4637 }
4638
4639 /* abso - abso. */
4640 static void gen_abso(DisasContext *ctx)
4641 {
4642 int l1 = gen_new_label();
4643 int l2 = gen_new_label();
4644 int l3 = gen_new_label();
4645 /* Start with XER OV disabled, the most likely case */
4646 tcg_gen_movi_tl(cpu_ov, 0);
4647 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4648 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4649 tcg_gen_movi_tl(cpu_ov, 1);
4650 tcg_gen_movi_tl(cpu_so, 1);
4651 tcg_gen_br(l2);
4652 gen_set_label(l1);
4653 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4654 tcg_gen_br(l3);
4655 gen_set_label(l2);
4656 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4657 gen_set_label(l3);
4658 if (unlikely(Rc(ctx->opcode) != 0))
4659 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4660 }
4661
4662 /* clcs */
4663 static void gen_clcs(DisasContext *ctx)
4664 {
4665 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4666 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4667 tcg_temp_free_i32(t0);
4668 /* Rc=1 sets CR0 to an undefined state */
4669 }
4670
4671 /* div - div. */
4672 static void gen_div(DisasContext *ctx)
4673 {
4674 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4675 cpu_gpr[rB(ctx->opcode)]);
4676 if (unlikely(Rc(ctx->opcode) != 0))
4677 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4678 }
4679
4680 /* divo - divo. */
4681 static void gen_divo(DisasContext *ctx)
4682 {
4683 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4684 cpu_gpr[rB(ctx->opcode)]);
4685 if (unlikely(Rc(ctx->opcode) != 0))
4686 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4687 }
4688
4689 /* divs - divs. */
4690 static void gen_divs(DisasContext *ctx)
4691 {
4692 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4693 cpu_gpr[rB(ctx->opcode)]);
4694 if (unlikely(Rc(ctx->opcode) != 0))
4695 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4696 }
4697
4698 /* divso - divso. */
4699 static void gen_divso(DisasContext *ctx)
4700 {
4701 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4702 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4703 if (unlikely(Rc(ctx->opcode) != 0))
4704 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4705 }
4706
4707 /* doz - doz. */
4708 static void gen_doz(DisasContext *ctx)
4709 {
4710 int l1 = gen_new_label();
4711 int l2 = gen_new_label();
4712 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4713 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4714 tcg_gen_br(l2);
4715 gen_set_label(l1);
4716 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4717 gen_set_label(l2);
4718 if (unlikely(Rc(ctx->opcode) != 0))
4719 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4720 }
4721
4722 /* dozo - dozo. */
4723 static void gen_dozo(DisasContext *ctx)
4724 {
4725 int l1 = gen_new_label();
4726 int l2 = gen_new_label();
4727 TCGv t0 = tcg_temp_new();
4728 TCGv t1 = tcg_temp_new();
4729 TCGv t2 = tcg_temp_new();
4730 /* Start with XER OV disabled, the most likely case */
4731 tcg_gen_movi_tl(cpu_ov, 0);
4732 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4733 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4734 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4735 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4736 tcg_gen_andc_tl(t1, t1, t2);
4737 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4738 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4739 tcg_gen_movi_tl(cpu_ov, 1);
4740 tcg_gen_movi_tl(cpu_so, 1);
4741 tcg_gen_br(l2);
4742 gen_set_label(l1);
4743 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4744 gen_set_label(l2);
4745 tcg_temp_free(t0);
4746 tcg_temp_free(t1);
4747 tcg_temp_free(t2);
4748 if (unlikely(Rc(ctx->opcode) != 0))
4749 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4750 }
4751
4752 /* dozi */
4753 static void gen_dozi(DisasContext *ctx)
4754 {
4755 target_long simm = SIMM(ctx->opcode);
4756 int l1 = gen_new_label();
4757 int l2 = gen_new_label();
4758 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4759 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4760 tcg_gen_br(l2);
4761 gen_set_label(l1);
4762 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4763 gen_set_label(l2);
4764 if (unlikely(Rc(ctx->opcode) != 0))
4765 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4766 }
4767
4768 /* lscbx - lscbx. */
4769 static void gen_lscbx(DisasContext *ctx)
4770 {
4771 TCGv t0 = tcg_temp_new();
4772 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4773 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4774 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4775
4776 gen_addr_reg_index(ctx, t0);
4777 /* NIP cannot be restored if the memory exception comes from an helper */
4778 gen_update_nip(ctx, ctx->nip - 4);
4779 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4780 tcg_temp_free_i32(t1);
4781 tcg_temp_free_i32(t2);
4782 tcg_temp_free_i32(t3);
4783 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4784 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4785 if (unlikely(Rc(ctx->opcode) != 0))
4786 gen_set_Rc0(ctx, t0);
4787 tcg_temp_free(t0);
4788 }
4789
4790 /* maskg - maskg. */
4791 static void gen_maskg(DisasContext *ctx)
4792 {
4793 int l1 = gen_new_label();
4794 TCGv t0 = tcg_temp_new();
4795 TCGv t1 = tcg_temp_new();
4796 TCGv t2 = tcg_temp_new();
4797 TCGv t3 = tcg_temp_new();
4798 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4799 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4800 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4801 tcg_gen_addi_tl(t2, t0, 1);
4802 tcg_gen_shr_tl(t2, t3, t2);
4803 tcg_gen_shr_tl(t3, t3, t1);
4804 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4805 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4806 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4807 gen_set_label(l1);
4808 tcg_temp_free(t0);
4809 tcg_temp_free(t1);
4810 tcg_temp_free(t2);
4811 tcg_temp_free(t3);
4812 if (unlikely(Rc(ctx->opcode) != 0))
4813 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4814 }
4815
4816 /* maskir - maskir. */
4817 static void gen_maskir(DisasContext *ctx)
4818 {
4819 TCGv t0 = tcg_temp_new();
4820 TCGv t1 = tcg_temp_new();
4821 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4822 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4823 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4824 tcg_temp_free(t0);
4825 tcg_temp_free(t1);
4826 if (unlikely(Rc(ctx->opcode) != 0))
4827 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4828 }
4829
4830 /* mul - mul. */
4831 static void gen_mul(DisasContext *ctx)
4832 {
4833 TCGv_i64 t0 = tcg_temp_new_i64();
4834 TCGv_i64 t1 = tcg_temp_new_i64();
4835 TCGv t2 = tcg_temp_new();
4836 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4837 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4838 tcg_gen_mul_i64(t0, t0, t1);
4839 tcg_gen_trunc_i64_tl(t2, t0);
4840 gen_store_spr(SPR_MQ, t2);
4841 tcg_gen_shri_i64(t1, t0, 32);
4842 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4843 tcg_temp_free_i64(t0);
4844 tcg_temp_free_i64(t1);
4845 tcg_temp_free(t2);
4846 if (unlikely(Rc(ctx->opcode) != 0))
4847 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4848 }
4849
4850 /* mulo - mulo. */
4851 static void gen_mulo(DisasContext *ctx)
4852 {
4853 int l1 = gen_new_label();
4854 TCGv_i64 t0 = tcg_temp_new_i64();
4855 TCGv_i64 t1 = tcg_temp_new_i64();
4856 TCGv t2 = tcg_temp_new();
4857 /* Start with XER OV disabled, the most likely case */
4858 tcg_gen_movi_tl(cpu_ov, 0);
4859 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4860 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4861 tcg_gen_mul_i64(t0, t0, t1);
4862 tcg_gen_trunc_i64_tl(t2, t0);
4863 gen_store_spr(SPR_MQ, t2);
4864 tcg_gen_shri_i64(t1, t0, 32);
4865 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4866 tcg_gen_ext32s_i64(t1, t0);
4867 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4868 tcg_gen_movi_tl(cpu_ov, 1);
4869 tcg_gen_movi_tl(cpu_so, 1);
4870 gen_set_label(l1);
4871 tcg_temp_free_i64(t0);
4872 tcg_temp_free_i64(t1);
4873 tcg_temp_free(t2);
4874 if (unlikely(Rc(ctx->opcode) != 0))
4875 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4876 }
4877
4878 /* nabs - nabs. */
4879 static void gen_nabs(DisasContext *ctx)
4880 {
4881 int l1 = gen_new_label();
4882 int l2 = gen_new_label();
4883 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4884 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4885 tcg_gen_br(l2);
4886 gen_set_label(l1);
4887 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4888 gen_set_label(l2);
4889 if (unlikely(Rc(ctx->opcode) != 0))
4890 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4891 }
4892
4893 /* nabso - nabso. */
4894 static void gen_nabso(DisasContext *ctx)
4895 {
4896 int l1 = gen_new_label();
4897 int l2 = gen_new_label();
4898 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4899 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4900 tcg_gen_br(l2);
4901 gen_set_label(l1);
4902 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4903 gen_set_label(l2);
4904 /* nabs never overflows */
4905 tcg_gen_movi_tl(cpu_ov, 0);
4906 if (unlikely(Rc(ctx->opcode) != 0))
4907 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4908 }
4909
4910 /* rlmi - rlmi. */
4911 static void gen_rlmi(DisasContext *ctx)
4912 {
4913 uint32_t mb = MB(ctx->opcode);
4914 uint32_t me = ME(ctx->opcode);
4915 TCGv t0 = tcg_temp_new();
4916 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4917 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4918 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4919 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4920 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4921 tcg_temp_free(t0);
4922 if (unlikely(Rc(ctx->opcode) != 0))
4923 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4924 }
4925
4926 /* rrib - rrib. */
4927 static void gen_rrib(DisasContext *ctx)
4928 {
4929 TCGv t0 = tcg_temp_new();
4930 TCGv t1 = tcg_temp_new();
4931 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4932 tcg_gen_movi_tl(t1, 0x80000000);
4933 tcg_gen_shr_tl(t1, t1, t0);
4934 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4935 tcg_gen_and_tl(t0, t0, t1);
4936 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4937 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4938 tcg_temp_free(t0);
4939 tcg_temp_free(t1);
4940 if (unlikely(Rc(ctx->opcode) != 0))
4941 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4942 }
4943
4944 /* sle - sle. */
4945 static void gen_sle(DisasContext *ctx)
4946 {
4947 TCGv t0 = tcg_temp_new();
4948 TCGv t1 = tcg_temp_new();
4949 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4950 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4951 tcg_gen_subfi_tl(t1, 32, t1);
4952 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4953 tcg_gen_or_tl(t1, t0, t1);
4954 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4955 gen_store_spr(SPR_MQ, t1);
4956 tcg_temp_free(t0);
4957 tcg_temp_free(t1);
4958 if (unlikely(Rc(ctx->opcode) != 0))
4959 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4960 }
4961
4962 /* sleq - sleq. */
4963 static void gen_sleq(DisasContext *ctx)
4964 {
4965 TCGv t0 = tcg_temp_new();
4966 TCGv t1 = tcg_temp_new();
4967 TCGv t2 = tcg_temp_new();
4968 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4969 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4970 tcg_gen_shl_tl(t2, t2, t0);
4971 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4972 gen_load_spr(t1, SPR_MQ);
4973 gen_store_spr(SPR_MQ, t0);
4974 tcg_gen_and_tl(t0, t0, t2);
4975 tcg_gen_andc_tl(t1, t1, t2);
4976 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4977 tcg_temp_free(t0);
4978 tcg_temp_free(t1);
4979 tcg_temp_free(t2);
4980 if (unlikely(Rc(ctx->opcode) != 0))
4981 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4982 }
4983
4984 /* sliq - sliq. */
4985 static void gen_sliq(DisasContext *ctx)
4986 {
4987 int sh = SH(ctx->opcode);
4988 TCGv t0 = tcg_temp_new();
4989 TCGv t1 = tcg_temp_new();
4990 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4991 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4992 tcg_gen_or_tl(t1, t0, t1);
4993 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4994 gen_store_spr(SPR_MQ, t1);
4995 tcg_temp_free(t0);
4996 tcg_temp_free(t1);
4997 if (unlikely(Rc(ctx->opcode) != 0))
4998 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4999 }
5000
5001 /* slliq - slliq. */
5002 static void gen_slliq(DisasContext *ctx)
5003 {
5004 int sh = SH(ctx->opcode);
5005 TCGv t0 = tcg_temp_new();
5006 TCGv t1 = tcg_temp_new();
5007 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5008 gen_load_spr(t1, SPR_MQ);
5009 gen_store_spr(SPR_MQ, t0);
5010 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5011 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5012 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5013 tcg_temp_free(t0);
5014 tcg_temp_free(t1);
5015 if (unlikely(Rc(ctx->opcode) != 0))
5016 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5017 }
5018
5019 /* sllq - sllq. */
5020 static void gen_sllq(DisasContext *ctx)
5021 {
5022 int l1 = gen_new_label();
5023 int l2 = gen_new_label();
5024 TCGv t0 = tcg_temp_local_new();
5025 TCGv t1 = tcg_temp_local_new();
5026 TCGv t2 = tcg_temp_local_new();
5027 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5028 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5029 tcg_gen_shl_tl(t1, t1, t2);
5030 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5031 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5032 gen_load_spr(t0, SPR_MQ);
5033 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5034 tcg_gen_br(l2);
5035 gen_set_label(l1);
5036 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5037 gen_load_spr(t2, SPR_MQ);
5038 tcg_gen_andc_tl(t1, t2, t1);
5039 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5040 gen_set_label(l2);
5041 tcg_temp_free(t0);
5042 tcg_temp_free(t1);
5043 tcg_temp_free(t2);
5044 if (unlikely(Rc(ctx->opcode) != 0))
5045 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5046 }
5047
5048 /* slq - slq. */
5049 static void gen_slq(DisasContext *ctx)
5050 {
5051 int l1 = gen_new_label();
5052 TCGv t0 = tcg_temp_new();
5053 TCGv t1 = tcg_temp_new();
5054 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5055 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5056 tcg_gen_subfi_tl(t1, 32, t1);
5057 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5058 tcg_gen_or_tl(t1, t0, t1);
5059 gen_store_spr(SPR_MQ, t1);
5060 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5061 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5062 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5063 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5064 gen_set_label(l1);
5065 tcg_temp_free(t0);
5066 tcg_temp_free(t1);
5067 if (unlikely(Rc(ctx->opcode) != 0))
5068 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5069 }
5070
5071 /* sraiq - sraiq. */
5072 static void gen_sraiq(DisasContext *ctx)
5073 {
5074 int sh = SH(ctx->opcode);
5075 int l1 = gen_new_label();
5076 TCGv t0 = tcg_temp_new();
5077 TCGv t1 = tcg_temp_new();
5078 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5079 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5080 tcg_gen_or_tl(t0, t0, t1);
5081 gen_store_spr(SPR_MQ, t0);
5082 tcg_gen_movi_tl(cpu_ca, 0);
5083 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5084 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5085 tcg_gen_movi_tl(cpu_ca, 1);
5086 gen_set_label(l1);
5087 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5088 tcg_temp_free(t0);
5089 tcg_temp_free(t1);
5090 if (unlikely(Rc(ctx->opcode) != 0))
5091 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5092 }
5093
5094 /* sraq - sraq. */
5095 static void gen_sraq(DisasContext *ctx)
5096 {
5097 int l1 = gen_new_label();
5098 int l2 = gen_new_label();
5099 TCGv t0 = tcg_temp_new();
5100 TCGv t1 = tcg_temp_local_new();
5101 TCGv t2 = tcg_temp_local_new();
5102 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5103 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5104 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5105 tcg_gen_subfi_tl(t2, 32, t2);
5106 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5107 tcg_gen_or_tl(t0, t0, t2);
5108 gen_store_spr(SPR_MQ, t0);
5109 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5110 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5111 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5112 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5113 gen_set_label(l1);
5114 tcg_temp_free(t0);
5115 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5116 tcg_gen_movi_tl(cpu_ca, 0);
5117 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5118 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5119 tcg_gen_movi_tl(cpu_ca, 1);
5120 gen_set_label(l2);
5121 tcg_temp_free(t1);
5122 tcg_temp_free(t2);
5123 if (unlikely(Rc(ctx->opcode) != 0))
5124 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5125 }
5126
5127 /* sre - sre. */
5128 static void gen_sre(DisasContext *ctx)
5129 {
5130 TCGv t0 = tcg_temp_new();
5131 TCGv t1 = tcg_temp_new();
5132 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5133 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5134 tcg_gen_subfi_tl(t1, 32, t1);
5135 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5136 tcg_gen_or_tl(t1, t0, t1);
5137 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5138 gen_store_spr(SPR_MQ, t1);
5139 tcg_temp_free(t0);
5140 tcg_temp_free(t1);
5141 if (unlikely(Rc(ctx->opcode) != 0))
5142 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5143 }
5144
5145 /* srea - srea. */
5146 static void gen_srea(DisasContext *ctx)
5147 {
5148 TCGv t0 = tcg_temp_new();
5149 TCGv t1 = tcg_temp_new();
5150 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5151 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5152 gen_store_spr(SPR_MQ, t0);
5153 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5154 tcg_temp_free(t0);
5155 tcg_temp_free(t1);
5156 if (unlikely(Rc(ctx->opcode) != 0))
5157 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5158 }
5159
5160 /* sreq */
5161 static void gen_sreq(DisasContext *ctx)
5162 {
5163 TCGv t0 = tcg_temp_new();
5164 TCGv t1 = tcg_temp_new();
5165 TCGv t2 = tcg_temp_new();
5166 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5167 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5168 tcg_gen_shr_tl(t1, t1, t0);
5169 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5170 gen_load_spr(t2, SPR_MQ);
5171 gen_store_spr(SPR_MQ, t0);
5172 tcg_gen_and_tl(t0, t0, t1);
5173 tcg_gen_andc_tl(t2, t2, t1);
5174 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5175 tcg_temp_free(t0);
5176 tcg_temp_free(t1);
5177 tcg_temp_free(t2);
5178 if (unlikely(Rc(ctx->opcode) != 0))
5179 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5180 }
5181
5182 /* sriq */
5183 static void gen_sriq(DisasContext *ctx)
5184 {
5185 int sh = SH(ctx->opcode);
5186 TCGv t0 = tcg_temp_new();
5187 TCGv t1 = tcg_temp_new();
5188 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5189 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5190 tcg_gen_or_tl(t1, t0, t1);
5191 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5192 gen_store_spr(SPR_MQ, t1);
5193 tcg_temp_free(t0);
5194 tcg_temp_free(t1);
5195 if (unlikely(Rc(ctx->opcode) != 0))
5196 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5197 }
5198
5199 /* srliq */
5200 static void gen_srliq(DisasContext *ctx)
5201 {
5202 int sh = SH(ctx->opcode);
5203 TCGv t0 = tcg_temp_new();
5204 TCGv t1 = tcg_temp_new();
5205 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5206 gen_load_spr(t1, SPR_MQ);
5207 gen_store_spr(SPR_MQ, t0);
5208 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5209 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5210 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5211 tcg_temp_free(t0);
5212 tcg_temp_free(t1);
5213 if (unlikely(Rc(ctx->opcode) != 0))
5214 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5215 }
5216
5217 /* srlq */
5218 static void gen_srlq(DisasContext *ctx)
5219 {
5220 int l1 = gen_new_label();
5221 int l2 = gen_new_label();
5222 TCGv t0 = tcg_temp_local_new();
5223 TCGv t1 = tcg_temp_local_new();
5224 TCGv t2 = tcg_temp_local_new();
5225 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5226 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5227 tcg_gen_shr_tl(t2, t1, t2);
5228 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5229 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5230 gen_load_spr(t0, SPR_MQ);
5231 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5232 tcg_gen_br(l2);
5233 gen_set_label(l1);
5234 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5235 tcg_gen_and_tl(t0, t0, t2);
5236 gen_load_spr(t1, SPR_MQ);
5237 tcg_gen_andc_tl(t1, t1, t2);
5238 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5239 gen_set_label(l2);
5240 tcg_temp_free(t0);
5241 tcg_temp_free(t1);
5242 tcg_temp_free(t2);
5243 if (unlikely(Rc(ctx->opcode) != 0))
5244 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5245 }
5246
5247 /* srq */
5248 static void gen_srq(DisasContext *ctx)
5249 {
5250 int l1 = gen_new_label();
5251 TCGv t0 = tcg_temp_new();
5252 TCGv t1 = tcg_temp_new();
5253 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5254 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5255 tcg_gen_subfi_tl(t1, 32, t1);
5256 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5257 tcg_gen_or_tl(t1, t0, t1);
5258 gen_store_spr(SPR_MQ, t1);
5259 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5260 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5261 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5262 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5263 gen_set_label(l1);
5264 tcg_temp_free(t0);
5265 tcg_temp_free(t1);
5266 if (unlikely(Rc(ctx->opcode) != 0))
5267 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5268 }
5269
5270 /* PowerPC 602 specific instructions */
5271
5272 /* dsa */
5273 static void gen_dsa(DisasContext *ctx)
5274 {
5275 /* XXX: TODO */
5276 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5277 }
5278
5279 /* esa */
5280 static void gen_esa(DisasContext *ctx)
5281 {
5282 /* XXX: TODO */
5283 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5284 }
5285
5286 /* mfrom */
5287 static void gen_mfrom(DisasContext *ctx)
5288 {
5289 #if defined(CONFIG_USER_ONLY)
5290 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5291 #else
5292 if (unlikely(!ctx->mem_idx)) {
5293 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5294 return;
5295 }
5296 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5297 #endif
5298 }
5299
5300 /* 602 - 603 - G2 TLB management */
5301
5302 /* tlbld */
5303 static void gen_tlbld_6xx(DisasContext *ctx)
5304 {
5305 #if defined(CONFIG_USER_ONLY)
5306 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5307 #else
5308 if (unlikely(!ctx->mem_idx)) {
5309 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5310 return;
5311 }
5312 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5313 #endif
5314 }
5315
5316 /* tlbli */
5317 static void gen_tlbli_6xx(DisasContext *ctx)
5318 {
5319 #if defined(CONFIG_USER_ONLY)
5320 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5321 #else
5322 if (unlikely(!ctx->mem_idx)) {
5323 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5324 return;
5325 }
5326 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5327 #endif
5328 }
5329
5330 /* 74xx TLB management */
5331
5332 /* tlbld */
5333 static void gen_tlbld_74xx(DisasContext *ctx)
5334 {
5335 #if defined(CONFIG_USER_ONLY)
5336 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5337 #else
5338 if (unlikely(!ctx->mem_idx)) {
5339 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5340 return;
5341 }
5342 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5343 #endif
5344 }
5345
5346 /* tlbli */
5347 static void gen_tlbli_74xx(DisasContext *ctx)
5348 {
5349 #if defined(CONFIG_USER_ONLY)
5350 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5351 #else
5352 if (unlikely(!ctx->mem_idx)) {
5353 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5354 return;
5355 }
5356 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5357 #endif
5358 }
5359
5360 /* POWER instructions not in PowerPC 601 */
5361
5362 /* clf */
5363 static void gen_clf(DisasContext *ctx)
5364 {
5365 /* Cache line flush: implemented as no-op */
5366 }
5367
5368 /* cli */
5369 static void gen_cli(DisasContext *ctx)
5370 {
5371 /* Cache line invalidate: privileged and treated as no-op */
5372 #if defined(CONFIG_USER_ONLY)
5373 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5374 #else
5375 if (unlikely(!ctx->mem_idx)) {
5376 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5377 return;
5378 }
5379 #endif
5380 }
5381
5382 /* dclst */
5383 static void gen_dclst(DisasContext *ctx)
5384 {
5385 /* Data cache line store: treated as no-op */
5386 }
5387
5388 static void gen_mfsri(DisasContext *ctx)
5389 {
5390 #if defined(CONFIG_USER_ONLY)
5391 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5392 #else
5393 int ra = rA(ctx->opcode);
5394 int rd = rD(ctx->opcode);
5395 TCGv t0;
5396 if (unlikely(!ctx->mem_idx)) {
5397 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5398 return;
5399 }
5400 t0 = tcg_temp_new();
5401 gen_addr_reg_index(ctx, t0);
5402 tcg_gen_shri_tl(t0, t0, 28);
5403 tcg_gen_andi_tl(t0, t0, 0xF);
5404 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5405 tcg_temp_free(t0);
5406 if (ra != 0 && ra != rd)
5407 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5408 #endif
5409 }
5410
5411 static void gen_rac(DisasContext *ctx)
5412 {
5413 #if defined(CONFIG_USER_ONLY)
5414 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5415 #else
5416 TCGv t0;
5417 if (unlikely(!ctx->mem_idx)) {
5418 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5419 return;
5420 }
5421 t0 = tcg_temp_new();
5422 gen_addr_reg_index(ctx, t0);
5423 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5424 tcg_temp_free(t0);
5425 #endif
5426 }
5427
5428 static void gen_rfsvc(DisasContext *ctx)
5429 {
5430 #if defined(CONFIG_USER_ONLY)
5431 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5432 #else
5433 if (unlikely(!ctx->mem_idx)) {
5434 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5435 return;
5436 }
5437 gen_helper_rfsvc(cpu_env);
5438 gen_sync_exception(ctx);
5439 #endif
5440 }
5441
5442 /* svc is not implemented for now */
5443
5444 /* POWER2 specific instructions */
5445 /* Quad manipulation (load/store two floats at a time) */
5446
5447 /* lfq */
5448 static void gen_lfq(DisasContext *ctx)
5449 {
5450 int rd = rD(ctx->opcode);
5451 TCGv t0;
5452 gen_set_access_type(ctx, ACCESS_FLOAT);
5453 t0 = tcg_temp_new();
5454 gen_addr_imm_index(ctx, t0, 0);
5455 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5456 gen_addr_add(ctx, t0, t0, 8);
5457 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5458 tcg_temp_free(t0);
5459 }
5460
5461 /* lfqu */
5462 static void gen_lfqu(DisasContext *ctx)
5463 {
5464 int ra = rA(ctx->opcode);
5465 int rd = rD(ctx->opcode);
5466 TCGv t0, t1;
5467 gen_set_access_type(ctx, ACCESS_FLOAT);
5468 t0 = tcg_temp_new();
5469 t1 = tcg_temp_new();
5470 gen_addr_imm_index(ctx, t0, 0);
5471 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5472 gen_addr_add(ctx, t1, t0, 8);
5473 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5474 if (ra != 0)
5475 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5476 tcg_temp_free(t0);
5477 tcg_temp_free(t1);
5478 }
5479
5480 /* lfqux */
5481 static void gen_lfqux(DisasContext *ctx)
5482 {
5483 int ra = rA(ctx->opcode);
5484 int rd = rD(ctx->opcode);
5485 gen_set_access_type(ctx, ACCESS_FLOAT);
5486 TCGv t0, t1;
5487 t0 = tcg_temp_new();
5488 gen_addr_reg_index(ctx, t0);
5489 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5490 t1 = tcg_temp_new();
5491 gen_addr_add(ctx, t1, t0, 8);
5492 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5493 tcg_temp_free(t1);
5494 if (ra != 0)
5495 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5496 tcg_temp_free(t0);
5497 }
5498
5499 /* lfqx */
5500 static void gen_lfqx(DisasContext *ctx)
5501 {
5502 int rd = rD(ctx->opcode);
5503 TCGv t0;
5504 gen_set_access_type(ctx, ACCESS_FLOAT);
5505 t0 = tcg_temp_new();
5506 gen_addr_reg_index(ctx, t0);
5507 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5508 gen_addr_add(ctx, t0, t0, 8);
5509 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5510 tcg_temp_free(t0);
5511 }
5512
5513 /* stfq */
5514 static void gen_stfq(DisasContext *ctx)
5515 {
5516 int rd = rD(ctx->opcode);
5517 TCGv t0;
5518 gen_set_access_type(ctx, ACCESS_FLOAT);
5519 t0 = tcg_temp_new();
5520 gen_addr_imm_index(ctx, t0, 0);
5521 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5522 gen_addr_add(ctx, t0, t0, 8);
5523 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5524 tcg_temp_free(t0);
5525 }
5526
5527 /* stfqu */
5528 static void gen_stfqu(DisasContext *ctx)
5529 {
5530 int ra = rA(ctx->opcode);
5531 int rd = rD(ctx->opcode);
5532 TCGv t0, t1;
5533 gen_set_access_type(ctx, ACCESS_FLOAT);
5534 t0 = tcg_temp_new();
5535 gen_addr_imm_index(ctx, t0, 0);
5536 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5537 t1 = tcg_temp_new();
5538 gen_addr_add(ctx, t1, t0, 8);
5539 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5540 tcg_temp_free(t1);
5541 if (ra != 0)
5542 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5543 tcg_temp_free(t0);
5544 }
5545
5546 /* stfqux */
5547 static void gen_stfqux(DisasContext *ctx)
5548 {
5549 int ra = rA(ctx->opcode);
5550 int rd = rD(ctx->opcode);
5551 TCGv t0, t1;
5552 gen_set_access_type(ctx, ACCESS_FLOAT);
5553 t0 = tcg_temp_new();
5554 gen_addr_reg_index(ctx, t0);
5555 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5556 t1 = tcg_temp_new();
5557 gen_addr_add(ctx, t1, t0, 8);
5558 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5559 tcg_temp_free(t1);
5560 if (ra != 0)
5561 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5562 tcg_temp_free(t0);
5563 }
5564
5565 /* stfqx */
5566 static void gen_stfqx(DisasContext *ctx)
5567 {
5568 int rd = rD(ctx->opcode);
5569 TCGv t0;
5570 gen_set_access_type(ctx, ACCESS_FLOAT);
5571 t0 = tcg_temp_new();
5572 gen_addr_reg_index(ctx, t0);
5573 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5574 gen_addr_add(ctx, t0, t0, 8);
5575 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5576 tcg_temp_free(t0);
5577 }
5578
5579 /* BookE specific instructions */
5580
5581 /* XXX: not implemented on 440 ? */
5582 static void gen_mfapidi(DisasContext *ctx)
5583 {
5584 /* XXX: TODO */
5585 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5586 }
5587
5588 /* XXX: not implemented on 440 ? */
5589 static void gen_tlbiva(DisasContext *ctx)
5590 {
5591 #if defined(CONFIG_USER_ONLY)
5592 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5593 #else
5594 TCGv t0;
5595 if (unlikely(!ctx->mem_idx)) {
5596 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5597 return;
5598 }
5599 t0 = tcg_temp_new();
5600 gen_addr_reg_index(ctx, t0);
5601 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5602 tcg_temp_free(t0);
5603 #endif
5604 }
5605
5606 /* All 405 MAC instructions are translated here */
5607 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5608 int ra, int rb, int rt, int Rc)
5609 {
5610 TCGv t0, t1;
5611
5612 t0 = tcg_temp_local_new();
5613 t1 = tcg_temp_local_new();
5614
5615 switch (opc3 & 0x0D) {
5616 case 0x05:
5617 /* macchw - macchw. - macchwo - macchwo. */
5618 /* macchws - macchws. - macchwso - macchwso. */
5619 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5620 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5621 /* mulchw - mulchw. */
5622 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5623 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5624 tcg_gen_ext16s_tl(t1, t1);
5625 break;
5626 case 0x04:
5627 /* macchwu - macchwu. - macchwuo - macchwuo. */
5628 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5629 /* mulchwu - mulchwu. */
5630 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5631 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5632 tcg_gen_ext16u_tl(t1, t1);
5633 break;
5634 case 0x01:
5635 /* machhw - machhw. - machhwo - machhwo. */
5636 /* machhws - machhws. - machhwso - machhwso. */
5637 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5638 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5639 /* mulhhw - mulhhw. */
5640 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5641 tcg_gen_ext16s_tl(t0, t0);
5642 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5643 tcg_gen_ext16s_tl(t1, t1);
5644 break;
5645 case 0x00:
5646 /* machhwu - machhwu. - machhwuo - machhwuo. */
5647 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5648 /* mulhhwu - mulhhwu. */
5649 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5650 tcg_gen_ext16u_tl(t0, t0);
5651 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5652 tcg_gen_ext16u_tl(t1, t1);
5653 break;
5654 case 0x0D:
5655 /* maclhw - maclhw. - maclhwo - maclhwo. */
5656 /* maclhws - maclhws. - maclhwso - maclhwso. */
5657 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5658 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5659 /* mullhw - mullhw. */
5660 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5661 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5662 break;
5663 case 0x0C:
5664 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5665 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5666 /* mullhwu - mullhwu. */
5667 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5668 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5669 break;
5670 }
5671 if (opc2 & 0x04) {
5672 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5673 tcg_gen_mul_tl(t1, t0, t1);
5674 if (opc2 & 0x02) {
5675 /* nmultiply-and-accumulate (0x0E) */
5676 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5677 } else {
5678 /* multiply-and-accumulate (0x0C) */
5679 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5680 }
5681
5682 if (opc3 & 0x12) {
5683 /* Check overflow and/or saturate */
5684 int l1 = gen_new_label();
5685
5686 if (opc3 & 0x10) {
5687 /* Start with XER OV disabled, the most likely case */
5688 tcg_gen_movi_tl(cpu_ov, 0);
5689 }
5690 if (opc3 & 0x01) {
5691 /* Signed */
5692 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5693 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5694 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5695 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5696 if (opc3 & 0x02) {
5697 /* Saturate */
5698 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5699 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5700 }
5701 } else {
5702 /* Unsigned */
5703 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5704 if (opc3 & 0x02) {
5705 /* Saturate */
5706 tcg_gen_movi_tl(t0, UINT32_MAX);
5707 }
5708 }
5709 if (opc3 & 0x10) {
5710 /* Check overflow */
5711 tcg_gen_movi_tl(cpu_ov, 1);
5712 tcg_gen_movi_tl(cpu_so, 1);
5713 }
5714 gen_set_label(l1);
5715 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5716 }
5717 } else {
5718 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5719 }
5720 tcg_temp_free(t0);
5721 tcg_temp_free(t1);
5722 if (unlikely(Rc) != 0) {
5723 /* Update Rc0 */
5724 gen_set_Rc0(ctx, cpu_gpr[rt]);
5725 }
5726 }
5727
5728 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5729 static void glue(gen_, name)(DisasContext *ctx) \
5730 { \
5731 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5732 rD(ctx->opcode), Rc(ctx->opcode)); \
5733 }
5734
5735 /* macchw - macchw. */
5736 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5737 /* macchwo - macchwo. */
5738 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5739 /* macchws - macchws. */
5740 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5741 /* macchwso - macchwso. */
5742 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5743 /* macchwsu - macchwsu. */
5744 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5745 /* macchwsuo - macchwsuo. */
5746 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5747 /* macchwu - macchwu. */
5748 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5749 /* macchwuo - macchwuo. */
5750 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5751 /* machhw - machhw. */
5752 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5753 /* machhwo - machhwo. */
5754 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5755 /* machhws - machhws. */
5756 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5757 /* machhwso - machhwso. */
5758 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5759 /* machhwsu - machhwsu. */
5760 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5761 /* machhwsuo - machhwsuo. */
5762 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5763 /* machhwu - machhwu. */
5764 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5765 /* machhwuo - machhwuo. */
5766 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5767 /* maclhw - maclhw. */
5768 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5769 /* maclhwo - maclhwo. */
5770 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5771 /* maclhws - maclhws. */
5772 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5773 /* maclhwso - maclhwso. */
5774 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5775 /* maclhwu - maclhwu. */
5776 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5777 /* maclhwuo - maclhwuo. */
5778 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5779 /* maclhwsu - maclhwsu. */
5780 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5781 /* maclhwsuo - maclhwsuo. */
5782 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5783 /* nmacchw - nmacchw. */
5784 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5785 /* nmacchwo - nmacchwo. */
5786 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5787 /* nmacchws - nmacchws. */
5788 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5789 /* nmacchwso - nmacchwso. */
5790 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5791 /* nmachhw - nmachhw. */
5792 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5793 /* nmachhwo - nmachhwo. */
5794 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5795 /* nmachhws - nmachhws. */
5796 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5797 /* nmachhwso - nmachhwso. */
5798 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5799 /* nmaclhw - nmaclhw. */
5800 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5801 /* nmaclhwo - nmaclhwo. */
5802 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5803 /* nmaclhws - nmaclhws. */
5804 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5805 /* nmaclhwso - nmaclhwso. */
5806 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5807
5808 /* mulchw - mulchw. */
5809 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5810 /* mulchwu - mulchwu. */
5811 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5812 /* mulhhw - mulhhw. */
5813 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5814 /* mulhhwu - mulhhwu. */
5815 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5816 /* mullhw - mullhw. */
5817 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5818 /* mullhwu - mullhwu. */
5819 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5820
5821 /* mfdcr */
5822 static void gen_mfdcr(DisasContext *ctx)
5823 {
5824 #if defined(CONFIG_USER_ONLY)
5825 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5826 #else
5827 TCGv dcrn;
5828 if (unlikely(!ctx->mem_idx)) {
5829 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5830 return;
5831 }
5832 /* NIP cannot be restored if the memory exception comes from an helper */
5833 gen_update_nip(ctx, ctx->nip - 4);
5834 dcrn = tcg_const_tl(SPR(ctx->opcode));
5835 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5836 tcg_temp_free(dcrn);
5837 #endif
5838 }
5839
5840 /* mtdcr */
5841 static void gen_mtdcr(DisasContext *ctx)
5842 {
5843 #if defined(CONFIG_USER_ONLY)
5844 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5845 #else
5846 TCGv dcrn;
5847 if (unlikely(!ctx->mem_idx)) {
5848 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5849 return;
5850 }
5851 /* NIP cannot be restored if the memory exception comes from an helper */
5852 gen_update_nip(ctx, ctx->nip - 4);
5853 dcrn = tcg_const_tl(SPR(ctx->opcode));
5854 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5855 tcg_temp_free(dcrn);
5856 #endif
5857 }
5858
5859 /* mfdcrx */
5860 /* XXX: not implemented on 440 ? */
5861 static void gen_mfdcrx(DisasContext *ctx)
5862 {
5863 #if defined(CONFIG_USER_ONLY)
5864 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5865 #else
5866 if (unlikely(!ctx->mem_idx)) {
5867 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5868 return;
5869 }
5870 /* NIP cannot be restored if the memory exception comes from an helper */
5871 gen_update_nip(ctx, ctx->nip - 4);
5872 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5873 cpu_gpr[rA(ctx->opcode)]);
5874 /* Note: Rc update flag set leads to undefined state of Rc0 */
5875 #endif
5876 }
5877
5878 /* mtdcrx */
5879 /* XXX: not implemented on 440 ? */
5880 static void gen_mtdcrx(DisasContext *ctx)
5881 {
5882 #if defined(CONFIG_USER_ONLY)
5883 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5884 #else
5885 if (unlikely(!ctx->mem_idx)) {
5886 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5887 return;
5888 }
5889 /* NIP cannot be restored if the memory exception comes from an helper */
5890 gen_update_nip(ctx, ctx->nip - 4);
5891 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5892 cpu_gpr[rS(ctx->opcode)]);
5893 /* Note: Rc update flag set leads to undefined state of Rc0 */
5894 #endif
5895 }
5896
5897 /* mfdcrux (PPC 460) : user-mode access to DCR */
5898 static void gen_mfdcrux(DisasContext *ctx)
5899 {
5900 /* NIP cannot be restored if the memory exception comes from an helper */
5901 gen_update_nip(ctx, ctx->nip - 4);
5902 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5903 cpu_gpr[rA(ctx->opcode)]);
5904 /* Note: Rc update flag set leads to undefined state of Rc0 */
5905 }
5906
5907 /* mtdcrux (PPC 460) : user-mode access to DCR */
5908 static void gen_mtdcrux(DisasContext *ctx)
5909 {
5910 /* NIP cannot be restored if the memory exception comes from an helper */
5911 gen_update_nip(ctx, ctx->nip - 4);
5912 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5913 cpu_gpr[rS(ctx->opcode)]);
5914 /* Note: Rc update flag set leads to undefined state of Rc0 */
5915 }
5916
5917 /* dccci */
5918 static void gen_dccci(DisasContext *ctx)
5919 {
5920 #if defined(CONFIG_USER_ONLY)
5921 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5922 #else
5923 if (unlikely(!ctx->mem_idx)) {
5924 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5925 return;
5926 }
5927 /* interpreted as no-op */
5928 #endif
5929 }
5930
5931 /* dcread */
5932 static void gen_dcread(DisasContext *ctx)
5933 {
5934 #if defined(CONFIG_USER_ONLY)
5935 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5936 #else
5937 TCGv EA, val;
5938 if (unlikely(!ctx->mem_idx)) {
5939 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5940 return;
5941 }
5942 gen_set_access_type(ctx, ACCESS_CACHE);
5943 EA = tcg_temp_new();
5944 gen_addr_reg_index(ctx, EA);
5945 val = tcg_temp_new();
5946 gen_qemu_ld32u(ctx, val, EA);
5947 tcg_temp_free(val);
5948 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5949 tcg_temp_free(EA);
5950 #endif
5951 }
5952
5953 /* icbt */
5954 static void gen_icbt_40x(DisasContext *ctx)
5955 {
5956 /* interpreted as no-op */
5957 /* XXX: specification say this is treated as a load by the MMU
5958 * but does not generate any exception
5959 */
5960 }
5961
5962 /* iccci */
5963 static void gen_iccci(DisasContext *ctx)
5964 {
5965 #if defined(CONFIG_USER_ONLY)
5966 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5967 #else
5968 if (unlikely(!ctx->mem_idx)) {
5969 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5970 return;
5971 }
5972 /* interpreted as no-op */
5973 #endif
5974 }
5975
5976 /* icread */
5977 static void gen_icread(DisasContext *ctx)
5978 {
5979 #if defined(CONFIG_USER_ONLY)
5980 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5981 #else
5982 if (unlikely(!ctx->mem_idx)) {
5983 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5984 return;
5985 }
5986 /* interpreted as no-op */
5987 #endif
5988 }
5989
5990 /* rfci (mem_idx only) */
5991 static void gen_rfci_40x(DisasContext *ctx)
5992 {
5993 #if defined(CONFIG_USER_ONLY)
5994 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5995 #else
5996 if (unlikely(!ctx->mem_idx)) {
5997 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5998 return;
5999 }
6000 /* Restore CPU state */
6001 gen_helper_40x_rfci(cpu_env);
6002 gen_sync_exception(ctx);
6003 #endif
6004 }
6005
6006 static void gen_rfci(DisasContext *ctx)
6007 {
6008 #if defined(CONFIG_USER_ONLY)
6009 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6010 #else
6011 if (unlikely(!ctx->mem_idx)) {
6012 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6013 return;
6014 }
6015 /* Restore CPU state */
6016 gen_helper_rfci(cpu_env);
6017 gen_sync_exception(ctx);
6018 #endif
6019 }
6020
6021 /* BookE specific */
6022
6023 /* XXX: not implemented on 440 ? */
6024 static void gen_rfdi(DisasContext *ctx)
6025 {
6026 #if defined(CONFIG_USER_ONLY)
6027 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6028 #else
6029 if (unlikely(!ctx->mem_idx)) {
6030 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6031 return;
6032 }
6033 /* Restore CPU state */
6034 gen_helper_rfdi(cpu_env);
6035 gen_sync_exception(ctx);
6036 #endif
6037 }
6038
6039 /* XXX: not implemented on 440 ? */
6040 static void gen_rfmci(DisasContext *ctx)
6041 {
6042 #if defined(CONFIG_USER_ONLY)
6043 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6044 #else
6045 if (unlikely(!ctx->mem_idx)) {
6046 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6047 return;
6048 }
6049 /* Restore CPU state */
6050 gen_helper_rfmci(cpu_env);
6051 gen_sync_exception(ctx);
6052 #endif
6053 }
6054
6055 /* TLB management - PowerPC 405 implementation */
6056
6057 /* tlbre */
6058 static void gen_tlbre_40x(DisasContext *ctx)
6059 {
6060 #if defined(CONFIG_USER_ONLY)
6061 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6062 #else
6063 if (unlikely(!ctx->mem_idx)) {
6064 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6065 return;
6066 }
6067 switch (rB(ctx->opcode)) {
6068 case 0:
6069 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6070 cpu_gpr[rA(ctx->opcode)]);
6071 break;
6072 case 1:
6073 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6074 cpu_gpr[rA(ctx->opcode)]);
6075 break;
6076 default:
6077 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6078 break;
6079 }
6080 #endif
6081 }
6082
6083 /* tlbsx - tlbsx. */
6084 static void gen_tlbsx_40x(DisasContext *ctx)
6085 {
6086 #if defined(CONFIG_USER_ONLY)
6087 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6088 #else
6089 TCGv t0;
6090 if (unlikely(!ctx->mem_idx)) {
6091 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6092 return;
6093 }
6094 t0 = tcg_temp_new();
6095 gen_addr_reg_index(ctx, t0);
6096 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6097 tcg_temp_free(t0);
6098 if (Rc(ctx->opcode)) {
6099 int l1 = gen_new_label();
6100 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6101 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6102 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6103 gen_set_label(l1);
6104 }
6105 #endif
6106 }
6107
6108 /* tlbwe */
6109 static void gen_tlbwe_40x(DisasContext *ctx)
6110 {
6111 #if defined(CONFIG_USER_ONLY)
6112 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6113 #else
6114 if (unlikely(!ctx->mem_idx)) {
6115 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6116 return;
6117 }
6118 switch (rB(ctx->opcode)) {
6119 case 0:
6120 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6121 cpu_gpr[rS(ctx->opcode)]);
6122 break;
6123 case 1:
6124 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6125 cpu_gpr[rS(ctx->opcode)]);
6126 break;
6127 default:
6128 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6129 break;
6130 }
6131 #endif
6132 }
6133
6134 /* TLB management - PowerPC 440 implementation */
6135
6136 /* tlbre */
6137 static void gen_tlbre_440(DisasContext *ctx)
6138 {
6139 #if defined(CONFIG_USER_ONLY)
6140 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6141 #else
6142 if (unlikely(!ctx->mem_idx)) {
6143 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6144 return;
6145 }
6146 switch (rB(ctx->opcode)) {
6147 case 0:
6148 case 1:
6149 case 2:
6150 {
6151 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6152 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6153 t0, cpu_gpr[rA(ctx->opcode)]);
6154 tcg_temp_free_i32(t0);
6155 }
6156 break;
6157 default:
6158 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6159 break;
6160 }
6161 #endif
6162 }
6163
6164 /* tlbsx - tlbsx. */
6165 static void gen_tlbsx_440(DisasContext *ctx)
6166 {
6167 #if defined(CONFIG_USER_ONLY)
6168 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6169 #else
6170 TCGv t0;
6171 if (unlikely(!ctx->mem_idx)) {
6172 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6173 return;
6174 }
6175 t0 = tcg_temp_new();
6176 gen_addr_reg_index(ctx, t0);
6177 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6178 tcg_temp_free(t0);
6179 if (Rc(ctx->opcode)) {
6180 int l1 = gen_new_label();
6181 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6182 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6183 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6184 gen_set_label(l1);
6185 }
6186 #endif
6187 }
6188
6189 /* tlbwe */
6190 static void gen_tlbwe_440(DisasContext *ctx)
6191 {
6192 #if defined(CONFIG_USER_ONLY)
6193 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6194 #else
6195 if (unlikely(!ctx->mem_idx)) {
6196 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6197 return;
6198 }
6199 switch (rB(ctx->opcode)) {
6200 case 0:
6201 case 1:
6202 case 2:
6203 {
6204 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6205 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6206 cpu_gpr[rS(ctx->opcode)]);
6207 tcg_temp_free_i32(t0);
6208 }
6209 break;
6210 default:
6211 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6212 break;
6213 }
6214 #endif
6215 }
6216
6217 /* TLB management - PowerPC BookE 2.06 implementation */
6218
6219 /* tlbre */
6220 static void gen_tlbre_booke206(DisasContext *ctx)
6221 {
6222 #if defined(CONFIG_USER_ONLY)
6223 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6224 #else
6225 if (unlikely(!ctx->mem_idx)) {
6226 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6227 return;
6228 }
6229
6230 gen_helper_booke206_tlbre(cpu_env);
6231 #endif
6232 }
6233
6234 /* tlbsx - tlbsx. */
6235 static void gen_tlbsx_booke206(DisasContext *ctx)
6236 {
6237 #if defined(CONFIG_USER_ONLY)
6238 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6239 #else
6240 TCGv t0;
6241 if (unlikely(!ctx->mem_idx)) {
6242 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6243 return;
6244 }
6245
6246 if (rA(ctx->opcode)) {
6247 t0 = tcg_temp_new();
6248 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6249 } else {
6250 t0 = tcg_const_tl(0);
6251 }
6252
6253 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6254 gen_helper_booke206_tlbsx(cpu_env, t0);
6255 #endif
6256 }
6257
6258 /* tlbwe */
6259 static void gen_tlbwe_booke206(DisasContext *ctx)
6260 {
6261 #if defined(CONFIG_USER_ONLY)
6262 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6263 #else
6264 if (unlikely(!ctx->mem_idx)) {
6265 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6266 return;
6267 }
6268 gen_update_nip(ctx, ctx->nip - 4);
6269 gen_helper_booke206_tlbwe(cpu_env);
6270 #endif
6271 }
6272
6273 static void gen_tlbivax_booke206(DisasContext *ctx)
6274 {
6275 #if defined(CONFIG_USER_ONLY)
6276 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6277 #else
6278 TCGv t0;
6279 if (unlikely(!ctx->mem_idx)) {
6280 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6281 return;
6282 }
6283
6284 t0 = tcg_temp_new();
6285 gen_addr_reg_index(ctx, t0);
6286
6287 gen_helper_booke206_tlbivax(cpu_env, t0);
6288 #endif
6289 }
6290
6291 static void gen_tlbilx_booke206(DisasContext *ctx)
6292 {
6293 #if defined(CONFIG_USER_ONLY)
6294 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6295 #else
6296 TCGv t0;
6297 if (unlikely(!ctx->mem_idx)) {
6298 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6299 return;
6300 }
6301
6302 t0 = tcg_temp_new();
6303 gen_addr_reg_index(ctx, t0);
6304
6305 switch((ctx->opcode >> 21) & 0x3) {
6306 case 0:
6307 gen_helper_booke206_tlbilx0(cpu_env, t0);
6308 break;
6309 case 1:
6310 gen_helper_booke206_tlbilx1(cpu_env, t0);
6311 break;
6312 case 3:
6313 gen_helper_booke206_tlbilx3(cpu_env, t0);
6314 break;
6315 default:
6316 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6317 break;
6318 }
6319
6320 tcg_temp_free(t0);
6321 #endif
6322 }
6323
6324
6325 /* wrtee */
6326 static void gen_wrtee(DisasContext *ctx)
6327 {
6328 #if defined(CONFIG_USER_ONLY)
6329 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6330 #else
6331 TCGv t0;
6332 if (unlikely(!ctx->mem_idx)) {
6333 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6334 return;
6335 }
6336 t0 = tcg_temp_new();
6337 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6338 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6339 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6340 tcg_temp_free(t0);
6341 /* Stop translation to have a chance to raise an exception
6342 * if we just set msr_ee to 1
6343 */
6344 gen_stop_exception(ctx);
6345 #endif
6346 }
6347
6348 /* wrteei */
6349 static void gen_wrteei(DisasContext *ctx)
6350 {
6351 #if defined(CONFIG_USER_ONLY)
6352 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6353 #else
6354 if (unlikely(!ctx->mem_idx)) {
6355 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6356 return;
6357 }
6358 if (ctx->opcode & 0x00008000) {
6359 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6360 /* Stop translation to have a chance to raise an exception */
6361 gen_stop_exception(ctx);
6362 } else {
6363 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6364 }
6365 #endif
6366 }
6367
6368 /* PowerPC 440 specific instructions */
6369
6370 /* dlmzb */
6371 static void gen_dlmzb(DisasContext *ctx)
6372 {
6373 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6374 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6375 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6376 tcg_temp_free_i32(t0);
6377 }
6378
6379 /* mbar replaces eieio on 440 */
6380 static void gen_mbar(DisasContext *ctx)
6381 {
6382 /* interpreted as no-op */
6383 }
6384
6385 /* msync replaces sync on 440 */
6386 static void gen_msync_4xx(DisasContext *ctx)
6387 {
6388 /* interpreted as no-op */
6389 }
6390
6391 /* icbt */
6392 static void gen_icbt_440(DisasContext *ctx)
6393 {
6394 /* interpreted as no-op */
6395 /* XXX: specification say this is treated as a load by the MMU
6396 * but does not generate any exception
6397 */
6398 }
6399
6400 /* Embedded.Processor Control */
6401
6402 static void gen_msgclr(DisasContext *ctx)
6403 {
6404 #if defined(CONFIG_USER_ONLY)
6405 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6406 #else
6407 if (unlikely(ctx->mem_idx == 0)) {
6408 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6409 return;
6410 }
6411
6412 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6413 #endif
6414 }
6415
6416 static void gen_msgsnd(DisasContext *ctx)
6417 {
6418 #if defined(CONFIG_USER_ONLY)
6419 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6420 #else
6421 if (unlikely(ctx->mem_idx == 0)) {
6422 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6423 return;
6424 }
6425
6426 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6427 #endif
6428 }
6429
6430 /*** Altivec vector extension ***/
6431 /* Altivec registers moves */
6432
6433 static inline TCGv_ptr gen_avr_ptr(int reg)
6434 {
6435 TCGv_ptr r = tcg_temp_new_ptr();
6436 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6437 return r;
6438 }
6439
6440 #define GEN_VR_LDX(name, opc2, opc3) \
6441 static void glue(gen_, name)(DisasContext *ctx) \
6442 { \
6443 TCGv EA; \
6444 if (unlikely(!ctx->altivec_enabled)) { \
6445 gen_exception(ctx, POWERPC_EXCP_VPU); \
6446 return; \
6447 } \
6448 gen_set_access_type(ctx, ACCESS_INT); \
6449 EA = tcg_temp_new(); \
6450 gen_addr_reg_index(ctx, EA); \
6451 tcg_gen_andi_tl(EA, EA, ~0xf); \
6452 if (ctx->le_mode) { \
6453 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6454 tcg_gen_addi_tl(EA, EA, 8); \
6455 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6456 } else { \
6457 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6458 tcg_gen_addi_tl(EA, EA, 8); \
6459 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6460 } \
6461 tcg_temp_free(EA); \
6462 }
6463
6464 #define GEN_VR_STX(name, opc2, opc3) \
6465 static void gen_st##name(DisasContext *ctx) \
6466 { \
6467 TCGv EA; \
6468 if (unlikely(!ctx->altivec_enabled)) { \
6469 gen_exception(ctx, POWERPC_EXCP_VPU); \
6470 return; \
6471 } \
6472 gen_set_access_type(ctx, ACCESS_INT); \
6473 EA = tcg_temp_new(); \
6474 gen_addr_reg_index(ctx, EA); \
6475 tcg_gen_andi_tl(EA, EA, ~0xf); \
6476 if (ctx->le_mode) { \
6477 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6478 tcg_gen_addi_tl(EA, EA, 8); \
6479 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6480 } else { \
6481 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6482 tcg_gen_addi_tl(EA, EA, 8); \
6483 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6484 } \
6485 tcg_temp_free(EA); \
6486 }
6487
6488 #define GEN_VR_LVE(name, opc2, opc3) \
6489 static void gen_lve##name(DisasContext *ctx) \
6490 { \
6491 TCGv EA; \
6492 TCGv_ptr rs; \
6493 if (unlikely(!ctx->altivec_enabled)) { \
6494 gen_exception(ctx, POWERPC_EXCP_VPU); \
6495 return; \
6496 } \
6497 gen_set_access_type(ctx, ACCESS_INT); \
6498 EA = tcg_temp_new(); \
6499 gen_addr_reg_index(ctx, EA); \
6500 rs = gen_avr_ptr(rS(ctx->opcode)); \
6501 gen_helper_lve##name(cpu_env, rs, EA); \
6502 tcg_temp_free(EA); \
6503 tcg_temp_free_ptr(rs); \
6504 }
6505
6506 #define GEN_VR_STVE(name, opc2, opc3) \
6507 static void gen_stve##name(DisasContext *ctx) \
6508 { \
6509 TCGv EA; \
6510 TCGv_ptr rs; \
6511 if (unlikely(!ctx->altivec_enabled)) { \
6512 gen_exception(ctx, POWERPC_EXCP_VPU); \
6513 return; \
6514 } \
6515 gen_set_access_type(ctx, ACCESS_INT); \
6516 EA = tcg_temp_new(); \
6517 gen_addr_reg_index(ctx, EA); \
6518 rs = gen_avr_ptr(rS(ctx->opcode)); \
6519 gen_helper_stve##name(cpu_env, rs, EA); \
6520 tcg_temp_free(EA); \
6521 tcg_temp_free_ptr(rs); \
6522 }
6523
6524 GEN_VR_LDX(lvx, 0x07, 0x03);
6525 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6526 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6527
6528 GEN_VR_LVE(bx, 0x07, 0x00);
6529 GEN_VR_LVE(hx, 0x07, 0x01);
6530 GEN_VR_LVE(wx, 0x07, 0x02);
6531
6532 GEN_VR_STX(svx, 0x07, 0x07);
6533 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6534 GEN_VR_STX(svxl, 0x07, 0x0F);
6535
6536 GEN_VR_STVE(bx, 0x07, 0x04);
6537 GEN_VR_STVE(hx, 0x07, 0x05);
6538 GEN_VR_STVE(wx, 0x07, 0x06);
6539
6540 static void gen_lvsl(DisasContext *ctx)
6541 {
6542 TCGv_ptr rd;
6543 TCGv EA;
6544 if (unlikely(!ctx->altivec_enabled)) {
6545 gen_exception(ctx, POWERPC_EXCP_VPU);
6546 return;
6547 }
6548 EA = tcg_temp_new();
6549 gen_addr_reg_index(ctx, EA);
6550 rd = gen_avr_ptr(rD(ctx->opcode));
6551 gen_helper_lvsl(rd, EA);
6552 tcg_temp_free(EA);
6553 tcg_temp_free_ptr(rd);
6554 }
6555
6556 static void gen_lvsr(DisasContext *ctx)
6557 {
6558 TCGv_ptr rd;
6559 TCGv EA;
6560 if (unlikely(!ctx->altivec_enabled)) {
6561 gen_exception(ctx, POWERPC_EXCP_VPU);
6562 return;
6563 }
6564 EA = tcg_temp_new();
6565 gen_addr_reg_index(ctx, EA);
6566 rd = gen_avr_ptr(rD(ctx->opcode));
6567 gen_helper_lvsr(rd, EA);
6568 tcg_temp_free(EA);
6569 tcg_temp_free_ptr(rd);
6570 }
6571
6572 static void gen_mfvscr(DisasContext *ctx)
6573 {
6574 TCGv_i32 t;
6575 if (unlikely(!ctx->altivec_enabled)) {
6576 gen_exception(ctx, POWERPC_EXCP_VPU);
6577 return;
6578 }
6579 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6580 t = tcg_temp_new_i32();
6581 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6582 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6583 tcg_temp_free_i32(t);
6584 }
6585
6586 static void gen_mtvscr(DisasContext *ctx)
6587 {
6588 TCGv_ptr p;
6589 if (unlikely(!ctx->altivec_enabled)) {
6590 gen_exception(ctx, POWERPC_EXCP_VPU);
6591 return;
6592 }
6593 p = gen_avr_ptr(rD(ctx->opcode));
6594 gen_helper_mtvscr(cpu_env, p);
6595 tcg_temp_free_ptr(p);
6596 }
6597
6598 /* Logical operations */
6599 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6600 static void glue(gen_, name)(DisasContext *ctx) \
6601 { \
6602 if (unlikely(!ctx->altivec_enabled)) { \
6603 gen_exception(ctx, POWERPC_EXCP_VPU); \
6604 return; \
6605 } \
6606 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6607 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6608 }
6609
6610 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6611 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6612 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6613 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6614 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6615
6616 #define GEN_VXFORM(name, opc2, opc3) \
6617 static void glue(gen_, name)(DisasContext *ctx) \
6618 { \
6619 TCGv_ptr ra, rb, rd; \
6620 if (unlikely(!ctx->altivec_enabled)) { \
6621 gen_exception(ctx, POWERPC_EXCP_VPU); \
6622 return; \
6623 } \
6624 ra = gen_avr_ptr(rA(ctx->opcode)); \
6625 rb = gen_avr_ptr(rB(ctx->opcode)); \
6626 rd = gen_avr_ptr(rD(ctx->opcode)); \
6627 gen_helper_##name (rd, ra, rb); \
6628 tcg_temp_free_ptr(ra); \
6629 tcg_temp_free_ptr(rb); \
6630 tcg_temp_free_ptr(rd); \
6631 }
6632
6633 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6634 static void glue(gen_, name)(DisasContext *ctx) \
6635 { \
6636 TCGv_ptr ra, rb, rd; \
6637 if (unlikely(!ctx->altivec_enabled)) { \
6638 gen_exception(ctx, POWERPC_EXCP_VPU); \
6639 return; \
6640 } \
6641 ra = gen_avr_ptr(rA(ctx->opcode)); \
6642 rb = gen_avr_ptr(rB(ctx->opcode)); \
6643 rd = gen_avr_ptr(rD(ctx->opcode)); \
6644 gen_helper_##name(cpu_env, rd, ra, rb); \
6645 tcg_temp_free_ptr(ra); \
6646 tcg_temp_free_ptr(rb); \
6647 tcg_temp_free_ptr(rd); \
6648 }
6649
6650 GEN_VXFORM(vaddubm, 0, 0);
6651 GEN_VXFORM(vadduhm, 0, 1);
6652 GEN_VXFORM(vadduwm, 0, 2);
6653 GEN_VXFORM(vsububm, 0, 16);
6654 GEN_VXFORM(vsubuhm, 0, 17);
6655 GEN_VXFORM(vsubuwm, 0, 18);
6656 GEN_VXFORM(vmaxub, 1, 0);
6657 GEN_VXFORM(vmaxuh, 1, 1);
6658 GEN_VXFORM(vmaxuw, 1, 2);
6659 GEN_VXFORM(vmaxsb, 1, 4);
6660 GEN_VXFORM(vmaxsh, 1, 5);
6661 GEN_VXFORM(vmaxsw, 1, 6);
6662 GEN_VXFORM(vminub, 1, 8);
6663 GEN_VXFORM(vminuh, 1, 9);
6664 GEN_VXFORM(vminuw, 1, 10);
6665 GEN_VXFORM(vminsb, 1, 12);
6666 GEN_VXFORM(vminsh, 1, 13);
6667 GEN_VXFORM(vminsw, 1, 14);
6668 GEN_VXFORM(vavgub, 1, 16);
6669 GEN_VXFORM(vavguh, 1, 17);
6670 GEN_VXFORM(vavguw, 1, 18);
6671 GEN_VXFORM(vavgsb, 1, 20);
6672 GEN_VXFORM(vavgsh, 1, 21);
6673 GEN_VXFORM(vavgsw, 1, 22);
6674 GEN_VXFORM(vmrghb, 6, 0);
6675 GEN_VXFORM(vmrghh, 6, 1);
6676 GEN_VXFORM(vmrghw, 6, 2);
6677 GEN_VXFORM(vmrglb, 6, 4);
6678 GEN_VXFORM(vmrglh, 6, 5);
6679 GEN_VXFORM(vmrglw, 6, 6);
6680 GEN_VXFORM(vmuloub, 4, 0);
6681 GEN_VXFORM(vmulouh, 4, 1);
6682 GEN_VXFORM(vmulosb, 4, 4);
6683 GEN_VXFORM(vmulosh, 4, 5);
6684 GEN_VXFORM(vmuleub, 4, 8);
6685 GEN_VXFORM(vmuleuh, 4, 9);
6686 GEN_VXFORM(vmulesb, 4, 12);
6687 GEN_VXFORM(vmulesh, 4, 13);
6688 GEN_VXFORM(vslb, 2, 4);
6689 GEN_VXFORM(vslh, 2, 5);
6690 GEN_VXFORM(vslw, 2, 6);
6691 GEN_VXFORM(vsrb, 2, 8);
6692 GEN_VXFORM(vsrh, 2, 9);
6693 GEN_VXFORM(vsrw, 2, 10);
6694 GEN_VXFORM(vsrab, 2, 12);
6695 GEN_VXFORM(vsrah, 2, 13);
6696 GEN_VXFORM(vsraw, 2, 14);
6697 GEN_VXFORM(vslo, 6, 16);
6698 GEN_VXFORM(vsro, 6, 17);
6699 GEN_VXFORM(vaddcuw, 0, 6);
6700 GEN_VXFORM(vsubcuw, 0, 22);
6701 GEN_VXFORM_ENV(vaddubs, 0, 8);
6702 GEN_VXFORM_ENV(vadduhs, 0, 9);
6703 GEN_VXFORM_ENV(vadduws, 0, 10);
6704 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6705 GEN_VXFORM_ENV(vaddshs, 0, 13);
6706 GEN_VXFORM_ENV(vaddsws, 0, 14);
6707 GEN_VXFORM_ENV(vsububs, 0, 24);
6708 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6709 GEN_VXFORM_ENV(vsubuws, 0, 26);
6710 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6711 GEN_VXFORM_ENV(vsubshs, 0, 29);
6712 GEN_VXFORM_ENV(vsubsws, 0, 30);
6713 GEN_VXFORM(vrlb, 2, 0);
6714 GEN_VXFORM(vrlh, 2, 1);
6715 GEN_VXFORM(vrlw, 2, 2);
6716 GEN_VXFORM(vsl, 2, 7);
6717 GEN_VXFORM(vsr, 2, 11);
6718 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6719 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6720 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6721 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6722 GEN_VXFORM_ENV(vpkshus, 7, 4);
6723 GEN_VXFORM_ENV(vpkswus, 7, 5);
6724 GEN_VXFORM_ENV(vpkshss, 7, 6);
6725 GEN_VXFORM_ENV(vpkswss, 7, 7);
6726 GEN_VXFORM(vpkpx, 7, 12);
6727 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6728 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6729 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6730 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6731 GEN_VXFORM_ENV(vsumsws, 4, 30);
6732 GEN_VXFORM_ENV(vaddfp, 5, 0);
6733 GEN_VXFORM_ENV(vsubfp, 5, 1);
6734 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6735 GEN_VXFORM_ENV(vminfp, 5, 17);
6736
6737 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6738 static void glue(gen_, name)(DisasContext *ctx) \
6739 { \
6740 TCGv_ptr ra, rb, rd; \
6741 if (unlikely(!ctx->altivec_enabled)) { \
6742 gen_exception(ctx, POWERPC_EXCP_VPU); \
6743 return; \
6744 } \
6745 ra = gen_avr_ptr(rA(ctx->opcode)); \
6746 rb = gen_avr_ptr(rB(ctx->opcode)); \
6747 rd = gen_avr_ptr(rD(ctx->opcode)); \
6748 gen_helper_##opname(cpu_env, rd, ra, rb); \
6749 tcg_temp_free_ptr(ra); \
6750 tcg_temp_free_ptr(rb); \
6751 tcg_temp_free_ptr(rd); \
6752 }
6753
6754 #define GEN_VXRFORM(name, opc2, opc3) \
6755 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6756 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6757
6758 GEN_VXRFORM(vcmpequb, 3, 0)
6759 GEN_VXRFORM(vcmpequh, 3, 1)
6760 GEN_VXRFORM(vcmpequw, 3, 2)
6761 GEN_VXRFORM(vcmpgtsb, 3, 12)
6762 GEN_VXRFORM(vcmpgtsh, 3, 13)
6763 GEN_VXRFORM(vcmpgtsw, 3, 14)
6764 GEN_VXRFORM(vcmpgtub, 3, 8)
6765 GEN_VXRFORM(vcmpgtuh, 3, 9)
6766 GEN_VXRFORM(vcmpgtuw, 3, 10)
6767 GEN_VXRFORM(vcmpeqfp, 3, 3)
6768 GEN_VXRFORM(vcmpgefp, 3, 7)
6769 GEN_VXRFORM(vcmpgtfp, 3, 11)
6770 GEN_VXRFORM(vcmpbfp, 3, 15)
6771
6772 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6773 static void glue(gen_, name)(DisasContext *ctx) \
6774 { \
6775 TCGv_ptr rd; \
6776 TCGv_i32 simm; \
6777 if (unlikely(!ctx->altivec_enabled)) { \
6778 gen_exception(ctx, POWERPC_EXCP_VPU); \
6779 return; \
6780 } \
6781 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6782 rd = gen_avr_ptr(rD(ctx->opcode)); \
6783 gen_helper_##name (rd, simm); \
6784 tcg_temp_free_i32(simm); \
6785 tcg_temp_free_ptr(rd); \
6786 }
6787
6788 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6789 GEN_VXFORM_SIMM(vspltish, 6, 13);
6790 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6791
6792 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6793 static void glue(gen_, name)(DisasContext *ctx) \
6794 { \
6795 TCGv_ptr rb, rd; \
6796 if (unlikely(!ctx->altivec_enabled)) { \
6797 gen_exception(ctx, POWERPC_EXCP_VPU); \
6798 return; \
6799 } \
6800 rb = gen_avr_ptr(rB(ctx->opcode)); \
6801 rd = gen_avr_ptr(rD(ctx->opcode)); \
6802 gen_helper_##name (rd, rb); \
6803 tcg_temp_free_ptr(rb); \
6804 tcg_temp_free_ptr(rd); \
6805 }
6806
6807 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6808 static void glue(gen_, name)(DisasContext *ctx) \
6809 { \
6810 TCGv_ptr rb, rd; \
6811 \
6812 if (unlikely(!ctx->altivec_enabled)) { \
6813 gen_exception(ctx, POWERPC_EXCP_VPU); \
6814 return; \
6815 } \
6816 rb = gen_avr_ptr(rB(ctx->opcode)); \
6817 rd = gen_avr_ptr(rD(ctx->opcode)); \
6818 gen_helper_##name(cpu_env, rd, rb); \
6819 tcg_temp_free_ptr(rb); \
6820 tcg_temp_free_ptr(rd); \
6821 }
6822
6823 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6824 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6825 GEN_VXFORM_NOA(vupklsb, 7, 10);
6826 GEN_VXFORM_NOA(vupklsh, 7, 11);
6827 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6828 GEN_VXFORM_NOA(vupklpx, 7, 15);
6829 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6830 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6831 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6832 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6833 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6834 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6835 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6836 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6837
6838 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6839 static void glue(gen_, name)(DisasContext *ctx) \
6840 { \
6841 TCGv_ptr rd; \
6842 TCGv_i32 simm; \
6843 if (unlikely(!ctx->altivec_enabled)) { \
6844 gen_exception(ctx, POWERPC_EXCP_VPU); \
6845 return; \
6846 } \
6847 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6848 rd = gen_avr_ptr(rD(ctx->opcode)); \
6849 gen_helper_##name (rd, simm); \
6850 tcg_temp_free_i32(simm); \
6851 tcg_temp_free_ptr(rd); \
6852 }
6853
6854 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6855 static void glue(gen_, name)(DisasContext *ctx) \
6856 { \
6857 TCGv_ptr rb, rd; \
6858 TCGv_i32 uimm; \
6859 if (unlikely(!ctx->altivec_enabled)) { \
6860 gen_exception(ctx, POWERPC_EXCP_VPU); \
6861 return; \
6862 } \
6863 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6864 rb = gen_avr_ptr(rB(ctx->opcode)); \
6865 rd = gen_avr_ptr(rD(ctx->opcode)); \
6866 gen_helper_##name (rd, rb, uimm); \
6867 tcg_temp_free_i32(uimm); \
6868 tcg_temp_free_ptr(rb); \
6869 tcg_temp_free_ptr(rd); \
6870 }
6871
6872 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6873 static void glue(gen_, name)(DisasContext *ctx) \
6874 { \
6875 TCGv_ptr rb, rd; \
6876 TCGv_i32 uimm; \
6877 \
6878 if (unlikely(!ctx->altivec_enabled)) { \
6879 gen_exception(ctx, POWERPC_EXCP_VPU); \
6880 return; \
6881 } \
6882 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6883 rb = gen_avr_ptr(rB(ctx->opcode)); \
6884 rd = gen_avr_ptr(rD(ctx->opcode)); \
6885 gen_helper_##name(cpu_env, rd, rb, uimm); \
6886 tcg_temp_free_i32(uimm); \
6887 tcg_temp_free_ptr(rb); \
6888 tcg_temp_free_ptr(rd); \
6889 }
6890
6891 GEN_VXFORM_UIMM(vspltb, 6, 8);
6892 GEN_VXFORM_UIMM(vsplth, 6, 9);
6893 GEN_VXFORM_UIMM(vspltw, 6, 10);
6894 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
6895 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
6896 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
6897 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
6898
6899 static void gen_vsldoi(DisasContext *ctx)
6900 {
6901 TCGv_ptr ra, rb, rd;
6902 TCGv_i32 sh;
6903 if (unlikely(!ctx->altivec_enabled)) {
6904 gen_exception(ctx, POWERPC_EXCP_VPU);
6905 return;
6906 }
6907 ra = gen_avr_ptr(rA(ctx->opcode));
6908 rb = gen_avr_ptr(rB(ctx->opcode));
6909 rd = gen_avr_ptr(rD(ctx->opcode));
6910 sh = tcg_const_i32(VSH(ctx->opcode));
6911 gen_helper_vsldoi (rd, ra, rb, sh);
6912 tcg_temp_free_ptr(ra);
6913 tcg_temp_free_ptr(rb);
6914 tcg_temp_free_ptr(rd);
6915 tcg_temp_free_i32(sh);
6916 }
6917
6918 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6919 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6920 { \
6921 TCGv_ptr ra, rb, rc, rd; \
6922 if (unlikely(!ctx->altivec_enabled)) { \
6923 gen_exception(ctx, POWERPC_EXCP_VPU); \
6924 return; \
6925 } \
6926 ra = gen_avr_ptr(rA(ctx->opcode)); \
6927 rb = gen_avr_ptr(rB(ctx->opcode)); \
6928 rc = gen_avr_ptr(rC(ctx->opcode)); \
6929 rd = gen_avr_ptr(rD(ctx->opcode)); \
6930 if (Rc(ctx->opcode)) { \
6931 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6932 } else { \
6933 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6934 } \
6935 tcg_temp_free_ptr(ra); \
6936 tcg_temp_free_ptr(rb); \
6937 tcg_temp_free_ptr(rc); \
6938 tcg_temp_free_ptr(rd); \
6939 }
6940
6941 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6942
6943 static void gen_vmladduhm(DisasContext *ctx)
6944 {
6945 TCGv_ptr ra, rb, rc, rd;
6946 if (unlikely(!ctx->altivec_enabled)) {
6947 gen_exception(ctx, POWERPC_EXCP_VPU);
6948 return;
6949 }
6950 ra = gen_avr_ptr(rA(ctx->opcode));
6951 rb = gen_avr_ptr(rB(ctx->opcode));
6952 rc = gen_avr_ptr(rC(ctx->opcode));
6953 rd = gen_avr_ptr(rD(ctx->opcode));
6954 gen_helper_vmladduhm(rd, ra, rb, rc);
6955 tcg_temp_free_ptr(ra);
6956 tcg_temp_free_ptr(rb);
6957 tcg_temp_free_ptr(rc);
6958 tcg_temp_free_ptr(rd);
6959 }
6960
6961 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6962 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6963 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6964 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6965 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6966
6967 /*** SPE extension ***/
6968 /* Register moves */
6969
6970
6971 static inline void gen_evmra(DisasContext *ctx)
6972 {
6973
6974 if (unlikely(!ctx->spe_enabled)) {
6975 gen_exception(ctx, POWERPC_EXCP_SPEU);
6976 return;
6977 }
6978
6979 #if defined(TARGET_PPC64)
6980 /* rD := rA */
6981 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6982
6983 /* spe_acc := rA */
6984 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6985 cpu_env,
6986 offsetof(CPUPPCState, spe_acc));
6987 #else
6988 TCGv_i64 tmp = tcg_temp_new_i64();
6989
6990 /* tmp := rA_lo + rA_hi << 32 */
6991 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6992
6993 /* spe_acc := tmp */
6994 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
6995 tcg_temp_free_i64(tmp);
6996
6997 /* rD := rA */
6998 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6999 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7000 #endif
7001 }
7002
7003 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
7004 {
7005 #if defined(TARGET_PPC64)
7006 tcg_gen_mov_i64(t, cpu_gpr[reg]);
7007 #else
7008 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
7009 #endif
7010 }
7011
7012 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
7013 {
7014 #if defined(TARGET_PPC64)
7015 tcg_gen_mov_i64(cpu_gpr[reg], t);
7016 #else
7017 TCGv_i64 tmp = tcg_temp_new_i64();
7018 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
7019 tcg_gen_shri_i64(tmp, t, 32);
7020 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
7021 tcg_temp_free_i64(tmp);
7022 #endif
7023 }
7024
7025 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
7026 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7027 { \
7028 if (Rc(ctx->opcode)) \
7029 gen_##name1(ctx); \
7030 else \
7031 gen_##name0(ctx); \
7032 }
7033
7034 /* Handler for undefined SPE opcodes */
7035 static inline void gen_speundef(DisasContext *ctx)
7036 {
7037 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7038 }
7039
7040 /* SPE logic */
7041 #if defined(TARGET_PPC64)
7042 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
7043 static inline void gen_##name(DisasContext *ctx) \
7044 { \
7045 if (unlikely(!ctx->spe_enabled)) { \
7046 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7047 return; \
7048 } \
7049 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7050 cpu_gpr[rB(ctx->opcode)]); \
7051 }
7052 #else
7053 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
7054 static inline void gen_##name(DisasContext *ctx) \
7055 { \
7056 if (unlikely(!ctx->spe_enabled)) { \
7057 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7058 return; \
7059 } \
7060 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7061 cpu_gpr[rB(ctx->opcode)]); \
7062 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7063 cpu_gprh[rB(ctx->opcode)]); \
7064 }
7065 #endif
7066
7067 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
7068 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
7069 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
7070 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
7071 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
7072 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
7073 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
7074 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
7075
7076 /* SPE logic immediate */
7077 #if defined(TARGET_PPC64)
7078 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
7079 static inline void gen_##name(DisasContext *ctx) \
7080 { \
7081 if (unlikely(!ctx->spe_enabled)) { \
7082 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7083 return; \
7084 } \
7085 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7086 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7087 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7088 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7089 tcg_opi(t0, t0, rB(ctx->opcode)); \
7090 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7091 tcg_gen_trunc_i64_i32(t1, t2); \
7092 tcg_temp_free_i64(t2); \
7093 tcg_opi(t1, t1, rB(ctx->opcode)); \
7094 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7095 tcg_temp_free_i32(t0); \
7096 tcg_temp_free_i32(t1); \
7097 }
7098 #else
7099 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
7100 static inline void gen_##name(DisasContext *ctx) \
7101 { \
7102 if (unlikely(!ctx->spe_enabled)) { \
7103 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7104 return; \
7105 } \
7106 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7107 rB(ctx->opcode)); \
7108 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7109 rB(ctx->opcode)); \
7110 }
7111 #endif
7112 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
7113 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
7114 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
7115 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
7116
7117 /* SPE arithmetic */
7118 #if defined(TARGET_PPC64)
7119 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7120 static inline void gen_##name(DisasContext *ctx) \
7121 { \
7122 if (unlikely(!ctx->spe_enabled)) { \
7123 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7124 return; \
7125 } \
7126 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7127 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7128 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7129 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7130 tcg_op(t0, t0); \
7131 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7132 tcg_gen_trunc_i64_i32(t1, t2); \
7133 tcg_temp_free_i64(t2); \
7134 tcg_op(t1, t1); \
7135 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7136 tcg_temp_free_i32(t0); \
7137 tcg_temp_free_i32(t1); \
7138 }
7139 #else
7140 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7141 static inline void gen_##name(DisasContext *ctx) \
7142 { \
7143 if (unlikely(!ctx->spe_enabled)) { \
7144 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7145 return; \
7146 } \
7147 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
7148 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
7149 }
7150 #endif
7151
7152 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
7153 {
7154 int l1 = gen_new_label();
7155 int l2 = gen_new_label();
7156
7157 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
7158 tcg_gen_neg_i32(ret, arg1);
7159 tcg_gen_br(l2);
7160 gen_set_label(l1);
7161 tcg_gen_mov_i32(ret, arg1);
7162 gen_set_label(l2);
7163 }
7164 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
7165 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
7166 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
7167 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
7168 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
7169 {
7170 tcg_gen_addi_i32(ret, arg1, 0x8000);
7171 tcg_gen_ext16u_i32(ret, ret);
7172 }
7173 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
7174 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
7175 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
7176
7177 #if defined(TARGET_PPC64)
7178 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7179 static inline void gen_##name(DisasContext *ctx) \
7180 { \
7181 if (unlikely(!ctx->spe_enabled)) { \
7182 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7183 return; \
7184 } \
7185 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7186 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7187 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
7188 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
7189 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7190 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
7191 tcg_op(t0, t0, t2); \
7192 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
7193 tcg_gen_trunc_i64_i32(t1, t3); \
7194 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
7195 tcg_gen_trunc_i64_i32(t2, t3); \
7196 tcg_temp_free_i64(t3); \
7197 tcg_op(t1, t1, t2); \
7198 tcg_temp_free_i32(t2); \
7199 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7200 tcg_temp_free_i32(t0); \
7201 tcg_temp_free_i32(t1); \
7202 }
7203 #else
7204 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7205 static inline void gen_##name(DisasContext *ctx) \
7206 { \
7207 if (unlikely(!ctx->spe_enabled)) { \
7208 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7209 return; \
7210 } \
7211 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7212 cpu_gpr[rB(ctx->opcode)]); \
7213 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7214 cpu_gprh[rB(ctx->opcode)]); \
7215 }
7216 #endif
7217
7218 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7219 {
7220 TCGv_i32 t0;
7221 int l1, l2;
7222
7223 l1 = gen_new_label();
7224 l2 = gen_new_label();
7225 t0 = tcg_temp_local_new_i32();
7226 /* No error here: 6 bits are used */
7227 tcg_gen_andi_i32(t0, arg2, 0x3F);
7228 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7229 tcg_gen_shr_i32(ret, arg1, t0);
7230 tcg_gen_br(l2);
7231 gen_set_label(l1);
7232 tcg_gen_movi_i32(ret, 0);
7233 gen_set_label(l2);
7234 tcg_temp_free_i32(t0);
7235 }
7236 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7237 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7238 {
7239 TCGv_i32 t0;
7240 int l1, l2;
7241
7242 l1 = gen_new_label();
7243 l2 = gen_new_label();
7244 t0 = tcg_temp_local_new_i32();
7245 /* No error here: 6 bits are used */
7246 tcg_gen_andi_i32(t0, arg2, 0x3F);
7247 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7248 tcg_gen_sar_i32(ret, arg1, t0);
7249 tcg_gen_br(l2);
7250 gen_set_label(l1);
7251 tcg_gen_movi_i32(ret, 0);
7252 gen_set_label(l2);
7253 tcg_temp_free_i32(t0);
7254 }
7255 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7256 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7257 {
7258 TCGv_i32 t0;
7259 int l1, l2;
7260
7261 l1 = gen_new_label();
7262 l2 = gen_new_label();
7263 t0 = tcg_temp_local_new_i32();
7264 /* No error here: 6 bits are used */
7265 tcg_gen_andi_i32(t0, arg2, 0x3F);
7266 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7267 tcg_gen_shl_i32(ret, arg1, t0);
7268 tcg_gen_br(l2);
7269 gen_set_label(l1);
7270 tcg_gen_movi_i32(ret, 0);
7271 gen_set_label(l2);
7272 tcg_temp_free_i32(t0);
7273 }
7274 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7275 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7276 {
7277 TCGv_i32 t0 = tcg_temp_new_i32();
7278 tcg_gen_andi_i32(t0, arg2, 0x1F);
7279 tcg_gen_rotl_i32(ret, arg1, t0);
7280 tcg_temp_free_i32(t0);
7281 }
7282 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7283 static inline void gen_evmergehi(DisasContext *ctx)
7284 {
7285 if (unlikely(!ctx->spe_enabled)) {
7286 gen_exception(ctx, POWERPC_EXCP_SPEU);
7287 return;
7288 }
7289 #if defined(TARGET_PPC64)
7290 TCGv t0 = tcg_temp_new();
7291 TCGv t1 = tcg_temp_new();
7292 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7293 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7294 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7295 tcg_temp_free(t0);
7296 tcg_temp_free(t1);
7297 #else
7298 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7299 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7300 #endif
7301 }
7302 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7303 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7304 {
7305 tcg_gen_sub_i32(ret, arg2, arg1);
7306 }
7307 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7308
7309 /* SPE arithmetic immediate */
7310 #if defined(TARGET_PPC64)
7311 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7312 static inline void gen_##name(DisasContext *ctx) \
7313 { \
7314 if (unlikely(!ctx->spe_enabled)) { \
7315 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7316 return; \
7317 } \
7318 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7319 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7320 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7321 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7322 tcg_op(t0, t0, rA(ctx->opcode)); \
7323 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7324 tcg_gen_trunc_i64_i32(t1, t2); \
7325 tcg_temp_free_i64(t2); \
7326 tcg_op(t1, t1, rA(ctx->opcode)); \
7327 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7328 tcg_temp_free_i32(t0); \
7329 tcg_temp_free_i32(t1); \
7330 }
7331 #else
7332 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7333 static inline void gen_##name(DisasContext *ctx) \
7334 { \
7335 if (unlikely(!ctx->spe_enabled)) { \
7336 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7337 return; \
7338 } \
7339 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7340 rA(ctx->opcode)); \
7341 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7342 rA(ctx->opcode)); \
7343 }
7344 #endif
7345 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7346 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7347
7348 /* SPE comparison */
7349 #if defined(TARGET_PPC64)
7350 #define GEN_SPEOP_COMP(name, tcg_cond) \
7351 static inline void gen_##name(DisasContext *ctx) \
7352 { \
7353 if (unlikely(!ctx->spe_enabled)) { \
7354 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7355 return; \
7356 } \
7357 int l1 = gen_new_label(); \
7358 int l2 = gen_new_label(); \
7359 int l3 = gen_new_label(); \
7360 int l4 = gen_new_label(); \
7361 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7362 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7363 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7364 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7365 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7366 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7367 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7368 tcg_gen_br(l2); \
7369 gen_set_label(l1); \
7370 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7371 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7372 gen_set_label(l2); \
7373 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7374 tcg_gen_trunc_i64_i32(t0, t2); \
7375 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7376 tcg_gen_trunc_i64_i32(t1, t2); \
7377 tcg_temp_free_i64(t2); \
7378 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7379 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7380 ~(CRF_CH | CRF_CH_AND_CL)); \
7381 tcg_gen_br(l4); \
7382 gen_set_label(l3); \
7383 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7384 CRF_CH | CRF_CH_OR_CL); \
7385 gen_set_label(l4); \
7386 tcg_temp_free_i32(t0); \
7387 tcg_temp_free_i32(t1); \
7388 }
7389 #else
7390 #define GEN_SPEOP_COMP(name, tcg_cond) \
7391 static inline void gen_##name(DisasContext *ctx) \
7392 { \
7393 if (unlikely(!ctx->spe_enabled)) { \
7394 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7395 return; \
7396 } \
7397 int l1 = gen_new_label(); \
7398 int l2 = gen_new_label(); \
7399 int l3 = gen_new_label(); \
7400 int l4 = gen_new_label(); \
7401 \
7402 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7403 cpu_gpr[rB(ctx->opcode)], l1); \
7404 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7405 tcg_gen_br(l2); \
7406 gen_set_label(l1); \
7407 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7408 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7409 gen_set_label(l2); \
7410 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7411 cpu_gprh[rB(ctx->opcode)], l3); \
7412 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7413 ~(CRF_CH | CRF_CH_AND_CL)); \
7414 tcg_gen_br(l4); \
7415 gen_set_label(l3); \
7416 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7417 CRF_CH | CRF_CH_OR_CL); \
7418 gen_set_label(l4); \
7419 }
7420 #endif
7421 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7422 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7423 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7424 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7425 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7426
7427 /* SPE misc */
7428 static inline void gen_brinc(DisasContext *ctx)
7429 {
7430 /* Note: brinc is usable even if SPE is disabled */
7431 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7432 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7433 }
7434 static inline void gen_evmergelo(DisasContext *ctx)
7435 {
7436 if (unlikely(!ctx->spe_enabled)) {
7437 gen_exception(ctx, POWERPC_EXCP_SPEU);
7438 return;
7439 }
7440 #if defined(TARGET_PPC64)
7441 TCGv t0 = tcg_temp_new();
7442 TCGv t1 = tcg_temp_new();
7443 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7444 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7445 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7446 tcg_temp_free(t0);
7447 tcg_temp_free(t1);
7448 #else
7449 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7450 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7451 #endif
7452 }
7453 static inline void gen_evmergehilo(DisasContext *ctx)
7454 {
7455 if (unlikely(!ctx->spe_enabled)) {
7456 gen_exception(ctx, POWERPC_EXCP_SPEU);
7457 return;
7458 }
7459 #if defined(TARGET_PPC64)
7460 TCGv t0 = tcg_temp_new();
7461 TCGv t1 = tcg_temp_new();
7462 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7463 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7464 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7465 tcg_temp_free(t0);
7466 tcg_temp_free(t1);
7467 #else
7468 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7469 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7470 #endif
7471 }
7472 static inline void gen_evmergelohi(DisasContext *ctx)
7473 {
7474 if (unlikely(!ctx->spe_enabled)) {
7475 gen_exception(ctx, POWERPC_EXCP_SPEU);
7476 return;
7477 }
7478 #if defined(TARGET_PPC64)
7479 TCGv t0 = tcg_temp_new();
7480 TCGv t1 = tcg_temp_new();
7481 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7482 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7483 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7484 tcg_temp_free(t0);
7485 tcg_temp_free(t1);
7486 #else
7487 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7488 TCGv_i32 tmp = tcg_temp_new_i32();
7489 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7490 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7491 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7492 tcg_temp_free_i32(tmp);
7493 } else {
7494 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7495 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7496 }
7497 #endif
7498 }
7499 static inline void gen_evsplati(DisasContext *ctx)
7500 {
7501 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7502
7503 #if defined(TARGET_PPC64)
7504 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7505 #else
7506 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7507 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7508 #endif
7509 }
7510 static inline void gen_evsplatfi(DisasContext *ctx)
7511 {
7512 uint64_t imm = rA(ctx->opcode) << 27;
7513
7514 #if defined(TARGET_PPC64)
7515 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7516 #else
7517 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7518 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7519 #endif
7520 }
7521
7522 static inline void gen_evsel(DisasContext *ctx)
7523 {
7524 int l1 = gen_new_label();
7525 int l2 = gen_new_label();
7526 int l3 = gen_new_label();
7527 int l4 = gen_new_label();
7528 TCGv_i32 t0 = tcg_temp_local_new_i32();
7529 #if defined(TARGET_PPC64)
7530 TCGv t1 = tcg_temp_local_new();
7531 TCGv t2 = tcg_temp_local_new();
7532 #endif
7533 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7534 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7535 #if defined(TARGET_PPC64)
7536 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7537 #else
7538 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7539 #endif
7540 tcg_gen_br(l2);
7541 gen_set_label(l1);
7542 #if defined(TARGET_PPC64)
7543 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7544 #else
7545 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7546 #endif
7547 gen_set_label(l2);
7548 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7549 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7550 #if defined(TARGET_PPC64)
7551 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7552 #else
7553 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7554 #endif
7555 tcg_gen_br(l4);
7556 gen_set_label(l3);
7557 #if defined(TARGET_PPC64)
7558 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7559 #else
7560 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7561 #endif
7562 gen_set_label(l4);
7563 tcg_temp_free_i32(t0);
7564 #if defined(TARGET_PPC64)
7565 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7566 tcg_temp_free(t1);
7567 tcg_temp_free(t2);
7568 #endif
7569 }
7570
7571 static void gen_evsel0(DisasContext *ctx)
7572 {
7573 gen_evsel(ctx);
7574 }
7575
7576 static void gen_evsel1(DisasContext *ctx)
7577 {
7578 gen_evsel(ctx);
7579 }
7580
7581 static void gen_evsel2(DisasContext *ctx)
7582 {
7583 gen_evsel(ctx);
7584 }
7585
7586 static void gen_evsel3(DisasContext *ctx)
7587 {
7588 gen_evsel(ctx);
7589 }
7590
7591 /* Multiply */
7592
7593 static inline void gen_evmwumi(DisasContext *ctx)
7594 {
7595 TCGv_i64 t0, t1;
7596
7597 if (unlikely(!ctx->spe_enabled)) {
7598 gen_exception(ctx, POWERPC_EXCP_SPEU);
7599 return;
7600 }
7601
7602 t0 = tcg_temp_new_i64();
7603 t1 = tcg_temp_new_i64();
7604
7605 /* t0 := rA; t1 := rB */
7606 #if defined(TARGET_PPC64)
7607 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7608 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7609 #else
7610 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7611 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7612 #endif
7613
7614 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7615
7616 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7617
7618 tcg_temp_free_i64(t0);
7619 tcg_temp_free_i64(t1);
7620 }
7621
7622 static inline void gen_evmwumia(DisasContext *ctx)
7623 {
7624 TCGv_i64 tmp;
7625
7626 if (unlikely(!ctx->spe_enabled)) {
7627 gen_exception(ctx, POWERPC_EXCP_SPEU);
7628 return;
7629 }
7630
7631 gen_evmwumi(ctx); /* rD := rA * rB */
7632
7633 tmp = tcg_temp_new_i64();
7634
7635 /* acc := rD */
7636 gen_load_gpr64(tmp, rD(ctx->opcode));
7637 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7638 tcg_temp_free_i64(tmp);
7639 }
7640
7641 static inline void gen_evmwumiaa(DisasContext *ctx)
7642 {
7643 TCGv_i64 acc;
7644 TCGv_i64 tmp;
7645
7646 if (unlikely(!ctx->spe_enabled)) {
7647 gen_exception(ctx, POWERPC_EXCP_SPEU);
7648 return;
7649 }
7650
7651 gen_evmwumi(ctx); /* rD := rA * rB */
7652
7653 acc = tcg_temp_new_i64();
7654 tmp = tcg_temp_new_i64();
7655
7656 /* tmp := rD */
7657 gen_load_gpr64(tmp, rD(ctx->opcode));
7658
7659 /* Load acc */
7660 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7661
7662 /* acc := tmp + acc */
7663 tcg_gen_add_i64(acc, acc, tmp);
7664
7665 /* Store acc */
7666 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7667
7668 /* rD := acc */
7669 gen_store_gpr64(rD(ctx->opcode), acc);
7670
7671 tcg_temp_free_i64(acc);
7672 tcg_temp_free_i64(tmp);
7673 }
7674
7675 static inline void gen_evmwsmi(DisasContext *ctx)
7676 {
7677 TCGv_i64 t0, t1;
7678
7679 if (unlikely(!ctx->spe_enabled)) {
7680 gen_exception(ctx, POWERPC_EXCP_SPEU);
7681 return;
7682 }
7683
7684 t0 = tcg_temp_new_i64();
7685 t1 = tcg_temp_new_i64();
7686
7687 /* t0 := rA; t1 := rB */
7688 #if defined(TARGET_PPC64)
7689 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7690 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7691 #else
7692 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7693 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7694 #endif
7695
7696 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7697
7698 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7699
7700 tcg_temp_free_i64(t0);
7701 tcg_temp_free_i64(t1);
7702 }
7703
7704 static inline void gen_evmwsmia(DisasContext *ctx)
7705 {
7706 TCGv_i64 tmp;
7707
7708 gen_evmwsmi(ctx); /* rD := rA * rB */
7709
7710 tmp = tcg_temp_new_i64();
7711
7712 /* acc := rD */
7713 gen_load_gpr64(tmp, rD(ctx->opcode));
7714 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7715
7716 tcg_temp_free_i64(tmp);
7717 }
7718
7719 static inline void gen_evmwsmiaa(DisasContext *ctx)
7720 {
7721 TCGv_i64 acc = tcg_temp_new_i64();
7722 TCGv_i64 tmp = tcg_temp_new_i64();
7723
7724 gen_evmwsmi(ctx); /* rD := rA * rB */
7725
7726 acc = tcg_temp_new_i64();
7727 tmp = tcg_temp_new_i64();
7728
7729 /* tmp := rD */
7730 gen_load_gpr64(tmp, rD(ctx->opcode));
7731
7732 /* Load acc */
7733 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7734
7735 /* acc := tmp + acc */
7736 tcg_gen_add_i64(acc, acc, tmp);
7737
7738 /* Store acc */
7739 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7740
7741 /* rD := acc */
7742 gen_store_gpr64(rD(ctx->opcode), acc);
7743
7744 tcg_temp_free_i64(acc);
7745 tcg_temp_free_i64(tmp);
7746 }
7747
7748 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7749 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7750 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7751 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7752 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7753 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7754 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7755 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7756 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7757 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7758 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7759 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7760 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7761 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7762 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7763 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7764 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7765 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7766 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7767 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7768 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7769 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7770 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7771 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7772 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7773 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7774 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7775 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7776 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7777
7778 /* SPE load and stores */
7779 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7780 {
7781 target_ulong uimm = rB(ctx->opcode);
7782
7783 if (rA(ctx->opcode) == 0) {
7784 tcg_gen_movi_tl(EA, uimm << sh);
7785 } else {
7786 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7787 if (NARROW_MODE(ctx)) {
7788 tcg_gen_ext32u_tl(EA, EA);
7789 }
7790 }
7791 }
7792
7793 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7794 {
7795 #if defined(TARGET_PPC64)
7796 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7797 #else
7798 TCGv_i64 t0 = tcg_temp_new_i64();
7799 gen_qemu_ld64(ctx, t0, addr);
7800 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7801 tcg_gen_shri_i64(t0, t0, 32);
7802 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7803 tcg_temp_free_i64(t0);
7804 #endif
7805 }
7806
7807 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7808 {
7809 #if defined(TARGET_PPC64)
7810 TCGv t0 = tcg_temp_new();
7811 gen_qemu_ld32u(ctx, t0, addr);
7812 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7813 gen_addr_add(ctx, addr, addr, 4);
7814 gen_qemu_ld32u(ctx, t0, addr);
7815 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7816 tcg_temp_free(t0);
7817 #else
7818 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7819 gen_addr_add(ctx, addr, addr, 4);
7820 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7821 #endif
7822 }
7823
7824 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7825 {
7826 TCGv t0 = tcg_temp_new();
7827 #if defined(TARGET_PPC64)
7828 gen_qemu_ld16u(ctx, t0, addr);
7829 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7830 gen_addr_add(ctx, addr, addr, 2);
7831 gen_qemu_ld16u(ctx, t0, addr);
7832 tcg_gen_shli_tl(t0, t0, 32);
7833 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7834 gen_addr_add(ctx, addr, addr, 2);
7835 gen_qemu_ld16u(ctx, t0, addr);
7836 tcg_gen_shli_tl(t0, t0, 16);
7837 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7838 gen_addr_add(ctx, addr, addr, 2);
7839 gen_qemu_ld16u(ctx, t0, addr);
7840 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7841 #else
7842 gen_qemu_ld16u(ctx, t0, addr);
7843 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7844 gen_addr_add(ctx, addr, addr, 2);
7845 gen_qemu_ld16u(ctx, t0, addr);
7846 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7847 gen_addr_add(ctx, addr, addr, 2);
7848 gen_qemu_ld16u(ctx, t0, addr);
7849 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7850 gen_addr_add(ctx, addr, addr, 2);
7851 gen_qemu_ld16u(ctx, t0, addr);
7852 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7853 #endif
7854 tcg_temp_free(t0);
7855 }
7856
7857 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7858 {
7859 TCGv t0 = tcg_temp_new();
7860 gen_qemu_ld16u(ctx, t0, addr);
7861 #if defined(TARGET_PPC64)
7862 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7863 tcg_gen_shli_tl(t0, t0, 16);
7864 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7865 #else
7866 tcg_gen_shli_tl(t0, t0, 16);
7867 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7868 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7869 #endif
7870 tcg_temp_free(t0);
7871 }
7872
7873 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7874 {
7875 TCGv t0 = tcg_temp_new();
7876 gen_qemu_ld16u(ctx, t0, addr);
7877 #if defined(TARGET_PPC64)
7878 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7879 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7880 #else
7881 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7882 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7883 #endif
7884 tcg_temp_free(t0);
7885 }
7886
7887 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7888 {
7889 TCGv t0 = tcg_temp_new();
7890 gen_qemu_ld16s(ctx, t0, addr);
7891 #if defined(TARGET_PPC64)
7892 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7893 tcg_gen_ext32u_tl(t0, t0);
7894 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7895 #else
7896 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7897 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7898 #endif
7899 tcg_temp_free(t0);
7900 }
7901
7902 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7903 {
7904 TCGv t0 = tcg_temp_new();
7905 #if defined(TARGET_PPC64)
7906 gen_qemu_ld16u(ctx, t0, addr);
7907 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7908 gen_addr_add(ctx, addr, addr, 2);
7909 gen_qemu_ld16u(ctx, t0, addr);
7910 tcg_gen_shli_tl(t0, t0, 16);
7911 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7912 #else
7913 gen_qemu_ld16u(ctx, t0, addr);
7914 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7915 gen_addr_add(ctx, addr, addr, 2);
7916 gen_qemu_ld16u(ctx, t0, addr);
7917 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7918 #endif
7919 tcg_temp_free(t0);
7920 }
7921
7922 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7923 {
7924 #if defined(TARGET_PPC64)
7925 TCGv t0 = tcg_temp_new();
7926 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7927 gen_addr_add(ctx, addr, addr, 2);
7928 gen_qemu_ld16u(ctx, t0, addr);
7929 tcg_gen_shli_tl(t0, t0, 32);
7930 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7931 tcg_temp_free(t0);
7932 #else
7933 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7934 gen_addr_add(ctx, addr, addr, 2);
7935 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7936 #endif
7937 }
7938
7939 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7940 {
7941 #if defined(TARGET_PPC64)
7942 TCGv t0 = tcg_temp_new();
7943 gen_qemu_ld16s(ctx, t0, addr);
7944 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7945 gen_addr_add(ctx, addr, addr, 2);
7946 gen_qemu_ld16s(ctx, t0, addr);
7947 tcg_gen_shli_tl(t0, t0, 32);
7948 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7949 tcg_temp_free(t0);
7950 #else
7951 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7952 gen_addr_add(ctx, addr, addr, 2);
7953 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7954 #endif
7955 }
7956
7957 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7958 {
7959 TCGv t0 = tcg_temp_new();
7960 gen_qemu_ld32u(ctx, t0, addr);
7961 #if defined(TARGET_PPC64)
7962 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7963 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7964 #else
7965 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7966 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7967 #endif
7968 tcg_temp_free(t0);
7969 }
7970
7971 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7972 {
7973 TCGv t0 = tcg_temp_new();
7974 #if defined(TARGET_PPC64)
7975 gen_qemu_ld16u(ctx, t0, addr);
7976 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7977 tcg_gen_shli_tl(t0, t0, 32);
7978 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7979 gen_addr_add(ctx, addr, addr, 2);
7980 gen_qemu_ld16u(ctx, t0, addr);
7981 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7982 tcg_gen_shli_tl(t0, t0, 16);
7983 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7984 #else
7985 gen_qemu_ld16u(ctx, t0, addr);
7986 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7987 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7988 gen_addr_add(ctx, addr, addr, 2);
7989 gen_qemu_ld16u(ctx, t0, addr);
7990 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7991 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7992 #endif
7993 tcg_temp_free(t0);
7994 }
7995
7996 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7997 {
7998 #if defined(TARGET_PPC64)
7999 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8000 #else
8001 TCGv_i64 t0 = tcg_temp_new_i64();
8002 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
8003 gen_qemu_st64(ctx, t0, addr);
8004 tcg_temp_free_i64(t0);
8005 #endif
8006 }
8007
8008 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
8009 {
8010 #if defined(TARGET_PPC64)
8011 TCGv t0 = tcg_temp_new();
8012 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8013 gen_qemu_st32(ctx, t0, addr);
8014 tcg_temp_free(t0);
8015 #else
8016 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8017 #endif
8018 gen_addr_add(ctx, addr, addr, 4);
8019 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8020 }
8021
8022 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
8023 {
8024 TCGv t0 = tcg_temp_new();
8025 #if defined(TARGET_PPC64)
8026 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
8027 #else
8028 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
8029 #endif
8030 gen_qemu_st16(ctx, t0, addr);
8031 gen_addr_add(ctx, addr, addr, 2);
8032 #if defined(TARGET_PPC64)
8033 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8034 gen_qemu_st16(ctx, t0, addr);
8035 #else
8036 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8037 #endif
8038 gen_addr_add(ctx, addr, addr, 2);
8039 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
8040 gen_qemu_st16(ctx, t0, addr);
8041 tcg_temp_free(t0);
8042 gen_addr_add(ctx, addr, addr, 2);
8043 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8044 }
8045
8046 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
8047 {
8048 TCGv t0 = tcg_temp_new();
8049 #if defined(TARGET_PPC64)
8050 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
8051 #else
8052 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
8053 #endif
8054 gen_qemu_st16(ctx, t0, addr);
8055 gen_addr_add(ctx, addr, addr, 2);
8056 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
8057 gen_qemu_st16(ctx, t0, addr);
8058 tcg_temp_free(t0);
8059 }
8060
8061 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
8062 {
8063 #if defined(TARGET_PPC64)
8064 TCGv t0 = tcg_temp_new();
8065 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8066 gen_qemu_st16(ctx, t0, addr);
8067 tcg_temp_free(t0);
8068 #else
8069 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8070 #endif
8071 gen_addr_add(ctx, addr, addr, 2);
8072 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8073 }
8074
8075 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
8076 {
8077 #if defined(TARGET_PPC64)
8078 TCGv t0 = tcg_temp_new();
8079 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8080 gen_qemu_st32(ctx, t0, addr);
8081 tcg_temp_free(t0);
8082 #else
8083 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8084 #endif
8085 }
8086
8087 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
8088 {
8089 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8090 }
8091
8092 #define GEN_SPEOP_LDST(name, opc2, sh) \
8093 static void glue(gen_, name)(DisasContext *ctx) \
8094 { \
8095 TCGv t0; \
8096 if (unlikely(!ctx->spe_enabled)) { \
8097 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8098 return; \
8099 } \
8100 gen_set_access_type(ctx, ACCESS_INT); \
8101 t0 = tcg_temp_new(); \
8102 if (Rc(ctx->opcode)) { \
8103 gen_addr_spe_imm_index(ctx, t0, sh); \
8104 } else { \
8105 gen_addr_reg_index(ctx, t0); \
8106 } \
8107 gen_op_##name(ctx, t0); \
8108 tcg_temp_free(t0); \
8109 }
8110
8111 GEN_SPEOP_LDST(evldd, 0x00, 3);
8112 GEN_SPEOP_LDST(evldw, 0x01, 3);
8113 GEN_SPEOP_LDST(evldh, 0x02, 3);
8114 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
8115 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
8116 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
8117 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
8118 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
8119 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
8120 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
8121 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
8122
8123 GEN_SPEOP_LDST(evstdd, 0x10, 3);
8124 GEN_SPEOP_LDST(evstdw, 0x11, 3);
8125 GEN_SPEOP_LDST(evstdh, 0x12, 3);
8126 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
8127 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
8128 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
8129 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
8130
8131 /* Multiply and add - TODO */
8132 #if 0
8133 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
8134 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8135 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8136 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8137 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8138 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8139 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8140 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8141 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8142 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8143 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8144 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8145
8146 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8147 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8148 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8149 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8150 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8151 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8152 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8153 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8154 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8155 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8156 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8157 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8158
8159 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8160 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8161 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8162 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8163 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
8164
8165 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8166 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8167 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8168 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8169 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8170 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8171 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8172 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8173 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8174 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8175 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8176 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8177
8178 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8179 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8180 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8181 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8182
8183 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8184 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8185 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8186 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8187 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8188 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8189 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8190 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8191 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8192 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8193 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8194 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8195
8196 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8197 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8198 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8199 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8200 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8201 #endif
8202
8203 /*** SPE floating-point extension ***/
8204 #if defined(TARGET_PPC64)
8205 #define GEN_SPEFPUOP_CONV_32_32(name) \
8206 static inline void gen_##name(DisasContext *ctx) \
8207 { \
8208 TCGv_i32 t0; \
8209 TCGv t1; \
8210 t0 = tcg_temp_new_i32(); \
8211 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8212 gen_helper_##name(t0, cpu_env, t0); \
8213 t1 = tcg_temp_new(); \
8214 tcg_gen_extu_i32_tl(t1, t0); \
8215 tcg_temp_free_i32(t0); \
8216 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8217 0xFFFFFFFF00000000ULL); \
8218 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8219 tcg_temp_free(t1); \
8220 }
8221 #define GEN_SPEFPUOP_CONV_32_64(name) \
8222 static inline void gen_##name(DisasContext *ctx) \
8223 { \
8224 TCGv_i32 t0; \
8225 TCGv t1; \
8226 t0 = tcg_temp_new_i32(); \
8227 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8228 t1 = tcg_temp_new(); \
8229 tcg_gen_extu_i32_tl(t1, t0); \
8230 tcg_temp_free_i32(t0); \
8231 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8232 0xFFFFFFFF00000000ULL); \
8233 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8234 tcg_temp_free(t1); \
8235 }
8236 #define GEN_SPEFPUOP_CONV_64_32(name) \
8237 static inline void gen_##name(DisasContext *ctx) \
8238 { \
8239 TCGv_i32 t0 = tcg_temp_new_i32(); \
8240 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8241 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8242 tcg_temp_free_i32(t0); \
8243 }
8244 #define GEN_SPEFPUOP_CONV_64_64(name) \
8245 static inline void gen_##name(DisasContext *ctx) \
8246 { \
8247 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8248 cpu_gpr[rB(ctx->opcode)]); \
8249 }
8250 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8251 static inline void gen_##name(DisasContext *ctx) \
8252 { \
8253 TCGv_i32 t0, t1; \
8254 TCGv_i64 t2; \
8255 if (unlikely(!ctx->spe_enabled)) { \
8256 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8257 return; \
8258 } \
8259 t0 = tcg_temp_new_i32(); \
8260 t1 = tcg_temp_new_i32(); \
8261 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8262 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8263 gen_helper_##name(t0, cpu_env, t0, t1); \
8264 tcg_temp_free_i32(t1); \
8265 t2 = tcg_temp_new(); \
8266 tcg_gen_extu_i32_tl(t2, t0); \
8267 tcg_temp_free_i32(t0); \
8268 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8269 0xFFFFFFFF00000000ULL); \
8270 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8271 tcg_temp_free(t2); \
8272 }
8273 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8274 static inline void gen_##name(DisasContext *ctx) \
8275 { \
8276 if (unlikely(!ctx->spe_enabled)) { \
8277 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8278 return; \
8279 } \
8280 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8281 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8282 }
8283 #define GEN_SPEFPUOP_COMP_32(name) \
8284 static inline void gen_##name(DisasContext *ctx) \
8285 { \
8286 TCGv_i32 t0, t1; \
8287 if (unlikely(!ctx->spe_enabled)) { \
8288 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8289 return; \
8290 } \
8291 t0 = tcg_temp_new_i32(); \
8292 t1 = tcg_temp_new_i32(); \
8293 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8294 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8295 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8296 tcg_temp_free_i32(t0); \
8297 tcg_temp_free_i32(t1); \
8298 }
8299 #define GEN_SPEFPUOP_COMP_64(name) \
8300 static inline void gen_##name(DisasContext *ctx) \
8301 { \
8302 if (unlikely(!ctx->spe_enabled)) { \
8303 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8304 return; \
8305 } \
8306 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8307 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8308 }
8309 #else
8310 #define GEN_SPEFPUOP_CONV_32_32(name) \
8311 static inline void gen_##name(DisasContext *ctx) \
8312 { \
8313 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8314 cpu_gpr[rB(ctx->opcode)]); \
8315 }
8316 #define GEN_SPEFPUOP_CONV_32_64(name) \
8317 static inline void gen_##name(DisasContext *ctx) \
8318 { \
8319 TCGv_i64 t0 = tcg_temp_new_i64(); \
8320 gen_load_gpr64(t0, rB(ctx->opcode)); \
8321 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8322 tcg_temp_free_i64(t0); \
8323 }
8324 #define GEN_SPEFPUOP_CONV_64_32(name) \
8325 static inline void gen_##name(DisasContext *ctx) \
8326 { \
8327 TCGv_i64 t0 = tcg_temp_new_i64(); \
8328 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8329 gen_store_gpr64(rD(ctx->opcode), t0); \
8330 tcg_temp_free_i64(t0); \
8331 }
8332 #define GEN_SPEFPUOP_CONV_64_64(name) \
8333 static inline void gen_##name(DisasContext *ctx) \
8334 { \
8335 TCGv_i64 t0 = tcg_temp_new_i64(); \
8336 gen_load_gpr64(t0, rB(ctx->opcode)); \
8337 gen_helper_##name(t0, cpu_env, t0); \
8338 gen_store_gpr64(rD(ctx->opcode), t0); \
8339 tcg_temp_free_i64(t0); \
8340 }
8341 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8342 static inline void gen_##name(DisasContext *ctx) \
8343 { \
8344 if (unlikely(!ctx->spe_enabled)) { \
8345 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8346 return; \
8347 } \
8348 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8349 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8350 }
8351 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8352 static inline void gen_##name(DisasContext *ctx) \
8353 { \
8354 TCGv_i64 t0, t1; \
8355 if (unlikely(!ctx->spe_enabled)) { \
8356 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8357 return; \
8358 } \
8359 t0 = tcg_temp_new_i64(); \
8360 t1 = tcg_temp_new_i64(); \
8361 gen_load_gpr64(t0, rA(ctx->opcode)); \
8362 gen_load_gpr64(t1, rB(ctx->opcode)); \
8363 gen_helper_##name(t0, cpu_env, t0, t1); \
8364 gen_store_gpr64(rD(ctx->opcode), t0); \
8365 tcg_temp_free_i64(t0); \
8366 tcg_temp_free_i64(t1); \
8367 }
8368 #define GEN_SPEFPUOP_COMP_32(name) \
8369 static inline void gen_##name(DisasContext *ctx) \
8370 { \
8371 if (unlikely(!ctx->spe_enabled)) { \
8372 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8373 return; \
8374 } \
8375 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8376 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8377 }
8378 #define GEN_SPEFPUOP_COMP_64(name) \
8379 static inline void gen_##name(DisasContext *ctx) \
8380 { \
8381 TCGv_i64 t0, t1; \
8382 if (unlikely(!ctx->spe_enabled)) { \
8383 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8384 return; \
8385 } \
8386 t0 = tcg_temp_new_i64(); \
8387 t1 = tcg_temp_new_i64(); \
8388 gen_load_gpr64(t0, rA(ctx->opcode)); \
8389 gen_load_gpr64(t1, rB(ctx->opcode)); \
8390 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8391 tcg_temp_free_i64(t0); \
8392 tcg_temp_free_i64(t1); \
8393 }
8394 #endif
8395
8396 /* Single precision floating-point vectors operations */
8397 /* Arithmetic */
8398 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8399 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8400 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8401 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8402 static inline void gen_evfsabs(DisasContext *ctx)
8403 {
8404 if (unlikely(!ctx->spe_enabled)) {
8405 gen_exception(ctx, POWERPC_EXCP_SPEU);
8406 return;
8407 }
8408 #if defined(TARGET_PPC64)
8409 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8410 #else
8411 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8412 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8413 #endif
8414 }
8415 static inline void gen_evfsnabs(DisasContext *ctx)
8416 {
8417 if (unlikely(!ctx->spe_enabled)) {
8418 gen_exception(ctx, POWERPC_EXCP_SPEU);
8419 return;
8420 }
8421 #if defined(TARGET_PPC64)
8422 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8423 #else
8424 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8425 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8426 #endif
8427 }
8428 static inline void gen_evfsneg(DisasContext *ctx)
8429 {
8430 if (unlikely(!ctx->spe_enabled)) {
8431 gen_exception(ctx, POWERPC_EXCP_SPEU);
8432 return;
8433 }
8434 #if defined(TARGET_PPC64)
8435 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8436 #else
8437 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8438 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8439 #endif
8440 }
8441
8442 /* Conversion */
8443 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8444 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8445 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8446 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8447 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8448 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8449 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8450 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8451 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8452 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8453
8454 /* Comparison */
8455 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8456 GEN_SPEFPUOP_COMP_64(evfscmplt);
8457 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8458 GEN_SPEFPUOP_COMP_64(evfststgt);
8459 GEN_SPEFPUOP_COMP_64(evfststlt);
8460 GEN_SPEFPUOP_COMP_64(evfststeq);
8461
8462 /* Opcodes definitions */
8463 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8464 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8465 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8466 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8467 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8468 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8469 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8470 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8471 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8472 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8473 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8474 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8475 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8476 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8477
8478 /* Single precision floating-point operations */
8479 /* Arithmetic */
8480 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8481 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8482 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8483 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8484 static inline void gen_efsabs(DisasContext *ctx)
8485 {
8486 if (unlikely(!ctx->spe_enabled)) {
8487 gen_exception(ctx, POWERPC_EXCP_SPEU);
8488 return;
8489 }
8490 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8491 }
8492 static inline void gen_efsnabs(DisasContext *ctx)
8493 {
8494 if (unlikely(!ctx->spe_enabled)) {
8495 gen_exception(ctx, POWERPC_EXCP_SPEU);
8496 return;
8497 }
8498 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8499 }
8500 static inline void gen_efsneg(DisasContext *ctx)
8501 {
8502 if (unlikely(!ctx->spe_enabled)) {
8503 gen_exception(ctx, POWERPC_EXCP_SPEU);
8504 return;
8505 }
8506 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8507 }
8508
8509 /* Conversion */
8510 GEN_SPEFPUOP_CONV_32_32(efscfui);
8511 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8512 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8513 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8514 GEN_SPEFPUOP_CONV_32_32(efsctui);
8515 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8516 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8517 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8518 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8519 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8520 GEN_SPEFPUOP_CONV_32_64(efscfd);
8521
8522 /* Comparison */
8523 GEN_SPEFPUOP_COMP_32(efscmpgt);
8524 GEN_SPEFPUOP_COMP_32(efscmplt);
8525 GEN_SPEFPUOP_COMP_32(efscmpeq);
8526 GEN_SPEFPUOP_COMP_32(efststgt);
8527 GEN_SPEFPUOP_COMP_32(efststlt);
8528 GEN_SPEFPUOP_COMP_32(efststeq);
8529
8530 /* Opcodes definitions */
8531 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8532 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8533 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8534 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8535 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8536 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8537 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8538 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8539 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8540 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8541 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8542 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8543 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8544 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8545
8546 /* Double precision floating-point operations */
8547 /* Arithmetic */
8548 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8549 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8550 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8551 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8552 static inline void gen_efdabs(DisasContext *ctx)
8553 {
8554 if (unlikely(!ctx->spe_enabled)) {
8555 gen_exception(ctx, POWERPC_EXCP_SPEU);
8556 return;
8557 }
8558 #if defined(TARGET_PPC64)
8559 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8560 #else
8561 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8562 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8563 #endif
8564 }
8565 static inline void gen_efdnabs(DisasContext *ctx)
8566 {
8567 if (unlikely(!ctx->spe_enabled)) {
8568 gen_exception(ctx, POWERPC_EXCP_SPEU);
8569 return;
8570 }
8571 #if defined(TARGET_PPC64)
8572 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8573 #else
8574 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8575 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8576 #endif
8577 }
8578 static inline void gen_efdneg(DisasContext *ctx)
8579 {
8580 if (unlikely(!ctx->spe_enabled)) {
8581 gen_exception(ctx, POWERPC_EXCP_SPEU);
8582 return;
8583 }
8584 #if defined(TARGET_PPC64)
8585 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8586 #else
8587 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8588 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8589 #endif
8590 }
8591
8592 /* Conversion */
8593 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8594 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8595 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8596 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8597 GEN_SPEFPUOP_CONV_32_64(efdctui);
8598 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8599 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8600 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8601 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8602 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8603 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8604 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8605 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8606 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8607 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8608
8609 /* Comparison */
8610 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8611 GEN_SPEFPUOP_COMP_64(efdcmplt);
8612 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8613 GEN_SPEFPUOP_COMP_64(efdtstgt);
8614 GEN_SPEFPUOP_COMP_64(efdtstlt);
8615 GEN_SPEFPUOP_COMP_64(efdtsteq);
8616
8617 /* Opcodes definitions */
8618 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8619 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8620 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8621 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8622 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8623 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8624 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8625 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8626 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8627 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8628 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8629 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8630 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8631 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8632 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8633 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8634
8635 static opcode_t opcodes[] = {
8636 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8637 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8638 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8639 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8640 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8641 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
8642 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8643 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8644 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8645 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8646 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8647 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8648 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8649 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8650 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8651 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8652 #if defined(TARGET_PPC64)
8653 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8654 #endif
8655 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8656 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8657 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8658 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8659 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8660 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8661 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8662 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8663 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8664 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8665 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8666 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8667 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8668 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8669 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
8670 #if defined(TARGET_PPC64)
8671 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8672 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8673 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
8674 #endif
8675 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8676 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8677 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8678 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8679 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8680 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8681 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8682 #if defined(TARGET_PPC64)
8683 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8684 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8685 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8686 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8687 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8688 #endif
8689 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8690 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8691 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8692 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8693 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8694 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
8695 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8696 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
8697 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
8698 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
8699 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8700 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8701 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8702 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8703 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
8704 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
8705 #if defined(TARGET_PPC64)
8706 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8707 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8708 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8709 #endif
8710 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8711 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8712 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8713 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8714 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8715 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8716 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8717 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8718 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8719 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8720 #if defined(TARGET_PPC64)
8721 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8722 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8723 #endif
8724 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8725 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8726 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8727 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8728 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8729 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8730 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8731 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8732 #if defined(TARGET_PPC64)
8733 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8734 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8735 #endif
8736 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8737 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8738 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8739 #if defined(TARGET_PPC64)
8740 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8741 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8742 #endif
8743 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8744 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8745 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8746 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8747 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8748 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8749 #if defined(TARGET_PPC64)
8750 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8751 #endif
8752 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8753 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8754 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8755 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8756 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8757 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8758 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8759 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
8760 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8761 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8762 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8763 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8764 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8765 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8766 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8767 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8768 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8769 #if defined(TARGET_PPC64)
8770 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8771 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8772 PPC_SEGMENT_64B),
8773 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8774 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8775 PPC_SEGMENT_64B),
8776 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8777 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8778 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8779 #endif
8780 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8781 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8782 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8783 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8784 #if defined(TARGET_PPC64)
8785 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8786 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8787 #endif
8788 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8789 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8790 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8791 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8792 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8793 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8794 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8795 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8796 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8797 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8798 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8799 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8800 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8801 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8802 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8803 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8804 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8805 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8806 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8807 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8808 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8809 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8810 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8811 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8812 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8813 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8814 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8815 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8816 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8817 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8818 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8819 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8820 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8821 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8822 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8823 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8824 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8825 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8826 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8827 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8828 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8829 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8830 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8831 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8832 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8833 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8834 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8835 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8836 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8837 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8838 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8839 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8840 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8841 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8842 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8843 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8844 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8845 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8846 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8847 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8848 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8849 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8850 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8851 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8852 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8853 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8854 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8855 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8856 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8857 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8858 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8859 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8860 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8861 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8862 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8863 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8864 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8865 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8866 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8867 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8868 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8869 PPC_NONE, PPC2_BOOKE206),
8870 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8871 PPC_NONE, PPC2_BOOKE206),
8872 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8873 PPC_NONE, PPC2_BOOKE206),
8874 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8875 PPC_NONE, PPC2_BOOKE206),
8876 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8877 PPC_NONE, PPC2_BOOKE206),
8878 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8879 PPC_NONE, PPC2_PRCNTL),
8880 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8881 PPC_NONE, PPC2_PRCNTL),
8882 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8883 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8884 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8885 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8886 PPC_BOOKE, PPC2_BOOKE206),
8887 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8888 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8889 PPC_BOOKE, PPC2_BOOKE206),
8890 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8891 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8892 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8893 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8894 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8895 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8896 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8897 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8898 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8899 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8900
8901 #undef GEN_INT_ARITH_ADD
8902 #undef GEN_INT_ARITH_ADD_CONST
8903 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8904 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8905 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8906 add_ca, compute_ca, compute_ov) \
8907 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8908 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8909 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8910 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8911 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8912 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8913 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8914 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8915 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8916 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8917 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8918
8919 #undef GEN_INT_ARITH_DIVW
8920 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8921 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8922 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8923 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8924 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8925 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8926
8927 #if defined(TARGET_PPC64)
8928 #undef GEN_INT_ARITH_DIVD
8929 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8930 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8931 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8932 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8933 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8934 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8935
8936 #undef GEN_INT_ARITH_MUL_HELPER
8937 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8938 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8939 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8940 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8941 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8942 #endif
8943
8944 #undef GEN_INT_ARITH_SUBF
8945 #undef GEN_INT_ARITH_SUBF_CONST
8946 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8947 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8948 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8949 add_ca, compute_ca, compute_ov) \
8950 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8951 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8952 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8953 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8954 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8955 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8956 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8957 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8958 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8959 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8960 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8961
8962 #undef GEN_LOGICAL1
8963 #undef GEN_LOGICAL2
8964 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8965 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8966 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8967 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8968 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8969 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8970 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8971 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8972 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8973 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8974 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8975 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8976 #if defined(TARGET_PPC64)
8977 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8978 #endif
8979
8980 #if defined(TARGET_PPC64)
8981 #undef GEN_PPC64_R2
8982 #undef GEN_PPC64_R4
8983 #define GEN_PPC64_R2(name, opc1, opc2) \
8984 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8985 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8986 PPC_64B)
8987 #define GEN_PPC64_R4(name, opc1, opc2) \
8988 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8989 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8990 PPC_64B), \
8991 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8992 PPC_64B), \
8993 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8994 PPC_64B)
8995 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8996 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8997 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8998 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8999 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
9000 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
9001 #endif
9002
9003 #undef _GEN_FLOAT_ACB
9004 #undef GEN_FLOAT_ACB
9005 #undef _GEN_FLOAT_AB
9006 #undef GEN_FLOAT_AB
9007 #undef _GEN_FLOAT_AC
9008 #undef GEN_FLOAT_AC
9009 #undef GEN_FLOAT_B
9010 #undef GEN_FLOAT_BS
9011 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
9012 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
9013 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
9014 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
9015 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
9016 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
9017 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
9018 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
9019 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
9020 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
9021 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
9022 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
9023 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
9024 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
9025 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
9026 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
9027 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
9028 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
9029 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
9030
9031 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
9032 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
9033 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
9034 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
9035 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
9036 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
9037 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
9038 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
9039 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
9040 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
9041 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
9042 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
9043 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
9044 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
9045 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
9046 #if defined(TARGET_PPC64)
9047 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
9048 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
9049 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
9050 #endif
9051 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
9052 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
9053 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
9054 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
9055
9056 #undef GEN_LD
9057 #undef GEN_LDU
9058 #undef GEN_LDUX
9059 #undef GEN_LDX_E
9060 #undef GEN_LDS
9061 #define GEN_LD(name, ldop, opc, type) \
9062 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9063 #define GEN_LDU(name, ldop, opc, type) \
9064 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9065 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
9066 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
9067 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
9068 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
9069 #define GEN_LDS(name, ldop, op, type) \
9070 GEN_LD(name, ldop, op | 0x20, type) \
9071 GEN_LDU(name, ldop, op | 0x21, type) \
9072 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
9073 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
9074
9075 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
9076 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
9077 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
9078 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
9079 #if defined(TARGET_PPC64)
9080 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
9081 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
9082 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
9083 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
9084 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
9085 #endif
9086 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
9087 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
9088
9089 #undef GEN_ST
9090 #undef GEN_STU
9091 #undef GEN_STUX
9092 #undef GEN_STX_E
9093 #undef GEN_STS
9094 #define GEN_ST(name, stop, opc, type) \
9095 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9096 #define GEN_STU(name, stop, opc, type) \
9097 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
9098 #define GEN_STUX(name, stop, opc2, opc3, type) \
9099 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
9100 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
9101 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
9102 #define GEN_STS(name, stop, op, type) \
9103 GEN_ST(name, stop, op | 0x20, type) \
9104 GEN_STU(name, stop, op | 0x21, type) \
9105 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
9106 GEN_STX(name, stop, 0x17, op | 0x00, type)
9107
9108 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
9109 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
9110 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
9111 #if defined(TARGET_PPC64)
9112 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
9113 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
9114 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
9115 #endif
9116 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
9117 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
9118
9119 #undef GEN_LDF
9120 #undef GEN_LDUF
9121 #undef GEN_LDUXF
9122 #undef GEN_LDXF
9123 #undef GEN_LDFS
9124 #define GEN_LDF(name, ldop, opc, type) \
9125 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9126 #define GEN_LDUF(name, ldop, opc, type) \
9127 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9128 #define GEN_LDUXF(name, ldop, opc, type) \
9129 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9130 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
9131 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9132 #define GEN_LDFS(name, ldop, op, type) \
9133 GEN_LDF(name, ldop, op | 0x20, type) \
9134 GEN_LDUF(name, ldop, op | 0x21, type) \
9135 GEN_LDUXF(name, ldop, op | 0x01, type) \
9136 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
9137
9138 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
9139 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
9140 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
9141 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
9142 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
9143
9144 #undef GEN_STF
9145 #undef GEN_STUF
9146 #undef GEN_STUXF
9147 #undef GEN_STXF
9148 #undef GEN_STFS
9149 #define GEN_STF(name, stop, opc, type) \
9150 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9151 #define GEN_STUF(name, stop, opc, type) \
9152 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9153 #define GEN_STUXF(name, stop, opc, type) \
9154 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9155 #define GEN_STXF(name, stop, opc2, opc3, type) \
9156 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9157 #define GEN_STFS(name, stop, op, type) \
9158 GEN_STF(name, stop, op | 0x20, type) \
9159 GEN_STUF(name, stop, op | 0x21, type) \
9160 GEN_STUXF(name, stop, op | 0x01, type) \
9161 GEN_STXF(name, stop, 0x17, op | 0x00, type)
9162
9163 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
9164 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
9165 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
9166 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
9167 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
9168
9169 #undef GEN_CRLOGIC
9170 #define GEN_CRLOGIC(name, tcg_op, opc) \
9171 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
9172 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
9173 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
9174 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
9175 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
9176 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
9177 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
9178 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
9179 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
9180
9181 #undef GEN_MAC_HANDLER
9182 #define GEN_MAC_HANDLER(name, opc2, opc3) \
9183 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
9184 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
9185 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
9186 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
9187 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
9188 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
9189 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
9190 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
9191 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
9192 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
9193 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
9194 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
9195 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
9196 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
9197 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
9198 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
9199 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
9200 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
9201 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
9202 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
9203 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
9204 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
9205 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
9206 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
9207 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
9208 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
9209 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
9210 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
9211 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
9212 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
9213 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
9214 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
9215 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
9216 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
9217 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
9218 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
9219 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
9220 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
9221 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
9222 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
9223 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
9224 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
9225 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
9226
9227 #undef GEN_VR_LDX
9228 #undef GEN_VR_STX
9229 #undef GEN_VR_LVE
9230 #undef GEN_VR_STVE
9231 #define GEN_VR_LDX(name, opc2, opc3) \
9232 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9233 #define GEN_VR_STX(name, opc2, opc3) \
9234 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9235 #define GEN_VR_LVE(name, opc2, opc3) \
9236 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9237 #define GEN_VR_STVE(name, opc2, opc3) \
9238 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9239 GEN_VR_LDX(lvx, 0x07, 0x03),
9240 GEN_VR_LDX(lvxl, 0x07, 0x0B),
9241 GEN_VR_LVE(bx, 0x07, 0x00),
9242 GEN_VR_LVE(hx, 0x07, 0x01),
9243 GEN_VR_LVE(wx, 0x07, 0x02),
9244 GEN_VR_STX(svx, 0x07, 0x07),
9245 GEN_VR_STX(svxl, 0x07, 0x0F),
9246 GEN_VR_STVE(bx, 0x07, 0x04),
9247 GEN_VR_STVE(hx, 0x07, 0x05),
9248 GEN_VR_STVE(wx, 0x07, 0x06),
9249
9250 #undef GEN_VX_LOGICAL
9251 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9252 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9253 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9254 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9255 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9256 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9257 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9258
9259 #undef GEN_VXFORM
9260 #define GEN_VXFORM(name, opc2, opc3) \
9261 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9262 GEN_VXFORM(vaddubm, 0, 0),
9263 GEN_VXFORM(vadduhm, 0, 1),
9264 GEN_VXFORM(vadduwm, 0, 2),
9265 GEN_VXFORM(vsububm, 0, 16),
9266 GEN_VXFORM(vsubuhm, 0, 17),
9267 GEN_VXFORM(vsubuwm, 0, 18),
9268 GEN_VXFORM(vmaxub, 1, 0),
9269 GEN_VXFORM(vmaxuh, 1, 1),
9270 GEN_VXFORM(vmaxuw, 1, 2),
9271 GEN_VXFORM(vmaxsb, 1, 4),
9272 GEN_VXFORM(vmaxsh, 1, 5),
9273 GEN_VXFORM(vmaxsw, 1, 6),
9274 GEN_VXFORM(vminub, 1, 8),
9275 GEN_VXFORM(vminuh, 1, 9),
9276 GEN_VXFORM(vminuw, 1, 10),
9277 GEN_VXFORM(vminsb, 1, 12),
9278 GEN_VXFORM(vminsh, 1, 13),
9279 GEN_VXFORM(vminsw, 1, 14),
9280 GEN_VXFORM(vavgub, 1, 16),
9281 GEN_VXFORM(vavguh, 1, 17),
9282 GEN_VXFORM(vavguw, 1, 18),
9283 GEN_VXFORM(vavgsb, 1, 20),
9284 GEN_VXFORM(vavgsh, 1, 21),
9285 GEN_VXFORM(vavgsw, 1, 22),
9286 GEN_VXFORM(vmrghb, 6, 0),
9287 GEN_VXFORM(vmrghh, 6, 1),
9288 GEN_VXFORM(vmrghw, 6, 2),
9289 GEN_VXFORM(vmrglb, 6, 4),
9290 GEN_VXFORM(vmrglh, 6, 5),
9291 GEN_VXFORM(vmrglw, 6, 6),
9292 GEN_VXFORM(vmuloub, 4, 0),
9293 GEN_VXFORM(vmulouh, 4, 1),
9294 GEN_VXFORM(vmulosb, 4, 4),
9295 GEN_VXFORM(vmulosh, 4, 5),
9296 GEN_VXFORM(vmuleub, 4, 8),
9297 GEN_VXFORM(vmuleuh, 4, 9),
9298 GEN_VXFORM(vmulesb, 4, 12),
9299 GEN_VXFORM(vmulesh, 4, 13),
9300 GEN_VXFORM(vslb, 2, 4),
9301 GEN_VXFORM(vslh, 2, 5),
9302 GEN_VXFORM(vslw, 2, 6),
9303 GEN_VXFORM(vsrb, 2, 8),
9304 GEN_VXFORM(vsrh, 2, 9),
9305 GEN_VXFORM(vsrw, 2, 10),
9306 GEN_VXFORM(vsrab, 2, 12),
9307 GEN_VXFORM(vsrah, 2, 13),
9308 GEN_VXFORM(vsraw, 2, 14),
9309 GEN_VXFORM(vslo, 6, 16),
9310 GEN_VXFORM(vsro, 6, 17),
9311 GEN_VXFORM(vaddcuw, 0, 6),
9312 GEN_VXFORM(vsubcuw, 0, 22),
9313 GEN_VXFORM(vaddubs, 0, 8),
9314 GEN_VXFORM(vadduhs, 0, 9),
9315 GEN_VXFORM(vadduws, 0, 10),
9316 GEN_VXFORM(vaddsbs, 0, 12),
9317 GEN_VXFORM(vaddshs, 0, 13),
9318 GEN_VXFORM(vaddsws, 0, 14),
9319 GEN_VXFORM(vsububs, 0, 24),
9320 GEN_VXFORM(vsubuhs, 0, 25),
9321 GEN_VXFORM(vsubuws, 0, 26),
9322 GEN_VXFORM(vsubsbs, 0, 28),
9323 GEN_VXFORM(vsubshs, 0, 29),
9324 GEN_VXFORM(vsubsws, 0, 30),
9325 GEN_VXFORM(vrlb, 2, 0),
9326 GEN_VXFORM(vrlh, 2, 1),
9327 GEN_VXFORM(vrlw, 2, 2),
9328 GEN_VXFORM(vsl, 2, 7),
9329 GEN_VXFORM(vsr, 2, 11),
9330 GEN_VXFORM(vpkuhum, 7, 0),
9331 GEN_VXFORM(vpkuwum, 7, 1),
9332 GEN_VXFORM(vpkuhus, 7, 2),
9333 GEN_VXFORM(vpkuwus, 7, 3),
9334 GEN_VXFORM(vpkshus, 7, 4),
9335 GEN_VXFORM(vpkswus, 7, 5),
9336 GEN_VXFORM(vpkshss, 7, 6),
9337 GEN_VXFORM(vpkswss, 7, 7),
9338 GEN_VXFORM(vpkpx, 7, 12),
9339 GEN_VXFORM(vsum4ubs, 4, 24),
9340 GEN_VXFORM(vsum4sbs, 4, 28),
9341 GEN_VXFORM(vsum4shs, 4, 25),
9342 GEN_VXFORM(vsum2sws, 4, 26),
9343 GEN_VXFORM(vsumsws, 4, 30),
9344 GEN_VXFORM(vaddfp, 5, 0),
9345 GEN_VXFORM(vsubfp, 5, 1),
9346 GEN_VXFORM(vmaxfp, 5, 16),
9347 GEN_VXFORM(vminfp, 5, 17),
9348
9349 #undef GEN_VXRFORM1
9350 #undef GEN_VXRFORM
9351 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9352 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9353 #define GEN_VXRFORM(name, opc2, opc3) \
9354 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9355 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9356 GEN_VXRFORM(vcmpequb, 3, 0)
9357 GEN_VXRFORM(vcmpequh, 3, 1)
9358 GEN_VXRFORM(vcmpequw, 3, 2)
9359 GEN_VXRFORM(vcmpgtsb, 3, 12)
9360 GEN_VXRFORM(vcmpgtsh, 3, 13)
9361 GEN_VXRFORM(vcmpgtsw, 3, 14)
9362 GEN_VXRFORM(vcmpgtub, 3, 8)
9363 GEN_VXRFORM(vcmpgtuh, 3, 9)
9364 GEN_VXRFORM(vcmpgtuw, 3, 10)
9365 GEN_VXRFORM(vcmpeqfp, 3, 3)
9366 GEN_VXRFORM(vcmpgefp, 3, 7)
9367 GEN_VXRFORM(vcmpgtfp, 3, 11)
9368 GEN_VXRFORM(vcmpbfp, 3, 15)
9369
9370 #undef GEN_VXFORM_SIMM
9371 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9372 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9373 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9374 GEN_VXFORM_SIMM(vspltish, 6, 13),
9375 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9376
9377 #undef GEN_VXFORM_NOA
9378 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9379 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9380 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9381 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9382 GEN_VXFORM_NOA(vupklsb, 7, 10),
9383 GEN_VXFORM_NOA(vupklsh, 7, 11),
9384 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9385 GEN_VXFORM_NOA(vupklpx, 7, 15),
9386 GEN_VXFORM_NOA(vrefp, 5, 4),
9387 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9388 GEN_VXFORM_NOA(vexptefp, 5, 6),
9389 GEN_VXFORM_NOA(vlogefp, 5, 7),
9390 GEN_VXFORM_NOA(vrfim, 5, 8),
9391 GEN_VXFORM_NOA(vrfin, 5, 9),
9392 GEN_VXFORM_NOA(vrfip, 5, 10),
9393 GEN_VXFORM_NOA(vrfiz, 5, 11),
9394
9395 #undef GEN_VXFORM_UIMM
9396 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9397 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9398 GEN_VXFORM_UIMM(vspltb, 6, 8),
9399 GEN_VXFORM_UIMM(vsplth, 6, 9),
9400 GEN_VXFORM_UIMM(vspltw, 6, 10),
9401 GEN_VXFORM_UIMM(vcfux, 5, 12),
9402 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9403 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9404 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9405
9406 #undef GEN_VAFORM_PAIRED
9407 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9408 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9409 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9410 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9411 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9412 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9413 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9414 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9415
9416 #undef GEN_SPE
9417 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9418 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9419 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9420 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9421 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9422 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9423 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9424 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9425 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9426 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9427 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9428 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9429 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9430 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9431 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9432 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9433 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9434 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9435 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9436 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9437 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9438 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9439 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9440 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9441 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9442 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9443 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9444 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9445 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9446 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9447 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9448
9449 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9450 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9451 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9452 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9453 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9454 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9455 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9456 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9457 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9458 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9459 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9460 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9461 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9462 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9463
9464 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9465 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9466 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9467 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9468 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9469 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9470 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9471 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9472 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9473 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9474 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9475 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9476 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9477 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9478
9479 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9480 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9481 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9482 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9483 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9484 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9485 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9486 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9487 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9488 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9489 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9490 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9491 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9492 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9493 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9494 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9495
9496 #undef GEN_SPEOP_LDST
9497 #define GEN_SPEOP_LDST(name, opc2, sh) \
9498 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9499 GEN_SPEOP_LDST(evldd, 0x00, 3),
9500 GEN_SPEOP_LDST(evldw, 0x01, 3),
9501 GEN_SPEOP_LDST(evldh, 0x02, 3),
9502 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9503 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9504 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9505 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9506 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9507 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9508 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9509 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9510
9511 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9512 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9513 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9514 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9515 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9516 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9517 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9518 };
9519
9520 #include "helper_regs.h"
9521 #include "translate_init.c"
9522
9523 /*****************************************************************************/
9524 /* Misc PowerPC helpers */
9525 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
9526 int flags)
9527 {
9528 #define RGPL 4
9529 #define RFPL 4
9530
9531 PowerPCCPU *cpu = POWERPC_CPU(cs);
9532 CPUPPCState *env = &cpu->env;
9533 int i;
9534
9535 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9536 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9537 env->nip, env->lr, env->ctr, cpu_read_xer(env));
9538 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9539 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9540 env->hflags, env->mmu_idx);
9541 #if !defined(NO_TIMER_DUMP)
9542 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9543 #if !defined(CONFIG_USER_ONLY)
9544 " DECR %08" PRIu32
9545 #endif
9546 "\n",
9547 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9548 #if !defined(CONFIG_USER_ONLY)
9549 , cpu_ppc_load_decr(env)
9550 #endif
9551 );
9552 #endif
9553 for (i = 0; i < 32; i++) {
9554 if ((i & (RGPL - 1)) == 0)
9555 cpu_fprintf(f, "GPR%02d", i);
9556 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9557 if ((i & (RGPL - 1)) == (RGPL - 1))
9558 cpu_fprintf(f, "\n");
9559 }
9560 cpu_fprintf(f, "CR ");
9561 for (i = 0; i < 8; i++)
9562 cpu_fprintf(f, "%01x", env->crf[i]);
9563 cpu_fprintf(f, " [");
9564 for (i = 0; i < 8; i++) {
9565 char a = '-';
9566 if (env->crf[i] & 0x08)
9567 a = 'L';
9568 else if (env->crf[i] & 0x04)
9569 a = 'G';
9570 else if (env->crf[i] & 0x02)
9571 a = 'E';
9572 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9573 }
9574 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9575 env->reserve_addr);
9576 for (i = 0; i < 32; i++) {
9577 if ((i & (RFPL - 1)) == 0)
9578 cpu_fprintf(f, "FPR%02d", i);
9579 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9580 if ((i & (RFPL - 1)) == (RFPL - 1))
9581 cpu_fprintf(f, "\n");
9582 }
9583 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
9584 #if !defined(CONFIG_USER_ONLY)
9585 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9586 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9587 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9588 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9589
9590 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9591 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9592 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9593 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9594
9595 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9596 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9597 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9598 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9599
9600 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9601 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9602 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9603 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9604 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9605
9606 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9607 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9608 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9609 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9610
9611 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9612 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9613 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9614 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9615
9616 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9617 " EPR " TARGET_FMT_lx "\n",
9618 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9619 env->spr[SPR_BOOKE_EPR]);
9620
9621 /* FSL-specific */
9622 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9623 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9624 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9625 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9626
9627 /*
9628 * IVORs are left out as they are large and do not change often --
9629 * they can be read with "p $ivor0", "p $ivor1", etc.
9630 */
9631 }
9632
9633 #if defined(TARGET_PPC64)
9634 if (env->flags & POWERPC_FLAG_CFAR) {
9635 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9636 }
9637 #endif
9638
9639 switch (env->mmu_model) {
9640 case POWERPC_MMU_32B:
9641 case POWERPC_MMU_601:
9642 case POWERPC_MMU_SOFT_6xx:
9643 case POWERPC_MMU_SOFT_74xx:
9644 #if defined(TARGET_PPC64)
9645 case POWERPC_MMU_64B:
9646 #endif
9647 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9648 break;
9649 case POWERPC_MMU_BOOKE206:
9650 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9651 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9652 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9653 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9654
9655 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9656 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9657 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9658 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9659
9660 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9661 " TLB1CFG " TARGET_FMT_lx "\n",
9662 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9663 env->spr[SPR_BOOKE_TLB1CFG]);
9664 break;
9665 default:
9666 break;
9667 }
9668 #endif
9669
9670 #undef RGPL
9671 #undef RFPL
9672 }
9673
9674 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
9675 fprintf_function cpu_fprintf, int flags)
9676 {
9677 #if defined(DO_PPC_STATISTICS)
9678 PowerPCCPU *cpu = POWERPC_CPU(cs);
9679 opc_handler_t **t1, **t2, **t3, *handler;
9680 int op1, op2, op3;
9681
9682 t1 = cpu->env.opcodes;
9683 for (op1 = 0; op1 < 64; op1++) {
9684 handler = t1[op1];
9685 if (is_indirect_opcode(handler)) {
9686 t2 = ind_table(handler);
9687 for (op2 = 0; op2 < 32; op2++) {
9688 handler = t2[op2];
9689 if (is_indirect_opcode(handler)) {
9690 t3 = ind_table(handler);
9691 for (op3 = 0; op3 < 32; op3++) {
9692 handler = t3[op3];
9693 if (handler->count == 0)
9694 continue;
9695 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9696 "%016" PRIx64 " %" PRId64 "\n",
9697 op1, op2, op3, op1, (op3 << 5) | op2,
9698 handler->oname,
9699 handler->count, handler->count);
9700 }
9701 } else {
9702 if (handler->count == 0)
9703 continue;
9704 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9705 "%016" PRIx64 " %" PRId64 "\n",
9706 op1, op2, op1, op2, handler->oname,
9707 handler->count, handler->count);
9708 }
9709 }
9710 } else {
9711 if (handler->count == 0)
9712 continue;
9713 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9714 " %" PRId64 "\n",
9715 op1, op1, handler->oname,
9716 handler->count, handler->count);
9717 }
9718 }
9719 #endif
9720 }
9721
9722 /*****************************************************************************/
9723 static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
9724 TranslationBlock *tb,
9725 bool search_pc)
9726 {
9727 CPUState *cs = CPU(cpu);
9728 CPUPPCState *env = &cpu->env;
9729 DisasContext ctx, *ctxp = &ctx;
9730 opc_handler_t **table, *handler;
9731 target_ulong pc_start;
9732 uint16_t *gen_opc_end;
9733 CPUBreakpoint *bp;
9734 int j, lj = -1;
9735 int num_insns;
9736 int max_insns;
9737
9738 pc_start = tb->pc;
9739 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
9740 ctx.nip = pc_start;
9741 ctx.tb = tb;
9742 ctx.exception = POWERPC_EXCP_NONE;
9743 ctx.spr_cb = env->spr_cb;
9744 ctx.mem_idx = env->mmu_idx;
9745 ctx.insns_flags = env->insns_flags;
9746 ctx.insns_flags2 = env->insns_flags2;
9747 ctx.access_type = -1;
9748 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9749 #if defined(TARGET_PPC64)
9750 ctx.sf_mode = msr_is_64bit(env, env->msr);
9751 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9752 #endif
9753 ctx.fpu_enabled = msr_fp;
9754 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9755 ctx.spe_enabled = msr_spe;
9756 else
9757 ctx.spe_enabled = 0;
9758 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9759 ctx.altivec_enabled = msr_vr;
9760 else
9761 ctx.altivec_enabled = 0;
9762 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9763 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9764 else
9765 ctx.singlestep_enabled = 0;
9766 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9767 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9768 if (unlikely(cs->singlestep_enabled)) {
9769 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9770 }
9771 #if defined (DO_SINGLE_STEP) && 0
9772 /* Single step trace mode */
9773 msr_se = 1;
9774 #endif
9775 num_insns = 0;
9776 max_insns = tb->cflags & CF_COUNT_MASK;
9777 if (max_insns == 0)
9778 max_insns = CF_COUNT_MASK;
9779
9780 gen_tb_start();
9781 /* Set env in case of segfault during code fetch */
9782 while (ctx.exception == POWERPC_EXCP_NONE
9783 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
9784 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9785 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9786 if (bp->pc == ctx.nip) {
9787 gen_debug_exception(ctxp);
9788 break;
9789 }
9790 }
9791 }
9792 if (unlikely(search_pc)) {
9793 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9794 if (lj < j) {
9795 lj++;
9796 while (lj < j)
9797 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9798 }
9799 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
9800 tcg_ctx.gen_opc_instr_start[lj] = 1;
9801 tcg_ctx.gen_opc_icount[lj] = num_insns;
9802 }
9803 LOG_DISAS("----------------\n");
9804 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9805 ctx.nip, ctx.mem_idx, (int)msr_ir);
9806 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9807 gen_io_start();
9808 if (unlikely(ctx.le_mode)) {
9809 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
9810 } else {
9811 ctx.opcode = cpu_ldl_code(env, ctx.nip);
9812 }
9813 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9814 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9815 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
9816 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
9817 tcg_gen_debug_insn_start(ctx.nip);
9818 }
9819 ctx.nip += 4;
9820 table = env->opcodes;
9821 num_insns++;
9822 handler = table[opc1(ctx.opcode)];
9823 if (is_indirect_opcode(handler)) {
9824 table = ind_table(handler);
9825 handler = table[opc2(ctx.opcode)];
9826 if (is_indirect_opcode(handler)) {
9827 table = ind_table(handler);
9828 handler = table[opc3(ctx.opcode)];
9829 }
9830 }
9831 /* Is opcode *REALLY* valid ? */
9832 if (unlikely(handler->handler == &gen_invalid)) {
9833 if (qemu_log_enabled()) {
9834 qemu_log("invalid/unsupported opcode: "
9835 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9836 opc1(ctx.opcode), opc2(ctx.opcode),
9837 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9838 }
9839 } else {
9840 uint32_t inval;
9841
9842 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9843 inval = handler->inval2;
9844 } else {
9845 inval = handler->inval1;
9846 }
9847
9848 if (unlikely((ctx.opcode & inval) != 0)) {
9849 if (qemu_log_enabled()) {
9850 qemu_log("invalid bits: %08x for opcode: "
9851 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9852 ctx.opcode & inval, opc1(ctx.opcode),
9853 opc2(ctx.opcode), opc3(ctx.opcode),
9854 ctx.opcode, ctx.nip - 4);
9855 }
9856 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9857 break;
9858 }
9859 }
9860 (*(handler->handler))(&ctx);
9861 #if defined(DO_PPC_STATISTICS)
9862 handler->count++;
9863 #endif
9864 /* Check trace mode exceptions */
9865 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9866 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9867 ctx.exception != POWERPC_SYSCALL &&
9868 ctx.exception != POWERPC_EXCP_TRAP &&
9869 ctx.exception != POWERPC_EXCP_BRANCH)) {
9870 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9871 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9872 (cs->singlestep_enabled) ||
9873 singlestep ||
9874 num_insns >= max_insns)) {
9875 /* if we reach a page boundary or are single stepping, stop
9876 * generation
9877 */
9878 break;
9879 }
9880 }
9881 if (tb->cflags & CF_LAST_IO)
9882 gen_io_end();
9883 if (ctx.exception == POWERPC_EXCP_NONE) {
9884 gen_goto_tb(&ctx, 0, ctx.nip);
9885 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9886 if (unlikely(cs->singlestep_enabled)) {
9887 gen_debug_exception(ctxp);
9888 }
9889 /* Generate the return instruction */
9890 tcg_gen_exit_tb(0);
9891 }
9892 gen_tb_end(tb, num_insns);
9893 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
9894 if (unlikely(search_pc)) {
9895 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9896 lj++;
9897 while (lj <= j)
9898 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9899 } else {
9900 tb->size = ctx.nip - pc_start;
9901 tb->icount = num_insns;
9902 }
9903 #if defined(DEBUG_DISAS)
9904 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9905 int flags;
9906 flags = env->bfd_mach;
9907 flags |= ctx.le_mode << 16;
9908 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9909 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
9910 qemu_log("\n");
9911 }
9912 #endif
9913 }
9914
9915 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
9916 {
9917 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false);
9918 }
9919
9920 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
9921 {
9922 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true);
9923 }
9924
9925 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
9926 {
9927 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
9928 }
AR7 emulation for QEMU