hw/m68k/mcf_intc.c

   1 /*
   2  * ColdFire Interrupt Controller emulation.
   3  *
   4  * Copyright (c) 2007 CodeSourcery.
   5  *
   6  * This code is licensed under the GPL
   7  */
   8
   9 #include "qemu/osdep.h"
  10 #include "qemu/module.h"
  11 #include "cpu.h"
  12 #include "hw/hw.h"
  13 #include "hw/sysbus.h"
  14 #include "hw/m68k/mcf.h"
  15
  16 #define TYPE_MCF_INTC "mcf-intc"
  17 #define MCF_INTC(obj) OBJECT_CHECK(mcf_intc_state, (obj), TYPE_MCF_INTC)
  18
  19 typedef struct {
  20     SysBusDevice parent_obj;
  21
  22     MemoryRegion iomem;
  23     uint64_t ipr;
  24     uint64_t imr;
  25     uint64_t ifr;
  26     uint64_t enabled;
  27     uint8_t icr[64];
  28     M68kCPU *cpu;
  29     int active_vector;
  30 } mcf_intc_state;
  31
  32 static void mcf_intc_update(mcf_intc_state *s)
  33 {
  34     uint64_t active;
  35     int i;
  36     int best;
  37     int best_level;
  38
  39     active = (s->ipr | s->ifr) & s->enabled & ~s->imr;
  40     best_level = 0;
  41     best = 64;
  42     if (active) {
  43         for (i = 0; i < 64; i++) {
  44             if ((active & 1) != 0 && s->icr[i] >= best_level) {
  45                 best_level = s->icr[i];
  46                 best = i;
  47             }
  48             active >>= 1;
  49         }
  50     }
  51     s->active_vector = ((best == 64) ? 24 : (best + 64));
  52     m68k_set_irq_level(s->cpu, best_level, s->active_vector);
  53 }
  54
  55 static uint64_t mcf_intc_read(void *opaque, hwaddr addr,
  56                               unsigned size)
  57 {
  58     int offset;
  59     mcf_intc_state *s = (mcf_intc_state *)opaque;
  60     offset = addr & 0xff;
  61     if (offset >= 0x40 && offset < 0x80) {
  62         return s->icr[offset - 0x40];
  63     }
  64     switch (offset) {
  65     case 0x00:
  66         return (uint32_t)(s->ipr >> 32);
  67     case 0x04:
  68         return (uint32_t)s->ipr;
  69     case 0x08:
  70         return (uint32_t)(s->imr >> 32);
  71     case 0x0c:
  72         return (uint32_t)s->imr;
  73     case 0x10:
  74         return (uint32_t)(s->ifr >> 32);
  75     case 0x14:
  76         return (uint32_t)s->ifr;
  77     case 0xe0: /* SWIACK.  */
  78         return s->active_vector;
  79     case 0xe1: case 0xe2: case 0xe3: case 0xe4:
  80     case 0xe5: case 0xe6: case 0xe7:
  81         /* LnIACK */
  82         hw_error("mcf_intc_read: LnIACK not implemented\n");
  83     default:
  84         return 0;
  85     }
  86 }
  87
  88 static void mcf_intc_write(void *opaque, hwaddr addr,
  89                            uint64_t val, unsigned size)
  90 {
  91     int offset;
  92     mcf_intc_state *s = (mcf_intc_state *)opaque;
  93     offset = addr & 0xff;
  94     if (offset >= 0x40 && offset < 0x80) {
  95         int n = offset - 0x40;
  96         s->icr[n] = val;
  97         if (val == 0)
  98             s->enabled &= ~(1ull << n);
  99         else
 100             s->enabled |= (1ull << n);
 101         mcf_intc_update(s);
 102         return;
 103     }
 104     switch (offset) {
 105     case 0x00: case 0x04:
 106         /* Ignore IPR writes.  */
 107         return;
 108     case 0x08:
 109         s->imr = (s->imr & 0xffffffff) | ((uint64_t)val << 32);
 110         break;
 111     case 0x0c:
 112         s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val;
 113         break;
 114     case 0x1c:
 115         if (val & 0x40) {
 116             s->imr = ~0ull;
 117         } else {
 118             s->imr |= (0x1ull << (val & 0x3f));
 119         }
 120         break;
 121     case 0x1d:
 122         if (val & 0x40) {
 123             s->imr = 0ull;
 124         } else {
 125             s->imr &= ~(0x1ull << (val & 0x3f));
 126         }
 127         break;
 128     default:
 129         hw_error("mcf_intc_write: Bad write offset %d\n", offset);
 130         break;
 131     }
 132     mcf_intc_update(s);
 133 }
 134
 135 static void mcf_intc_set_irq(void *opaque, int irq, int level)
 136 {
 137     mcf_intc_state *s = (mcf_intc_state *)opaque;
 138     if (irq >= 64)
 139         return;
 140     if (level)
 141         s->ipr |= 1ull << irq;
 142     else
 143         s->ipr &= ~(1ull << irq);
 144     mcf_intc_update(s);
 145 }
 146
 147 static void mcf_intc_reset(DeviceState *dev)
 148 {
 149     mcf_intc_state *s = MCF_INTC(dev);
 150
 151     s->imr = ~0ull;
 152     s->ipr = 0;
 153     s->ifr = 0;
 154     s->enabled = 0;
 155     memset(s->icr, 0, 64);
 156     s->active_vector = 24;
 157 }
 158
 159 static const MemoryRegionOps mcf_intc_ops = {
 160     .read = mcf_intc_read,
 161     .write = mcf_intc_write,
 162     .endianness = DEVICE_NATIVE_ENDIAN,
 163 };
 164
 165 static void mcf_intc_instance_init(Object *obj)
 166 {
 167     mcf_intc_state *s = MCF_INTC(obj);
 168
 169     memory_region_init_io(&s->iomem, obj, &mcf_intc_ops, s, "mcf", 0x100);
 170 }
 171
 172 static void mcf_intc_class_init(ObjectClass *oc, void *data)
 173 {
 174     DeviceClass *dc = DEVICE_CLASS(oc);
 175
 176     set_bit(DEVICE_CATEGORY_MISC, dc->categories);
 177     dc->reset = mcf_intc_reset;
 178 }
 179
 180 static const TypeInfo mcf_intc_gate_info = {
 181     .name          = TYPE_MCF_INTC,
 182     .parent        = TYPE_SYS_BUS_DEVICE,
 183     .instance_size = sizeof(mcf_intc_state),
 184     .instance_init = mcf_intc_instance_init,
 185     .class_init    = mcf_intc_class_init,
 186 };
 187
 188 static void mcf_intc_register_types(void)
 189 {
 190     type_register_static(&mcf_intc_gate_info);
 191 }
 192
 193 type_init(mcf_intc_register_types)
 194
 195 qemu_irq *mcf_intc_init(MemoryRegion *sysmem,
 196                         hwaddr base,
 197                         M68kCPU *cpu)
 198 {
 199     DeviceState  *dev;
 200     mcf_intc_state *s;
 201
 202     dev = qdev_create(NULL, TYPE_MCF_INTC);
 203     qdev_init_nofail(dev);
 204
 205     s = MCF_INTC(dev);
 206     s->cpu = cpu;
 207
 208     memory_region_add_subregion(sysmem, base, &s->iomem);
 209
 210     return qemu_allocate_irqs(mcf_intc_set_irq, s, 64);
 211 }