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slirp: fix build on mingw32
[qemu/ar7.git] / hw / sun4m.c
bloba959261209ba034e2c6df913ab76b2fae86e938b
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "esp.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39 #include "empty_slot.h"
40 #include "qdev-addr.h"
41 #include "loader.h"
42 #include "elf.h"
43 #include "blockdev.h"
44 #include "trace.h"
45
46 /*
47 * Sun4m architecture was used in the following machines:
48 *
49 * SPARCserver 6xxMP/xx
50 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51 * SPARCclassic X (4/10)
52 * SPARCstation LX/ZX (4/30)
53 * SPARCstation Voyager
54 * SPARCstation 10/xx, SPARCserver 10/xx
55 * SPARCstation 5, SPARCserver 5
56 * SPARCstation 20/xx, SPARCserver 20
57 * SPARCstation 4
58 *
59 * Sun4d architecture was used in the following machines:
60 *
61 * SPARCcenter 2000
62 * SPARCserver 1000
63 *
64 * Sun4c architecture was used in the following machines:
65 * SPARCstation 1/1+, SPARCserver 1/1+
66 * SPARCstation SLC
67 * SPARCstation IPC
68 * SPARCstation ELC
69 * SPARCstation IPX
70 *
71 * See for example: http://www.sunhelp.org/faq/sunref1.html
72 */
73
74 #define KERNEL_LOAD_ADDR 0x00004000
75 #define CMDLINE_ADDR 0x007ff000
76 #define INITRD_LOAD_ADDR 0x00800000
77 #define PROM_SIZE_MAX (1024 * 1024)
78 #define PROM_VADDR 0xffd00000
79 #define PROM_FILENAME "openbios-sparc32"
80 #define CFG_ADDR 0xd00000510ULL
81 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
82
83 #define MAX_CPUS 16
84 #define MAX_PILS 16
85 #define MAX_VSIMMS 4
86
87 #define ESCC_CLOCK 4915200
88
89 struct sun4m_hwdef {
90 target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
91 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
92 target_phys_addr_t serial_base, fd_base;
93 target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
94 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
95 target_phys_addr_t bpp_base, dbri_base, sx_base;
96 struct {
97 target_phys_addr_t reg_base, vram_base;
98 } vsimm[MAX_VSIMMS];
99 target_phys_addr_t ecc_base;
100 uint64_t max_mem;
101 const char * const default_cpu_model;
102 uint32_t ecc_version;
103 uint32_t iommu_version;
104 uint16_t machine_id;
105 uint8_t nvram_machine_id;
106 };
107
108 #define MAX_IOUNITS 5
109
110 struct sun4d_hwdef {
111 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
112 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
113 target_phys_addr_t serial_base;
114 target_phys_addr_t espdma_base, esp_base;
115 target_phys_addr_t ledma_base, le_base;
116 target_phys_addr_t tcx_base;
117 target_phys_addr_t sbi_base;
118 uint64_t max_mem;
119 const char * const default_cpu_model;
120 uint32_t iounit_version;
121 uint16_t machine_id;
122 uint8_t nvram_machine_id;
123 };
124
125 struct sun4c_hwdef {
126 target_phys_addr_t iommu_base, slavio_base;
127 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
128 target_phys_addr_t serial_base, fd_base;
129 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
130 target_phys_addr_t tcx_base, aux1_base;
131 uint64_t max_mem;
132 const char * const default_cpu_model;
133 uint32_t iommu_version;
134 uint16_t machine_id;
135 uint8_t nvram_machine_id;
136 };
137
138 int DMA_get_channel_mode (int nchan)
139 {
140 return 0;
141 }
142 int DMA_read_memory (int nchan, void *buf, int pos, int size)
143 {
144 return 0;
145 }
146 int DMA_write_memory (int nchan, void *buf, int pos, int size)
147 {
148 return 0;
149 }
150 void DMA_hold_DREQ (int nchan) {}
151 void DMA_release_DREQ (int nchan) {}
152 void DMA_schedule(int nchan) {}
153
154 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
155 {
156 }
157
158 void DMA_register_channel (int nchan,
159 DMA_transfer_handler transfer_handler,
160 void *opaque)
161 {
162 }
163
164 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
165 {
166 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
167 return 0;
168 }
169
170 static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
171 const char *cmdline, const char *boot_devices,
172 ram_addr_t RAM_size, uint32_t kernel_size,
173 int width, int height, int depth,
174 int nvram_machine_id, const char *arch)
175 {
176 unsigned int i;
177 uint32_t start, end;
178 uint8_t image[0x1ff0];
179 struct OpenBIOS_nvpart_v1 *part_header;
180
181 memset(image, '\0', sizeof(image));
182
183 start = 0;
184
185 // OpenBIOS nvram variables
186 // Variable partition
187 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
188 part_header->signature = OPENBIOS_PART_SYSTEM;
189 pstrcpy(part_header->name, sizeof(part_header->name), "system");
190
191 end = start + sizeof(struct OpenBIOS_nvpart_v1);
192 for (i = 0; i < nb_prom_envs; i++)
193 end = OpenBIOS_set_var(image, end, prom_envs[i]);
194
195 // End marker
196 image[end++] = '\0';
197
198 end = start + ((end - start + 15) & ~15);
199 OpenBIOS_finish_partition(part_header, end - start);
200
201 // free partition
202 start = end;
203 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
204 part_header->signature = OPENBIOS_PART_FREE;
205 pstrcpy(part_header->name, sizeof(part_header->name), "free");
206
207 end = 0x1fd0;
208 OpenBIOS_finish_partition(part_header, end - start);
209
210 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
211 nvram_machine_id);
212
213 for (i = 0; i < sizeof(image); i++)
214 m48t59_write(nvram, i, image[i]);
215 }
216
217 static DeviceState *slavio_intctl;
218
219 void sun4m_pic_info(Monitor *mon)
220 {
221 if (slavio_intctl)
222 slavio_pic_info(mon, slavio_intctl);
223 }
224
225 void sun4m_irq_info(Monitor *mon)
226 {
227 if (slavio_intctl)
228 slavio_irq_info(mon, slavio_intctl);
229 }
230
231 void cpu_check_irqs(CPUSPARCState *env)
232 {
233 if (env->pil_in && (env->interrupt_index == 0 ||
234 (env->interrupt_index & ~15) == TT_EXTINT)) {
235 unsigned int i;
236
237 for (i = 15; i > 0; i--) {
238 if (env->pil_in & (1 << i)) {
239 int old_interrupt = env->interrupt_index;
240
241 env->interrupt_index = TT_EXTINT | i;
242 if (old_interrupt != env->interrupt_index) {
243 trace_sun4m_cpu_interrupt(i);
244 cpu_interrupt(env, CPU_INTERRUPT_HARD);
245 }
246 break;
247 }
248 }
249 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
250 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
251 env->interrupt_index = 0;
252 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
253 }
254 }
255
256 static void cpu_kick_irq(CPUSPARCState *env)
257 {
258 env->halted = 0;
259 cpu_check_irqs(env);
260 qemu_cpu_kick(env);
261 }
262
263 static void cpu_set_irq(void *opaque, int irq, int level)
264 {
265 CPUSPARCState *env = opaque;
266
267 if (level) {
268 trace_sun4m_cpu_set_irq_raise(irq);
269 env->pil_in |= 1 << irq;
270 cpu_kick_irq(env);
271 } else {
272 trace_sun4m_cpu_set_irq_lower(irq);
273 env->pil_in &= ~(1 << irq);
274 cpu_check_irqs(env);
275 }
276 }
277
278 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
279 {
280 }
281
282 static void main_cpu_reset(void *opaque)
283 {
284 SPARCCPU *cpu = opaque;
285 CPUSPARCState *env = &cpu->env;
286
287 cpu_reset(CPU(cpu));
288 env->halted = 0;
289 }
290
291 static void secondary_cpu_reset(void *opaque)
292 {
293 SPARCCPU *cpu = opaque;
294 CPUSPARCState *env = &cpu->env;
295
296 cpu_reset(CPU(cpu));
297 env->halted = 1;
298 }
299
300 static void cpu_halt_signal(void *opaque, int irq, int level)
301 {
302 if (level && cpu_single_env)
303 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
304 }
305
306 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
307 {
308 return addr - 0xf0000000ULL;
309 }
310
311 static unsigned long sun4m_load_kernel(const char *kernel_filename,
312 const char *initrd_filename,
313 ram_addr_t RAM_size)
314 {
315 int linux_boot;
316 unsigned int i;
317 long initrd_size, kernel_size;
318 uint8_t *ptr;
319
320 linux_boot = (kernel_filename != NULL);
321
322 kernel_size = 0;
323 if (linux_boot) {
324 int bswap_needed;
325
326 #ifdef BSWAP_NEEDED
327 bswap_needed = 1;
328 #else
329 bswap_needed = 0;
330 #endif
331 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
332 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
333 if (kernel_size < 0)
334 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
335 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
336 TARGET_PAGE_SIZE);
337 if (kernel_size < 0)
338 kernel_size = load_image_targphys(kernel_filename,
339 KERNEL_LOAD_ADDR,
340 RAM_size - KERNEL_LOAD_ADDR);
341 if (kernel_size < 0) {
342 fprintf(stderr, "qemu: could not load kernel '%s'\n",
343 kernel_filename);
344 exit(1);
345 }
346
347 /* load initrd */
348 initrd_size = 0;
349 if (initrd_filename) {
350 initrd_size = load_image_targphys(initrd_filename,
351 INITRD_LOAD_ADDR,
352 RAM_size - INITRD_LOAD_ADDR);
353 if (initrd_size < 0) {
354 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
355 initrd_filename);
356 exit(1);
357 }
358 }
359 if (initrd_size > 0) {
360 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
361 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
362 if (ldl_p(ptr) == 0x48647253) { // HdrS
363 stl_p(ptr + 16, INITRD_LOAD_ADDR);
364 stl_p(ptr + 20, initrd_size);
365 break;
366 }
367 }
368 }
369 }
370 return kernel_size;
371 }
372
373 static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
374 {
375 DeviceState *dev;
376 SysBusDevice *s;
377
378 dev = qdev_create(NULL, "iommu");
379 qdev_prop_set_uint32(dev, "version", version);
380 qdev_init_nofail(dev);
381 s = sysbus_from_qdev(dev);
382 sysbus_connect_irq(s, 0, irq);
383 sysbus_mmio_map(s, 0, addr);
384
385 return s;
386 }
387
388 static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
389 void *iommu, qemu_irq *dev_irq, int is_ledma)
390 {
391 DeviceState *dev;
392 SysBusDevice *s;
393
394 dev = qdev_create(NULL, "sparc32_dma");
395 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
396 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
397 qdev_init_nofail(dev);
398 s = sysbus_from_qdev(dev);
399 sysbus_connect_irq(s, 0, parent_irq);
400 *dev_irq = qdev_get_gpio_in(dev, 0);
401 sysbus_mmio_map(s, 0, daddr);
402
403 return s;
404 }
405
406 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
407 void *dma_opaque, qemu_irq irq)
408 {
409 DeviceState *dev;
410 SysBusDevice *s;
411 qemu_irq reset;
412
413 qemu_check_nic_model(&nd_table[0], "lance");
414
415 dev = qdev_create(NULL, "lance");
416 qdev_set_nic_properties(dev, nd);
417 qdev_prop_set_ptr(dev, "dma", dma_opaque);
418 qdev_init_nofail(dev);
419 s = sysbus_from_qdev(dev);
420 sysbus_mmio_map(s, 0, leaddr);
421 sysbus_connect_irq(s, 0, irq);
422 reset = qdev_get_gpio_in(dev, 0);
423 qdev_connect_gpio_out(dma_opaque, 0, reset);
424 }
425
426 static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
427 target_phys_addr_t addrg,
428 qemu_irq **parent_irq)
429 {
430 DeviceState *dev;
431 SysBusDevice *s;
432 unsigned int i, j;
433
434 dev = qdev_create(NULL, "slavio_intctl");
435 qdev_init_nofail(dev);
436
437 s = sysbus_from_qdev(dev);
438
439 for (i = 0; i < MAX_CPUS; i++) {
440 for (j = 0; j < MAX_PILS; j++) {
441 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
442 }
443 }
444 sysbus_mmio_map(s, 0, addrg);
445 for (i = 0; i < MAX_CPUS; i++) {
446 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
447 }
448
449 return dev;
450 }
451
452 #define SYS_TIMER_OFFSET 0x10000ULL
453 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
454
455 static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
456 qemu_irq *cpu_irqs, unsigned int num_cpus)
457 {
458 DeviceState *dev;
459 SysBusDevice *s;
460 unsigned int i;
461
462 dev = qdev_create(NULL, "slavio_timer");
463 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
464 qdev_init_nofail(dev);
465 s = sysbus_from_qdev(dev);
466 sysbus_connect_irq(s, 0, master_irq);
467 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
468
469 for (i = 0; i < MAX_CPUS; i++) {
470 sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
471 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
472 }
473 }
474
475 #define MISC_LEDS 0x01600000
476 #define MISC_CFG 0x01800000
477 #define MISC_DIAG 0x01a00000
478 #define MISC_MDM 0x01b00000
479 #define MISC_SYS 0x01f00000
480
481 static void slavio_misc_init(target_phys_addr_t base,
482 target_phys_addr_t aux1_base,
483 target_phys_addr_t aux2_base, qemu_irq irq,
484 qemu_irq fdc_tc)
485 {
486 DeviceState *dev;
487 SysBusDevice *s;
488
489 dev = qdev_create(NULL, "slavio_misc");
490 qdev_init_nofail(dev);
491 s = sysbus_from_qdev(dev);
492 if (base) {
493 /* 8 bit registers */
494 /* Slavio control */
495 sysbus_mmio_map(s, 0, base + MISC_CFG);
496 /* Diagnostics */
497 sysbus_mmio_map(s, 1, base + MISC_DIAG);
498 /* Modem control */
499 sysbus_mmio_map(s, 2, base + MISC_MDM);
500 /* 16 bit registers */
501 /* ss600mp diag LEDs */
502 sysbus_mmio_map(s, 3, base + MISC_LEDS);
503 /* 32 bit registers */
504 /* System control */
505 sysbus_mmio_map(s, 4, base + MISC_SYS);
506 }
507 if (aux1_base) {
508 /* AUX 1 (Misc System Functions) */
509 sysbus_mmio_map(s, 5, aux1_base);
510 }
511 if (aux2_base) {
512 /* AUX 2 (Software Powerdown Control) */
513 sysbus_mmio_map(s, 6, aux2_base);
514 }
515 sysbus_connect_irq(s, 0, irq);
516 sysbus_connect_irq(s, 1, fdc_tc);
517 qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
518 }
519
520 static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
521 {
522 DeviceState *dev;
523 SysBusDevice *s;
524
525 dev = qdev_create(NULL, "eccmemctl");
526 qdev_prop_set_uint32(dev, "version", version);
527 qdev_init_nofail(dev);
528 s = sysbus_from_qdev(dev);
529 sysbus_connect_irq(s, 0, irq);
530 sysbus_mmio_map(s, 0, base);
531 if (version == 0) { // SS-600MP only
532 sysbus_mmio_map(s, 1, base + 0x1000);
533 }
534 }
535
536 static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
537 {
538 DeviceState *dev;
539 SysBusDevice *s;
540
541 dev = qdev_create(NULL, "apc");
542 qdev_init_nofail(dev);
543 s = sysbus_from_qdev(dev);
544 /* Power management (APC) XXX: not a Slavio device */
545 sysbus_mmio_map(s, 0, power_base);
546 sysbus_connect_irq(s, 0, cpu_halt);
547 }
548
549 static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
550 int height, int depth)
551 {
552 DeviceState *dev;
553 SysBusDevice *s;
554
555 dev = qdev_create(NULL, "SUNW,tcx");
556 qdev_prop_set_taddr(dev, "addr", addr);
557 qdev_prop_set_uint32(dev, "vram_size", vram_size);
558 qdev_prop_set_uint16(dev, "width", width);
559 qdev_prop_set_uint16(dev, "height", height);
560 qdev_prop_set_uint16(dev, "depth", depth);
561 qdev_init_nofail(dev);
562 s = sysbus_from_qdev(dev);
563 /* 8-bit plane */
564 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
565 /* DAC */
566 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
567 /* TEC (dummy) */
568 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
569 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
570 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
571 if (depth == 24) {
572 /* 24-bit plane */
573 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
574 /* Control plane */
575 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
576 } else {
577 /* THC 8 bit (dummy) */
578 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
579 }
580 }
581
582 /* NCR89C100/MACIO Internal ID register */
583 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
584
585 static void idreg_init(target_phys_addr_t addr)
586 {
587 DeviceState *dev;
588 SysBusDevice *s;
589
590 dev = qdev_create(NULL, "macio_idreg");
591 qdev_init_nofail(dev);
592 s = sysbus_from_qdev(dev);
593
594 sysbus_mmio_map(s, 0, addr);
595 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
596 }
597
598 typedef struct IDRegState {
599 SysBusDevice busdev;
600 MemoryRegion mem;
601 } IDRegState;
602
603 static int idreg_init1(SysBusDevice *dev)
604 {
605 IDRegState *s = FROM_SYSBUS(IDRegState, dev);
606
607 memory_region_init_ram(&s->mem, "sun4m.idreg", sizeof(idreg_data));
608 vmstate_register_ram_global(&s->mem);
609 memory_region_set_readonly(&s->mem, true);
610 sysbus_init_mmio(dev, &s->mem);
611 return 0;
612 }
613
614 static void idreg_class_init(ObjectClass *klass, void *data)
615 {
616 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
617
618 k->init = idreg_init1;
619 }
620
621 static TypeInfo idreg_info = {
622 .name = "macio_idreg",
623 .parent = TYPE_SYS_BUS_DEVICE,
624 .instance_size = sizeof(IDRegState),
625 .class_init = idreg_class_init,
626 };
627
628 typedef struct AFXState {
629 SysBusDevice busdev;
630 MemoryRegion mem;
631 } AFXState;
632
633 /* SS-5 TCX AFX register */
634 static void afx_init(target_phys_addr_t addr)
635 {
636 DeviceState *dev;
637 SysBusDevice *s;
638
639 dev = qdev_create(NULL, "tcx_afx");
640 qdev_init_nofail(dev);
641 s = sysbus_from_qdev(dev);
642
643 sysbus_mmio_map(s, 0, addr);
644 }
645
646 static int afx_init1(SysBusDevice *dev)
647 {
648 AFXState *s = FROM_SYSBUS(AFXState, dev);
649
650 memory_region_init_ram(&s->mem, "sun4m.afx", 4);
651 vmstate_register_ram_global(&s->mem);
652 sysbus_init_mmio(dev, &s->mem);
653 return 0;
654 }
655
656 static void afx_class_init(ObjectClass *klass, void *data)
657 {
658 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
659
660 k->init = afx_init1;
661 }
662
663 static TypeInfo afx_info = {
664 .name = "tcx_afx",
665 .parent = TYPE_SYS_BUS_DEVICE,
666 .instance_size = sizeof(AFXState),
667 .class_init = afx_class_init,
668 };
669
670 typedef struct PROMState {
671 SysBusDevice busdev;
672 MemoryRegion prom;
673 } PROMState;
674
675 /* Boot PROM (OpenBIOS) */
676 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
677 {
678 target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
679 return addr + *base_addr - PROM_VADDR;
680 }
681
682 static void prom_init(target_phys_addr_t addr, const char *bios_name)
683 {
684 DeviceState *dev;
685 SysBusDevice *s;
686 char *filename;
687 int ret;
688
689 dev = qdev_create(NULL, "openprom");
690 qdev_init_nofail(dev);
691 s = sysbus_from_qdev(dev);
692
693 sysbus_mmio_map(s, 0, addr);
694
695 /* load boot prom */
696 if (bios_name == NULL) {
697 bios_name = PROM_FILENAME;
698 }
699 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
700 if (filename) {
701 ret = load_elf(filename, translate_prom_address, &addr, NULL,
702 NULL, NULL, 1, ELF_MACHINE, 0);
703 if (ret < 0 || ret > PROM_SIZE_MAX) {
704 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
705 }
706 g_free(filename);
707 } else {
708 ret = -1;
709 }
710 if (ret < 0 || ret > PROM_SIZE_MAX) {
711 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
712 exit(1);
713 }
714 }
715
716 static int prom_init1(SysBusDevice *dev)
717 {
718 PROMState *s = FROM_SYSBUS(PROMState, dev);
719
720 memory_region_init_ram(&s->prom, "sun4m.prom", PROM_SIZE_MAX);
721 vmstate_register_ram_global(&s->prom);
722 memory_region_set_readonly(&s->prom, true);
723 sysbus_init_mmio(dev, &s->prom);
724 return 0;
725 }
726
727 static Property prom_properties[] = {
728 {/* end of property list */},
729 };
730
731 static void prom_class_init(ObjectClass *klass, void *data)
732 {
733 DeviceClass *dc = DEVICE_CLASS(klass);
734 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
735
736 k->init = prom_init1;
737 dc->props = prom_properties;
738 }
739
740 static TypeInfo prom_info = {
741 .name = "openprom",
742 .parent = TYPE_SYS_BUS_DEVICE,
743 .instance_size = sizeof(PROMState),
744 .class_init = prom_class_init,
745 };
746
747 typedef struct RamDevice
748 {
749 SysBusDevice busdev;
750 MemoryRegion ram;
751 uint64_t size;
752 } RamDevice;
753
754 /* System RAM */
755 static int ram_init1(SysBusDevice *dev)
756 {
757 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
758
759 memory_region_init_ram(&d->ram, "sun4m.ram", d->size);
760 vmstate_register_ram_global(&d->ram);
761 sysbus_init_mmio(dev, &d->ram);
762 return 0;
763 }
764
765 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
766 uint64_t max_mem)
767 {
768 DeviceState *dev;
769 SysBusDevice *s;
770 RamDevice *d;
771
772 /* allocate RAM */
773 if ((uint64_t)RAM_size > max_mem) {
774 fprintf(stderr,
775 "qemu: Too much memory for this machine: %d, maximum %d\n",
776 (unsigned int)(RAM_size / (1024 * 1024)),
777 (unsigned int)(max_mem / (1024 * 1024)));
778 exit(1);
779 }
780 dev = qdev_create(NULL, "memory");
781 s = sysbus_from_qdev(dev);
782
783 d = FROM_SYSBUS(RamDevice, s);
784 d->size = RAM_size;
785 qdev_init_nofail(dev);
786
787 sysbus_mmio_map(s, 0, addr);
788 }
789
790 static Property ram_properties[] = {
791 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
792 DEFINE_PROP_END_OF_LIST(),
793 };
794
795 static void ram_class_init(ObjectClass *klass, void *data)
796 {
797 DeviceClass *dc = DEVICE_CLASS(klass);
798 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
799
800 k->init = ram_init1;
801 dc->props = ram_properties;
802 }
803
804 static TypeInfo ram_info = {
805 .name = "memory",
806 .parent = TYPE_SYS_BUS_DEVICE,
807 .instance_size = sizeof(RamDevice),
808 .class_init = ram_class_init,
809 };
810
811 static void cpu_devinit(const char *cpu_model, unsigned int id,
812 uint64_t prom_addr, qemu_irq **cpu_irqs)
813 {
814 SPARCCPU *cpu;
815 CPUSPARCState *env;
816
817 cpu = cpu_sparc_init(cpu_model);
818 if (cpu == NULL) {
819 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
820 exit(1);
821 }
822 env = &cpu->env;
823
824 cpu_sparc_set_id(env, id);
825 if (id == 0) {
826 qemu_register_reset(main_cpu_reset, cpu);
827 } else {
828 qemu_register_reset(secondary_cpu_reset, cpu);
829 env->halted = 1;
830 }
831 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
832 env->prom_addr = prom_addr;
833 }
834
835 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
836 const char *boot_device,
837 const char *kernel_filename,
838 const char *kernel_cmdline,
839 const char *initrd_filename, const char *cpu_model)
840 {
841 unsigned int i;
842 void *iommu, *espdma, *ledma, *nvram;
843 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
844 espdma_irq, ledma_irq;
845 qemu_irq esp_reset, dma_enable;
846 qemu_irq fdc_tc;
847 qemu_irq *cpu_halt;
848 unsigned long kernel_size;
849 DriveInfo *fd[MAX_FD];
850 void *fw_cfg;
851 unsigned int num_vsimms;
852
853 /* init CPUs */
854 if (!cpu_model)
855 cpu_model = hwdef->default_cpu_model;
856
857 for(i = 0; i < smp_cpus; i++) {
858 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
859 }
860
861 for (i = smp_cpus; i < MAX_CPUS; i++)
862 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
863
864
865 /* set up devices */
866 ram_init(0, RAM_size, hwdef->max_mem);
867 /* models without ECC don't trap when missing ram is accessed */
868 if (!hwdef->ecc_base) {
869 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
870 }
871
872 prom_init(hwdef->slavio_base, bios_name);
873
874 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
875 hwdef->intctl_base + 0x10000ULL,
876 cpu_irqs);
877
878 for (i = 0; i < 32; i++) {
879 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
880 }
881 for (i = 0; i < MAX_CPUS; i++) {
882 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
883 }
884
885 if (hwdef->idreg_base) {
886 idreg_init(hwdef->idreg_base);
887 }
888
889 if (hwdef->afx_base) {
890 afx_init(hwdef->afx_base);
891 }
892
893 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
894 slavio_irq[30]);
895
896 if (hwdef->iommu_pad_base) {
897 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
898 Software shouldn't use aliased addresses, neither should it crash
899 when does. Using empty_slot instead of aliasing can help with
900 debugging such accesses */
901 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
902 }
903
904 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
905 iommu, &espdma_irq, 0);
906
907 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
908 slavio_irq[16], iommu, &ledma_irq, 1);
909
910 if (graphic_depth != 8 && graphic_depth != 24) {
911 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
912 exit (1);
913 }
914 num_vsimms = 0;
915 if (num_vsimms == 0) {
916 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
917 graphic_depth);
918 }
919
920 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
921 /* vsimm registers probed by OBP */
922 if (hwdef->vsimm[i].reg_base) {
923 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
924 }
925 }
926
927 if (hwdef->sx_base) {
928 empty_slot_init(hwdef->sx_base, 0x2000);
929 }
930
931 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
932
933 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
934
935 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
936
937 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
938 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
939 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
940 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
941 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
942 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
943
944 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
945 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
946 slavio_irq[30], fdc_tc);
947
948 if (hwdef->apc_base) {
949 apc_init(hwdef->apc_base, cpu_halt[0]);
950 }
951
952 if (hwdef->fd_base) {
953 /* there is zero or one floppy drive */
954 memset(fd, 0, sizeof(fd));
955 fd[0] = drive_get(IF_FLOPPY, 0, 0);
956 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
957 &fdc_tc);
958 }
959
960 if (drive_get_max_bus(IF_SCSI) > 0) {
961 fprintf(stderr, "qemu: too many SCSI bus\n");
962 exit(1);
963 }
964
965 esp_init(hwdef->esp_base, 2,
966 espdma_memory_read, espdma_memory_write,
967 espdma, espdma_irq, &esp_reset, &dma_enable);
968
969 qdev_connect_gpio_out(espdma, 0, esp_reset);
970 qdev_connect_gpio_out(espdma, 1, dma_enable);
971
972 if (hwdef->cs_base) {
973 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
974 slavio_irq[5]);
975 }
976
977 if (hwdef->dbri_base) {
978 /* ISDN chip with attached CS4215 audio codec */
979 /* prom space */
980 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
981 /* reg space */
982 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
983 }
984
985 if (hwdef->bpp_base) {
986 /* parallel port */
987 empty_slot_init(hwdef->bpp_base, 0x20);
988 }
989
990 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
991 RAM_size);
992
993 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
994 boot_device, RAM_size, kernel_size, graphic_width,
995 graphic_height, graphic_depth, hwdef->nvram_machine_id,
996 "Sun4m");
997
998 if (hwdef->ecc_base)
999 ecc_init(hwdef->ecc_base, slavio_irq[28],
1000 hwdef->ecc_version);
1001
1002 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1003 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1004 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1005 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1006 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1007 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1008 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1009 if (kernel_cmdline) {
1010 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1011 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1012 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1013 (uint8_t*)strdup(kernel_cmdline),
1014 strlen(kernel_cmdline) + 1);
1015 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1016 strlen(kernel_cmdline) + 1);
1017 } else {
1018 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1019 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1020 }
1021 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1022 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1023 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1024 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1025 }
1026
1027 enum {
1028 ss2_id = 0,
1029 ss5_id = 32,
1030 vger_id,
1031 lx_id,
1032 ss4_id,
1033 scls_id,
1034 sbook_id,
1035 ss10_id = 64,
1036 ss20_id,
1037 ss600mp_id,
1038 ss1000_id = 96,
1039 ss2000_id,
1040 };
1041
1042 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1043 /* SS-5 */
1044 {
1045 .iommu_base = 0x10000000,
1046 .iommu_pad_base = 0x10004000,
1047 .iommu_pad_len = 0x0fffb000,
1048 .tcx_base = 0x50000000,
1049 .cs_base = 0x6c000000,
1050 .slavio_base = 0x70000000,
1051 .ms_kb_base = 0x71000000,
1052 .serial_base = 0x71100000,
1053 .nvram_base = 0x71200000,
1054 .fd_base = 0x71400000,
1055 .counter_base = 0x71d00000,
1056 .intctl_base = 0x71e00000,
1057 .idreg_base = 0x78000000,
1058 .dma_base = 0x78400000,
1059 .esp_base = 0x78800000,
1060 .le_base = 0x78c00000,
1061 .apc_base = 0x6a000000,
1062 .afx_base = 0x6e000000,
1063 .aux1_base = 0x71900000,
1064 .aux2_base = 0x71910000,
1065 .nvram_machine_id = 0x80,
1066 .machine_id = ss5_id,
1067 .iommu_version = 0x05000000,
1068 .max_mem = 0x10000000,
1069 .default_cpu_model = "Fujitsu MB86904",
1070 },
1071 /* SS-10 */
1072 {
1073 .iommu_base = 0xfe0000000ULL,
1074 .tcx_base = 0xe20000000ULL,
1075 .slavio_base = 0xff0000000ULL,
1076 .ms_kb_base = 0xff1000000ULL,
1077 .serial_base = 0xff1100000ULL,
1078 .nvram_base = 0xff1200000ULL,
1079 .fd_base = 0xff1700000ULL,
1080 .counter_base = 0xff1300000ULL,
1081 .intctl_base = 0xff1400000ULL,
1082 .idreg_base = 0xef0000000ULL,
1083 .dma_base = 0xef0400000ULL,
1084 .esp_base = 0xef0800000ULL,
1085 .le_base = 0xef0c00000ULL,
1086 .apc_base = 0xefa000000ULL, // XXX should not exist
1087 .aux1_base = 0xff1800000ULL,
1088 .aux2_base = 0xff1a01000ULL,
1089 .ecc_base = 0xf00000000ULL,
1090 .ecc_version = 0x10000000, // version 0, implementation 1
1091 .nvram_machine_id = 0x72,
1092 .machine_id = ss10_id,
1093 .iommu_version = 0x03000000,
1094 .max_mem = 0xf00000000ULL,
1095 .default_cpu_model = "TI SuperSparc II",
1096 },
1097 /* SS-600MP */
1098 {
1099 .iommu_base = 0xfe0000000ULL,
1100 .tcx_base = 0xe20000000ULL,
1101 .slavio_base = 0xff0000000ULL,
1102 .ms_kb_base = 0xff1000000ULL,
1103 .serial_base = 0xff1100000ULL,
1104 .nvram_base = 0xff1200000ULL,
1105 .counter_base = 0xff1300000ULL,
1106 .intctl_base = 0xff1400000ULL,
1107 .dma_base = 0xef0081000ULL,
1108 .esp_base = 0xef0080000ULL,
1109 .le_base = 0xef0060000ULL,
1110 .apc_base = 0xefa000000ULL, // XXX should not exist
1111 .aux1_base = 0xff1800000ULL,
1112 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1113 .ecc_base = 0xf00000000ULL,
1114 .ecc_version = 0x00000000, // version 0, implementation 0
1115 .nvram_machine_id = 0x71,
1116 .machine_id = ss600mp_id,
1117 .iommu_version = 0x01000000,
1118 .max_mem = 0xf00000000ULL,
1119 .default_cpu_model = "TI SuperSparc II",
1120 },
1121 /* SS-20 */
1122 {
1123 .iommu_base = 0xfe0000000ULL,
1124 .tcx_base = 0xe20000000ULL,
1125 .slavio_base = 0xff0000000ULL,
1126 .ms_kb_base = 0xff1000000ULL,
1127 .serial_base = 0xff1100000ULL,
1128 .nvram_base = 0xff1200000ULL,
1129 .fd_base = 0xff1700000ULL,
1130 .counter_base = 0xff1300000ULL,
1131 .intctl_base = 0xff1400000ULL,
1132 .idreg_base = 0xef0000000ULL,
1133 .dma_base = 0xef0400000ULL,
1134 .esp_base = 0xef0800000ULL,
1135 .le_base = 0xef0c00000ULL,
1136 .bpp_base = 0xef4800000ULL,
1137 .apc_base = 0xefa000000ULL, // XXX should not exist
1138 .aux1_base = 0xff1800000ULL,
1139 .aux2_base = 0xff1a01000ULL,
1140 .dbri_base = 0xee0000000ULL,
1141 .sx_base = 0xf80000000ULL,
1142 .vsimm = {
1143 {
1144 .reg_base = 0x9c000000ULL,
1145 .vram_base = 0xfc000000ULL
1146 }, {
1147 .reg_base = 0x90000000ULL,
1148 .vram_base = 0xf0000000ULL
1149 }, {
1150 .reg_base = 0x94000000ULL
1151 }, {
1152 .reg_base = 0x98000000ULL
1153 }
1154 },
1155 .ecc_base = 0xf00000000ULL,
1156 .ecc_version = 0x20000000, // version 0, implementation 2
1157 .nvram_machine_id = 0x72,
1158 .machine_id = ss20_id,
1159 .iommu_version = 0x13000000,
1160 .max_mem = 0xf00000000ULL,
1161 .default_cpu_model = "TI SuperSparc II",
1162 },
1163 /* Voyager */
1164 {
1165 .iommu_base = 0x10000000,
1166 .tcx_base = 0x50000000,
1167 .slavio_base = 0x70000000,
1168 .ms_kb_base = 0x71000000,
1169 .serial_base = 0x71100000,
1170 .nvram_base = 0x71200000,
1171 .fd_base = 0x71400000,
1172 .counter_base = 0x71d00000,
1173 .intctl_base = 0x71e00000,
1174 .idreg_base = 0x78000000,
1175 .dma_base = 0x78400000,
1176 .esp_base = 0x78800000,
1177 .le_base = 0x78c00000,
1178 .apc_base = 0x71300000, // pmc
1179 .aux1_base = 0x71900000,
1180 .aux2_base = 0x71910000,
1181 .nvram_machine_id = 0x80,
1182 .machine_id = vger_id,
1183 .iommu_version = 0x05000000,
1184 .max_mem = 0x10000000,
1185 .default_cpu_model = "Fujitsu MB86904",
1186 },
1187 /* LX */
1188 {
1189 .iommu_base = 0x10000000,
1190 .iommu_pad_base = 0x10004000,
1191 .iommu_pad_len = 0x0fffb000,
1192 .tcx_base = 0x50000000,
1193 .slavio_base = 0x70000000,
1194 .ms_kb_base = 0x71000000,
1195 .serial_base = 0x71100000,
1196 .nvram_base = 0x71200000,
1197 .fd_base = 0x71400000,
1198 .counter_base = 0x71d00000,
1199 .intctl_base = 0x71e00000,
1200 .idreg_base = 0x78000000,
1201 .dma_base = 0x78400000,
1202 .esp_base = 0x78800000,
1203 .le_base = 0x78c00000,
1204 .aux1_base = 0x71900000,
1205 .aux2_base = 0x71910000,
1206 .nvram_machine_id = 0x80,
1207 .machine_id = lx_id,
1208 .iommu_version = 0x04000000,
1209 .max_mem = 0x10000000,
1210 .default_cpu_model = "TI MicroSparc I",
1211 },
1212 /* SS-4 */
1213 {
1214 .iommu_base = 0x10000000,
1215 .tcx_base = 0x50000000,
1216 .cs_base = 0x6c000000,
1217 .slavio_base = 0x70000000,
1218 .ms_kb_base = 0x71000000,
1219 .serial_base = 0x71100000,
1220 .nvram_base = 0x71200000,
1221 .fd_base = 0x71400000,
1222 .counter_base = 0x71d00000,
1223 .intctl_base = 0x71e00000,
1224 .idreg_base = 0x78000000,
1225 .dma_base = 0x78400000,
1226 .esp_base = 0x78800000,
1227 .le_base = 0x78c00000,
1228 .apc_base = 0x6a000000,
1229 .aux1_base = 0x71900000,
1230 .aux2_base = 0x71910000,
1231 .nvram_machine_id = 0x80,
1232 .machine_id = ss4_id,
1233 .iommu_version = 0x05000000,
1234 .max_mem = 0x10000000,
1235 .default_cpu_model = "Fujitsu MB86904",
1236 },
1237 /* SPARCClassic */
1238 {
1239 .iommu_base = 0x10000000,
1240 .tcx_base = 0x50000000,
1241 .slavio_base = 0x70000000,
1242 .ms_kb_base = 0x71000000,
1243 .serial_base = 0x71100000,
1244 .nvram_base = 0x71200000,
1245 .fd_base = 0x71400000,
1246 .counter_base = 0x71d00000,
1247 .intctl_base = 0x71e00000,
1248 .idreg_base = 0x78000000,
1249 .dma_base = 0x78400000,
1250 .esp_base = 0x78800000,
1251 .le_base = 0x78c00000,
1252 .apc_base = 0x6a000000,
1253 .aux1_base = 0x71900000,
1254 .aux2_base = 0x71910000,
1255 .nvram_machine_id = 0x80,
1256 .machine_id = scls_id,
1257 .iommu_version = 0x05000000,
1258 .max_mem = 0x10000000,
1259 .default_cpu_model = "TI MicroSparc I",
1260 },
1261 /* SPARCbook */
1262 {
1263 .iommu_base = 0x10000000,
1264 .tcx_base = 0x50000000, // XXX
1265 .slavio_base = 0x70000000,
1266 .ms_kb_base = 0x71000000,
1267 .serial_base = 0x71100000,
1268 .nvram_base = 0x71200000,
1269 .fd_base = 0x71400000,
1270 .counter_base = 0x71d00000,
1271 .intctl_base = 0x71e00000,
1272 .idreg_base = 0x78000000,
1273 .dma_base = 0x78400000,
1274 .esp_base = 0x78800000,
1275 .le_base = 0x78c00000,
1276 .apc_base = 0x6a000000,
1277 .aux1_base = 0x71900000,
1278 .aux2_base = 0x71910000,
1279 .nvram_machine_id = 0x80,
1280 .machine_id = sbook_id,
1281 .iommu_version = 0x05000000,
1282 .max_mem = 0x10000000,
1283 .default_cpu_model = "TI MicroSparc I",
1284 },
1285 };
1286
1287 /* SPARCstation 5 hardware initialisation */
1288 static void ss5_init(ram_addr_t RAM_size,
1289 const char *boot_device,
1290 const char *kernel_filename, const char *kernel_cmdline,
1291 const char *initrd_filename, const char *cpu_model)
1292 {
1293 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1294 kernel_cmdline, initrd_filename, cpu_model);
1295 }
1296
1297 /* SPARCstation 10 hardware initialisation */
1298 static void ss10_init(ram_addr_t RAM_size,
1299 const char *boot_device,
1300 const char *kernel_filename, const char *kernel_cmdline,
1301 const char *initrd_filename, const char *cpu_model)
1302 {
1303 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1304 kernel_cmdline, initrd_filename, cpu_model);
1305 }
1306
1307 /* SPARCserver 600MP hardware initialisation */
1308 static void ss600mp_init(ram_addr_t RAM_size,
1309 const char *boot_device,
1310 const char *kernel_filename,
1311 const char *kernel_cmdline,
1312 const char *initrd_filename, const char *cpu_model)
1313 {
1314 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1315 kernel_cmdline, initrd_filename, cpu_model);
1316 }
1317
1318 /* SPARCstation 20 hardware initialisation */
1319 static void ss20_init(ram_addr_t RAM_size,
1320 const char *boot_device,
1321 const char *kernel_filename, const char *kernel_cmdline,
1322 const char *initrd_filename, const char *cpu_model)
1323 {
1324 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1325 kernel_cmdline, initrd_filename, cpu_model);
1326 }
1327
1328 /* SPARCstation Voyager hardware initialisation */
1329 static void vger_init(ram_addr_t RAM_size,
1330 const char *boot_device,
1331 const char *kernel_filename, const char *kernel_cmdline,
1332 const char *initrd_filename, const char *cpu_model)
1333 {
1334 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1335 kernel_cmdline, initrd_filename, cpu_model);
1336 }
1337
1338 /* SPARCstation LX hardware initialisation */
1339 static void ss_lx_init(ram_addr_t RAM_size,
1340 const char *boot_device,
1341 const char *kernel_filename, const char *kernel_cmdline,
1342 const char *initrd_filename, const char *cpu_model)
1343 {
1344 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1345 kernel_cmdline, initrd_filename, cpu_model);
1346 }
1347
1348 /* SPARCstation 4 hardware initialisation */
1349 static void ss4_init(ram_addr_t RAM_size,
1350 const char *boot_device,
1351 const char *kernel_filename, const char *kernel_cmdline,
1352 const char *initrd_filename, const char *cpu_model)
1353 {
1354 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1355 kernel_cmdline, initrd_filename, cpu_model);
1356 }
1357
1358 /* SPARCClassic hardware initialisation */
1359 static void scls_init(ram_addr_t RAM_size,
1360 const char *boot_device,
1361 const char *kernel_filename, const char *kernel_cmdline,
1362 const char *initrd_filename, const char *cpu_model)
1363 {
1364 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1365 kernel_cmdline, initrd_filename, cpu_model);
1366 }
1367
1368 /* SPARCbook hardware initialisation */
1369 static void sbook_init(ram_addr_t RAM_size,
1370 const char *boot_device,
1371 const char *kernel_filename, const char *kernel_cmdline,
1372 const char *initrd_filename, const char *cpu_model)
1373 {
1374 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1375 kernel_cmdline, initrd_filename, cpu_model);
1376 }
1377
1378 static QEMUMachine ss5_machine = {
1379 .name = "SS-5",
1380 .desc = "Sun4m platform, SPARCstation 5",
1381 .init = ss5_init,
1382 .use_scsi = 1,
1383 .is_default = 1,
1384 };
1385
1386 static QEMUMachine ss10_machine = {
1387 .name = "SS-10",
1388 .desc = "Sun4m platform, SPARCstation 10",
1389 .init = ss10_init,
1390 .use_scsi = 1,
1391 .max_cpus = 4,
1392 };
1393
1394 static QEMUMachine ss600mp_machine = {
1395 .name = "SS-600MP",
1396 .desc = "Sun4m platform, SPARCserver 600MP",
1397 .init = ss600mp_init,
1398 .use_scsi = 1,
1399 .max_cpus = 4,
1400 };
1401
1402 static QEMUMachine ss20_machine = {
1403 .name = "SS-20",
1404 .desc = "Sun4m platform, SPARCstation 20",
1405 .init = ss20_init,
1406 .use_scsi = 1,
1407 .max_cpus = 4,
1408 };
1409
1410 static QEMUMachine voyager_machine = {
1411 .name = "Voyager",
1412 .desc = "Sun4m platform, SPARCstation Voyager",
1413 .init = vger_init,
1414 .use_scsi = 1,
1415 };
1416
1417 static QEMUMachine ss_lx_machine = {
1418 .name = "LX",
1419 .desc = "Sun4m platform, SPARCstation LX",
1420 .init = ss_lx_init,
1421 .use_scsi = 1,
1422 };
1423
1424 static QEMUMachine ss4_machine = {
1425 .name = "SS-4",
1426 .desc = "Sun4m platform, SPARCstation 4",
1427 .init = ss4_init,
1428 .use_scsi = 1,
1429 };
1430
1431 static QEMUMachine scls_machine = {
1432 .name = "SPARCClassic",
1433 .desc = "Sun4m platform, SPARCClassic",
1434 .init = scls_init,
1435 .use_scsi = 1,
1436 };
1437
1438 static QEMUMachine sbook_machine = {
1439 .name = "SPARCbook",
1440 .desc = "Sun4m platform, SPARCbook",
1441 .init = sbook_init,
1442 .use_scsi = 1,
1443 };
1444
1445 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1446 /* SS-1000 */
1447 {
1448 .iounit_bases = {
1449 0xfe0200000ULL,
1450 0xfe1200000ULL,
1451 0xfe2200000ULL,
1452 0xfe3200000ULL,
1453 -1,
1454 },
1455 .tcx_base = 0x820000000ULL,
1456 .slavio_base = 0xf00000000ULL,
1457 .ms_kb_base = 0xf00240000ULL,
1458 .serial_base = 0xf00200000ULL,
1459 .nvram_base = 0xf00280000ULL,
1460 .counter_base = 0xf00300000ULL,
1461 .espdma_base = 0x800081000ULL,
1462 .esp_base = 0x800080000ULL,
1463 .ledma_base = 0x800040000ULL,
1464 .le_base = 0x800060000ULL,
1465 .sbi_base = 0xf02800000ULL,
1466 .nvram_machine_id = 0x80,
1467 .machine_id = ss1000_id,
1468 .iounit_version = 0x03000000,
1469 .max_mem = 0xf00000000ULL,
1470 .default_cpu_model = "TI SuperSparc II",
1471 },
1472 /* SS-2000 */
1473 {
1474 .iounit_bases = {
1475 0xfe0200000ULL,
1476 0xfe1200000ULL,
1477 0xfe2200000ULL,
1478 0xfe3200000ULL,
1479 0xfe4200000ULL,
1480 },
1481 .tcx_base = 0x820000000ULL,
1482 .slavio_base = 0xf00000000ULL,
1483 .ms_kb_base = 0xf00240000ULL,
1484 .serial_base = 0xf00200000ULL,
1485 .nvram_base = 0xf00280000ULL,
1486 .counter_base = 0xf00300000ULL,
1487 .espdma_base = 0x800081000ULL,
1488 .esp_base = 0x800080000ULL,
1489 .ledma_base = 0x800040000ULL,
1490 .le_base = 0x800060000ULL,
1491 .sbi_base = 0xf02800000ULL,
1492 .nvram_machine_id = 0x80,
1493 .machine_id = ss2000_id,
1494 .iounit_version = 0x03000000,
1495 .max_mem = 0xf00000000ULL,
1496 .default_cpu_model = "TI SuperSparc II",
1497 },
1498 };
1499
1500 static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
1501 {
1502 DeviceState *dev;
1503 SysBusDevice *s;
1504 unsigned int i;
1505
1506 dev = qdev_create(NULL, "sbi");
1507 qdev_init_nofail(dev);
1508
1509 s = sysbus_from_qdev(dev);
1510
1511 for (i = 0; i < MAX_CPUS; i++) {
1512 sysbus_connect_irq(s, i, *parent_irq[i]);
1513 }
1514
1515 sysbus_mmio_map(s, 0, addr);
1516
1517 return dev;
1518 }
1519
1520 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1521 const char *boot_device,
1522 const char *kernel_filename,
1523 const char *kernel_cmdline,
1524 const char *initrd_filename, const char *cpu_model)
1525 {
1526 unsigned int i;
1527 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1528 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1529 espdma_irq, ledma_irq;
1530 qemu_irq esp_reset, dma_enable;
1531 unsigned long kernel_size;
1532 void *fw_cfg;
1533 DeviceState *dev;
1534
1535 /* init CPUs */
1536 if (!cpu_model)
1537 cpu_model = hwdef->default_cpu_model;
1538
1539 for(i = 0; i < smp_cpus; i++) {
1540 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1541 }
1542
1543 for (i = smp_cpus; i < MAX_CPUS; i++)
1544 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1545
1546 /* set up devices */
1547 ram_init(0, RAM_size, hwdef->max_mem);
1548
1549 prom_init(hwdef->slavio_base, bios_name);
1550
1551 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1552
1553 for (i = 0; i < 32; i++) {
1554 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1555 }
1556 for (i = 0; i < MAX_CPUS; i++) {
1557 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1558 }
1559
1560 for (i = 0; i < MAX_IOUNITS; i++)
1561 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1562 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1563 hwdef->iounit_version,
1564 sbi_irq[0]);
1565
1566 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1567 iounits[0], &espdma_irq, 0);
1568
1569 /* should be lebuffer instead */
1570 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1571 iounits[0], &ledma_irq, 0);
1572
1573 if (graphic_depth != 8 && graphic_depth != 24) {
1574 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1575 exit (1);
1576 }
1577 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1578 graphic_depth);
1579
1580 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1581
1582 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1583
1584 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1585
1586 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1587 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1588 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1589 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1590 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1591 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1592
1593 if (drive_get_max_bus(IF_SCSI) > 0) {
1594 fprintf(stderr, "qemu: too many SCSI bus\n");
1595 exit(1);
1596 }
1597
1598 esp_init(hwdef->esp_base, 2,
1599 espdma_memory_read, espdma_memory_write,
1600 espdma, espdma_irq, &esp_reset, &dma_enable);
1601
1602 qdev_connect_gpio_out(espdma, 0, esp_reset);
1603 qdev_connect_gpio_out(espdma, 1, dma_enable);
1604
1605 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1606 RAM_size);
1607
1608 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1609 boot_device, RAM_size, kernel_size, graphic_width,
1610 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1611 "Sun4d");
1612
1613 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1614 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1615 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1616 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1617 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1618 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1619 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1620 if (kernel_cmdline) {
1621 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1622 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1623 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1624 (uint8_t*)strdup(kernel_cmdline),
1625 strlen(kernel_cmdline) + 1);
1626 } else {
1627 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1628 }
1629 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1630 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1631 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1632 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1633 }
1634
1635 /* SPARCserver 1000 hardware initialisation */
1636 static void ss1000_init(ram_addr_t RAM_size,
1637 const char *boot_device,
1638 const char *kernel_filename, const char *kernel_cmdline,
1639 const char *initrd_filename, const char *cpu_model)
1640 {
1641 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1642 kernel_cmdline, initrd_filename, cpu_model);
1643 }
1644
1645 /* SPARCcenter 2000 hardware initialisation */
1646 static void ss2000_init(ram_addr_t RAM_size,
1647 const char *boot_device,
1648 const char *kernel_filename, const char *kernel_cmdline,
1649 const char *initrd_filename, const char *cpu_model)
1650 {
1651 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1652 kernel_cmdline, initrd_filename, cpu_model);
1653 }
1654
1655 static QEMUMachine ss1000_machine = {
1656 .name = "SS-1000",
1657 .desc = "Sun4d platform, SPARCserver 1000",
1658 .init = ss1000_init,
1659 .use_scsi = 1,
1660 .max_cpus = 8,
1661 };
1662
1663 static QEMUMachine ss2000_machine = {
1664 .name = "SS-2000",
1665 .desc = "Sun4d platform, SPARCcenter 2000",
1666 .init = ss2000_init,
1667 .use_scsi = 1,
1668 .max_cpus = 20,
1669 };
1670
1671 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1672 /* SS-2 */
1673 {
1674 .iommu_base = 0xf8000000,
1675 .tcx_base = 0xfe000000,
1676 .slavio_base = 0xf6000000,
1677 .intctl_base = 0xf5000000,
1678 .counter_base = 0xf3000000,
1679 .ms_kb_base = 0xf0000000,
1680 .serial_base = 0xf1000000,
1681 .nvram_base = 0xf2000000,
1682 .fd_base = 0xf7200000,
1683 .dma_base = 0xf8400000,
1684 .esp_base = 0xf8800000,
1685 .le_base = 0xf8c00000,
1686 .aux1_base = 0xf7400003,
1687 .nvram_machine_id = 0x55,
1688 .machine_id = ss2_id,
1689 .max_mem = 0x10000000,
1690 .default_cpu_model = "Cypress CY7C601",
1691 },
1692 };
1693
1694 static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
1695 qemu_irq *parent_irq)
1696 {
1697 DeviceState *dev;
1698 SysBusDevice *s;
1699 unsigned int i;
1700
1701 dev = qdev_create(NULL, "sun4c_intctl");
1702 qdev_init_nofail(dev);
1703
1704 s = sysbus_from_qdev(dev);
1705
1706 for (i = 0; i < MAX_PILS; i++) {
1707 sysbus_connect_irq(s, i, parent_irq[i]);
1708 }
1709 sysbus_mmio_map(s, 0, addr);
1710
1711 return dev;
1712 }
1713
1714 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1715 const char *boot_device,
1716 const char *kernel_filename,
1717 const char *kernel_cmdline,
1718 const char *initrd_filename, const char *cpu_model)
1719 {
1720 void *iommu, *espdma, *ledma, *nvram;
1721 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1722 qemu_irq esp_reset, dma_enable;
1723 qemu_irq fdc_tc;
1724 unsigned long kernel_size;
1725 DriveInfo *fd[MAX_FD];
1726 void *fw_cfg;
1727 DeviceState *dev;
1728 unsigned int i;
1729
1730 /* init CPU */
1731 if (!cpu_model)
1732 cpu_model = hwdef->default_cpu_model;
1733
1734 cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1735
1736 /* set up devices */
1737 ram_init(0, RAM_size, hwdef->max_mem);
1738
1739 prom_init(hwdef->slavio_base, bios_name);
1740
1741 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1742
1743 for (i = 0; i < 8; i++) {
1744 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1745 }
1746
1747 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1748 slavio_irq[1]);
1749
1750 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1751 iommu, &espdma_irq, 0);
1752
1753 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1754 slavio_irq[3], iommu, &ledma_irq, 1);
1755
1756 if (graphic_depth != 8 && graphic_depth != 24) {
1757 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1758 exit (1);
1759 }
1760 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1761 graphic_depth);
1762
1763 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1764
1765 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1766
1767 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1768 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1769 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1770 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1771 escc_init(hwdef->serial_base, slavio_irq[1],
1772 slavio_irq[1], serial_hds[0], serial_hds[1],
1773 ESCC_CLOCK, 1);
1774
1775 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1776
1777 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1778 /* there is zero or one floppy drive */
1779 memset(fd, 0, sizeof(fd));
1780 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1781 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1782 &fdc_tc);
1783 }
1784
1785 if (drive_get_max_bus(IF_SCSI) > 0) {
1786 fprintf(stderr, "qemu: too many SCSI bus\n");
1787 exit(1);
1788 }
1789
1790 esp_init(hwdef->esp_base, 2,
1791 espdma_memory_read, espdma_memory_write,
1792 espdma, espdma_irq, &esp_reset, &dma_enable);
1793
1794 qdev_connect_gpio_out(espdma, 0, esp_reset);
1795 qdev_connect_gpio_out(espdma, 1, dma_enable);
1796
1797 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1798 RAM_size);
1799
1800 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1801 boot_device, RAM_size, kernel_size, graphic_width,
1802 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1803 "Sun4c");
1804
1805 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1806 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1807 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1808 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1809 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1810 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1811 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1812 if (kernel_cmdline) {
1813 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1814 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1815 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1816 (uint8_t*)strdup(kernel_cmdline),
1817 strlen(kernel_cmdline) + 1);
1818 } else {
1819 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1820 }
1821 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1822 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1823 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1824 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1825 }
1826
1827 /* SPARCstation 2 hardware initialisation */
1828 static void ss2_init(ram_addr_t RAM_size,
1829 const char *boot_device,
1830 const char *kernel_filename, const char *kernel_cmdline,
1831 const char *initrd_filename, const char *cpu_model)
1832 {
1833 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1834 kernel_cmdline, initrd_filename, cpu_model);
1835 }
1836
1837 static QEMUMachine ss2_machine = {
1838 .name = "SS-2",
1839 .desc = "Sun4c platform, SPARCstation 2",
1840 .init = ss2_init,
1841 .use_scsi = 1,
1842 };
1843
1844 static void sun4m_register_types(void)
1845 {
1846 type_register_static(&idreg_info);
1847 type_register_static(&afx_info);
1848 type_register_static(&prom_info);
1849 type_register_static(&ram_info);
1850 }
1851
1852 static void ss2_machine_init(void)
1853 {
1854 qemu_register_machine(&ss5_machine);
1855 qemu_register_machine(&ss10_machine);
1856 qemu_register_machine(&ss600mp_machine);
1857 qemu_register_machine(&ss20_machine);
1858 qemu_register_machine(&voyager_machine);
1859 qemu_register_machine(&ss_lx_machine);
1860 qemu_register_machine(&ss4_machine);
1861 qemu_register_machine(&scls_machine);
1862 qemu_register_machine(&sbook_machine);
1863 qemu_register_machine(&ss1000_machine);
1864 qemu_register_machine(&ss2000_machine);
1865 qemu_register_machine(&ss2_machine);
1866 }
1867
1868 type_init(sun4m_register_types)
1869 machine_init(ss2_machine_init);
AR7 emulation for QEMU