hw/timer/sse-timer: Model the SSE Subsystem System Timer
[qemu/ar7.git] / target / xtensa / core-dsp3400.c
blob4e0bc8a8c46cf96e2e727d9703c3d086c69eaf37
1 /*
2 * Copyright (c) 2020, Max Filippov, Open Source and Linux Lab.
3 * All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #include "qemu/osdep.h"
29 #include "cpu.h"
30 #include "exec/gdbstub.h"
31 #include "qemu-common.h"
32 #include "qemu/host-utils.h"
34 #include "core-dsp3400/core-isa.h"
35 #include "core-dsp3400/core-matmap.h"
36 #include "overlay_tool.h"
38 #define xtensa_modules xtensa_modules_dsp3400
39 #include "core-dsp3400/xtensa-modules.c.inc"
41 static XtensaConfig dsp3400 __attribute__((unused)) = {
42 .name = "dsp3400",
43 .gdb_regmap = {
44 .reg = {
45 #include "core-dsp3400/gdb-config.c.inc"
48 .isa_internal = &xtensa_modules,
49 .clock_freq_khz = 40000,
50 .opcode_translators = (const XtensaOpcodeTranslators *[]){
51 &xtensa_core_opcodes,
52 &xtensa_fpu2000_opcodes,
53 NULL,
55 DEFAULT_SECTIONS
58 REGISTER_CORE(dsp3400)