target/riscv/cpu.c

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/qemu-print.h"
  22 #include "qemu/ctype.h"
  23 #include "qemu/log.h"
  24 #include "cpu.h"
  25 #include "internals.h"
  26 #include "exec/exec-all.h"
  27 #include "qapi/error.h"
  28 #include "qemu/error-report.h"
  29 #include "hw/qdev-properties.h"
  30 #include "migration/vmstate.h"
  31 #include "fpu/softfloat-helpers.h"
  32
  33 /* RISC-V CPU definitions */
  34
  35 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
  36
  37 const char * const riscv_int_regnames[] = {
  38   "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
  39   "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
  40   "x14/a4",  "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3",  "x20/s4",
  41   "x21/s5",  "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
  42   "x28/t3",  "x29/t4", "x30/t5", "x31/t6"
  43 };
  44
  45 const char * const riscv_fpr_regnames[] = {
  46   "f0/ft0",   "f1/ft1",  "f2/ft2",   "f3/ft3",   "f4/ft4",  "f5/ft5",
  47   "f6/ft6",   "f7/ft7",  "f8/fs0",   "f9/fs1",   "f10/fa0", "f11/fa1",
  48   "f12/fa2",  "f13/fa3", "f14/fa4",  "f15/fa5",  "f16/fa6", "f17/fa7",
  49   "f18/fs2",  "f19/fs3", "f20/fs4",  "f21/fs5",  "f22/fs6", "f23/fs7",
  50   "f24/fs8",  "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
  51   "f30/ft10", "f31/ft11"
  52 };
  53
  54 const char * const riscv_excp_names[] = {
  55     "misaligned_fetch",
  56     "fault_fetch",
  57     "illegal_instruction",
  58     "breakpoint",
  59     "misaligned_load",
  60     "fault_load",
  61     "misaligned_store",
  62     "fault_store",
  63     "user_ecall",
  64     "supervisor_ecall",
  65     "hypervisor_ecall",
  66     "machine_ecall",
  67     "exec_page_fault",
  68     "load_page_fault",
  69     "reserved",
  70     "store_page_fault",
  71     "reserved",
  72     "reserved",
  73     "reserved",
  74     "reserved",
  75     "guest_exec_page_fault",
  76     "guest_load_page_fault",
  77     "reserved",
  78     "guest_store_page_fault",
  79 };
  80
  81 const char * const riscv_intr_names[] = {
  82     "u_software",
  83     "s_software",
  84     "vs_software",
  85     "m_software",
  86     "u_timer",
  87     "s_timer",
  88     "vs_timer",
  89     "m_timer",
  90     "u_external",
  91     "vs_external",
  92     "h_external",
  93     "m_external",
  94     "reserved",
  95     "reserved",
  96     "reserved",
  97     "reserved"
  98 };
  99
 100 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
 101 {
 102     if (async) {
 103         return (cause < ARRAY_SIZE(riscv_intr_names)) ?
 104                riscv_intr_names[cause] : "(unknown)";
 105     } else {
 106         return (cause < ARRAY_SIZE(riscv_excp_names)) ?
 107                riscv_excp_names[cause] : "(unknown)";
 108     }
 109 }
 110
 111 bool riscv_cpu_is_32bit(CPURISCVState *env)
 112 {
 113     if (env->misa & RV64) {
 114         return false;
 115     }
 116
 117     return true;
 118 }
 119
 120 static void set_misa(CPURISCVState *env, target_ulong misa)
 121 {
 122     env->misa_mask = env->misa = misa;
 123 }
 124
 125 static void set_priv_version(CPURISCVState *env, int priv_ver)
 126 {
 127     env->priv_ver = priv_ver;
 128 }
 129
 130 static void set_vext_version(CPURISCVState *env, int vext_ver)
 131 {
 132     env->vext_ver = vext_ver;
 133 }
 134
 135 static void set_feature(CPURISCVState *env, int feature)
 136 {
 137     env->features |= (1ULL << feature);
 138 }
 139
 140 static void set_resetvec(CPURISCVState *env, int resetvec)
 141 {
 142 #ifndef CONFIG_USER_ONLY
 143     env->resetvec = resetvec;
 144 #endif
 145 }
 146
 147 static void riscv_any_cpu_init(Object *obj)
 148 {
 149     CPURISCVState *env = &RISCV_CPU(obj)->env;
 150     set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 151     set_priv_version(env, PRIV_VERSION_1_11_0);
 152 }
 153
 154 #if defined(TARGET_RISCV64)
 155 static void rv64_base_cpu_init(Object *obj)
 156 {
 157     CPURISCVState *env = &RISCV_CPU(obj)->env;
 158     /* We set this in the realise function */
 159     set_misa(env, RV64);
 160 }
 161
 162 static void rv64_sifive_u_cpu_init(Object *obj)
 163 {
 164     CPURISCVState *env = &RISCV_CPU(obj)->env;
 165     set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 166     set_priv_version(env, PRIV_VERSION_1_10_0);
 167 }
 168
 169 static void rv64_sifive_e_cpu_init(Object *obj)
 170 {
 171     CPURISCVState *env = &RISCV_CPU(obj)->env;
 172     set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
 173     set_priv_version(env, PRIV_VERSION_1_10_0);
 174     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 175 }
 176 #else
 177 static void rv32_base_cpu_init(Object *obj)
 178 {
 179     CPURISCVState *env = &RISCV_CPU(obj)->env;
 180     /* We set this in the realise function */
 181     set_misa(env, RV32);
 182 }
 183
 184 static void rv32_sifive_u_cpu_init(Object *obj)
 185 {
 186     CPURISCVState *env = &RISCV_CPU(obj)->env;
 187     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 188     set_priv_version(env, PRIV_VERSION_1_10_0);
 189 }
 190
 191 static void rv32_sifive_e_cpu_init(Object *obj)
 192 {
 193     CPURISCVState *env = &RISCV_CPU(obj)->env;
 194     set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
 195     set_priv_version(env, PRIV_VERSION_1_10_0);
 196     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 197 }
 198
 199 static void rv32_ibex_cpu_init(Object *obj)
 200 {
 201     CPURISCVState *env = &RISCV_CPU(obj)->env;
 202     set_misa(env, RV32 | RVI | RVM | RVC | RVU);
 203     set_priv_version(env, PRIV_VERSION_1_10_0);
 204     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 205 }
 206
 207 static void rv32_imafcu_nommu_cpu_init(Object *obj)
 208 {
 209     CPURISCVState *env = &RISCV_CPU(obj)->env;
 210     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
 211     set_priv_version(env, PRIV_VERSION_1_10_0);
 212     set_resetvec(env, DEFAULT_RSTVEC);
 213     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 214 }
 215 #endif
 216
 217 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
 218 {
 219     ObjectClass *oc;
 220     char *typename;
 221     char **cpuname;
 222
 223     cpuname = g_strsplit(cpu_model, ",", 1);
 224     typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
 225     oc = object_class_by_name(typename);
 226     g_strfreev(cpuname);
 227     g_free(typename);
 228     if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
 229         object_class_is_abstract(oc)) {
 230         return NULL;
 231     }
 232     return oc;
 233 }
 234
 235 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 236 {
 237     RISCVCPU *cpu = RISCV_CPU(cs);
 238     CPURISCVState *env = &cpu->env;
 239     int i;
 240
 241 #if !defined(CONFIG_USER_ONLY)
 242     if (riscv_has_ext(env, RVH)) {
 243         qemu_fprintf(f, " %s %d\n", "V      =  ", riscv_cpu_virt_enabled(env));
 244     }
 245 #endif
 246     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
 247 #ifndef CONFIG_USER_ONLY
 248     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
 249     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
 250     if (riscv_cpu_is_32bit(env)) {
 251         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
 252                      (target_ulong)(env->mstatus >> 32));
 253     }
 254     if (riscv_has_ext(env, RVH)) {
 255         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
 256         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ",
 257                      (target_ulong)env->vsstatus);
 258     }
 259     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
 260     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
 261     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
 262     if (riscv_has_ext(env, RVH)) {
 263         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
 264     }
 265     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
 266     if (riscv_has_ext(env, RVH)) {
 267         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
 268     }
 269     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec   ", env->mtvec);
 270     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec   ", env->stvec);
 271     if (riscv_has_ext(env, RVH)) {
 272         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec  ", env->vstvec);
 273     }
 274     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc    ", env->mepc);
 275     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc    ", env->sepc);
 276     if (riscv_has_ext(env, RVH)) {
 277         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc   ", env->vsepc);
 278     }
 279     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause  ", env->mcause);
 280     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause  ", env->scause);
 281     if (riscv_has_ext(env, RVH)) {
 282         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
 283     }
 284     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
 285     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr);
 286     if (riscv_has_ext(env, RVH)) {
 287         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
 288         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
 289     }
 290 #endif
 291
 292     for (i = 0; i < 32; i++) {
 293         qemu_fprintf(f, " %s " TARGET_FMT_lx,
 294                      riscv_int_regnames[i], env->gpr[i]);
 295         if ((i & 3) == 3) {
 296             qemu_fprintf(f, "\n");
 297         }
 298     }
 299     if (flags & CPU_DUMP_FPU) {
 300         for (i = 0; i < 32; i++) {
 301             qemu_fprintf(f, " %s %016" PRIx64,
 302                          riscv_fpr_regnames[i], env->fpr[i]);
 303             if ((i & 3) == 3) {
 304                 qemu_fprintf(f, "\n");
 305             }
 306         }
 307     }
 308 }
 309
 310 static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
 311 {
 312     RISCVCPU *cpu = RISCV_CPU(cs);
 313     CPURISCVState *env = &cpu->env;
 314     env->pc = value;
 315 }
 316
 317 static void riscv_cpu_synchronize_from_tb(CPUState *cs,
 318                                           const TranslationBlock *tb)
 319 {
 320     RISCVCPU *cpu = RISCV_CPU(cs);
 321     CPURISCVState *env = &cpu->env;
 322     env->pc = tb->pc;
 323 }
 324
 325 static bool riscv_cpu_has_work(CPUState *cs)
 326 {
 327 #ifndef CONFIG_USER_ONLY
 328     RISCVCPU *cpu = RISCV_CPU(cs);
 329     CPURISCVState *env = &cpu->env;
 330     /*
 331      * Definition of the WFI instruction requires it to ignore the privilege
 332      * mode and delegation registers, but respect individual enables
 333      */
 334     return (env->mip & env->mie) != 0;
 335 #else
 336     return true;
 337 #endif
 338 }
 339
 340 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
 341                           target_ulong *data)
 342 {
 343     env->pc = data[0];
 344 }
 345
 346 static void riscv_cpu_reset(DeviceState *dev)
 347 {
 348     CPUState *cs = CPU(dev);
 349     RISCVCPU *cpu = RISCV_CPU(cs);
 350     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
 351     CPURISCVState *env = &cpu->env;
 352
 353     mcc->parent_reset(dev);
 354 #ifndef CONFIG_USER_ONLY
 355     env->priv = PRV_M;
 356     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
 357     env->mcause = 0;
 358     env->pc = env->resetvec;
 359 #endif
 360     cs->exception_index = EXCP_NONE;
 361     env->load_res = -1;
 362     set_default_nan_mode(1, &env->fp_status);
 363 }
 364
 365 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 366 {
 367     RISCVCPU *cpu = RISCV_CPU(s);
 368     if (riscv_cpu_is_32bit(&cpu->env)) {
 369         info->print_insn = print_insn_riscv32;
 370     } else {
 371         info->print_insn = print_insn_riscv64;
 372     }
 373 }
 374
 375 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 376 {
 377     CPUState *cs = CPU(dev);
 378     RISCVCPU *cpu = RISCV_CPU(dev);
 379     CPURISCVState *env = &cpu->env;
 380     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
 381     int priv_version = PRIV_VERSION_1_11_0;
 382     int vext_version = VEXT_VERSION_0_07_1;
 383     target_ulong target_misa = env->misa;
 384     Error *local_err = NULL;
 385
 386     cpu_exec_realizefn(cs, &local_err);
 387     if (local_err != NULL) {
 388         error_propagate(errp, local_err);
 389         return;
 390     }
 391
 392     if (cpu->cfg.priv_spec) {
 393         if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
 394             priv_version = PRIV_VERSION_1_11_0;
 395         } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
 396             priv_version = PRIV_VERSION_1_10_0;
 397         } else {
 398             error_setg(errp,
 399                        "Unsupported privilege spec version '%s'",
 400                        cpu->cfg.priv_spec);
 401             return;
 402         }
 403     }
 404
 405     set_priv_version(env, priv_version);
 406     set_vext_version(env, vext_version);
 407
 408     if (cpu->cfg.mmu) {
 409         set_feature(env, RISCV_FEATURE_MMU);
 410     }
 411
 412     if (cpu->cfg.pmp) {
 413         set_feature(env, RISCV_FEATURE_PMP);
 414     }
 415
 416     set_resetvec(env, cpu->cfg.resetvec);
 417
 418     /* If only XLEN is set for misa, then set misa from properties */
 419     if (env->misa == RV32 || env->misa == RV64) {
 420         /* Do some ISA extension error checking */
 421         if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
 422             error_setg(errp,
 423                        "I and E extensions are incompatible");
 424                        return;
 425        }
 426
 427         if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
 428             error_setg(errp,
 429                        "Either I or E extension must be set");
 430                        return;
 431        }
 432
 433        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
 434                                cpu->cfg.ext_a & cpu->cfg.ext_f &
 435                                cpu->cfg.ext_d)) {
 436             warn_report("Setting G will also set IMAFD");
 437             cpu->cfg.ext_i = true;
 438             cpu->cfg.ext_m = true;
 439             cpu->cfg.ext_a = true;
 440             cpu->cfg.ext_f = true;
 441             cpu->cfg.ext_d = true;
 442         }
 443
 444         /* Set the ISA extensions, checks should have happened above */
 445         if (cpu->cfg.ext_i) {
 446             target_misa |= RVI;
 447         }
 448         if (cpu->cfg.ext_e) {
 449             target_misa |= RVE;
 450         }
 451         if (cpu->cfg.ext_m) {
 452             target_misa |= RVM;
 453         }
 454         if (cpu->cfg.ext_a) {
 455             target_misa |= RVA;
 456         }
 457         if (cpu->cfg.ext_f) {
 458             target_misa |= RVF;
 459         }
 460         if (cpu->cfg.ext_d) {
 461             target_misa |= RVD;
 462         }
 463         if (cpu->cfg.ext_c) {
 464             target_misa |= RVC;
 465         }
 466         if (cpu->cfg.ext_s) {
 467             target_misa |= RVS;
 468         }
 469         if (cpu->cfg.ext_u) {
 470             target_misa |= RVU;
 471         }
 472         if (cpu->cfg.ext_h) {
 473             target_misa |= RVH;
 474         }
 475         if (cpu->cfg.ext_v) {
 476             target_misa |= RVV;
 477             if (!is_power_of_2(cpu->cfg.vlen)) {
 478                 error_setg(errp,
 479                         "Vector extension VLEN must be power of 2");
 480                 return;
 481             }
 482             if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
 483                 error_setg(errp,
 484                         "Vector extension implementation only supports VLEN "
 485                         "in the range [128, %d]", RV_VLEN_MAX);
 486                 return;
 487             }
 488             if (!is_power_of_2(cpu->cfg.elen)) {
 489                 error_setg(errp,
 490                         "Vector extension ELEN must be power of 2");
 491                 return;
 492             }
 493             if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) {
 494                 error_setg(errp,
 495                         "Vector extension implementation only supports ELEN "
 496                         "in the range [8, 64]");
 497                 return;
 498             }
 499             if (cpu->cfg.vext_spec) {
 500                 if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
 501                     vext_version = VEXT_VERSION_0_07_1;
 502                 } else {
 503                     error_setg(errp,
 504                            "Unsupported vector spec version '%s'",
 505                            cpu->cfg.vext_spec);
 506                     return;
 507                 }
 508             } else {
 509                 qemu_log("vector verison is not specified, "
 510                         "use the default value v0.7.1\n");
 511             }
 512             set_vext_version(env, vext_version);
 513         }
 514
 515         set_misa(env, target_misa);
 516     }
 517
 518     riscv_cpu_register_gdb_regs_for_features(cs);
 519
 520     qemu_init_vcpu(cs);
 521     cpu_reset(cs);
 522
 523     mcc->parent_realize(dev, errp);
 524 }
 525
 526 static void riscv_cpu_init(Object *obj)
 527 {
 528     RISCVCPU *cpu = RISCV_CPU(obj);
 529
 530     cpu_set_cpustate_pointers(cpu);
 531 }
 532
 533 static Property riscv_cpu_properties[] = {
 534     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
 535     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
 536     DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
 537     DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
 538     DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
 539     DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
 540     DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
 541     DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
 542     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
 543     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
 544     /* This is experimental so mark with 'x-' */
 545     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
 546     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
 547     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
 548     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
 549     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
 550     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
 551     DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
 552     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
 553     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
 554     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
 555     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
 556     DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
 557     DEFINE_PROP_END_OF_LIST(),
 558 };
 559
 560 static gchar *riscv_gdb_arch_name(CPUState *cs)
 561 {
 562     RISCVCPU *cpu = RISCV_CPU(cs);
 563     CPURISCVState *env = &cpu->env;
 564
 565     if (riscv_cpu_is_32bit(env)) {
 566         return g_strdup("riscv:rv32");
 567     } else {
 568         return g_strdup("riscv:rv64");
 569     }
 570 }
 571
 572 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
 573 {
 574     RISCVCPU *cpu = RISCV_CPU(cs);
 575
 576     if (strcmp(xmlname, "riscv-csr.xml") == 0) {
 577         return cpu->dyn_csr_xml;
 578     }
 579
 580     return NULL;
 581 }
 582
 583 #include "hw/core/tcg-cpu-ops.h"
 584
 585 static struct TCGCPUOps riscv_tcg_ops = {
 586     .initialize = riscv_translate_init,
 587     .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
 588     .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
 589     .tlb_fill = riscv_cpu_tlb_fill,
 590
 591 #ifndef CONFIG_USER_ONLY
 592     .do_interrupt = riscv_cpu_do_interrupt,
 593     .do_transaction_failed = riscv_cpu_do_transaction_failed,
 594     .do_unaligned_access = riscv_cpu_do_unaligned_access,
 595 #endif /* !CONFIG_USER_ONLY */
 596 };
 597
 598 static void riscv_cpu_class_init(ObjectClass *c, void *data)
 599 {
 600     RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
 601     CPUClass *cc = CPU_CLASS(c);
 602     DeviceClass *dc = DEVICE_CLASS(c);
 603
 604     device_class_set_parent_realize(dc, riscv_cpu_realize,
 605                                     &mcc->parent_realize);
 606
 607     device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
 608
 609     cc->class_by_name = riscv_cpu_class_by_name;
 610     cc->has_work = riscv_cpu_has_work;
 611     cc->dump_state = riscv_cpu_dump_state;
 612     cc->set_pc = riscv_cpu_set_pc;
 613     cc->gdb_read_register = riscv_cpu_gdb_read_register;
 614     cc->gdb_write_register = riscv_cpu_gdb_write_register;
 615     cc->gdb_num_core_regs = 33;
 616 #if defined(TARGET_RISCV32)
 617     cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
 618 #elif defined(TARGET_RISCV64)
 619     cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
 620 #endif
 621     cc->gdb_stop_before_watchpoint = true;
 622     cc->disas_set_info = riscv_cpu_disas_set_info;
 623 #ifndef CONFIG_USER_ONLY
 624     cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
 625     /* For now, mark unmigratable: */
 626     cc->vmsd = &vmstate_riscv_cpu;
 627     cc->write_elf64_note = riscv_cpu_write_elf64_note;
 628     cc->write_elf32_note = riscv_cpu_write_elf32_note;
 629 #endif
 630     cc->gdb_arch_name = riscv_gdb_arch_name;
 631     cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
 632     cc->tcg_ops = &riscv_tcg_ops;
 633
 634     device_class_set_props(dc, riscv_cpu_properties);
 635 }
 636
 637 char *riscv_isa_string(RISCVCPU *cpu)
 638 {
 639     int i;
 640     const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
 641     char *isa_str = g_new(char, maxlen);
 642     char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
 643     for (i = 0; i < sizeof(riscv_exts); i++) {
 644         if (cpu->env.misa & RV(riscv_exts[i])) {
 645             *p++ = qemu_tolower(riscv_exts[i]);
 646         }
 647     }
 648     *p = '\0';
 649     return isa_str;
 650 }
 651
 652 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
 653 {
 654     ObjectClass *class_a = (ObjectClass *)a;
 655     ObjectClass *class_b = (ObjectClass *)b;
 656     const char *name_a, *name_b;
 657
 658     name_a = object_class_get_name(class_a);
 659     name_b = object_class_get_name(class_b);
 660     return strcmp(name_a, name_b);
 661 }
 662
 663 static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
 664 {
 665     const char *typename = object_class_get_name(OBJECT_CLASS(data));
 666     int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
 667
 668     qemu_printf("%.*s\n", len, typename);
 669 }
 670
 671 void riscv_cpu_list(void)
 672 {
 673     GSList *list;
 674
 675     list = object_class_get_list(TYPE_RISCV_CPU, false);
 676     list = g_slist_sort(list, riscv_cpu_list_compare);
 677     g_slist_foreach(list, riscv_cpu_list_entry, NULL);
 678     g_slist_free(list);
 679 }
 680
 681 #define DEFINE_CPU(type_name, initfn)      \
 682     {                                      \
 683         .name = type_name,                 \
 684         .parent = TYPE_RISCV_CPU,          \
 685         .instance_init = initfn            \
 686     }
 687
 688 static const TypeInfo riscv_cpu_type_infos[] = {
 689     {
 690         .name = TYPE_RISCV_CPU,
 691         .parent = TYPE_CPU,
 692         .instance_size = sizeof(RISCVCPU),
 693         .instance_align = __alignof__(RISCVCPU),
 694         .instance_init = riscv_cpu_init,
 695         .abstract = true,
 696         .class_size = sizeof(RISCVCPUClass),
 697         .class_init = riscv_cpu_class_init,
 698     },
 699     DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
 700 #if defined(TARGET_RISCV32)
 701     DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           rv32_base_cpu_init),
 702     DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),
 703     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32_sifive_e_cpu_init),
 704     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,       rv32_imafcu_nommu_cpu_init),
 705     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32_sifive_u_cpu_init),
 706 #elif defined(TARGET_RISCV64)
 707     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           rv64_base_cpu_init),
 708     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64_sifive_e_cpu_init),
 709     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64_sifive_u_cpu_init),
 710 #endif
 711 };
 712
 713 DEFINE_TYPES(riscv_cpu_type_infos)