target/avr/helper.c

   1 /*
   2  * QEMU AVR CPU helpers
   3  *
   4  * Copyright (c) 2016-2020 Michael Rolnik
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "cpu.h"
  23 #include "hw/core/tcg-cpu-ops.h"
  24 #include "exec/exec-all.h"
  25 #include "exec/address-spaces.h"
  26 #include "exec/helper-proto.h"
  27
  28 bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
  29 {
  30     bool ret = false;
  31     CPUClass *cc = CPU_GET_CLASS(cs);
  32     AVRCPU *cpu = AVR_CPU(cs);
  33     CPUAVRState *env = &cpu->env;
  34
  35     if (interrupt_request & CPU_INTERRUPT_RESET) {
  36         if (cpu_interrupts_enabled(env)) {
  37             cs->exception_index = EXCP_RESET;
  38             cc->tcg_ops->do_interrupt(cs);
  39
  40             cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
  41
  42             ret = true;
  43         }
  44     }
  45     if (interrupt_request & CPU_INTERRUPT_HARD) {
  46         if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
  47             int index = ctz32(env->intsrc);
  48             cs->exception_index = EXCP_INT(index);
  49             cc->tcg_ops->do_interrupt(cs);
  50
  51             env->intsrc &= env->intsrc - 1; /* clear the interrupt */
  52             cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
  53
  54             ret = true;
  55         }
  56     }
  57     return ret;
  58 }
  59
  60 void avr_cpu_do_interrupt(CPUState *cs)
  61 {
  62     AVRCPU *cpu = AVR_CPU(cs);
  63     CPUAVRState *env = &cpu->env;
  64
  65     uint32_t ret = env->pc_w;
  66     int vector = 0;
  67     int size = avr_feature(env, AVR_FEATURE_JMP_CALL) ? 2 : 1;
  68     int base = 0;
  69
  70     if (cs->exception_index == EXCP_RESET) {
  71         vector = 0;
  72     } else if (env->intsrc != 0) {
  73         vector = ctz32(env->intsrc) + 1;
  74     }
  75
  76     if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {
  77         cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
  78         cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
  79         cpu_stb_data(env, env->sp--, (ret & 0xff0000) >> 16);
  80     } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) {
  81         cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
  82         cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
  83     } else {
  84         cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
  85     }
  86
  87     env->pc_w = base + vector * size;
  88     env->sregI = 0; /* clear Global Interrupt Flag */
  89
  90     cs->exception_index = -1;
  91 }
  92
  93 int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf,
  94                             int len, bool is_write)
  95 {
  96     return cpu_memory_rw_debug(cs, addr, buf, len, is_write);
  97 }
  98
  99 hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 100 {
 101     return addr; /* I assume 1:1 address correspondance */
 102 }
 103
 104 bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 105                       MMUAccessType access_type, int mmu_idx,
 106                       bool probe, uintptr_t retaddr)
 107 {
 108     int prot = 0;
 109     MemTxAttrs attrs = {};
 110     uint32_t paddr;
 111
 112     address &= TARGET_PAGE_MASK;
 113
 114     if (mmu_idx == MMU_CODE_IDX) {
 115         /* access to code in flash */
 116         paddr = OFFSET_CODE + address;
 117         prot = PAGE_READ | PAGE_EXEC;
 118         if (paddr + TARGET_PAGE_SIZE > OFFSET_DATA) {
 119             error_report("execution left flash memory");
 120             abort();
 121         }
 122     } else if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
 123         /*
 124          * access to CPU registers, exit and rebuilt this TB to use full access
 125          * incase it touches specially handled registers like SREG or SP
 126          */
 127         AVRCPU *cpu = AVR_CPU(cs);
 128         CPUAVRState *env = &cpu->env;
 129         env->fullacc = 1;
 130         cpu_loop_exit_restore(cs, retaddr);
 131     } else {
 132         /* access to memory. nothing special */
 133         paddr = OFFSET_DATA + address;
 134         prot = PAGE_READ | PAGE_WRITE;
 135     }
 136
 137     tlb_set_page_with_attrs(cs, address, paddr, attrs, prot,
 138                             mmu_idx, TARGET_PAGE_SIZE);
 139
 140     return true;
 141 }
 142
 143 /*
 144  *  helpers
 145  */
 146
 147 void helper_sleep(CPUAVRState *env)
 148 {
 149     CPUState *cs = env_cpu(env);
 150
 151     cs->exception_index = EXCP_HLT;
 152     cpu_loop_exit(cs);
 153 }
 154
 155 void helper_unsupported(CPUAVRState *env)
 156 {
 157     CPUState *cs = env_cpu(env);
 158
 159     /*
 160      *  I count not find what happens on the real platform, so
 161      *  it's EXCP_DEBUG for meanwhile
 162      */
 163     cs->exception_index = EXCP_DEBUG;
 164     if (qemu_loglevel_mask(LOG_UNIMP)) {
 165         qemu_log("UNSUPPORTED\n");
 166         cpu_dump_state(cs, stderr, 0);
 167     }
 168     cpu_loop_exit(cs);
 169 }
 170
 171 void helper_debug(CPUAVRState *env)
 172 {
 173     CPUState *cs = env_cpu(env);
 174
 175     cs->exception_index = EXCP_DEBUG;
 176     cpu_loop_exit(cs);
 177 }
 178
 179 void helper_break(CPUAVRState *env)
 180 {
 181     CPUState *cs = env_cpu(env);
 182
 183     cs->exception_index = EXCP_DEBUG;
 184     cpu_loop_exit(cs);
 185 }
 186
 187 void helper_wdr(CPUAVRState *env)
 188 {
 189     CPUState *cs = env_cpu(env);
 190
 191     /* WD is not implemented yet, placeholder */
 192     cs->exception_index = EXCP_DEBUG;
 193     cpu_loop_exit(cs);
 194 }
 195
 196 /*
 197  * This function implements IN instruction
 198  *
 199  * It does the following
 200  * a.  if an IO register belongs to CPU, its value is read and returned
 201  * b.  otherwise io address is translated to mem address and physical memory
 202  *     is read.
 203  * c.  it caches the value for sake of SBI, SBIC, SBIS & CBI implementation
 204  *
 205  */
 206 target_ulong helper_inb(CPUAVRState *env, uint32_t port)
 207 {
 208     target_ulong data = 0;
 209
 210     switch (port) {
 211     case 0x38: /* RAMPD */
 212         data = 0xff & (env->rampD >> 16);
 213         break;
 214     case 0x39: /* RAMPX */
 215         data = 0xff & (env->rampX >> 16);
 216         break;
 217     case 0x3a: /* RAMPY */
 218         data = 0xff & (env->rampY >> 16);
 219         break;
 220     case 0x3b: /* RAMPZ */
 221         data = 0xff & (env->rampZ >> 16);
 222         break;
 223     case 0x3c: /* EIND */
 224         data = 0xff & (env->eind >> 16);
 225         break;
 226     case 0x3d: /* SPL */
 227         data = env->sp & 0x00ff;
 228         break;
 229     case 0x3e: /* SPH */
 230         data = env->sp >> 8;
 231         break;
 232     case 0x3f: /* SREG */
 233         data = cpu_get_sreg(env);
 234         break;
 235     default:
 236         /* not a special register, pass to normal memory access */
 237         data = address_space_ldub(&address_space_memory,
 238                                   OFFSET_IO_REGISTERS + port,
 239                                   MEMTXATTRS_UNSPECIFIED, NULL);
 240     }
 241
 242     return data;
 243 }
 244
 245 /*
 246  *  This function implements OUT instruction
 247  *
 248  *  It does the following
 249  *  a.  if an IO register belongs to CPU, its value is written into the register
 250  *  b.  otherwise io address is translated to mem address and physical memory
 251  *      is written.
 252  *  c.  it caches the value for sake of SBI, SBIC, SBIS & CBI implementation
 253  *
 254  */
 255 void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data)
 256 {
 257     data &= 0x000000ff;
 258
 259     switch (port) {
 260     case 0x38: /* RAMPD */
 261         if (avr_feature(env, AVR_FEATURE_RAMPD)) {
 262             env->rampD = (data & 0xff) << 16;
 263         }
 264         break;
 265     case 0x39: /* RAMPX */
 266         if (avr_feature(env, AVR_FEATURE_RAMPX)) {
 267             env->rampX = (data & 0xff) << 16;
 268         }
 269         break;
 270     case 0x3a: /* RAMPY */
 271         if (avr_feature(env, AVR_FEATURE_RAMPY)) {
 272             env->rampY = (data & 0xff) << 16;
 273         }
 274         break;
 275     case 0x3b: /* RAMPZ */
 276         if (avr_feature(env, AVR_FEATURE_RAMPZ)) {
 277             env->rampZ = (data & 0xff) << 16;
 278         }
 279         break;
 280     case 0x3c: /* EIDN */
 281         env->eind = (data & 0xff) << 16;
 282         break;
 283     case 0x3d: /* SPL */
 284         env->sp = (env->sp & 0xff00) | (data);
 285         break;
 286     case 0x3e: /* SPH */
 287         if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) {
 288             env->sp = (env->sp & 0x00ff) | (data << 8);
 289         }
 290         break;
 291     case 0x3f: /* SREG */
 292         cpu_set_sreg(env, data);
 293         break;
 294     default:
 295         /* not a special register, pass to normal memory access */
 296         address_space_stb(&address_space_memory, OFFSET_IO_REGISTERS + port,
 297                           data, MEMTXATTRS_UNSPECIFIED, NULL);
 298     }
 299 }
 300
 301 /*
 302  *  this function implements LD instruction when there is a posibility to read
 303  *  from a CPU register
 304  */
 305 target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr)
 306 {
 307     uint8_t data;
 308
 309     env->fullacc = false;
 310
 311     if (addr < NUMBER_OF_CPU_REGISTERS) {
 312         /* CPU registers */
 313         data = env->r[addr];
 314     } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
 315         /* IO registers */
 316         data = helper_inb(env, addr - NUMBER_OF_CPU_REGISTERS);
 317     } else {
 318         /* memory */
 319         data = address_space_ldub(&address_space_memory, OFFSET_DATA + addr,
 320                                   MEMTXATTRS_UNSPECIFIED, NULL);
 321     }
 322     return data;
 323 }
 324
 325 /*
 326  *  this function implements ST instruction when there is a posibility to write
 327  *  into a CPU register
 328  */
 329 void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr)
 330 {
 331     env->fullacc = false;
 332
 333     /* Following logic assumes this: */
 334     assert(OFFSET_CPU_REGISTERS == OFFSET_DATA);
 335     assert(OFFSET_IO_REGISTERS == OFFSET_CPU_REGISTERS +
 336                                   NUMBER_OF_CPU_REGISTERS);
 337
 338     if (addr < NUMBER_OF_CPU_REGISTERS) {
 339         /* CPU registers */
 340         env->r[addr] = data;
 341     } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
 342         /* IO registers */
 343         helper_outb(env, addr - NUMBER_OF_CPU_REGISTERS, data);
 344     } else {
 345         /* memory */
 346         address_space_stb(&address_space_memory, OFFSET_DATA + addr, data,
 347                           MEMTXATTRS_UNSPECIFIED, NULL);
 348     }
 349 }