2 * QEMU PowerPC sPAPR IRQ interface
4 * Copyright (c) 2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/error-report.h"
13 #include "qapi/error.h"
15 #include "hw/ppc/spapr.h"
16 #include "hw/ppc/spapr_cpu_core.h"
17 #include "hw/ppc/spapr_xive.h"
18 #include "hw/ppc/xics.h"
19 #include "hw/ppc/xics_spapr.h"
20 #include "hw/qdev-properties.h"
21 #include "cpu-models.h"
22 #include "sysemu/kvm.h"
26 static const TypeInfo spapr_intc_info
= {
27 .name
= TYPE_SPAPR_INTC
,
28 .parent
= TYPE_INTERFACE
,
29 .class_size
= sizeof(SpaprInterruptControllerClass
),
32 void spapr_irq_msi_init(SpaprMachineState
*spapr
, uint32_t nr_msis
)
34 spapr
->irq_map_nr
= nr_msis
;
35 spapr
->irq_map
= bitmap_new(spapr
->irq_map_nr
);
38 int spapr_irq_msi_alloc(SpaprMachineState
*spapr
, uint32_t num
, bool align
,
44 * The 'align_mask' parameter of bitmap_find_next_zero_area()
45 * should be one less than a power of 2; 0 means no
46 * alignment. Adapt the 'align' value of the former allocator
47 * to fit the requirements of bitmap_find_next_zero_area()
51 irq
= bitmap_find_next_zero_area(spapr
->irq_map
, spapr
->irq_map_nr
, 0, num
,
53 if (irq
== spapr
->irq_map_nr
) {
54 error_setg(errp
, "can't find a free %d-IRQ block", num
);
58 bitmap_set(spapr
->irq_map
, irq
, num
);
60 return irq
+ SPAPR_IRQ_MSI
;
63 void spapr_irq_msi_free(SpaprMachineState
*spapr
, int irq
, uint32_t num
)
65 bitmap_clear(spapr
->irq_map
, irq
- SPAPR_IRQ_MSI
, num
);
68 static void spapr_irq_init_kvm(SpaprMachineState
*spapr
,
69 SpaprIrq
*irq
, Error
**errp
)
71 MachineState
*machine
= MACHINE(spapr
);
72 Error
*local_err
= NULL
;
74 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine
)) {
75 irq
->init_kvm(spapr
, &local_err
);
76 if (local_err
&& machine_kernel_irqchip_required(machine
)) {
77 error_prepend(&local_err
,
78 "kernel_irqchip requested but unavailable: ");
79 error_propagate(errp
, local_err
);
88 * We failed to initialize the KVM device, fallback to
91 error_prepend(&local_err
, "kernel_irqchip allowed but unavailable: ");
92 error_append_hint(&local_err
, "Falling back to kernel-irqchip=off\n");
93 warn_report_err(local_err
);
101 static void spapr_irq_print_info_xics(SpaprMachineState
*spapr
, Monitor
*mon
)
106 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
108 icp_pic_print_info(spapr_cpu_state(cpu
)->icp
, mon
);
111 ics_pic_print_info(spapr
->ics
, mon
);
114 static int spapr_irq_post_load_xics(SpaprMachineState
*spapr
, int version_id
)
116 if (!kvm_irqchip_in_kernel()) {
119 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
120 icp_resend(spapr_cpu_state(cpu
)->icp
);
126 static void spapr_irq_set_irq_xics(void *opaque
, int irq
, int val
)
128 SpaprMachineState
*spapr
= opaque
;
129 uint32_t srcno
= irq
- spapr
->ics
->offset
;
131 ics_set_irq(spapr
->ics
, srcno
, val
);
134 static void spapr_irq_reset_xics(SpaprMachineState
*spapr
, Error
**errp
)
136 Error
*local_err
= NULL
;
138 spapr_irq_init_kvm(spapr
, &spapr_irq_xics
, &local_err
);
140 error_propagate(errp
, local_err
);
145 static void spapr_irq_init_kvm_xics(SpaprMachineState
*spapr
, Error
**errp
)
148 xics_kvm_connect(spapr
, errp
);
152 SpaprIrq spapr_irq_xics
= {
153 .nr_xirqs
= SPAPR_NR_XIRQS
,
154 .nr_msis
= SPAPR_NR_MSIS
,
158 .print_info
= spapr_irq_print_info_xics
,
159 .dt_populate
= spapr_dt_xics
,
160 .post_load
= spapr_irq_post_load_xics
,
161 .reset
= spapr_irq_reset_xics
,
162 .set_irq
= spapr_irq_set_irq_xics
,
163 .init_kvm
= spapr_irq_init_kvm_xics
,
170 static void spapr_irq_print_info_xive(SpaprMachineState
*spapr
,
176 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
178 xive_tctx_pic_print_info(spapr_cpu_state(cpu
)->tctx
, mon
);
181 spapr_xive_pic_print_info(spapr
->xive
, mon
);
184 static int spapr_irq_post_load_xive(SpaprMachineState
*spapr
, int version_id
)
186 return spapr_xive_post_load(spapr
->xive
, version_id
);
189 static void spapr_irq_reset_xive(SpaprMachineState
*spapr
, Error
**errp
)
192 Error
*local_err
= NULL
;
195 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
197 /* (TCG) Set the OS CAM line of the thread interrupt context. */
198 spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu
)->tctx
);
201 spapr_irq_init_kvm(spapr
, &spapr_irq_xive
, &local_err
);
203 error_propagate(errp
, local_err
);
207 /* Activate the XIVE MMIOs */
208 spapr_xive_mmio_set_enabled(spapr
->xive
, true);
211 static void spapr_irq_set_irq_xive(void *opaque
, int irq
, int val
)
213 SpaprMachineState
*spapr
= opaque
;
215 if (kvm_irqchip_in_kernel()) {
216 kvmppc_xive_source_set_irq(&spapr
->xive
->source
, irq
, val
);
218 xive_source_set_irq(&spapr
->xive
->source
, irq
, val
);
222 static void spapr_irq_init_kvm_xive(SpaprMachineState
*spapr
, Error
**errp
)
225 kvmppc_xive_connect(spapr
->xive
, errp
);
229 SpaprIrq spapr_irq_xive
= {
230 .nr_xirqs
= SPAPR_NR_XIRQS
,
231 .nr_msis
= SPAPR_NR_MSIS
,
235 .print_info
= spapr_irq_print_info_xive
,
236 .dt_populate
= spapr_dt_xive
,
237 .post_load
= spapr_irq_post_load_xive
,
238 .reset
= spapr_irq_reset_xive
,
239 .set_irq
= spapr_irq_set_irq_xive
,
240 .init_kvm
= spapr_irq_init_kvm_xive
,
244 * Dual XIVE and XICS IRQ backend.
246 * Both interrupt mode, XIVE and XICS, objects are created but the
247 * machine starts in legacy interrupt mode (XICS). It can be changed
248 * by the CAS negotiation process and, in that case, the new mode is
249 * activated after an extra machine reset.
253 * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the
256 static SpaprIrq
*spapr_irq_current(SpaprMachineState
*spapr
)
258 return spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
) ?
259 &spapr_irq_xive
: &spapr_irq_xics
;
262 static void spapr_irq_print_info_dual(SpaprMachineState
*spapr
, Monitor
*mon
)
264 spapr_irq_current(spapr
)->print_info(spapr
, mon
);
267 static void spapr_irq_dt_populate_dual(SpaprMachineState
*spapr
,
268 uint32_t nr_servers
, void *fdt
,
271 spapr_irq_current(spapr
)->dt_populate(spapr
, nr_servers
, fdt
, phandle
);
274 static int spapr_irq_post_load_dual(SpaprMachineState
*spapr
, int version_id
)
277 * Force a reset of the XIVE backend after migration. The machine
278 * defaults to XICS at startup.
280 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
281 if (kvm_irqchip_in_kernel()) {
282 xics_kvm_disconnect(spapr
, &error_fatal
);
284 spapr_irq_xive
.reset(spapr
, &error_fatal
);
287 return spapr_irq_current(spapr
)->post_load(spapr
, version_id
);
290 static void spapr_irq_reset_dual(SpaprMachineState
*spapr
, Error
**errp
)
292 Error
*local_err
= NULL
;
295 * Deactivate the XIVE MMIOs. The XIVE backend will reenable them
298 spapr_xive_mmio_set_enabled(spapr
->xive
, false);
300 /* Destroy all KVM devices */
301 if (kvm_irqchip_in_kernel()) {
302 xics_kvm_disconnect(spapr
, &local_err
);
304 error_propagate(errp
, local_err
);
305 error_prepend(errp
, "KVM XICS disconnect failed: ");
308 kvmppc_xive_disconnect(spapr
->xive
, &local_err
);
310 error_propagate(errp
, local_err
);
311 error_prepend(errp
, "KVM XIVE disconnect failed: ");
316 spapr_irq_current(spapr
)->reset(spapr
, errp
);
319 static void spapr_irq_set_irq_dual(void *opaque
, int irq
, int val
)
321 SpaprMachineState
*spapr
= opaque
;
323 spapr_irq_current(spapr
)->set_irq(spapr
, irq
, val
);
327 * Define values in sync with the XIVE and XICS backend
329 SpaprIrq spapr_irq_dual
= {
330 .nr_xirqs
= SPAPR_NR_XIRQS
,
331 .nr_msis
= SPAPR_NR_MSIS
,
335 .print_info
= spapr_irq_print_info_dual
,
336 .dt_populate
= spapr_irq_dt_populate_dual
,
337 .post_load
= spapr_irq_post_load_dual
,
338 .reset
= spapr_irq_reset_dual
,
339 .set_irq
= spapr_irq_set_irq_dual
,
340 .init_kvm
= NULL
, /* should not be used */
344 static int spapr_irq_check(SpaprMachineState
*spapr
, Error
**errp
)
346 MachineState
*machine
= MACHINE(spapr
);
349 * Sanity checks on non-P9 machines. On these, XIVE is not
350 * advertised, see spapr_dt_ov5_platform_support()
352 if (!ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
,
353 0, spapr
->max_compat_pvr
)) {
355 * If the 'dual' interrupt mode is selected, force XICS as CAS
356 * negotiation is useless.
358 if (spapr
->irq
== &spapr_irq_dual
) {
359 spapr
->irq
= &spapr_irq_xics
;
364 * Non-P9 machines using only XIVE is a bogus setup. We have two
365 * scenarios to take into account because of the compat mode:
367 * 1. POWER7/8 machines should fail to init later on when creating
368 * the XIVE interrupt presenters because a POWER9 exception
371 * 2. POWER9 machines using the POWER8 compat mode won't fail and
372 * will let the OS boot with a partial XIVE setup : DT
373 * properties but no hcalls.
375 * To cover both and not confuse the OS, add an early failure in
378 if (spapr
->irq
== &spapr_irq_xive
) {
379 error_setg(errp
, "XIVE-only machines require a POWER9 CPU");
385 * On a POWER9 host, some older KVM XICS devices cannot be destroyed and
386 * re-created. Detect that early to avoid QEMU to exit later when the
390 spapr
->irq
== &spapr_irq_dual
&&
391 machine_kernel_irqchip_required(machine
) &&
392 xics_kvm_has_broken_disconnect(spapr
)) {
393 error_setg(errp
, "KVM is too old to support ic-mode=dual,kernel-irqchip=on");
401 * sPAPR IRQ frontend routines for devices
403 #define ALL_INTCS(spapr_) \
404 { SPAPR_INTC((spapr_)->ics), SPAPR_INTC((spapr_)->xive), }
406 int spapr_irq_cpu_intc_create(SpaprMachineState
*spapr
,
407 PowerPCCPU
*cpu
, Error
**errp
)
409 SpaprInterruptController
*intcs
[] = ALL_INTCS(spapr
);
413 for (i
= 0; i
< ARRAY_SIZE(intcs
); i
++) {
414 SpaprInterruptController
*intc
= intcs
[i
];
416 SpaprInterruptControllerClass
*sicc
= SPAPR_INTC_GET_CLASS(intc
);
417 rc
= sicc
->cpu_intc_create(intc
, cpu
, errp
);
427 void spapr_irq_init(SpaprMachineState
*spapr
, Error
**errp
)
429 MachineState
*machine
= MACHINE(spapr
);
431 if (machine_kernel_irqchip_split(machine
)) {
432 error_setg(errp
, "kernel_irqchip split mode not supported on pseries");
436 if (!kvm_enabled() && machine_kernel_irqchip_required(machine
)) {
438 "kernel_irqchip requested but only available with KVM");
442 if (spapr_irq_check(spapr
, errp
) < 0) {
446 /* Initialize the MSI IRQ allocator. */
447 if (!SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
448 spapr_irq_msi_init(spapr
, spapr
->irq
->nr_msis
);
451 if (spapr
->irq
->xics
) {
452 Error
*local_err
= NULL
;
455 obj
= object_new(TYPE_ICS_SPAPR
);
456 object_property_add_child(OBJECT(spapr
), "ics", obj
, &local_err
);
458 error_propagate(errp
, local_err
);
462 object_property_add_const_link(obj
, ICS_PROP_XICS
, OBJECT(spapr
),
465 error_propagate(errp
, local_err
);
469 object_property_set_int(obj
, spapr
->irq
->nr_xirqs
, "nr-irqs",
472 error_propagate(errp
, local_err
);
476 object_property_set_bool(obj
, true, "realized", &local_err
);
478 error_propagate(errp
, local_err
);
482 spapr
->ics
= ICS_SPAPR(obj
);
485 if (spapr
->irq
->xive
) {
486 uint32_t nr_servers
= spapr_max_server_number(spapr
);
490 dev
= qdev_create(NULL
, TYPE_SPAPR_XIVE
);
491 qdev_prop_set_uint32(dev
, "nr-irqs",
492 spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
);
494 * 8 XIVE END structures per CPU. One for each available
497 qdev_prop_set_uint32(dev
, "nr-ends", nr_servers
<< 3);
498 qdev_init_nofail(dev
);
500 spapr
->xive
= SPAPR_XIVE(dev
);
502 /* Enable the CPU IPIs */
503 for (i
= 0; i
< nr_servers
; ++i
) {
504 SpaprInterruptControllerClass
*sicc
505 = SPAPR_INTC_GET_CLASS(spapr
->xive
);
507 if (sicc
->claim_irq(SPAPR_INTC(spapr
->xive
), SPAPR_IRQ_IPI
+ i
,
513 spapr_xive_hcall_init(spapr
);
516 spapr
->qirqs
= qemu_allocate_irqs(spapr
->irq
->set_irq
, spapr
,
517 spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
);
520 int spapr_irq_claim(SpaprMachineState
*spapr
, int irq
, bool lsi
, Error
**errp
)
522 SpaprInterruptController
*intcs
[] = ALL_INTCS(spapr
);
526 assert(irq
>= SPAPR_XIRQ_BASE
);
527 assert(irq
< (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
529 for (i
= 0; i
< ARRAY_SIZE(intcs
); i
++) {
530 SpaprInterruptController
*intc
= intcs
[i
];
532 SpaprInterruptControllerClass
*sicc
= SPAPR_INTC_GET_CLASS(intc
);
533 rc
= sicc
->claim_irq(intc
, irq
, lsi
, errp
);
543 void spapr_irq_free(SpaprMachineState
*spapr
, int irq
, int num
)
545 SpaprInterruptController
*intcs
[] = ALL_INTCS(spapr
);
548 assert(irq
>= SPAPR_XIRQ_BASE
);
549 assert((irq
+ num
) <= (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
551 for (i
= irq
; i
< (irq
+ num
); i
++) {
552 for (j
= 0; j
< ARRAY_SIZE(intcs
); j
++) {
553 SpaprInterruptController
*intc
= intcs
[j
];
556 SpaprInterruptControllerClass
*sicc
557 = SPAPR_INTC_GET_CLASS(intc
);
558 sicc
->free_irq(intc
, i
);
564 qemu_irq
spapr_qirq(SpaprMachineState
*spapr
, int irq
)
567 * This interface is basically for VIO and PHB devices to find the
568 * right qemu_irq to manipulate, so we only allow access to the
569 * external irqs for now. Currently anything which needs to
570 * access the IPIs most naturally gets there via the guest side
571 * interfaces, we can change this if we need to in future.
573 assert(irq
>= SPAPR_XIRQ_BASE
);
574 assert(irq
< (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
577 assert(ics_valid_irq(spapr
->ics
, irq
));
580 assert(irq
< spapr
->xive
->nr_irqs
);
581 assert(xive_eas_is_valid(&spapr
->xive
->eat
[irq
]));
584 return spapr
->qirqs
[irq
];
587 int spapr_irq_post_load(SpaprMachineState
*spapr
, int version_id
)
589 return spapr
->irq
->post_load(spapr
, version_id
);
592 void spapr_irq_reset(SpaprMachineState
*spapr
, Error
**errp
)
594 assert(!spapr
->irq_map
|| bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
));
596 if (spapr
->irq
->reset
) {
597 spapr
->irq
->reset(spapr
, errp
);
601 int spapr_irq_get_phandle(SpaprMachineState
*spapr
, void *fdt
, Error
**errp
)
603 const char *nodename
= "interrupt-controller";
606 offset
= fdt_subnode_offset(fdt
, 0, nodename
);
608 error_setg(errp
, "Can't find node \"%s\": %s",
609 nodename
, fdt_strerror(offset
));
613 phandle
= fdt_get_phandle(fdt
, offset
);
615 error_setg(errp
, "Can't get phandle of node \"%s\"", nodename
);
623 * XICS legacy routines - to deprecate one day
626 static int ics_find_free_block(ICSState
*ics
, int num
, int alignnum
)
630 for (first
= 0; first
< ics
->nr_irqs
; first
+= alignnum
) {
631 if (num
> (ics
->nr_irqs
- first
)) {
634 for (i
= first
; i
< first
+ num
; ++i
) {
635 if (!ics_irq_free(ics
, i
)) {
639 if (i
== (first
+ num
)) {
647 int spapr_irq_find(SpaprMachineState
*spapr
, int num
, bool align
, Error
**errp
)
649 ICSState
*ics
= spapr
->ics
;
655 * MSIMesage::data is used for storing VIRQ so
656 * it has to be aligned to num to support multiple
657 * MSI vectors. MSI-X is not affected by this.
658 * The hint is used for the first IRQ, the rest should
659 * be allocated continuously.
662 assert((num
== 1) || (num
== 2) || (num
== 4) ||
663 (num
== 8) || (num
== 16) || (num
== 32));
664 first
= ics_find_free_block(ics
, num
, num
);
666 first
= ics_find_free_block(ics
, num
, 1);
670 error_setg(errp
, "can't find a free %d-IRQ block", num
);
674 return first
+ ics
->offset
;
677 #define SPAPR_IRQ_XICS_LEGACY_NR_XIRQS 0x400
679 SpaprIrq spapr_irq_xics_legacy
= {
680 .nr_xirqs
= SPAPR_IRQ_XICS_LEGACY_NR_XIRQS
,
681 .nr_msis
= SPAPR_IRQ_XICS_LEGACY_NR_XIRQS
,
685 .print_info
= spapr_irq_print_info_xics
,
686 .dt_populate
= spapr_dt_xics
,
687 .post_load
= spapr_irq_post_load_xics
,
688 .reset
= spapr_irq_reset_xics
,
689 .set_irq
= spapr_irq_set_irq_xics
,
690 .init_kvm
= spapr_irq_init_kvm_xics
,
693 static void spapr_irq_register_types(void)
695 type_register_static(&spapr_intc_info
);
698 type_init(spapr_irq_register_types
)