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fw_cfg: Refactor extra pci roots addition
[qemu/ar7.git] / hw / sparc / sun4m.c
blob66fecb152ac61dfb651da7dbc4db72d637df516a
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qapi/error.h"
28 #include "qemu-common.h"
29 #include "cpu.h"
30 #include "hw/sysbus.h"
31 #include "qemu/error-report.h"
32 #include "qemu/timer.h"
33 #include "hw/sparc/sun4m_iommu.h"
34 #include "hw/rtc/m48t59.h"
35 #include "migration/vmstate.h"
36 #include "hw/sparc/sparc32_dma.h"
37 #include "hw/block/fdc.h"
38 #include "sysemu/reset.h"
39 #include "sysemu/runstate.h"
40 #include "sysemu/sysemu.h"
41 #include "net/net.h"
42 #include "hw/boards.h"
43 #include "hw/scsi/esp.h"
44 #include "hw/nvram/sun_nvram.h"
45 #include "hw/qdev-properties.h"
46 #include "hw/nvram/chrp_nvram.h"
47 #include "hw/nvram/fw_cfg.h"
48 #include "hw/char/escc.h"
49 #include "hw/misc/empty_slot.h"
50 #include "hw/misc/unimp.h"
51 #include "hw/irq.h"
52 #include "hw/loader.h"
53 #include "elf.h"
54 #include "trace.h"
55 #include "qom/object.h"
56
57 /*
58 * Sun4m architecture was used in the following machines:
59 *
60 * SPARCserver 6xxMP/xx
61 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
62 * SPARCclassic X (4/10)
63 * SPARCstation LX/ZX (4/30)
64 * SPARCstation Voyager
65 * SPARCstation 10/xx, SPARCserver 10/xx
66 * SPARCstation 5, SPARCserver 5
67 * SPARCstation 20/xx, SPARCserver 20
68 * SPARCstation 4
69 *
70 * See for example: http://www.sunhelp.org/faq/sunref1.html
71 */
72
73 #define KERNEL_LOAD_ADDR 0x00004000
74 #define CMDLINE_ADDR 0x007ff000
75 #define INITRD_LOAD_ADDR 0x00800000
76 #define PROM_SIZE_MAX (1 * MiB)
77 #define PROM_VADDR 0xffd00000
78 #define PROM_FILENAME "openbios-sparc32"
79 #define CFG_ADDR 0xd00000510ULL
80 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
81 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
82 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
83
84 #define MAX_CPUS 16
85 #define MAX_PILS 16
86 #define MAX_VSIMMS 4
87
88 #define ESCC_CLOCK 4915200
89
90 struct sun4m_hwdef {
91 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
92 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
93 hwaddr serial_base, fd_base;
94 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
95 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
96 hwaddr bpp_base, dbri_base, sx_base;
97 struct {
98 hwaddr reg_base, vram_base;
99 } vsimm[MAX_VSIMMS];
100 hwaddr ecc_base;
101 uint64_t max_mem;
102 uint32_t ecc_version;
103 uint32_t iommu_version;
104 uint16_t machine_id;
105 uint8_t nvram_machine_id;
106 };
107
108 const char *fw_cfg_arch_key_name(uint16_t key)
109 {
110 static const struct {
111 uint16_t key;
112 const char *name;
113 } fw_cfg_arch_wellknown_keys[] = {
114 {FW_CFG_SUN4M_DEPTH, "depth"},
115 {FW_CFG_SUN4M_WIDTH, "width"},
116 {FW_CFG_SUN4M_HEIGHT, "height"},
117 };
118
119 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
120 if (fw_cfg_arch_wellknown_keys[i].key == key) {
121 return fw_cfg_arch_wellknown_keys[i].name;
122 }
123 }
124 return NULL;
125 }
126
127 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
128 Error **errp)
129 {
130 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
131 }
132
133 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
134 const char *cmdline, const char *boot_devices,
135 ram_addr_t RAM_size, uint32_t kernel_size,
136 int width, int height, int depth,
137 int nvram_machine_id, const char *arch)
138 {
139 unsigned int i;
140 int sysp_end;
141 uint8_t image[0x1ff0];
142 NvramClass *k = NVRAM_GET_CLASS(nvram);
143
144 memset(image, '\0', sizeof(image));
145
146 /* OpenBIOS nvram variables partition */
147 sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0);
148
149 /* Free space partition */
150 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
151
152 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
153 nvram_machine_id);
154
155 for (i = 0; i < sizeof(image); i++) {
156 (k->write)(nvram, i, image[i]);
157 }
158 }
159
160 void cpu_check_irqs(CPUSPARCState *env)
161 {
162 CPUState *cs;
163
164 /* We should be holding the BQL before we mess with IRQs */
165 g_assert(qemu_mutex_iothread_locked());
166
167 if (env->pil_in && (env->interrupt_index == 0 ||
168 (env->interrupt_index & ~15) == TT_EXTINT)) {
169 unsigned int i;
170
171 for (i = 15; i > 0; i--) {
172 if (env->pil_in & (1 << i)) {
173 int old_interrupt = env->interrupt_index;
174
175 env->interrupt_index = TT_EXTINT | i;
176 if (old_interrupt != env->interrupt_index) {
177 cs = env_cpu(env);
178 trace_sun4m_cpu_interrupt(i);
179 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
180 }
181 break;
182 }
183 }
184 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
185 cs = env_cpu(env);
186 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
187 env->interrupt_index = 0;
188 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
189 }
190 }
191
192 static void cpu_kick_irq(SPARCCPU *cpu)
193 {
194 CPUSPARCState *env = &cpu->env;
195 CPUState *cs = CPU(cpu);
196
197 cs->halted = 0;
198 cpu_check_irqs(env);
199 qemu_cpu_kick(cs);
200 }
201
202 static void cpu_set_irq(void *opaque, int irq, int level)
203 {
204 SPARCCPU *cpu = opaque;
205 CPUSPARCState *env = &cpu->env;
206
207 if (level) {
208 trace_sun4m_cpu_set_irq_raise(irq);
209 env->pil_in |= 1 << irq;
210 cpu_kick_irq(cpu);
211 } else {
212 trace_sun4m_cpu_set_irq_lower(irq);
213 env->pil_in &= ~(1 << irq);
214 cpu_check_irqs(env);
215 }
216 }
217
218 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
219 {
220 }
221
222 static void sun4m_cpu_reset(void *opaque)
223 {
224 SPARCCPU *cpu = opaque;
225 CPUState *cs = CPU(cpu);
226
227 cpu_reset(cs);
228 }
229
230 static void cpu_halt_signal(void *opaque, int irq, int level)
231 {
232 if (level && current_cpu) {
233 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
234 }
235 }
236
237 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
238 {
239 return addr - 0xf0000000ULL;
240 }
241
242 static unsigned long sun4m_load_kernel(const char *kernel_filename,
243 const char *initrd_filename,
244 ram_addr_t RAM_size,
245 uint32_t *initrd_size)
246 {
247 int linux_boot;
248 unsigned int i;
249 long kernel_size;
250 uint8_t *ptr;
251
252 linux_boot = (kernel_filename != NULL);
253
254 kernel_size = 0;
255 if (linux_boot) {
256 int bswap_needed;
257
258 #ifdef BSWAP_NEEDED
259 bswap_needed = 1;
260 #else
261 bswap_needed = 0;
262 #endif
263 kernel_size = load_elf(kernel_filename, NULL,
264 translate_kernel_address, NULL,
265 NULL, NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
266 if (kernel_size < 0)
267 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
268 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
269 TARGET_PAGE_SIZE);
270 if (kernel_size < 0)
271 kernel_size = load_image_targphys(kernel_filename,
272 KERNEL_LOAD_ADDR,
273 RAM_size - KERNEL_LOAD_ADDR);
274 if (kernel_size < 0) {
275 error_report("could not load kernel '%s'", kernel_filename);
276 exit(1);
277 }
278
279 /* load initrd */
280 *initrd_size = 0;
281 if (initrd_filename) {
282 *initrd_size = load_image_targphys(initrd_filename,
283 INITRD_LOAD_ADDR,
284 RAM_size - INITRD_LOAD_ADDR);
285 if ((int)*initrd_size < 0) {
286 error_report("could not load initial ram disk '%s'",
287 initrd_filename);
288 exit(1);
289 }
290 }
291 if (*initrd_size > 0) {
292 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
293 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24);
294 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */
295 stl_p(ptr + 16, INITRD_LOAD_ADDR);
296 stl_p(ptr + 20, *initrd_size);
297 break;
298 }
299 }
300 }
301 }
302 return kernel_size;
303 }
304
305 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
306 {
307 DeviceState *dev;
308 SysBusDevice *s;
309
310 dev = qdev_new(TYPE_SUN4M_IOMMU);
311 qdev_prop_set_uint32(dev, "version", version);
312 s = SYS_BUS_DEVICE(dev);
313 sysbus_realize_and_unref(s, &error_fatal);
314 sysbus_connect_irq(s, 0, irq);
315 sysbus_mmio_map(s, 0, addr);
316
317 return s;
318 }
319
320 static void *sparc32_dma_init(hwaddr dma_base,
321 hwaddr esp_base, qemu_irq espdma_irq,
322 hwaddr le_base, qemu_irq ledma_irq, NICInfo *nd)
323 {
324 DeviceState *dma;
325 ESPDMADeviceState *espdma;
326 LEDMADeviceState *ledma;
327 SysBusESPState *esp;
328 SysBusPCNetState *lance;
329
330 dma = qdev_new(TYPE_SPARC32_DMA);
331 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
332 OBJECT(dma), "espdma"));
333 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
334
335 esp = ESP(object_resolve_path_component(OBJECT(espdma), "esp"));
336
337 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
338 OBJECT(dma), "ledma"));
339 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
340
341 lance = SYSBUS_PCNET(object_resolve_path_component(
342 OBJECT(ledma), "lance"));
343 qdev_set_nic_properties(DEVICE(lance), nd);
344
345 sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
346 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
347
348 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
349 scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
350
351 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
352
353 return dma;
354 }
355
356 static DeviceState *slavio_intctl_init(hwaddr addr,
357 hwaddr addrg,
358 qemu_irq **parent_irq)
359 {
360 DeviceState *dev;
361 SysBusDevice *s;
362 unsigned int i, j;
363
364 dev = qdev_new("slavio_intctl");
365
366 s = SYS_BUS_DEVICE(dev);
367 sysbus_realize_and_unref(s, &error_fatal);
368
369 for (i = 0; i < MAX_CPUS; i++) {
370 for (j = 0; j < MAX_PILS; j++) {
371 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
372 }
373 }
374 sysbus_mmio_map(s, 0, addrg);
375 for (i = 0; i < MAX_CPUS; i++) {
376 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
377 }
378
379 return dev;
380 }
381
382 #define SYS_TIMER_OFFSET 0x10000ULL
383 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
384
385 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
386 qemu_irq *cpu_irqs, unsigned int num_cpus)
387 {
388 DeviceState *dev;
389 SysBusDevice *s;
390 unsigned int i;
391
392 dev = qdev_new("slavio_timer");
393 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
394 s = SYS_BUS_DEVICE(dev);
395 sysbus_realize_and_unref(s, &error_fatal);
396 sysbus_connect_irq(s, 0, master_irq);
397 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
398
399 for (i = 0; i < MAX_CPUS; i++) {
400 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
401 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
402 }
403 }
404
405 static qemu_irq slavio_system_powerdown;
406
407 static void slavio_powerdown_req(Notifier *n, void *opaque)
408 {
409 qemu_irq_raise(slavio_system_powerdown);
410 }
411
412 static Notifier slavio_system_powerdown_notifier = {
413 .notify = slavio_powerdown_req
414 };
415
416 #define MISC_LEDS 0x01600000
417 #define MISC_CFG 0x01800000
418 #define MISC_DIAG 0x01a00000
419 #define MISC_MDM 0x01b00000
420 #define MISC_SYS 0x01f00000
421
422 static void slavio_misc_init(hwaddr base,
423 hwaddr aux1_base,
424 hwaddr aux2_base, qemu_irq irq,
425 qemu_irq fdc_tc)
426 {
427 DeviceState *dev;
428 SysBusDevice *s;
429
430 dev = qdev_new("slavio_misc");
431 s = SYS_BUS_DEVICE(dev);
432 sysbus_realize_and_unref(s, &error_fatal);
433 if (base) {
434 /* 8 bit registers */
435 /* Slavio control */
436 sysbus_mmio_map(s, 0, base + MISC_CFG);
437 /* Diagnostics */
438 sysbus_mmio_map(s, 1, base + MISC_DIAG);
439 /* Modem control */
440 sysbus_mmio_map(s, 2, base + MISC_MDM);
441 /* 16 bit registers */
442 /* ss600mp diag LEDs */
443 sysbus_mmio_map(s, 3, base + MISC_LEDS);
444 /* 32 bit registers */
445 /* System control */
446 sysbus_mmio_map(s, 4, base + MISC_SYS);
447 }
448 if (aux1_base) {
449 /* AUX 1 (Misc System Functions) */
450 sysbus_mmio_map(s, 5, aux1_base);
451 }
452 if (aux2_base) {
453 /* AUX 2 (Software Powerdown Control) */
454 sysbus_mmio_map(s, 6, aux2_base);
455 }
456 sysbus_connect_irq(s, 0, irq);
457 sysbus_connect_irq(s, 1, fdc_tc);
458 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
459 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
460 }
461
462 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
463 {
464 DeviceState *dev;
465 SysBusDevice *s;
466
467 dev = qdev_new("eccmemctl");
468 qdev_prop_set_uint32(dev, "version", version);
469 s = SYS_BUS_DEVICE(dev);
470 sysbus_realize_and_unref(s, &error_fatal);
471 sysbus_connect_irq(s, 0, irq);
472 sysbus_mmio_map(s, 0, base);
473 if (version == 0) { // SS-600MP only
474 sysbus_mmio_map(s, 1, base + 0x1000);
475 }
476 }
477
478 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
479 {
480 DeviceState *dev;
481 SysBusDevice *s;
482
483 dev = qdev_new("apc");
484 s = SYS_BUS_DEVICE(dev);
485 sysbus_realize_and_unref(s, &error_fatal);
486 /* Power management (APC) XXX: not a Slavio device */
487 sysbus_mmio_map(s, 0, power_base);
488 sysbus_connect_irq(s, 0, cpu_halt);
489 }
490
491 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
492 int height, int depth)
493 {
494 DeviceState *dev;
495 SysBusDevice *s;
496
497 dev = qdev_new("SUNW,tcx");
498 qdev_prop_set_uint32(dev, "vram_size", vram_size);
499 qdev_prop_set_uint16(dev, "width", width);
500 qdev_prop_set_uint16(dev, "height", height);
501 qdev_prop_set_uint16(dev, "depth", depth);
502 s = SYS_BUS_DEVICE(dev);
503 sysbus_realize_and_unref(s, &error_fatal);
504
505 /* 10/ROM : FCode ROM */
506 sysbus_mmio_map(s, 0, addr);
507 /* 2/STIP : Stipple */
508 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
509 /* 3/BLIT : Blitter */
510 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
511 /* 5/RSTIP : Raw Stipple */
512 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
513 /* 6/RBLIT : Raw Blitter */
514 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
515 /* 7/TEC : Transform Engine */
516 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
517 /* 8/CMAP : DAC */
518 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
519 /* 9/THC : */
520 if (depth == 8) {
521 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
522 } else {
523 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
524 }
525 /* 11/DHC : */
526 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
527 /* 12/ALT : */
528 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
529 /* 0/DFB8 : 8-bit plane */
530 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
531 /* 1/DFB24 : 24bit plane */
532 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
533 /* 4/RDFB32: Raw framebuffer. Control plane */
534 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
535 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
536 if (depth == 8) {
537 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
538 }
539
540 sysbus_connect_irq(s, 0, irq);
541 }
542
543 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
544 int height, int depth)
545 {
546 DeviceState *dev;
547 SysBusDevice *s;
548
549 dev = qdev_new("cgthree");
550 qdev_prop_set_uint32(dev, "vram-size", vram_size);
551 qdev_prop_set_uint16(dev, "width", width);
552 qdev_prop_set_uint16(dev, "height", height);
553 qdev_prop_set_uint16(dev, "depth", depth);
554 s = SYS_BUS_DEVICE(dev);
555 sysbus_realize_and_unref(s, &error_fatal);
556
557 /* FCode ROM */
558 sysbus_mmio_map(s, 0, addr);
559 /* DAC */
560 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
561 /* 8-bit plane */
562 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
563
564 sysbus_connect_irq(s, 0, irq);
565 }
566
567 /* NCR89C100/MACIO Internal ID register */
568
569 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
570
571 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
572
573 static void idreg_init(hwaddr addr)
574 {
575 DeviceState *dev;
576 SysBusDevice *s;
577
578 dev = qdev_new(TYPE_MACIO_ID_REGISTER);
579 s = SYS_BUS_DEVICE(dev);
580 sysbus_realize_and_unref(s, &error_fatal);
581
582 sysbus_mmio_map(s, 0, addr);
583 address_space_write_rom(&address_space_memory, addr,
584 MEMTXATTRS_UNSPECIFIED,
585 idreg_data, sizeof(idreg_data));
586 }
587
588 OBJECT_DECLARE_SIMPLE_TYPE(IDRegState, MACIO_ID_REGISTER)
589
590 struct IDRegState {
591 SysBusDevice parent_obj;
592
593 MemoryRegion mem;
594 };
595
596 static void idreg_realize(DeviceState *ds, Error **errp)
597 {
598 IDRegState *s = MACIO_ID_REGISTER(ds);
599 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
600 Error *local_err = NULL;
601
602 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg",
603 sizeof(idreg_data), &local_err);
604 if (local_err) {
605 error_propagate(errp, local_err);
606 return;
607 }
608
609 vmstate_register_ram_global(&s->mem);
610 memory_region_set_readonly(&s->mem, true);
611 sysbus_init_mmio(dev, &s->mem);
612 }
613
614 static void idreg_class_init(ObjectClass *oc, void *data)
615 {
616 DeviceClass *dc = DEVICE_CLASS(oc);
617
618 dc->realize = idreg_realize;
619 }
620
621 static const TypeInfo idreg_info = {
622 .name = TYPE_MACIO_ID_REGISTER,
623 .parent = TYPE_SYS_BUS_DEVICE,
624 .instance_size = sizeof(IDRegState),
625 .class_init = idreg_class_init,
626 };
627
628 #define TYPE_TCX_AFX "tcx_afx"
629 OBJECT_DECLARE_SIMPLE_TYPE(AFXState, TCX_AFX)
630
631 struct AFXState {
632 SysBusDevice parent_obj;
633
634 MemoryRegion mem;
635 };
636
637 /* SS-5 TCX AFX register */
638 static void afx_init(hwaddr addr)
639 {
640 DeviceState *dev;
641 SysBusDevice *s;
642
643 dev = qdev_new(TYPE_TCX_AFX);
644 s = SYS_BUS_DEVICE(dev);
645 sysbus_realize_and_unref(s, &error_fatal);
646
647 sysbus_mmio_map(s, 0, addr);
648 }
649
650 static void afx_realize(DeviceState *ds, Error **errp)
651 {
652 AFXState *s = TCX_AFX(ds);
653 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
654 Error *local_err = NULL;
655
656 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4,
657 &local_err);
658 if (local_err) {
659 error_propagate(errp, local_err);
660 return;
661 }
662
663 vmstate_register_ram_global(&s->mem);
664 sysbus_init_mmio(dev, &s->mem);
665 }
666
667 static void afx_class_init(ObjectClass *oc, void *data)
668 {
669 DeviceClass *dc = DEVICE_CLASS(oc);
670
671 dc->realize = afx_realize;
672 }
673
674 static const TypeInfo afx_info = {
675 .name = TYPE_TCX_AFX,
676 .parent = TYPE_SYS_BUS_DEVICE,
677 .instance_size = sizeof(AFXState),
678 .class_init = afx_class_init,
679 };
680
681 #define TYPE_OPENPROM "openprom"
682 typedef struct PROMState PROMState;
683 DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM,
684 TYPE_OPENPROM)
685
686 struct PROMState {
687 SysBusDevice parent_obj;
688
689 MemoryRegion prom;
690 };
691
692 /* Boot PROM (OpenBIOS) */
693 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
694 {
695 hwaddr *base_addr = (hwaddr *)opaque;
696 return addr + *base_addr - PROM_VADDR;
697 }
698
699 static void prom_init(hwaddr addr, const char *bios_name)
700 {
701 DeviceState *dev;
702 SysBusDevice *s;
703 char *filename;
704 int ret;
705
706 dev = qdev_new(TYPE_OPENPROM);
707 s = SYS_BUS_DEVICE(dev);
708 sysbus_realize_and_unref(s, &error_fatal);
709
710 sysbus_mmio_map(s, 0, addr);
711
712 /* load boot prom */
713 if (bios_name == NULL) {
714 bios_name = PROM_FILENAME;
715 }
716 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
717 if (filename) {
718 ret = load_elf(filename, NULL,
719 translate_prom_address, &addr, NULL,
720 NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
721 if (ret < 0 || ret > PROM_SIZE_MAX) {
722 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
723 }
724 g_free(filename);
725 } else {
726 ret = -1;
727 }
728 if (ret < 0 || ret > PROM_SIZE_MAX) {
729 error_report("could not load prom '%s'", bios_name);
730 exit(1);
731 }
732 }
733
734 static void prom_realize(DeviceState *ds, Error **errp)
735 {
736 PROMState *s = OPENPROM(ds);
737 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
738 Error *local_err = NULL;
739
740 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom",
741 PROM_SIZE_MAX, &local_err);
742 if (local_err) {
743 error_propagate(errp, local_err);
744 return;
745 }
746
747 vmstate_register_ram_global(&s->prom);
748 memory_region_set_readonly(&s->prom, true);
749 sysbus_init_mmio(dev, &s->prom);
750 }
751
752 static Property prom_properties[] = {
753 {/* end of property list */},
754 };
755
756 static void prom_class_init(ObjectClass *klass, void *data)
757 {
758 DeviceClass *dc = DEVICE_CLASS(klass);
759
760 device_class_set_props(dc, prom_properties);
761 dc->realize = prom_realize;
762 }
763
764 static const TypeInfo prom_info = {
765 .name = TYPE_OPENPROM,
766 .parent = TYPE_SYS_BUS_DEVICE,
767 .instance_size = sizeof(PROMState),
768 .class_init = prom_class_init,
769 };
770
771 #define TYPE_SUN4M_MEMORY "memory"
772 typedef struct RamDevice RamDevice;
773 DECLARE_INSTANCE_CHECKER(RamDevice, SUN4M_RAM,
774 TYPE_SUN4M_MEMORY)
775
776 struct RamDevice {
777 SysBusDevice parent_obj;
778 HostMemoryBackend *memdev;
779 };
780
781 /* System RAM */
782 static void ram_realize(DeviceState *dev, Error **errp)
783 {
784 RamDevice *d = SUN4M_RAM(dev);
785 MemoryRegion *ram = host_memory_backend_get_memory(d->memdev);
786
787 sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram);
788 }
789
790 static void ram_initfn(Object *obj)
791 {
792 RamDevice *d = SUN4M_RAM(obj);
793 object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND,
794 (Object **)&d->memdev,
795 object_property_allow_set_link,
796 OBJ_PROP_LINK_STRONG);
797 object_property_set_description(obj, "memdev", "Set RAM backend"
798 "Valid value is ID of a hostmem backend");
799 }
800
801 static void ram_class_init(ObjectClass *klass, void *data)
802 {
803 DeviceClass *dc = DEVICE_CLASS(klass);
804
805 dc->realize = ram_realize;
806 }
807
808 static const TypeInfo ram_info = {
809 .name = TYPE_SUN4M_MEMORY,
810 .parent = TYPE_SYS_BUS_DEVICE,
811 .instance_size = sizeof(RamDevice),
812 .instance_init = ram_initfn,
813 .class_init = ram_class_init,
814 };
815
816 static void cpu_devinit(const char *cpu_type, unsigned int id,
817 uint64_t prom_addr, qemu_irq **cpu_irqs)
818 {
819 SPARCCPU *cpu;
820 CPUSPARCState *env;
821
822 cpu = SPARC_CPU(object_new(cpu_type));
823 env = &cpu->env;
824
825 cpu_sparc_set_id(env, id);
826 qemu_register_reset(sun4m_cpu_reset, cpu);
827 object_property_set_bool(OBJECT(cpu), "start-powered-off", id != 0,
828 &error_fatal);
829 qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal);
830 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
831 env->prom_addr = prom_addr;
832 }
833
834 static void dummy_fdc_tc(void *opaque, int irq, int level)
835 {
836 }
837
838 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
839 MachineState *machine)
840 {
841 DeviceState *slavio_intctl;
842 unsigned int i;
843 Nvram *nvram;
844 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
845 qemu_irq fdc_tc;
846 unsigned long kernel_size;
847 uint32_t initrd_size;
848 DriveInfo *fd[MAX_FD];
849 FWCfgState *fw_cfg;
850 DeviceState *dev;
851 SysBusDevice *s;
852 unsigned int smp_cpus = machine->smp.cpus;
853 unsigned int max_cpus = machine->smp.max_cpus;
854 Object *ram_memdev = object_resolve_path_type(machine->ram_memdev_id,
855 TYPE_MEMORY_BACKEND, NULL);
856 NICInfo *nd = &nd_table[0];
857
858 if (machine->ram_size > hwdef->max_mem) {
859 error_report("Too much memory for this machine: %" PRId64 ","
860 " maximum %" PRId64,
861 machine->ram_size / MiB, hwdef->max_mem / MiB);
862 exit(1);
863 }
864
865 /* init CPUs */
866 for(i = 0; i < smp_cpus; i++) {
867 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]);
868 }
869
870 for (i = smp_cpus; i < MAX_CPUS; i++)
871 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
872
873 /* Create and map RAM frontend */
874 dev = qdev_new("memory");
875 object_property_set_link(OBJECT(dev), "memdev", ram_memdev, &error_fatal);
876 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
877 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0);
878
879 /* models without ECC don't trap when missing ram is accessed */
880 if (!hwdef->ecc_base) {
881 empty_slot_init("ecc", machine->ram_size,
882 hwdef->max_mem - machine->ram_size);
883 }
884
885 prom_init(hwdef->slavio_base, bios_name);
886
887 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
888 hwdef->intctl_base + 0x10000ULL,
889 cpu_irqs);
890
891 for (i = 0; i < 32; i++) {
892 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
893 }
894 for (i = 0; i < MAX_CPUS; i++) {
895 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
896 }
897
898 if (hwdef->idreg_base) {
899 idreg_init(hwdef->idreg_base);
900 }
901
902 if (hwdef->afx_base) {
903 afx_init(hwdef->afx_base);
904 }
905
906 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]);
907
908 if (hwdef->iommu_pad_base) {
909 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
910 Software shouldn't use aliased addresses, neither should it crash
911 when does. Using empty_slot instead of aliasing can help with
912 debugging such accesses */
913 empty_slot_init("iommu.alias",
914 hwdef->iommu_pad_base, hwdef->iommu_pad_len);
915 }
916
917 qemu_check_nic_model(nd, TYPE_LANCE);
918 sparc32_dma_init(hwdef->dma_base,
919 hwdef->esp_base, slavio_irq[18],
920 hwdef->le_base, slavio_irq[16], nd);
921
922 if (graphic_depth != 8 && graphic_depth != 24) {
923 error_report("Unsupported depth: %d", graphic_depth);
924 exit (1);
925 }
926 if (vga_interface_type != VGA_NONE) {
927 if (vga_interface_type == VGA_CG3) {
928 if (graphic_depth != 8) {
929 error_report("Unsupported depth: %d", graphic_depth);
930 exit(1);
931 }
932
933 if (!(graphic_width == 1024 && graphic_height == 768) &&
934 !(graphic_width == 1152 && graphic_height == 900)) {
935 error_report("Unsupported resolution: %d x %d", graphic_width,
936 graphic_height);
937 exit(1);
938 }
939
940 /* sbus irq 5 */
941 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
942 graphic_width, graphic_height, graphic_depth);
943 } else {
944 /* If no display specified, default to TCX */
945 if (graphic_depth != 8 && graphic_depth != 24) {
946 error_report("Unsupported depth: %d", graphic_depth);
947 exit(1);
948 }
949
950 if (!(graphic_width == 1024 && graphic_height == 768)) {
951 error_report("Unsupported resolution: %d x %d",
952 graphic_width, graphic_height);
953 exit(1);
954 }
955
956 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
957 graphic_width, graphic_height, graphic_depth);
958 }
959 }
960
961 for (i = 0; i < MAX_VSIMMS; i++) {
962 /* vsimm registers probed by OBP */
963 if (hwdef->vsimm[i].reg_base) {
964 char *name = g_strdup_printf("vsimm[%d]", i);
965 empty_slot_init(name, hwdef->vsimm[i].reg_base, 0x2000);
966 g_free(name);
967 }
968 }
969
970 if (hwdef->sx_base) {
971 create_unimplemented_device("SUNW,sx", hwdef->sx_base, 0x2000);
972 }
973
974 dev = qdev_new("sysbus-m48t08");
975 qdev_prop_set_int32(dev, "base-year", 1968);
976 s = SYS_BUS_DEVICE(dev);
977 sysbus_realize_and_unref(s, &error_fatal);
978 sysbus_connect_irq(s, 0, slavio_irq[0]);
979 sysbus_mmio_map(s, 0, hwdef->nvram_base);
980 nvram = NVRAM(dev);
981
982 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
983
984 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
985 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
986 dev = qdev_new(TYPE_ESCC);
987 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics);
988 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
989 qdev_prop_set_uint32(dev, "it_shift", 1);
990 qdev_prop_set_chr(dev, "chrB", NULL);
991 qdev_prop_set_chr(dev, "chrA", NULL);
992 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
993 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
994 s = SYS_BUS_DEVICE(dev);
995 sysbus_realize_and_unref(s, &error_fatal);
996 sysbus_connect_irq(s, 0, slavio_irq[14]);
997 sysbus_connect_irq(s, 1, slavio_irq[14]);
998 sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
999
1000 dev = qdev_new(TYPE_ESCC);
1001 qdev_prop_set_uint32(dev, "disabled", 0);
1002 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
1003 qdev_prop_set_uint32(dev, "it_shift", 1);
1004 qdev_prop_set_chr(dev, "chrB", serial_hd(1));
1005 qdev_prop_set_chr(dev, "chrA", serial_hd(0));
1006 qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
1007 qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
1008
1009 s = SYS_BUS_DEVICE(dev);
1010 sysbus_realize_and_unref(s, &error_fatal);
1011 sysbus_connect_irq(s, 0, slavio_irq[15]);
1012 sysbus_connect_irq(s, 1, slavio_irq[15]);
1013 sysbus_mmio_map(s, 0, hwdef->serial_base);
1014
1015 if (hwdef->apc_base) {
1016 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
1017 }
1018
1019 if (hwdef->fd_base) {
1020 /* there is zero or one floppy drive */
1021 memset(fd, 0, sizeof(fd));
1022 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1023 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1024 &fdc_tc);
1025 } else {
1026 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
1027 }
1028
1029 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1030 slavio_irq[30], fdc_tc);
1031
1032 if (hwdef->cs_base) {
1033 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1034 slavio_irq[5]);
1035 }
1036
1037 if (hwdef->dbri_base) {
1038 /* ISDN chip with attached CS4215 audio codec */
1039 /* prom space */
1040 create_unimplemented_device("SUNW,DBRI.prom",
1041 hwdef->dbri_base + 0x1000, 0x30);
1042 /* reg space */
1043 create_unimplemented_device("SUNW,DBRI",
1044 hwdef->dbri_base + 0x10000, 0x100);
1045 }
1046
1047 if (hwdef->bpp_base) {
1048 /* parallel port */
1049 create_unimplemented_device("SUNW,bpp", hwdef->bpp_base, 0x20);
1050 }
1051
1052 initrd_size = 0;
1053 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1054 machine->initrd_filename,
1055 machine->ram_size, &initrd_size);
1056
1057 nvram_init(nvram, (uint8_t *)&nd->macaddr, machine->kernel_cmdline,
1058 machine->boot_order, machine->ram_size, kernel_size,
1059 graphic_width, graphic_height, graphic_depth,
1060 hwdef->nvram_machine_id, "Sun4m");
1061
1062 if (hwdef->ecc_base)
1063 ecc_init(hwdef->ecc_base, slavio_irq[28],
1064 hwdef->ecc_version);
1065
1066 dev = qdev_new(TYPE_FW_CFG_MEM);
1067 fw_cfg = FW_CFG(dev);
1068 qdev_prop_set_uint32(dev, "data_width", 1);
1069 qdev_prop_set_bit(dev, "dma_enabled", false);
1070 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
1071 OBJECT(fw_cfg));
1072 s = SYS_BUS_DEVICE(dev);
1073 sysbus_realize_and_unref(s, &error_fatal);
1074 sysbus_mmio_map(s, 0, CFG_ADDR);
1075 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
1076
1077 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1078 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1079 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
1080 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1081 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1082 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1083 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1084 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1085 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1086 if (machine->kernel_cmdline) {
1087 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1088 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1089 machine->kernel_cmdline);
1090 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1091 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1092 strlen(machine->kernel_cmdline) + 1);
1093 } else {
1094 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1095 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1096 }
1097 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1098 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1099 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1100 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1101 }
1102
1103 enum {
1104 ss5_id = 32,
1105 vger_id,
1106 lx_id,
1107 ss4_id,
1108 scls_id,
1109 sbook_id,
1110 ss10_id = 64,
1111 ss20_id,
1112 ss600mp_id,
1113 };
1114
1115 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1116 /* SS-5 */
1117 {
1118 .iommu_base = 0x10000000,
1119 .iommu_pad_base = 0x10004000,
1120 .iommu_pad_len = 0x0fffb000,
1121 .tcx_base = 0x50000000,
1122 .cs_base = 0x6c000000,
1123 .slavio_base = 0x70000000,
1124 .ms_kb_base = 0x71000000,
1125 .serial_base = 0x71100000,
1126 .nvram_base = 0x71200000,
1127 .fd_base = 0x71400000,
1128 .counter_base = 0x71d00000,
1129 .intctl_base = 0x71e00000,
1130 .idreg_base = 0x78000000,
1131 .dma_base = 0x78400000,
1132 .esp_base = 0x78800000,
1133 .le_base = 0x78c00000,
1134 .apc_base = 0x6a000000,
1135 .afx_base = 0x6e000000,
1136 .aux1_base = 0x71900000,
1137 .aux2_base = 0x71910000,
1138 .nvram_machine_id = 0x80,
1139 .machine_id = ss5_id,
1140 .iommu_version = 0x05000000,
1141 .max_mem = 0x10000000,
1142 },
1143 /* SS-10 */
1144 {
1145 .iommu_base = 0xfe0000000ULL,
1146 .tcx_base = 0xe20000000ULL,
1147 .slavio_base = 0xff0000000ULL,
1148 .ms_kb_base = 0xff1000000ULL,
1149 .serial_base = 0xff1100000ULL,
1150 .nvram_base = 0xff1200000ULL,
1151 .fd_base = 0xff1700000ULL,
1152 .counter_base = 0xff1300000ULL,
1153 .intctl_base = 0xff1400000ULL,
1154 .idreg_base = 0xef0000000ULL,
1155 .dma_base = 0xef0400000ULL,
1156 .esp_base = 0xef0800000ULL,
1157 .le_base = 0xef0c00000ULL,
1158 .apc_base = 0xefa000000ULL, // XXX should not exist
1159 .aux1_base = 0xff1800000ULL,
1160 .aux2_base = 0xff1a01000ULL,
1161 .ecc_base = 0xf00000000ULL,
1162 .ecc_version = 0x10000000, // version 0, implementation 1
1163 .nvram_machine_id = 0x72,
1164 .machine_id = ss10_id,
1165 .iommu_version = 0x03000000,
1166 .max_mem = 0xf00000000ULL,
1167 },
1168 /* SS-600MP */
1169 {
1170 .iommu_base = 0xfe0000000ULL,
1171 .tcx_base = 0xe20000000ULL,
1172 .slavio_base = 0xff0000000ULL,
1173 .ms_kb_base = 0xff1000000ULL,
1174 .serial_base = 0xff1100000ULL,
1175 .nvram_base = 0xff1200000ULL,
1176 .counter_base = 0xff1300000ULL,
1177 .intctl_base = 0xff1400000ULL,
1178 .dma_base = 0xef0081000ULL,
1179 .esp_base = 0xef0080000ULL,
1180 .le_base = 0xef0060000ULL,
1181 .apc_base = 0xefa000000ULL, // XXX should not exist
1182 .aux1_base = 0xff1800000ULL,
1183 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1184 .ecc_base = 0xf00000000ULL,
1185 .ecc_version = 0x00000000, // version 0, implementation 0
1186 .nvram_machine_id = 0x71,
1187 .machine_id = ss600mp_id,
1188 .iommu_version = 0x01000000,
1189 .max_mem = 0xf00000000ULL,
1190 },
1191 /* SS-20 */
1192 {
1193 .iommu_base = 0xfe0000000ULL,
1194 .tcx_base = 0xe20000000ULL,
1195 .slavio_base = 0xff0000000ULL,
1196 .ms_kb_base = 0xff1000000ULL,
1197 .serial_base = 0xff1100000ULL,
1198 .nvram_base = 0xff1200000ULL,
1199 .fd_base = 0xff1700000ULL,
1200 .counter_base = 0xff1300000ULL,
1201 .intctl_base = 0xff1400000ULL,
1202 .idreg_base = 0xef0000000ULL,
1203 .dma_base = 0xef0400000ULL,
1204 .esp_base = 0xef0800000ULL,
1205 .le_base = 0xef0c00000ULL,
1206 .bpp_base = 0xef4800000ULL,
1207 .apc_base = 0xefa000000ULL, // XXX should not exist
1208 .aux1_base = 0xff1800000ULL,
1209 .aux2_base = 0xff1a01000ULL,
1210 .dbri_base = 0xee0000000ULL,
1211 .sx_base = 0xf80000000ULL,
1212 .vsimm = {
1213 {
1214 .reg_base = 0x9c000000ULL,
1215 .vram_base = 0xfc000000ULL
1216 }, {
1217 .reg_base = 0x90000000ULL,
1218 .vram_base = 0xf0000000ULL
1219 }, {
1220 .reg_base = 0x94000000ULL
1221 }, {
1222 .reg_base = 0x98000000ULL
1223 }
1224 },
1225 .ecc_base = 0xf00000000ULL,
1226 .ecc_version = 0x20000000, // version 0, implementation 2
1227 .nvram_machine_id = 0x72,
1228 .machine_id = ss20_id,
1229 .iommu_version = 0x13000000,
1230 .max_mem = 0xf00000000ULL,
1231 },
1232 /* Voyager */
1233 {
1234 .iommu_base = 0x10000000,
1235 .tcx_base = 0x50000000,
1236 .slavio_base = 0x70000000,
1237 .ms_kb_base = 0x71000000,
1238 .serial_base = 0x71100000,
1239 .nvram_base = 0x71200000,
1240 .fd_base = 0x71400000,
1241 .counter_base = 0x71d00000,
1242 .intctl_base = 0x71e00000,
1243 .idreg_base = 0x78000000,
1244 .dma_base = 0x78400000,
1245 .esp_base = 0x78800000,
1246 .le_base = 0x78c00000,
1247 .apc_base = 0x71300000, // pmc
1248 .aux1_base = 0x71900000,
1249 .aux2_base = 0x71910000,
1250 .nvram_machine_id = 0x80,
1251 .machine_id = vger_id,
1252 .iommu_version = 0x05000000,
1253 .max_mem = 0x10000000,
1254 },
1255 /* LX */
1256 {
1257 .iommu_base = 0x10000000,
1258 .iommu_pad_base = 0x10004000,
1259 .iommu_pad_len = 0x0fffb000,
1260 .tcx_base = 0x50000000,
1261 .slavio_base = 0x70000000,
1262 .ms_kb_base = 0x71000000,
1263 .serial_base = 0x71100000,
1264 .nvram_base = 0x71200000,
1265 .fd_base = 0x71400000,
1266 .counter_base = 0x71d00000,
1267 .intctl_base = 0x71e00000,
1268 .idreg_base = 0x78000000,
1269 .dma_base = 0x78400000,
1270 .esp_base = 0x78800000,
1271 .le_base = 0x78c00000,
1272 .aux1_base = 0x71900000,
1273 .aux2_base = 0x71910000,
1274 .nvram_machine_id = 0x80,
1275 .machine_id = lx_id,
1276 .iommu_version = 0x04000000,
1277 .max_mem = 0x10000000,
1278 },
1279 /* SS-4 */
1280 {
1281 .iommu_base = 0x10000000,
1282 .tcx_base = 0x50000000,
1283 .cs_base = 0x6c000000,
1284 .slavio_base = 0x70000000,
1285 .ms_kb_base = 0x71000000,
1286 .serial_base = 0x71100000,
1287 .nvram_base = 0x71200000,
1288 .fd_base = 0x71400000,
1289 .counter_base = 0x71d00000,
1290 .intctl_base = 0x71e00000,
1291 .idreg_base = 0x78000000,
1292 .dma_base = 0x78400000,
1293 .esp_base = 0x78800000,
1294 .le_base = 0x78c00000,
1295 .apc_base = 0x6a000000,
1296 .aux1_base = 0x71900000,
1297 .aux2_base = 0x71910000,
1298 .nvram_machine_id = 0x80,
1299 .machine_id = ss4_id,
1300 .iommu_version = 0x05000000,
1301 .max_mem = 0x10000000,
1302 },
1303 /* SPARCClassic */
1304 {
1305 .iommu_base = 0x10000000,
1306 .tcx_base = 0x50000000,
1307 .slavio_base = 0x70000000,
1308 .ms_kb_base = 0x71000000,
1309 .serial_base = 0x71100000,
1310 .nvram_base = 0x71200000,
1311 .fd_base = 0x71400000,
1312 .counter_base = 0x71d00000,
1313 .intctl_base = 0x71e00000,
1314 .idreg_base = 0x78000000,
1315 .dma_base = 0x78400000,
1316 .esp_base = 0x78800000,
1317 .le_base = 0x78c00000,
1318 .apc_base = 0x6a000000,
1319 .aux1_base = 0x71900000,
1320 .aux2_base = 0x71910000,
1321 .nvram_machine_id = 0x80,
1322 .machine_id = scls_id,
1323 .iommu_version = 0x05000000,
1324 .max_mem = 0x10000000,
1325 },
1326 /* SPARCbook */
1327 {
1328 .iommu_base = 0x10000000,
1329 .tcx_base = 0x50000000, // XXX
1330 .slavio_base = 0x70000000,
1331 .ms_kb_base = 0x71000000,
1332 .serial_base = 0x71100000,
1333 .nvram_base = 0x71200000,
1334 .fd_base = 0x71400000,
1335 .counter_base = 0x71d00000,
1336 .intctl_base = 0x71e00000,
1337 .idreg_base = 0x78000000,
1338 .dma_base = 0x78400000,
1339 .esp_base = 0x78800000,
1340 .le_base = 0x78c00000,
1341 .apc_base = 0x6a000000,
1342 .aux1_base = 0x71900000,
1343 .aux2_base = 0x71910000,
1344 .nvram_machine_id = 0x80,
1345 .machine_id = sbook_id,
1346 .iommu_version = 0x05000000,
1347 .max_mem = 0x10000000,
1348 },
1349 };
1350
1351 /* SPARCstation 5 hardware initialisation */
1352 static void ss5_init(MachineState *machine)
1353 {
1354 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1355 }
1356
1357 /* SPARCstation 10 hardware initialisation */
1358 static void ss10_init(MachineState *machine)
1359 {
1360 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1361 }
1362
1363 /* SPARCserver 600MP hardware initialisation */
1364 static void ss600mp_init(MachineState *machine)
1365 {
1366 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1367 }
1368
1369 /* SPARCstation 20 hardware initialisation */
1370 static void ss20_init(MachineState *machine)
1371 {
1372 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1373 }
1374
1375 /* SPARCstation Voyager hardware initialisation */
1376 static void vger_init(MachineState *machine)
1377 {
1378 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1379 }
1380
1381 /* SPARCstation LX hardware initialisation */
1382 static void ss_lx_init(MachineState *machine)
1383 {
1384 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1385 }
1386
1387 /* SPARCstation 4 hardware initialisation */
1388 static void ss4_init(MachineState *machine)
1389 {
1390 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1391 }
1392
1393 /* SPARCClassic hardware initialisation */
1394 static void scls_init(MachineState *machine)
1395 {
1396 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1397 }
1398
1399 /* SPARCbook hardware initialisation */
1400 static void sbook_init(MachineState *machine)
1401 {
1402 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1403 }
1404
1405 static void ss5_class_init(ObjectClass *oc, void *data)
1406 {
1407 MachineClass *mc = MACHINE_CLASS(oc);
1408
1409 mc->desc = "Sun4m platform, SPARCstation 5";
1410 mc->init = ss5_init;
1411 mc->block_default_type = IF_SCSI;
1412 mc->is_default = true;
1413 mc->default_boot_order = "c";
1414 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1415 mc->default_display = "tcx";
1416 mc->default_ram_id = "sun4m.ram";
1417 }
1418
1419 static const TypeInfo ss5_type = {
1420 .name = MACHINE_TYPE_NAME("SS-5"),
1421 .parent = TYPE_MACHINE,
1422 .class_init = ss5_class_init,
1423 };
1424
1425 static void ss10_class_init(ObjectClass *oc, void *data)
1426 {
1427 MachineClass *mc = MACHINE_CLASS(oc);
1428
1429 mc->desc = "Sun4m platform, SPARCstation 10";
1430 mc->init = ss10_init;
1431 mc->block_default_type = IF_SCSI;
1432 mc->max_cpus = 4;
1433 mc->default_boot_order = "c";
1434 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1435 mc->default_display = "tcx";
1436 mc->default_ram_id = "sun4m.ram";
1437 }
1438
1439 static const TypeInfo ss10_type = {
1440 .name = MACHINE_TYPE_NAME("SS-10"),
1441 .parent = TYPE_MACHINE,
1442 .class_init = ss10_class_init,
1443 };
1444
1445 static void ss600mp_class_init(ObjectClass *oc, void *data)
1446 {
1447 MachineClass *mc = MACHINE_CLASS(oc);
1448
1449 mc->desc = "Sun4m platform, SPARCserver 600MP";
1450 mc->init = ss600mp_init;
1451 mc->block_default_type = IF_SCSI;
1452 mc->max_cpus = 4;
1453 mc->default_boot_order = "c";
1454 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1455 mc->default_display = "tcx";
1456 mc->default_ram_id = "sun4m.ram";
1457 }
1458
1459 static const TypeInfo ss600mp_type = {
1460 .name = MACHINE_TYPE_NAME("SS-600MP"),
1461 .parent = TYPE_MACHINE,
1462 .class_init = ss600mp_class_init,
1463 };
1464
1465 static void ss20_class_init(ObjectClass *oc, void *data)
1466 {
1467 MachineClass *mc = MACHINE_CLASS(oc);
1468
1469 mc->desc = "Sun4m platform, SPARCstation 20";
1470 mc->init = ss20_init;
1471 mc->block_default_type = IF_SCSI;
1472 mc->max_cpus = 4;
1473 mc->default_boot_order = "c";
1474 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1475 mc->default_display = "tcx";
1476 mc->default_ram_id = "sun4m.ram";
1477 }
1478
1479 static const TypeInfo ss20_type = {
1480 .name = MACHINE_TYPE_NAME("SS-20"),
1481 .parent = TYPE_MACHINE,
1482 .class_init = ss20_class_init,
1483 };
1484
1485 static void voyager_class_init(ObjectClass *oc, void *data)
1486 {
1487 MachineClass *mc = MACHINE_CLASS(oc);
1488
1489 mc->desc = "Sun4m platform, SPARCstation Voyager";
1490 mc->init = vger_init;
1491 mc->block_default_type = IF_SCSI;
1492 mc->default_boot_order = "c";
1493 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1494 mc->default_display = "tcx";
1495 mc->default_ram_id = "sun4m.ram";
1496 }
1497
1498 static const TypeInfo voyager_type = {
1499 .name = MACHINE_TYPE_NAME("Voyager"),
1500 .parent = TYPE_MACHINE,
1501 .class_init = voyager_class_init,
1502 };
1503
1504 static void ss_lx_class_init(ObjectClass *oc, void *data)
1505 {
1506 MachineClass *mc = MACHINE_CLASS(oc);
1507
1508 mc->desc = "Sun4m platform, SPARCstation LX";
1509 mc->init = ss_lx_init;
1510 mc->block_default_type = IF_SCSI;
1511 mc->default_boot_order = "c";
1512 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1513 mc->default_display = "tcx";
1514 mc->default_ram_id = "sun4m.ram";
1515 }
1516
1517 static const TypeInfo ss_lx_type = {
1518 .name = MACHINE_TYPE_NAME("LX"),
1519 .parent = TYPE_MACHINE,
1520 .class_init = ss_lx_class_init,
1521 };
1522
1523 static void ss4_class_init(ObjectClass *oc, void *data)
1524 {
1525 MachineClass *mc = MACHINE_CLASS(oc);
1526
1527 mc->desc = "Sun4m platform, SPARCstation 4";
1528 mc->init = ss4_init;
1529 mc->block_default_type = IF_SCSI;
1530 mc->default_boot_order = "c";
1531 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1532 mc->default_display = "tcx";
1533 mc->default_ram_id = "sun4m.ram";
1534 }
1535
1536 static const TypeInfo ss4_type = {
1537 .name = MACHINE_TYPE_NAME("SS-4"),
1538 .parent = TYPE_MACHINE,
1539 .class_init = ss4_class_init,
1540 };
1541
1542 static void scls_class_init(ObjectClass *oc, void *data)
1543 {
1544 MachineClass *mc = MACHINE_CLASS(oc);
1545
1546 mc->desc = "Sun4m platform, SPARCClassic";
1547 mc->init = scls_init;
1548 mc->block_default_type = IF_SCSI;
1549 mc->default_boot_order = "c";
1550 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1551 mc->default_display = "tcx";
1552 mc->default_ram_id = "sun4m.ram";
1553 }
1554
1555 static const TypeInfo scls_type = {
1556 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1557 .parent = TYPE_MACHINE,
1558 .class_init = scls_class_init,
1559 };
1560
1561 static void sbook_class_init(ObjectClass *oc, void *data)
1562 {
1563 MachineClass *mc = MACHINE_CLASS(oc);
1564
1565 mc->desc = "Sun4m platform, SPARCbook";
1566 mc->init = sbook_init;
1567 mc->block_default_type = IF_SCSI;
1568 mc->default_boot_order = "c";
1569 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1570 mc->default_display = "tcx";
1571 mc->default_ram_id = "sun4m.ram";
1572 }
1573
1574 static const TypeInfo sbook_type = {
1575 .name = MACHINE_TYPE_NAME("SPARCbook"),
1576 .parent = TYPE_MACHINE,
1577 .class_init = sbook_class_init,
1578 };
1579
1580 static void sun4m_register_types(void)
1581 {
1582 type_register_static(&idreg_info);
1583 type_register_static(&afx_info);
1584 type_register_static(&prom_info);
1585 type_register_static(&ram_info);
1586
1587 type_register_static(&ss5_type);
1588 type_register_static(&ss10_type);
1589 type_register_static(&ss600mp_type);
1590 type_register_static(&ss20_type);
1591 type_register_static(&voyager_type);
1592 type_register_static(&ss_lx_type);
1593 type_register_static(&ss4_type);
1594 type_register_static(&scls_type);
1595 type_register_static(&sbook_type);
1596 }
1597
1598 type_init(sun4m_register_types)
AR7 emulation for QEMU