hw/ppc/ppc405_boards.c

   1 /*
   2  * QEMU PowerPC 405 evaluation boards emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/units.h"
  27 #include "qapi/error.h"
  28 #include "qemu-common.h"
  29 #include "cpu.h"
  30 #include "hw/ppc/ppc.h"
  31 #include "hw/qdev-properties.h"
  32 #include "hw/sysbus.h"
  33 #include "ppc405.h"
  34 #include "hw/rtc/m48t59.h"
  35 #include "hw/block/flash.h"
  36 #include "sysemu/sysemu.h"
  37 #include "sysemu/qtest.h"
  38 #include "sysemu/reset.h"
  39 #include "sysemu/block-backend.h"
  40 #include "hw/boards.h"
  41 #include "qemu/log.h"
  42 #include "qemu/error-report.h"
  43 #include "hw/loader.h"
  44 #include "exec/address-spaces.h"
  45 #include "qemu/cutils.h"
  46
  47 #define BIOS_FILENAME "ppc405_rom.bin"
  48 #define BIOS_SIZE (2 * MiB)
  49
  50 #define KERNEL_LOAD_ADDR 0x00000000
  51 #define INITRD_LOAD_ADDR 0x01800000
  52
  53 #define USE_FLASH_BIOS
  54
  55 /*****************************************************************************/
  56 /* PPC405EP reference board (IBM) */
  57 /* Standalone board with:
  58  * - PowerPC 405EP CPU
  59  * - SDRAM (0x00000000)
  60  * - Flash (0xFFF80000)
  61  * - SRAM  (0xFFF00000)
  62  * - NVRAM (0xF0000000)
  63  * - FPGA  (0xF0300000)
  64  */
  65 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
  66 struct ref405ep_fpga_t {
  67     uint8_t reg0;
  68     uint8_t reg1;
  69 };
  70
  71 static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
  72 {
  73     ref405ep_fpga_t *fpga;
  74     uint32_t ret;
  75
  76     fpga = opaque;
  77     switch (addr) {
  78     case 0x0:
  79         ret = fpga->reg0;
  80         break;
  81     case 0x1:
  82         ret = fpga->reg1;
  83         break;
  84     default:
  85         ret = 0;
  86         break;
  87     }
  88
  89     return ret;
  90 }
  91
  92 static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
  93                                  unsigned size)
  94 {
  95     ref405ep_fpga_t *fpga;
  96
  97     fpga = opaque;
  98     switch (addr) {
  99     case 0x0:
 100         /* Read only */
 101         break;
 102     case 0x1:
 103         fpga->reg1 = value;
 104         break;
 105     default:
 106         break;
 107     }
 108 }
 109
 110 static const MemoryRegionOps ref405ep_fpga_ops = {
 111     .read = ref405ep_fpga_readb,
 112     .write = ref405ep_fpga_writeb,
 113     .impl.min_access_size = 1,
 114     .impl.max_access_size = 1,
 115     .valid.min_access_size = 1,
 116     .valid.max_access_size = 4,
 117     .endianness = DEVICE_BIG_ENDIAN,
 118 };
 119
 120 static void ref405ep_fpga_reset (void *opaque)
 121 {
 122     ref405ep_fpga_t *fpga;
 123
 124     fpga = opaque;
 125     fpga->reg0 = 0x00;
 126     fpga->reg1 = 0x0F;
 127 }
 128
 129 static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
 130 {
 131     ref405ep_fpga_t *fpga;
 132     MemoryRegion *fpga_memory = g_new(MemoryRegion, 1);
 133
 134     fpga = g_malloc0(sizeof(ref405ep_fpga_t));
 135     memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga,
 136                           "fpga", 0x00000100);
 137     memory_region_add_subregion(sysmem, base, fpga_memory);
 138     qemu_register_reset(&ref405ep_fpga_reset, fpga);
 139 }
 140
 141 static void ref405ep_init(MachineState *machine)
 142 {
 143     MachineClass *mc = MACHINE_GET_CLASS(machine);
 144     const char *kernel_filename = machine->kernel_filename;
 145     const char *kernel_cmdline = machine->kernel_cmdline;
 146     const char *initrd_filename = machine->initrd_filename;
 147     char *filename;
 148     ppc4xx_bd_info_t bd;
 149     CPUPPCState *env;
 150     DeviceState *dev;
 151     SysBusDevice *s;
 152     qemu_irq *pic;
 153     MemoryRegion *bios;
 154     MemoryRegion *sram = g_new(MemoryRegion, 1);
 155     ram_addr_t bdloc;
 156     MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
 157     hwaddr ram_bases[2], ram_sizes[2];
 158     target_ulong sram_size;
 159     long bios_size;
 160     //int phy_addr = 0;
 161     //static int phy_addr = 1;
 162     target_ulong kernel_base, initrd_base;
 163     long kernel_size, initrd_size;
 164     int linux_boot;
 165     int len;
 166     DriveInfo *dinfo;
 167     MemoryRegion *sysmem = get_system_memory();
 168
 169     if (machine->ram_size != mc->default_ram_size) {
 170         char *sz = size_to_str(mc->default_ram_size);
 171         error_report("Invalid RAM size, should be %s", sz);
 172         g_free(sz);
 173         exit(EXIT_FAILURE);
 174     }
 175
 176     /* XXX: fix this */
 177     memory_region_init_alias(&ram_memories[0], NULL, "ef405ep.ram.alias",
 178                              machine->ram, 0, machine->ram_size);
 179     ram_bases[0] = 0;
 180     ram_sizes[0] = machine->ram_size;
 181     memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
 182     ram_bases[1] = 0x00000000;
 183     ram_sizes[1] = 0x00000000;
 184     env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
 185                         33333333, &pic, kernel_filename == NULL ? 0 : 1);
 186     /* allocate SRAM */
 187     sram_size = 512 * KiB;
 188     memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size,
 189                            &error_fatal);
 190     memory_region_add_subregion(sysmem, 0xFFF00000, sram);
 191     /* allocate and load BIOS */
 192 #ifdef USE_FLASH_BIOS
 193     dinfo = drive_get(IF_PFLASH, 0, 0);
 194     if (dinfo) {
 195         bios_size = 8 * MiB;
 196         pflash_cfi02_register((uint32_t)(-bios_size),
 197                               "ef405ep.bios", bios_size,
 198                               blk_by_legacy_dinfo(dinfo),
 199                               64 * KiB, 1,
 200                               2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 201                               1);
 202     } else
 203 #endif
 204     {
 205         bios = g_new(MemoryRegion, 1);
 206         memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE,
 207                                &error_fatal);
 208
 209         if (bios_name == NULL)
 210             bios_name = BIOS_FILENAME;
 211         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 212         if (filename) {
 213             bios_size = load_image_size(filename,
 214                                         memory_region_get_ram_ptr(bios),
 215                                         BIOS_SIZE);
 216             g_free(filename);
 217             if (bios_size < 0) {
 218                 error_report("Could not load PowerPC BIOS '%s'", bios_name);
 219                 exit(1);
 220             }
 221             bios_size = (bios_size + 0xfff) & ~0xfff;
 222             memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
 223         } else if (!qtest_enabled() || kernel_filename != NULL) {
 224             error_report("Could not load PowerPC BIOS '%s'", bios_name);
 225             exit(1);
 226         } else {
 227             /* Avoid an uninitialized variable warning */
 228             bios_size = -1;
 229         }
 230     }
 231     /* Register FPGA */
 232     ref405ep_fpga_init(sysmem, 0xF0300000);
 233     /* Register NVRAM */
 234     dev = qdev_new("sysbus-m48t08");
 235     qdev_prop_set_int32(dev, "base-year", 1968);
 236     s = SYS_BUS_DEVICE(dev);
 237     sysbus_realize_and_unref(s, &error_fatal);
 238     sysbus_mmio_map(s, 0, 0xF0000000);
 239     /* Load kernel */
 240     linux_boot = (kernel_filename != NULL);
 241     if (linux_boot) {
 242         memset(&bd, 0, sizeof(bd));
 243         bd.bi_memstart = 0x00000000;
 244         bd.bi_memsize = machine->ram_size;
 245         bd.bi_flashstart = -bios_size;
 246         bd.bi_flashsize = -bios_size;
 247         bd.bi_flashoffset = 0;
 248         bd.bi_sramstart = 0xFFF00000;
 249         bd.bi_sramsize = sram_size;
 250         bd.bi_bootflags = 0;
 251         bd.bi_intfreq = 133333333;
 252         bd.bi_busfreq = 33333333;
 253         bd.bi_baudrate = 115200;
 254         bd.bi_s_version[0] = 'Q';
 255         bd.bi_s_version[1] = 'M';
 256         bd.bi_s_version[2] = 'U';
 257         bd.bi_s_version[3] = '\0';
 258         bd.bi_r_version[0] = 'Q';
 259         bd.bi_r_version[1] = 'E';
 260         bd.bi_r_version[2] = 'M';
 261         bd.bi_r_version[3] = 'U';
 262         bd.bi_r_version[4] = '\0';
 263         bd.bi_procfreq = 133333333;
 264         bd.bi_plb_busfreq = 33333333;
 265         bd.bi_pci_busfreq = 33333333;
 266         bd.bi_opbfreq = 33333333;
 267         bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
 268         env->gpr[3] = bdloc;
 269         kernel_base = KERNEL_LOAD_ADDR;
 270         /* now we can load the kernel */
 271         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 272                                           machine->ram_size - kernel_base);
 273         if (kernel_size < 0) {
 274             error_report("could not load kernel '%s'", kernel_filename);
 275             exit(1);
 276         }
 277         printf("Load kernel size %ld at " TARGET_FMT_lx,
 278                kernel_size, kernel_base);
 279         /* load initrd */
 280         if (initrd_filename) {
 281             initrd_base = INITRD_LOAD_ADDR;
 282             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 283                                               machine->ram_size - initrd_base);
 284             if (initrd_size < 0) {
 285                 error_report("could not load initial ram disk '%s'",
 286                              initrd_filename);
 287                 exit(1);
 288             }
 289         } else {
 290             initrd_base = 0;
 291             initrd_size = 0;
 292         }
 293         env->gpr[4] = initrd_base;
 294         env->gpr[5] = initrd_size;
 295         if (kernel_cmdline != NULL) {
 296             len = strlen(kernel_cmdline);
 297             bdloc -= ((len + 255) & ~255);
 298             cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1);
 299             env->gpr[6] = bdloc;
 300             env->gpr[7] = bdloc + len;
 301         } else {
 302             env->gpr[6] = 0;
 303             env->gpr[7] = 0;
 304         }
 305         env->nip = KERNEL_LOAD_ADDR;
 306     } else {
 307         kernel_base = 0;
 308         kernel_size = 0;
 309         initrd_base = 0;
 310         initrd_size = 0;
 311         bdloc = 0;
 312     }
 313 }
 314
 315 static void ref405ep_class_init(ObjectClass *oc, void *data)
 316 {
 317     MachineClass *mc = MACHINE_CLASS(oc);
 318
 319     mc->desc = "ref405ep";
 320     mc->init = ref405ep_init;
 321     mc->default_ram_size = 0x08000000;
 322     mc->default_ram_id = "ef405ep.ram";
 323 }
 324
 325 static const TypeInfo ref405ep_type = {
 326     .name = MACHINE_TYPE_NAME("ref405ep"),
 327     .parent = TYPE_MACHINE,
 328     .class_init = ref405ep_class_init,
 329 };
 330
 331 /*****************************************************************************/
 332 /* AMCC Taihu evaluation board */
 333 /* - PowerPC 405EP processor
 334  * - SDRAM               128 MB at 0x00000000
 335  * - Boot flash          2 MB   at 0xFFE00000
 336  * - Application flash   32 MB  at 0xFC000000
 337  * - 2 serial ports
 338  * - 2 ethernet PHY
 339  * - 1 USB 1.1 device    0x50000000
 340  * - 1 LCD display       0x50100000
 341  * - 1 CPLD              0x50100000
 342  * - 1 I2C EEPROM
 343  * - 1 I2C thermal sensor
 344  * - a set of LEDs
 345  * - bit-bang SPI port using GPIOs
 346  * - 1 EBC interface connector 0 0x50200000
 347  * - 1 cardbus controller + expansion slot.
 348  * - 1 PCI expansion slot.
 349  */
 350 typedef struct taihu_cpld_t taihu_cpld_t;
 351 struct taihu_cpld_t {
 352     uint8_t reg0;
 353     uint8_t reg1;
 354 };
 355
 356 static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size)
 357 {
 358     taihu_cpld_t *cpld;
 359     uint32_t ret;
 360
 361     cpld = opaque;
 362     switch (addr) {
 363     case 0x0:
 364         ret = cpld->reg0;
 365         break;
 366     case 0x1:
 367         ret = cpld->reg1;
 368         break;
 369     default:
 370         ret = 0;
 371         break;
 372     }
 373
 374     return ret;
 375 }
 376
 377 static void taihu_cpld_write(void *opaque, hwaddr addr,
 378                              uint64_t value, unsigned size)
 379 {
 380     taihu_cpld_t *cpld;
 381
 382     cpld = opaque;
 383     switch (addr) {
 384     case 0x0:
 385         /* Read only */
 386         break;
 387     case 0x1:
 388         cpld->reg1 = value;
 389         break;
 390     default:
 391         break;
 392     }
 393 }
 394
 395 static const MemoryRegionOps taihu_cpld_ops = {
 396     .read = taihu_cpld_read,
 397     .write = taihu_cpld_write,
 398     .impl = {
 399         .min_access_size = 1,
 400         .max_access_size = 1,
 401     },
 402     .endianness = DEVICE_NATIVE_ENDIAN,
 403 };
 404
 405 static void taihu_cpld_reset (void *opaque)
 406 {
 407     taihu_cpld_t *cpld;
 408
 409     cpld = opaque;
 410     cpld->reg0 = 0x01;
 411     cpld->reg1 = 0x80;
 412 }
 413
 414 static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base)
 415 {
 416     taihu_cpld_t *cpld;
 417     MemoryRegion *cpld_memory = g_new(MemoryRegion, 1);
 418
 419     cpld = g_malloc0(sizeof(taihu_cpld_t));
 420     memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100);
 421     memory_region_add_subregion(sysmem, base, cpld_memory);
 422     qemu_register_reset(&taihu_cpld_reset, cpld);
 423 }
 424
 425 static void taihu_405ep_init(MachineState *machine)
 426 {
 427     MachineClass *mc = MACHINE_GET_CLASS(machine);
 428     const char *kernel_filename = machine->kernel_filename;
 429     const char *initrd_filename = machine->initrd_filename;
 430     char *filename;
 431     qemu_irq *pic;
 432     MemoryRegion *sysmem = get_system_memory();
 433     MemoryRegion *bios;
 434     MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
 435     hwaddr ram_bases[2], ram_sizes[2];
 436     long bios_size;
 437     target_ulong kernel_base, initrd_base;
 438     long kernel_size, initrd_size;
 439     int linux_boot;
 440     int fl_idx;
 441     DriveInfo *dinfo;
 442
 443     if (machine->ram_size != mc->default_ram_size) {
 444         char *sz = size_to_str(mc->default_ram_size);
 445         error_report("Invalid RAM size, should be %s", sz);
 446         g_free(sz);
 447         exit(EXIT_FAILURE);
 448     }
 449
 450     ram_bases[0] = 0;
 451     ram_sizes[0] = 0x04000000;
 452     memory_region_init_alias(&ram_memories[0], NULL,
 453                              "taihu_405ep.ram-0", machine->ram, ram_bases[0],
 454                              ram_sizes[0]);
 455     ram_bases[1] = 0x04000000;
 456     ram_sizes[1] = 0x04000000;
 457     memory_region_init_alias(&ram_memories[1], NULL,
 458                              "taihu_405ep.ram-1", machine->ram, ram_bases[1],
 459                              ram_sizes[1]);
 460     ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
 461                   33333333, &pic, kernel_filename == NULL ? 0 : 1);
 462     /* allocate and load BIOS */
 463     fl_idx = 0;
 464 #if defined(USE_FLASH_BIOS)
 465     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 466     if (dinfo) {
 467         bios_size = 2 * MiB;
 468         pflash_cfi02_register(0xFFE00000,
 469                               "taihu_405ep.bios", bios_size,
 470                               blk_by_legacy_dinfo(dinfo),
 471                               64 * KiB, 1,
 472                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 473                               1);
 474         fl_idx++;
 475     } else
 476 #endif
 477     {
 478         if (bios_name == NULL)
 479             bios_name = BIOS_FILENAME;
 480         bios = g_new(MemoryRegion, 1);
 481         memory_region_init_rom(bios, NULL, "taihu_405ep.bios", BIOS_SIZE,
 482                                &error_fatal);
 483         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 484         if (filename) {
 485             bios_size = load_image_size(filename,
 486                                         memory_region_get_ram_ptr(bios),
 487                                         BIOS_SIZE);
 488             g_free(filename);
 489             if (bios_size < 0) {
 490                 error_report("Could not load PowerPC BIOS '%s'", bios_name);
 491                 exit(1);
 492             }
 493             bios_size = (bios_size + 0xfff) & ~0xfff;
 494             memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
 495         } else if (!qtest_enabled()) {
 496             error_report("Could not load PowerPC BIOS '%s'", bios_name);
 497             exit(1);
 498         }
 499     }
 500     /* Register Linux flash */
 501     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 502     if (dinfo) {
 503         bios_size = 32 * MiB;
 504         pflash_cfi02_register(0xfc000000, "taihu_405ep.flash", bios_size,
 505                               blk_by_legacy_dinfo(dinfo),
 506                               64 * KiB, 1,
 507                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 508                               1);
 509         fl_idx++;
 510     }
 511     /* Register CLPD & LCD display */
 512     taihu_cpld_init(sysmem, 0x50100000);
 513     /* Load kernel */
 514     linux_boot = (kernel_filename != NULL);
 515     if (linux_boot) {
 516         kernel_base = KERNEL_LOAD_ADDR;
 517         /* now we can load the kernel */
 518         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 519                                           machine->ram_size - kernel_base);
 520         if (kernel_size < 0) {
 521             error_report("could not load kernel '%s'", kernel_filename);
 522             exit(1);
 523         }
 524         /* load initrd */
 525         if (initrd_filename) {
 526             initrd_base = INITRD_LOAD_ADDR;
 527             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 528                                               machine->ram_size - initrd_base);
 529             if (initrd_size < 0) {
 530                 error_report("could not load initial ram disk '%s'",
 531                              initrd_filename);
 532                 exit(1);
 533             }
 534         } else {
 535             initrd_base = 0;
 536             initrd_size = 0;
 537         }
 538     } else {
 539         kernel_base = 0;
 540         kernel_size = 0;
 541         initrd_base = 0;
 542         initrd_size = 0;
 543     }
 544 }
 545
 546 static void taihu_class_init(ObjectClass *oc, void *data)
 547 {
 548     MachineClass *mc = MACHINE_CLASS(oc);
 549
 550     mc->desc = "taihu";
 551     mc->init = taihu_405ep_init;
 552     mc->default_ram_size = 0x08000000;
 553     mc->default_ram_id = "taihu_405ep.ram";
 554 }
 555
 556 static const TypeInfo taihu_type = {
 557     .name = MACHINE_TYPE_NAME("taihu"),
 558     .parent = TYPE_MACHINE,
 559     .class_init = taihu_class_init,
 560 };
 561
 562 static void ppc405_machine_init(void)
 563 {
 564     type_register_static(&ref405ep_type);
 565     type_register_static(&taihu_type);
 566 }
 567
 568 type_init(ppc405_machine_init)