include/exec/cpu-defs.h

   1 /*
   2  * common defines for all CPUs
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_DEFS_H
  20 #define CPU_DEFS_H
  21
  22 #ifndef NEED_CPU_H
  23 #error cpu.h included from common code
  24 #endif
  25
  26 #include "qemu/host-utils.h"
  27 #include "qemu/thread.h"
  28 #include "qemu/queue.h"
  29 #ifdef CONFIG_TCG
  30 #include "tcg-target.h"
  31 #endif
  32 #ifndef CONFIG_USER_ONLY
  33 #include "exec/hwaddr.h"
  34 #endif
  35 #include "exec/memattrs.h"
  36
  37 #ifndef TARGET_LONG_BITS
  38 #error TARGET_LONG_BITS must be defined before including this header
  39 #endif
  40
  41 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
  42
  43 /* target_ulong is the type of a virtual address */
  44 #if TARGET_LONG_SIZE == 4
  45 typedef int32_t target_long;
  46 typedef uint32_t target_ulong;
  47 #define TARGET_FMT_lx "%08x"
  48 #define TARGET_FMT_ld "%d"
  49 #define TARGET_FMT_lu "%u"
  50 #elif TARGET_LONG_SIZE == 8
  51 typedef int64_t target_long;
  52 typedef uint64_t target_ulong;
  53 #define TARGET_FMT_lx "%016" PRIx64
  54 #define TARGET_FMT_ld "%" PRId64
  55 #define TARGET_FMT_lu "%" PRIu64
  56 #else
  57 #error TARGET_LONG_SIZE undefined
  58 #endif
  59
  60 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
  61 /* use a fully associative victim tlb of 8 entries */
  62 #define CPU_VTLB_SIZE 8
  63
  64 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
  65 #define CPU_TLB_ENTRY_BITS 4
  66 #else
  67 #define CPU_TLB_ENTRY_BITS 5
  68 #endif
  69
  70 #if TCG_TARGET_IMPLEMENTS_DYN_TLB
  71 #define CPU_TLB_DYN_MIN_BITS 6
  72 #define CPU_TLB_DYN_DEFAULT_BITS 8
  73
  74
  75 # if HOST_LONG_BITS == 32
  76 /* Make sure we do not require a double-word shift for the TLB load */
  77 #  define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS)
  78 # else /* HOST_LONG_BITS == 64 */
  79 /*
  80  * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) ==
  81  * 2**34 == 16G of address space. This is roughly what one would expect a
  82  * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel
  83  * Skylake's Level-2 STLB has 16 1G entries.
  84  * Also, make sure we do not size the TLB past the guest's address space.
  85  */
  86 #  define CPU_TLB_DYN_MAX_BITS                                  \
  87     MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
  88 # endif
  89
  90 #else /* !TCG_TARGET_IMPLEMENTS_DYN_TLB */
  91
  92 /* TCG_TARGET_TLB_DISPLACEMENT_BITS is used in CPU_TLB_BITS to ensure that
  93  * the TLB is not unnecessarily small, but still small enough for the
  94  * TLB lookup instruction sequence used by the TCG target.
  95  *
  96  * TCG will have to generate an operand as large as the distance between
  97  * env and the tlb_table[NB_MMU_MODES - 1][0].addend.  For simplicity,
  98  * the TCG targets just round everything up to the next power of two, and
  99  * count bits.  This works because: 1) the size of each TLB is a largish
 100  * power of two, 2) and because the limit of the displacement is really close
 101  * to a power of two, 3) the offset of tlb_table[0][0] inside env is smaller
 102  * than the size of a TLB.
 103  *
 104  * For example, the maximum displacement 0xFFF0 on PPC and MIPS, but TCG
 105  * just says "the displacement is 16 bits".  TCG_TARGET_TLB_DISPLACEMENT_BITS
 106  * then ensures that tlb_table at least 0x8000 bytes large ("not unnecessarily
 107  * small": 2^15).  The operand then will come up smaller than 0xFFF0 without
 108  * any particular care, because the TLB for a single MMU mode is larger than
 109  * 0x10000-0xFFF0=16 bytes.  In the end, the maximum value of the operand
 110  * could be something like 0xC000 (the offset of the last TLB table) plus
 111  * 0x18 (the offset of the addend field in each TLB entry) plus the offset
 112  * of tlb_table inside env (which is non-trivial but not huge).
 113  */
 114 #define CPU_TLB_BITS                                             \
 115     MIN(8,                                                       \
 116         TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS -  \
 117         (NB_MMU_MODES <= 1 ? 0 :                                 \
 118          NB_MMU_MODES <= 2 ? 1 :                                 \
 119          NB_MMU_MODES <= 4 ? 2 :                                 \
 120          NB_MMU_MODES <= 8 ? 3 : 4))
 121
 122 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
 123 #endif /* TCG_TARGET_IMPLEMENTS_DYN_TLB */
 124
 125 typedef struct CPUTLBEntry {
 126     /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
 127        bit TARGET_PAGE_BITS-1..4  : Nonzero for accesses that should not
 128                                     go directly to ram.
 129        bit 3                      : indicates that the entry is invalid
 130        bit 2..0                   : zero
 131     */
 132     union {
 133         struct {
 134             target_ulong addr_read;
 135             target_ulong addr_write;
 136             target_ulong addr_code;
 137             /* Addend to virtual address to get host address.  IO accesses
 138                use the corresponding iotlb value.  */
 139             uintptr_t addend;
 140         };
 141         /* padding to get a power of two size */
 142         uint8_t dummy[1 << CPU_TLB_ENTRY_BITS];
 143     };
 144 } CPUTLBEntry;
 145
 146 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
 147
 148 /* The IOTLB is not accessed directly inline by generated TCG code,
 149  * so the CPUIOTLBEntry layout is not as critical as that of the
 150  * CPUTLBEntry. (This is also why we don't want to combine the two
 151  * structs into one.)
 152  */
 153 typedef struct CPUIOTLBEntry {
 154     /*
 155      * @addr contains:
 156      *  - in the lower TARGET_PAGE_BITS, a physical section number
 157      *  - with the lower TARGET_PAGE_BITS masked off, an offset which
 158      *    must be added to the virtual address to obtain:
 159      *     + the ram_addr_t of the target RAM (if the physical section
 160      *       number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM)
 161      *     + the offset within the target MemoryRegion (otherwise)
 162      */
 163     hwaddr addr;
 164     MemTxAttrs attrs;
 165 } CPUIOTLBEntry;
 166
 167 /**
 168  * struct CPUTLBWindow
 169  * @begin_ns: host time (in ns) at the beginning of the time window
 170  * @max_entries: maximum number of entries observed in the window
 171  *
 172  * See also: tlb_mmu_resize_locked()
 173  */
 174 typedef struct CPUTLBWindow {
 175     int64_t begin_ns;
 176     size_t max_entries;
 177 } CPUTLBWindow;
 178
 179 typedef struct CPUTLBDesc {
 180     /*
 181      * Describe a region covering all of the large pages allocated
 182      * into the tlb.  When any page within this region is flushed,
 183      * we must flush the entire tlb.  The region is matched if
 184      * (addr & large_page_mask) == large_page_addr.
 185      */
 186     target_ulong large_page_addr;
 187     target_ulong large_page_mask;
 188     /* The next index to use in the tlb victim table.  */
 189     size_t vindex;
 190 #if TCG_TARGET_IMPLEMENTS_DYN_TLB
 191     CPUTLBWindow window;
 192     size_t n_used_entries;
 193 #endif
 194 } CPUTLBDesc;
 195
 196 /*
 197  * Data elements that are shared between all MMU modes.
 198  */
 199 typedef struct CPUTLBCommon {
 200     /* Serialize updates to tlb_table and tlb_v_table, and others as noted. */
 201     QemuSpin lock;
 202     /*
 203      * Within dirty, for each bit N, modifications have been made to
 204      * mmu_idx N since the last time that mmu_idx was flushed.
 205      * Protected by tlb_c.lock.
 206      */
 207     uint16_t dirty;
 208     /*
 209      * Statistics.  These are not lock protected, but are read and
 210      * written atomically.  This allows the monitor to print a snapshot
 211      * of the stats without interfering with the cpu.
 212      */
 213     size_t full_flush_count;
 214     size_t part_flush_count;
 215     size_t elide_flush_count;
 216 } CPUTLBCommon;
 217
 218 #if TCG_TARGET_IMPLEMENTS_DYN_TLB
 219 # define CPU_TLB                                                        \
 220     /* tlb_mask[i] contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */    \
 221     uintptr_t tlb_mask[NB_MMU_MODES];                                   \
 222     CPUTLBEntry *tlb_table[NB_MMU_MODES];
 223 # define CPU_IOTLB                              \
 224     CPUIOTLBEntry *iotlb[NB_MMU_MODES];
 225 #else
 226 # define CPU_TLB                                        \
 227     CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];
 228 # define CPU_IOTLB                                      \
 229     CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE];
 230 #endif
 231
 232 /*
 233  * The meaning of each of the MMU modes is defined in the target code.
 234  * Note that NB_MMU_MODES is not yet defined; we can only reference it
 235  * within preprocessor defines that will be expanded later.
 236  */
 237 #define CPU_COMMON_TLB \
 238     CPUTLBCommon tlb_c;                                                 \
 239     CPUTLBDesc tlb_d[NB_MMU_MODES];                                     \
 240     CPU_TLB                                                             \
 241     CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE];               \
 242     CPU_IOTLB                                                           \
 243     CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE];
 244
 245 #else
 246
 247 #define CPU_COMMON_TLB
 248
 249 #endif
 250
 251
 252 #define CPU_COMMON                                                      \
 253     /* soft mmu support */                                              \
 254     CPU_COMMON_TLB                                                      \
 255
 256 #endif