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configure: Compile with -Wimplicit-fallthrough=2
[qemu/ar7.git] / target / mips / helper.c
blob87296fbad69fa362675e268955659ad184173d39
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20
21 #include "cpu.h"
22 #include "internal.h"
23 #include "exec/exec-all.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/log.h"
26 #include "hw/mips/cpudevs.h"
27
28 enum {
29 TLBRET_XI = -6,
30 TLBRET_RI = -5,
31 TLBRET_DIRTY = -4,
32 TLBRET_INVALID = -3,
33 TLBRET_NOMATCH = -2,
34 TLBRET_BADADDR = -1,
35 TLBRET_MATCH = 0
36 };
37
38 #if !defined(CONFIG_USER_ONLY)
39
40 /* no MMU emulation */
41 int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
42 target_ulong address, int rw, int access_type)
43 {
44 *physical = address;
45 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
46 return TLBRET_MATCH;
47 }
48
49 /* fixed mapping MMU emulation */
50 int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
51 target_ulong address, int rw, int access_type)
52 {
53 if (address <= (int32_t)0x7FFFFFFFUL) {
54 if (!(env->CP0_Status & (1 << CP0St_ERL))) {
55 *physical = address + 0x40000000UL;
56 } else {
57 *physical = address;
58 }
59 } else if (address <= (int32_t)0xBFFFFFFFUL) {
60 *physical = address & 0x1FFFFFFF;
61 } else {
62 *physical = address;
63 }
64
65 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
66 return TLBRET_MATCH;
67 }
68
69 /* MIPS32/MIPS64 R4000-style MMU emulation */
70 int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
71 target_ulong address, int rw, int access_type)
72 {
73 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
74 uint32_t MMID = env->CP0_MemoryMapID;
75 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
76 uint32_t tlb_mmid;
77 int i;
78
79 MMID = mi ? MMID : (uint32_t) ASID;
80
81 for (i = 0; i < env->tlb->tlb_in_use; i++) {
82 r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
83 /* 1k pages are not supported. */
84 target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
85 target_ulong tag = address & ~mask;
86 target_ulong VPN = tlb->VPN & ~mask;
87 #if defined(TARGET_MIPS64)
88 tag &= env->SEGMask;
89 #endif
90
91 /* Check ASID/MMID, virtual page number & size */
92 tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID;
93 if ((tlb->G == 1 || tlb_mmid == MMID) && VPN == tag && !tlb->EHINV) {
94 /* TLB match */
95 int n = !!(address & mask & ~(mask >> 1));
96 /* Check access rights */
97 if (!(n ? tlb->V1 : tlb->V0)) {
98 return TLBRET_INVALID;
99 }
100 if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
101 return TLBRET_XI;
102 }
103 if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
104 return TLBRET_RI;
105 }
106 if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
107 *physical = tlb->PFN[n] | (address & (mask >> 1));
108 *prot = PAGE_READ;
109 if (n ? tlb->D1 : tlb->D0) {
110 *prot |= PAGE_WRITE;
111 }
112 if (!(n ? tlb->XI1 : tlb->XI0)) {
113 *prot |= PAGE_EXEC;
114 }
115 return TLBRET_MATCH;
116 }
117 return TLBRET_DIRTY;
118 }
119 }
120 return TLBRET_NOMATCH;
121 }
122
123 static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
124 {
125 /*
126 * Interpret access control mode and mmu_idx.
127 * AdE? TLB?
128 * AM K S U E K S U E
129 * UK 0 0 1 1 0 0 - - 0
130 * MK 1 0 1 1 0 1 - - !eu
131 * MSK 2 0 0 1 0 1 1 - !eu
132 * MUSK 3 0 0 0 0 1 1 1 !eu
133 * MUSUK 4 0 0 0 0 0 1 1 0
134 * USK 5 0 0 1 0 0 0 - 0
135 * - 6 - - - - - - - -
136 * UUSK 7 0 0 0 0 0 0 0 0
137 */
138 int32_t adetlb_mask;
139
140 switch (mmu_idx) {
141 case 3: /* ERL */
142 /* If EU is set, always unmapped */
143 if (eu) {
144 return 0;
145 }
146 /* fall through */
147 case MIPS_HFLAG_KM:
148 /* Never AdE, TLB mapped if AM={1,2,3} */
149 adetlb_mask = 0x70000000;
150 goto check_tlb;
151
152 case MIPS_HFLAG_SM:
153 /* AdE if AM={0,1}, TLB mapped if AM={2,3,4} */
154 adetlb_mask = 0xc0380000;
155 goto check_ade;
156
157 case MIPS_HFLAG_UM:
158 /* AdE if AM={0,1,2,5}, TLB mapped if AM={3,4} */
159 adetlb_mask = 0xe4180000;
160 /* fall through */
161 check_ade:
162 /* does this AM cause AdE in current execution mode */
163 if ((adetlb_mask << am) < 0) {
164 return TLBRET_BADADDR;
165 }
166 adetlb_mask <<= 8;
167 /* fall through */
168 check_tlb:
169 /* is this AM mapped in current execution mode */
170 return ((adetlb_mask << am) < 0);
171 default:
172 assert(0);
173 return TLBRET_BADADDR;
174 };
175 }
176
177 static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical,
178 int *prot, target_ulong real_address,
179 int rw, int access_type, int mmu_idx,
180 unsigned int am, bool eu,
181 target_ulong segmask,
182 hwaddr physical_base)
183 {
184 int mapped = is_seg_am_mapped(am, eu, mmu_idx);
185
186 if (mapped < 0) {
187 /* is_seg_am_mapped can report TLBRET_BADADDR */
188 return mapped;
189 } else if (mapped) {
190 /* The segment is TLB mapped */
191 return env->tlb->map_address(env, physical, prot, real_address, rw,
192 access_type);
193 } else {
194 /* The segment is unmapped */
195 *physical = physical_base | (real_address & segmask);
196 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
197 return TLBRET_MATCH;
198 }
199 }
200
201 static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical,
202 int *prot, target_ulong real_address,
203 int rw, int access_type, int mmu_idx,
204 uint16_t segctl, target_ulong segmask)
205 {
206 unsigned int am = (segctl & CP0SC_AM_MASK) >> CP0SC_AM;
207 bool eu = (segctl >> CP0SC_EU) & 1;
208 hwaddr pa = ((hwaddr)segctl & CP0SC_PA_MASK) << 20;
209
210 return get_seg_physical_address(env, physical, prot, real_address, rw,
211 access_type, mmu_idx, am, eu, segmask,
212 pa & ~(hwaddr)segmask);
213 }
214
215 static int get_physical_address(CPUMIPSState *env, hwaddr *physical,
216 int *prot, target_ulong real_address,
217 int rw, int access_type, int mmu_idx)
218 {
219 /* User mode can only access useg/xuseg */
220 #if defined(TARGET_MIPS64)
221 int user_mode = mmu_idx == MIPS_HFLAG_UM;
222 int supervisor_mode = mmu_idx == MIPS_HFLAG_SM;
223 int kernel_mode = !user_mode && !supervisor_mode;
224 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
225 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
226 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
227 #endif
228 int ret = TLBRET_MATCH;
229 /* effective address (modified for KVM T&E kernel segments) */
230 target_ulong address = real_address;
231
232 #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL)
233 #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL)
234 #define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL)
235 #define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL)
236 #define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL)
237
238 #define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL)
239 #define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL)
240
241 if (mips_um_ksegs_enabled()) {
242 /* KVM T&E adds guest kernel segments in useg */
243 if (real_address >= KVM_KSEG0_BASE) {
244 if (real_address < KVM_KSEG2_BASE) {
245 /* kseg0 */
246 address += KSEG0_BASE - KVM_KSEG0_BASE;
247 } else if (real_address <= USEG_LIMIT) {
248 /* kseg2/3 */
249 address += KSEG2_BASE - KVM_KSEG2_BASE;
250 }
251 }
252 }
253
254 if (address <= USEG_LIMIT) {
255 /* useg */
256 uint16_t segctl;
257
258 if (address >= 0x40000000UL) {
259 segctl = env->CP0_SegCtl2;
260 } else {
261 segctl = env->CP0_SegCtl2 >> 16;
262 }
263 ret = get_segctl_physical_address(env, physical, prot,
264 real_address, rw, access_type,
265 mmu_idx, segctl, 0x3FFFFFFF);
266 #if defined(TARGET_MIPS64)
267 } else if (address < 0x4000000000000000ULL) {
268 /* xuseg */
269 if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
270 ret = env->tlb->map_address(env, physical, prot,
271 real_address, rw, access_type);
272 } else {
273 ret = TLBRET_BADADDR;
274 }
275 } else if (address < 0x8000000000000000ULL) {
276 /* xsseg */
277 if ((supervisor_mode || kernel_mode) &&
278 SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
279 ret = env->tlb->map_address(env, physical, prot,
280 real_address, rw, access_type);
281 } else {
282 ret = TLBRET_BADADDR;
283 }
284 } else if (address < 0xC000000000000000ULL) {
285 /* xkphys */
286 if ((address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
287 /* KX/SX/UX bit to check for each xkphys EVA access mode */
288 static const uint8_t am_ksux[8] = {
289 [CP0SC_AM_UK] = (1u << CP0St_KX),
290 [CP0SC_AM_MK] = (1u << CP0St_KX),
291 [CP0SC_AM_MSK] = (1u << CP0St_SX),
292 [CP0SC_AM_MUSK] = (1u << CP0St_UX),
293 [CP0SC_AM_MUSUK] = (1u << CP0St_UX),
294 [CP0SC_AM_USK] = (1u << CP0St_SX),
295 [6] = (1u << CP0St_KX),
296 [CP0SC_AM_UUSK] = (1u << CP0St_UX),
297 };
298 unsigned int am = CP0SC_AM_UK;
299 unsigned int xr = (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0SC2_XR;
300
301 if (xr & (1 << ((address >> 59) & 0x7))) {
302 am = (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM;
303 }
304 /* Does CP0_Status.KX/SX/UX permit the access mode (am) */
305 if (env->CP0_Status & am_ksux[am]) {
306 ret = get_seg_physical_address(env, physical, prot,
307 real_address, rw, access_type,
308 mmu_idx, am, false, env->PAMask,
309 0);
310 } else {
311 ret = TLBRET_BADADDR;
312 }
313 } else {
314 ret = TLBRET_BADADDR;
315 }
316 } else if (address < 0xFFFFFFFF80000000ULL) {
317 /* xkseg */
318 if (kernel_mode && KX &&
319 address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
320 ret = env->tlb->map_address(env, physical, prot,
321 real_address, rw, access_type);
322 } else {
323 ret = TLBRET_BADADDR;
324 }
325 #endif
326 } else if (address < KSEG1_BASE) {
327 /* kseg0 */
328 ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
329 access_type, mmu_idx,
330 env->CP0_SegCtl1 >> 16, 0x1FFFFFFF);
331 } else if (address < KSEG2_BASE) {
332 /* kseg1 */
333 ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
334 access_type, mmu_idx,
335 env->CP0_SegCtl1, 0x1FFFFFFF);
336 } else if (address < KSEG3_BASE) {
337 /* sseg (kseg2) */
338 ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
339 access_type, mmu_idx,
340 env->CP0_SegCtl0 >> 16, 0x1FFFFFFF);
341 } else {
342 /*
343 * kseg3
344 * XXX: debug segment is not emulated
345 */
346 ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
347 access_type, mmu_idx,
348 env->CP0_SegCtl0, 0x1FFFFFFF);
349 }
350 return ret;
351 }
352
353 void cpu_mips_tlb_flush(CPUMIPSState *env)
354 {
355 /* Flush qemu's TLB and discard all shadowed entries. */
356 tlb_flush(env_cpu(env));
357 env->tlb->tlb_in_use = env->tlb->nb_tlb;
358 }
359
360 /* Called for updates to CP0_Status. */
361 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
362 {
363 int32_t tcstatus, *tcst;
364 uint32_t v = cpu->CP0_Status;
365 uint32_t cu, mx, asid, ksu;
366 uint32_t mask = ((1 << CP0TCSt_TCU3)
367 | (1 << CP0TCSt_TCU2)
368 | (1 << CP0TCSt_TCU1)
369 | (1 << CP0TCSt_TCU0)
370 | (1 << CP0TCSt_TMX)
371 | (3 << CP0TCSt_TKSU)
372 | (0xff << CP0TCSt_TASID));
373
374 cu = (v >> CP0St_CU0) & 0xf;
375 mx = (v >> CP0St_MX) & 0x1;
376 ksu = (v >> CP0St_KSU) & 0x3;
377 asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
378
379 tcstatus = cu << CP0TCSt_TCU0;
380 tcstatus |= mx << CP0TCSt_TMX;
381 tcstatus |= ksu << CP0TCSt_TKSU;
382 tcstatus |= asid;
383
384 if (tc == cpu->current_tc) {
385 tcst = &cpu->active_tc.CP0_TCStatus;
386 } else {
387 tcst = &cpu->tcs[tc].CP0_TCStatus;
388 }
389
390 *tcst &= ~mask;
391 *tcst |= tcstatus;
392 compute_hflags(cpu);
393 }
394
395 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
396 {
397 uint32_t mask = env->CP0_Status_rw_bitmask;
398 target_ulong old = env->CP0_Status;
399
400 if (env->insn_flags & ISA_MIPS32R6) {
401 bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
402 #if defined(TARGET_MIPS64)
403 uint32_t ksux = (1 << CP0St_KX) & val;
404 ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
405 ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
406 val = (val & ~(7 << CP0St_UX)) | ksux;
407 #endif
408 if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
409 mask &= ~(3 << CP0St_KSU);
410 }
411 mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
412 }
413
414 env->CP0_Status = (old & ~mask) | (val & mask);
415 #if defined(TARGET_MIPS64)
416 if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
417 /* Access to at least one of the 64-bit segments has been disabled */
418 tlb_flush(env_cpu(env));
419 }
420 #endif
421 if (ase_mt_available(env)) {
422 sync_c0_status(env, env, env->current_tc);
423 } else {
424 compute_hflags(env);
425 }
426 }
427
428 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
429 {
430 uint32_t mask = 0x00C00300;
431 uint32_t old = env->CP0_Cause;
432 int i;
433
434 if (env->insn_flags & ISA_MIPS32R2) {
435 mask |= 1 << CP0Ca_DC;
436 }
437 if (env->insn_flags & ISA_MIPS32R6) {
438 mask &= ~((1 << CP0Ca_WP) & val);
439 }
440
441 env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
442
443 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
444 if (env->CP0_Cause & (1 << CP0Ca_DC)) {
445 cpu_mips_stop_count(env);
446 } else {
447 cpu_mips_start_count(env);
448 }
449 }
450
451 /* Set/reset software interrupts */
452 for (i = 0 ; i < 2 ; i++) {
453 if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
454 cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
455 }
456 }
457 }
458 #endif
459
460 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
461 int rw, int tlb_error)
462 {
463 CPUState *cs = env_cpu(env);
464 int exception = 0, error_code = 0;
465
466 if (rw == MMU_INST_FETCH) {
467 error_code |= EXCP_INST_NOTAVAIL;
468 }
469
470 switch (tlb_error) {
471 default:
472 case TLBRET_BADADDR:
473 /* Reference to kernel address from user mode or supervisor mode */
474 /* Reference to supervisor address from user mode */
475 if (rw == MMU_DATA_STORE) {
476 exception = EXCP_AdES;
477 } else {
478 exception = EXCP_AdEL;
479 }
480 break;
481 case TLBRET_NOMATCH:
482 /* No TLB match for a mapped address */
483 if (rw == MMU_DATA_STORE) {
484 exception = EXCP_TLBS;
485 } else {
486 exception = EXCP_TLBL;
487 }
488 error_code |= EXCP_TLB_NOMATCH;
489 break;
490 case TLBRET_INVALID:
491 /* TLB match with no valid bit */
492 if (rw == MMU_DATA_STORE) {
493 exception = EXCP_TLBS;
494 } else {
495 exception = EXCP_TLBL;
496 }
497 break;
498 case TLBRET_DIRTY:
499 /* TLB match but 'D' bit is cleared */
500 exception = EXCP_LTLBL;
501 break;
502 case TLBRET_XI:
503 /* Execute-Inhibit Exception */
504 if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
505 exception = EXCP_TLBXI;
506 } else {
507 exception = EXCP_TLBL;
508 }
509 break;
510 case TLBRET_RI:
511 /* Read-Inhibit Exception */
512 if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
513 exception = EXCP_TLBRI;
514 } else {
515 exception = EXCP_TLBL;
516 }
517 break;
518 }
519 /* Raise exception */
520 if (!(env->hflags & MIPS_HFLAG_DM)) {
521 env->CP0_BadVAddr = address;
522 }
523 env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
524 ((address >> 9) & 0x007ffff0);
525 env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
526 (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) |
527 (address & (TARGET_PAGE_MASK << 1));
528 #if defined(TARGET_MIPS64)
529 env->CP0_EntryHi &= env->SEGMask;
530 env->CP0_XContext =
531 (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | /* PTEBase */
532 (extract64(address, 62, 2) << (env->SEGBITS - 9)) | /* R */
533 (extract64(address, 13, env->SEGBITS - 13) << 4); /* BadVPN2 */
534 #endif
535 cs->exception_index = exception;
536 env->error_code = error_code;
537 }
538
539 #if !defined(CONFIG_USER_ONLY)
540 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
541 {
542 MIPSCPU *cpu = MIPS_CPU(cs);
543 CPUMIPSState *env = &cpu->env;
544 hwaddr phys_addr;
545 int prot;
546
547 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT,
548 cpu_mmu_index(env, false)) != 0) {
549 return -1;
550 }
551 return phys_addr;
552 }
553 #endif
554
555 #if !defined(CONFIG_USER_ONLY)
556 #if !defined(TARGET_MIPS64)
557
558 /*
559 * Perform hardware page table walk
560 *
561 * Memory accesses are performed using the KERNEL privilege level.
562 * Synchronous exceptions detected on memory accesses cause a silent exit
563 * from page table walking, resulting in a TLB or XTLB Refill exception.
564 *
565 * Implementations are not required to support page table walk memory
566 * accesses from mapped memory regions. When an unsupported access is
567 * attempted, a silent exit is taken, resulting in a TLB or XTLB Refill
568 * exception.
569 *
570 * Note that if an exception is caused by AddressTranslation or LoadMemory
571 * functions, the exception is not taken, a silent exit is taken,
572 * resulting in a TLB or XTLB Refill exception.
573 */
574
575 static bool get_pte(CPUMIPSState *env, uint64_t vaddr, int entry_size,
576 uint64_t *pte)
577 {
578 if ((vaddr & ((entry_size >> 3) - 1)) != 0) {
579 return false;
580 }
581 if (entry_size == 64) {
582 *pte = cpu_ldq_code(env, vaddr);
583 } else {
584 *pte = cpu_ldl_code(env, vaddr);
585 }
586 return true;
587 }
588
589 static uint64_t get_tlb_entry_layout(CPUMIPSState *env, uint64_t entry,
590 int entry_size, int ptei)
591 {
592 uint64_t result = entry;
593 uint64_t rixi;
594 if (ptei > entry_size) {
595 ptei -= 32;
596 }
597 result >>= (ptei - 2);
598 rixi = result & 3;
599 result >>= 2;
600 result |= rixi << CP0EnLo_XI;
601 return result;
602 }
603
604 static int walk_directory(CPUMIPSState *env, uint64_t *vaddr,
605 int directory_index, bool *huge_page, bool *hgpg_directory_hit,
606 uint64_t *pw_entrylo0, uint64_t *pw_entrylo1)
607 {
608 int dph = (env->CP0_PWCtl >> CP0PC_DPH) & 0x1;
609 int psn = (env->CP0_PWCtl >> CP0PC_PSN) & 0x3F;
610 int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1;
611 int pf_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
612 int ptew = (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F;
613 int native_shift = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? 2 : 3;
614 int directory_shift = (ptew > 1) ? -1 :
615 (hugepg && (ptew == 1)) ? native_shift + 1 : native_shift;
616 int leaf_shift = (ptew > 1) ? -1 :
617 (ptew == 1) ? native_shift + 1 : native_shift;
618 uint32_t direntry_size = 1 << (directory_shift + 3);
619 uint32_t leafentry_size = 1 << (leaf_shift + 3);
620 uint64_t entry;
621 uint64_t paddr;
622 int prot;
623 uint64_t lsb = 0;
624 uint64_t w = 0;
625
626 if (get_physical_address(env, &paddr, &prot, *vaddr, MMU_DATA_LOAD,
627 ACCESS_INT, cpu_mmu_index(env, false)) !=
628 TLBRET_MATCH) {
629 /* wrong base address */
630 return 0;
631 }
632 if (!get_pte(env, *vaddr, direntry_size, &entry)) {
633 return 0;
634 }
635
636 if ((entry & (1 << psn)) && hugepg) {
637 *huge_page = true;
638 *hgpg_directory_hit = true;
639 entry = get_tlb_entry_layout(env, entry, leafentry_size, pf_ptew);
640 w = directory_index - 1;
641 if (directory_index & 0x1) {
642 /* Generate adjacent page from same PTE for odd TLB page */
643 lsb = (1 << w) >> 6;
644 *pw_entrylo0 = entry & ~lsb; /* even page */
645 *pw_entrylo1 = entry | lsb; /* odd page */
646 } else if (dph) {
647 int oddpagebit = 1 << leaf_shift;
648 uint64_t vaddr2 = *vaddr ^ oddpagebit;
649 if (*vaddr & oddpagebit) {
650 *pw_entrylo1 = entry;
651 } else {
652 *pw_entrylo0 = entry;
653 }
654 if (get_physical_address(env, &paddr, &prot, vaddr2, MMU_DATA_LOAD,
655 ACCESS_INT, cpu_mmu_index(env, false)) !=
656 TLBRET_MATCH) {
657 return 0;
658 }
659 if (!get_pte(env, vaddr2, leafentry_size, &entry)) {
660 return 0;
661 }
662 entry = get_tlb_entry_layout(env, entry, leafentry_size, pf_ptew);
663 if (*vaddr & oddpagebit) {
664 *pw_entrylo0 = entry;
665 } else {
666 *pw_entrylo1 = entry;
667 }
668 } else {
669 return 0;
670 }
671 return 1;
672 } else {
673 *vaddr = entry;
674 return 2;
675 }
676 }
677
678 static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, int rw,
679 int mmu_idx)
680 {
681 int gdw = (env->CP0_PWSize >> CP0PS_GDW) & 0x3F;
682 int udw = (env->CP0_PWSize >> CP0PS_UDW) & 0x3F;
683 int mdw = (env->CP0_PWSize >> CP0PS_MDW) & 0x3F;
684 int ptw = (env->CP0_PWSize >> CP0PS_PTW) & 0x3F;
685 int ptew = (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F;
686
687 /* Initial values */
688 bool huge_page = false;
689 bool hgpg_bdhit = false;
690 bool hgpg_gdhit = false;
691 bool hgpg_udhit = false;
692 bool hgpg_mdhit = false;
693
694 int32_t pw_pagemask = 0;
695 target_ulong pw_entryhi = 0;
696 uint64_t pw_entrylo0 = 0;
697 uint64_t pw_entrylo1 = 0;
698
699 /* Native pointer size */
700 /*For the 32-bit architectures, this bit is fixed to 0.*/
701 int native_shift = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? 2 : 3;
702
703 /* Indices from PWField */
704 int pf_gdw = (env->CP0_PWField >> CP0PF_GDW) & 0x3F;
705 int pf_udw = (env->CP0_PWField >> CP0PF_UDW) & 0x3F;
706 int pf_mdw = (env->CP0_PWField >> CP0PF_MDW) & 0x3F;
707 int pf_ptw = (env->CP0_PWField >> CP0PF_PTW) & 0x3F;
708 int pf_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
709
710 /* Indices computed from faulting address */
711 int gindex = (address >> pf_gdw) & ((1 << gdw) - 1);
712 int uindex = (address >> pf_udw) & ((1 << udw) - 1);
713 int mindex = (address >> pf_mdw) & ((1 << mdw) - 1);
714 int ptindex = (address >> pf_ptw) & ((1 << ptw) - 1);
715
716 /* Other HTW configs */
717 int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1;
718
719 /* HTW Shift values (depend on entry size) */
720 int directory_shift = (ptew > 1) ? -1 :
721 (hugepg && (ptew == 1)) ? native_shift + 1 : native_shift;
722 int leaf_shift = (ptew > 1) ? -1 :
723 (ptew == 1) ? native_shift + 1 : native_shift;
724
725 /* Offsets into tables */
726 int goffset = gindex << directory_shift;
727 int uoffset = uindex << directory_shift;
728 int moffset = mindex << directory_shift;
729 int ptoffset0 = (ptindex >> 1) << (leaf_shift + 1);
730 int ptoffset1 = ptoffset0 | (1 << (leaf_shift));
731
732 uint32_t leafentry_size = 1 << (leaf_shift + 3);
733
734 /* Starting address - Page Table Base */
735 uint64_t vaddr = env->CP0_PWBase;
736
737 uint64_t dir_entry;
738 uint64_t paddr;
739 int prot;
740 int m;
741
742 if (!(env->CP0_Config3 & (1 << CP0C3_PW))) {
743 /* walker is unimplemented */
744 return false;
745 }
746 if (!(env->CP0_PWCtl & (1 << CP0PC_PWEN))) {
747 /* walker is disabled */
748 return false;
749 }
750 if (!(gdw > 0 || udw > 0 || mdw > 0)) {
751 /* no structure to walk */
752 return false;
753 }
754 if ((directory_shift == -1) || (leaf_shift == -1)) {
755 return false;
756 }
757
758 /* Global Directory */
759 if (gdw > 0) {
760 vaddr |= goffset;
761 switch (walk_directory(env, &vaddr, pf_gdw, &huge_page, &hgpg_gdhit,
762 &pw_entrylo0, &pw_entrylo1))
763 {
764 case 0:
765 return false;
766 case 1:
767 goto refill;
768 case 2:
769 default:
770 break;
771 }
772 }
773
774 /* Upper directory */
775 if (udw > 0) {
776 vaddr |= uoffset;
777 switch (walk_directory(env, &vaddr, pf_udw, &huge_page, &hgpg_udhit,
778 &pw_entrylo0, &pw_entrylo1))
779 {
780 case 0:
781 return false;
782 case 1:
783 goto refill;
784 case 2:
785 default:
786 break;
787 }
788 }
789
790 /* Middle directory */
791 if (mdw > 0) {
792 vaddr |= moffset;
793 switch (walk_directory(env, &vaddr, pf_mdw, &huge_page, &hgpg_mdhit,
794 &pw_entrylo0, &pw_entrylo1))
795 {
796 case 0:
797 return false;
798 case 1:
799 goto refill;
800 case 2:
801 default:
802 break;
803 }
804 }
805
806 /* Leaf Level Page Table - First half of PTE pair */
807 vaddr |= ptoffset0;
808 if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD,
809 ACCESS_INT, cpu_mmu_index(env, false)) !=
810 TLBRET_MATCH) {
811 return false;
812 }
813 if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) {
814 return false;
815 }
816 dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, pf_ptew);
817 pw_entrylo0 = dir_entry;
818
819 /* Leaf Level Page Table - Second half of PTE pair */
820 vaddr |= ptoffset1;
821 if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD,
822 ACCESS_INT, cpu_mmu_index(env, false)) !=
823 TLBRET_MATCH) {
824 return false;
825 }
826 if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) {
827 return false;
828 }
829 dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, pf_ptew);
830 pw_entrylo1 = dir_entry;
831
832 refill:
833
834 m = (1 << pf_ptw) - 1;
835
836 if (huge_page) {
837 switch (hgpg_bdhit << 3 | hgpg_gdhit << 2 | hgpg_udhit << 1 |
838 hgpg_mdhit)
839 {
840 case 4:
841 m = (1 << pf_gdw) - 1;
842 if (pf_gdw & 1) {
843 m >>= 1;
844 }
845 break;
846 case 2:
847 m = (1 << pf_udw) - 1;
848 if (pf_udw & 1) {
849 m >>= 1;
850 }
851 break;
852 case 1:
853 m = (1 << pf_mdw) - 1;
854 if (pf_mdw & 1) {
855 m >>= 1;
856 }
857 break;
858 }
859 }
860 pw_pagemask = m >> TARGET_PAGE_BITS_MIN;
861 update_pagemask(env, pw_pagemask << CP0PM_MASK, &pw_pagemask);
862 pw_entryhi = (address & ~0x1fff) | (env->CP0_EntryHi & 0xFF);
863 {
864 target_ulong tmp_entryhi = env->CP0_EntryHi;
865 int32_t tmp_pagemask = env->CP0_PageMask;
866 uint64_t tmp_entrylo0 = env->CP0_EntryLo0;
867 uint64_t tmp_entrylo1 = env->CP0_EntryLo1;
868
869 env->CP0_EntryHi = pw_entryhi;
870 env->CP0_PageMask = pw_pagemask;
871 env->CP0_EntryLo0 = pw_entrylo0;
872 env->CP0_EntryLo1 = pw_entrylo1;
873
874 /*
875 * The hardware page walker inserts a page into the TLB in a manner
876 * identical to a TLBWR instruction as executed by the software refill
877 * handler.
878 */
879 r4k_helper_tlbwr(env);
880
881 env->CP0_EntryHi = tmp_entryhi;
882 env->CP0_PageMask = tmp_pagemask;
883 env->CP0_EntryLo0 = tmp_entrylo0;
884 env->CP0_EntryLo1 = tmp_entrylo1;
885 }
886 return true;
887 }
888 #endif
889 #endif
890
891 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
892 MMUAccessType access_type, int mmu_idx,
893 bool probe, uintptr_t retaddr)
894 {
895 MIPSCPU *cpu = MIPS_CPU(cs);
896 CPUMIPSState *env = &cpu->env;
897 #if !defined(CONFIG_USER_ONLY)
898 hwaddr physical;
899 int prot;
900 int mips_access_type;
901 #endif
902 int ret = TLBRET_BADADDR;
903
904 /* data access */
905 #if !defined(CONFIG_USER_ONLY)
906 /* XXX: put correct access by using cpu_restore_state() correctly */
907 mips_access_type = ACCESS_INT;
908 ret = get_physical_address(env, &physical, &prot, address,
909 access_type, mips_access_type, mmu_idx);
910 switch (ret) {
911 case TLBRET_MATCH:
912 qemu_log_mask(CPU_LOG_MMU,
913 "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx
914 " prot %d\n", __func__, address, physical, prot);
915 break;
916 default:
917 qemu_log_mask(CPU_LOG_MMU,
918 "%s address=%" VADDR_PRIx " ret %d\n", __func__, address,
919 ret);
920 break;
921 }
922 if (ret == TLBRET_MATCH) {
923 tlb_set_page(cs, address & TARGET_PAGE_MASK,
924 physical & TARGET_PAGE_MASK, prot,
925 mmu_idx, TARGET_PAGE_SIZE);
926 return true;
927 }
928 #if !defined(TARGET_MIPS64)
929 if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) {
930 /*
931 * Memory reads during hardware page table walking are performed
932 * as if they were kernel-mode load instructions.
933 */
934 int mode = (env->hflags & MIPS_HFLAG_KSU);
935 bool ret_walker;
936 env->hflags &= ~MIPS_HFLAG_KSU;
937 ret_walker = page_table_walk_refill(env, address, access_type, mmu_idx);
938 env->hflags |= mode;
939 if (ret_walker) {
940 ret = get_physical_address(env, &physical, &prot, address,
941 access_type, mips_access_type, mmu_idx);
942 if (ret == TLBRET_MATCH) {
943 tlb_set_page(cs, address & TARGET_PAGE_MASK,
944 physical & TARGET_PAGE_MASK, prot,
945 mmu_idx, TARGET_PAGE_SIZE);
946 return true;
947 }
948 }
949 }
950 #endif
951 if (probe) {
952 return false;
953 }
954 #endif
955
956 raise_mmu_exception(env, address, access_type, ret);
957 do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr);
958 }
959
960 #ifndef CONFIG_USER_ONLY
961 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
962 int rw)
963 {
964 hwaddr physical;
965 int prot;
966 int access_type;
967 int ret = 0;
968
969 /* data access */
970 access_type = ACCESS_INT;
971 ret = get_physical_address(env, &physical, &prot, address, rw, access_type,
972 cpu_mmu_index(env, false));
973 if (ret != TLBRET_MATCH) {
974 raise_mmu_exception(env, address, rw, ret);
975 return -1LL;
976 } else {
977 return physical;
978 }
979 }
980 #endif /* !CONFIG_USER_ONLY */
981
982 static const char * const excp_names[EXCP_LAST + 1] = {
983 [EXCP_RESET] = "reset",
984 [EXCP_SRESET] = "soft reset",
985 [EXCP_DSS] = "debug single step",
986 [EXCP_DINT] = "debug interrupt",
987 [EXCP_NMI] = "non-maskable interrupt",
988 [EXCP_MCHECK] = "machine check",
989 [EXCP_EXT_INTERRUPT] = "interrupt",
990 [EXCP_DFWATCH] = "deferred watchpoint",
991 [EXCP_DIB] = "debug instruction breakpoint",
992 [EXCP_IWATCH] = "instruction fetch watchpoint",
993 [EXCP_AdEL] = "address error load",
994 [EXCP_AdES] = "address error store",
995 [EXCP_TLBF] = "TLB refill",
996 [EXCP_IBE] = "instruction bus error",
997 [EXCP_DBp] = "debug breakpoint",
998 [EXCP_SYSCALL] = "syscall",
999 [EXCP_BREAK] = "break",
1000 [EXCP_CpU] = "coprocessor unusable",
1001 [EXCP_RI] = "reserved instruction",
1002 [EXCP_OVERFLOW] = "arithmetic overflow",
1003 [EXCP_TRAP] = "trap",
1004 [EXCP_FPE] = "floating point",
1005 [EXCP_DDBS] = "debug data break store",
1006 [EXCP_DWATCH] = "data watchpoint",
1007 [EXCP_LTLBL] = "TLB modify",
1008 [EXCP_TLBL] = "TLB load",
1009 [EXCP_TLBS] = "TLB store",
1010 [EXCP_DBE] = "data bus error",
1011 [EXCP_DDBL] = "debug data break load",
1012 [EXCP_THREAD] = "thread",
1013 [EXCP_MDMX] = "MDMX",
1014 [EXCP_C2E] = "precise coprocessor 2",
1015 [EXCP_CACHE] = "cache error",
1016 [EXCP_TLBXI] = "TLB execute-inhibit",
1017 [EXCP_TLBRI] = "TLB read-inhibit",
1018 [EXCP_MSADIS] = "MSA disabled",
1019 [EXCP_MSAFPE] = "MSA floating point",
1020 };
1021
1022 static const char *mips_exception_name(int32_t exception)
1023 {
1024 if (exception < 0 || exception > EXCP_LAST) {
1025 return "unknown";
1026 }
1027 return excp_names[exception];
1028 }
1029
1030 target_ulong exception_resume_pc(CPUMIPSState *env)
1031 {
1032 target_ulong bad_pc;
1033 target_ulong isa_mode;
1034
1035 isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
1036 bad_pc = env->active_tc.PC | isa_mode;
1037 if (env->hflags & MIPS_HFLAG_BMASK) {
1038 /*
1039 * If the exception was raised from a delay slot, come back to
1040 * the jump.
1041 */
1042 bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
1043 }
1044
1045 return bad_pc;
1046 }
1047
1048 #if !defined(CONFIG_USER_ONLY)
1049 static void set_hflags_for_handler(CPUMIPSState *env)
1050 {
1051 /* Exception handlers are entered in 32-bit mode. */
1052 env->hflags &= ~(MIPS_HFLAG_M16);
1053 /* ...except that microMIPS lets you choose. */
1054 if (env->insn_flags & ASE_MICROMIPS) {
1055 env->hflags |= (!!(env->CP0_Config3 &
1056 (1 << CP0C3_ISA_ON_EXC))
1057 << MIPS_HFLAG_M16_SHIFT);
1058 }
1059 }
1060
1061 static inline void set_badinstr_registers(CPUMIPSState *env)
1062 {
1063 if (env->insn_flags & ISA_NANOMIPS32) {
1064 if (env->CP0_Config3 & (1 << CP0C3_BI)) {
1065 uint32_t instr = (cpu_lduw_code(env, env->active_tc.PC)) << 16;
1066 if ((instr & 0x10000000) == 0) {
1067 instr |= cpu_lduw_code(env, env->active_tc.PC + 2);
1068 }
1069 env->CP0_BadInstr = instr;
1070
1071 if ((instr & 0xFC000000) == 0x60000000) {
1072 instr = cpu_lduw_code(env, env->active_tc.PC + 4) << 16;
1073 env->CP0_BadInstrX = instr;
1074 }
1075 }
1076 return;
1077 }
1078
1079 if (env->hflags & MIPS_HFLAG_M16) {
1080 /* TODO: add BadInstr support for microMIPS */
1081 return;
1082 }
1083 if (env->CP0_Config3 & (1 << CP0C3_BI)) {
1084 env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC);
1085 }
1086 if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
1087 (env->hflags & MIPS_HFLAG_BMASK)) {
1088 env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
1089 }
1090 }
1091 #endif
1092
1093 void mips_cpu_do_interrupt(CPUState *cs)
1094 {
1095 #if !defined(CONFIG_USER_ONLY)
1096 MIPSCPU *cpu = MIPS_CPU(cs);
1097 CPUMIPSState *env = &cpu->env;
1098 bool update_badinstr = 0;
1099 target_ulong offset;
1100 int cause = -1;
1101
1102 if (qemu_loglevel_mask(CPU_LOG_INT)
1103 && cs->exception_index != EXCP_EXT_INTERRUPT) {
1104 qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx
1105 " %s exception\n",
1106 __func__, env->active_tc.PC, env->CP0_EPC,
1107 mips_exception_name(cs->exception_index));
1108 }
1109 if (cs->exception_index == EXCP_EXT_INTERRUPT &&
1110 (env->hflags & MIPS_HFLAG_DM)) {
1111 cs->exception_index = EXCP_DINT;
1112 }
1113 offset = 0x180;
1114 switch (cs->exception_index) {
1115 case EXCP_DSS:
1116 env->CP0_Debug |= 1 << CP0DB_DSS;
1117 /*
1118 * Debug single step cannot be raised inside a delay slot and
1119 * resume will always occur on the next instruction
1120 * (but we assume the pc has always been updated during
1121 * code translation).
1122 */
1123 env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
1124 goto enter_debug_mode;
1125 case EXCP_DINT:
1126 env->CP0_Debug |= 1 << CP0DB_DINT;
1127 goto set_DEPC;
1128 case EXCP_DIB:
1129 env->CP0_Debug |= 1 << CP0DB_DIB;
1130 goto set_DEPC;
1131 case EXCP_DBp:
1132 env->CP0_Debug |= 1 << CP0DB_DBp;
1133 /* Setup DExcCode - SDBBP instruction */
1134 env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) |
1135 (9 << CP0DB_DEC);
1136 goto set_DEPC;
1137 case EXCP_DDBS:
1138 env->CP0_Debug |= 1 << CP0DB_DDBS;
1139 goto set_DEPC;
1140 case EXCP_DDBL:
1141 env->CP0_Debug |= 1 << CP0DB_DDBL;
1142 set_DEPC:
1143 env->CP0_DEPC = exception_resume_pc(env);
1144 env->hflags &= ~MIPS_HFLAG_BMASK;
1145 enter_debug_mode:
1146 if (env->insn_flags & ISA_MIPS3) {
1147 env->hflags |= MIPS_HFLAG_64;
1148 if (!(env->insn_flags & ISA_MIPS64R6) ||
1149 env->CP0_Status & (1 << CP0St_KX)) {
1150 env->hflags &= ~MIPS_HFLAG_AWRAP;
1151 }
1152 }
1153 env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;
1154 env->hflags &= ~(MIPS_HFLAG_KSU);
1155 /* EJTAG probe trap enable is not implemented... */
1156 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
1157 env->CP0_Cause &= ~(1U << CP0Ca_BD);
1158 }
1159 env->active_tc.PC = env->exception_base + 0x480;
1160 set_hflags_for_handler(env);
1161 break;
1162 case EXCP_RESET:
1163 cpu_reset(CPU(cpu));
1164 break;
1165 case EXCP_SRESET:
1166 env->CP0_Status |= (1 << CP0St_SR);
1167 memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo));
1168 goto set_error_EPC;
1169 case EXCP_NMI:
1170 env->CP0_Status |= (1 << CP0St_NMI);
1171 set_error_EPC:
1172 env->CP0_ErrorEPC = exception_resume_pc(env);
1173 env->hflags &= ~MIPS_HFLAG_BMASK;
1174 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
1175 if (env->insn_flags & ISA_MIPS3) {
1176 env->hflags |= MIPS_HFLAG_64;
1177 if (!(env->insn_flags & ISA_MIPS64R6) ||
1178 env->CP0_Status & (1 << CP0St_KX)) {
1179 env->hflags &= ~MIPS_HFLAG_AWRAP;
1180 }
1181 }
1182 env->hflags |= MIPS_HFLAG_CP0;
1183 env->hflags &= ~(MIPS_HFLAG_KSU);
1184 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
1185 env->CP0_Cause &= ~(1U << CP0Ca_BD);
1186 }
1187 env->active_tc.PC = env->exception_base;
1188 set_hflags_for_handler(env);
1189 break;
1190 case EXCP_EXT_INTERRUPT:
1191 cause = 0;
1192 if (env->CP0_Cause & (1 << CP0Ca_IV)) {
1193 uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f;
1194
1195 if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) {
1196 offset = 0x200;
1197 } else {
1198 uint32_t vector = 0;
1199 uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP;
1200
1201 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
1202 /*
1203 * For VEIC mode, the external interrupt controller feeds
1204 * the vector through the CP0Cause IP lines.
1205 */
1206 vector = pending;
1207 } else {
1208 /*
1209 * Vectored Interrupts
1210 * Mask with Status.IM7-IM0 to get enabled interrupts.
1211 */
1212 pending &= (env->CP0_Status >> CP0St_IM) & 0xff;
1213 /* Find the highest-priority interrupt. */
1214 while (pending >>= 1) {
1215 vector++;
1216 }
1217 }
1218 offset = 0x200 + (vector * (spacing << 5));
1219 }
1220 }
1221 goto set_EPC;
1222 case EXCP_LTLBL:
1223 cause = 1;
1224 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
1225 goto set_EPC;
1226 case EXCP_TLBL:
1227 cause = 2;
1228 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
1229 if ((env->error_code & EXCP_TLB_NOMATCH) &&
1230 !(env->CP0_Status & (1 << CP0St_EXL))) {
1231 #if defined(TARGET_MIPS64)
1232 int R = env->CP0_BadVAddr >> 62;
1233 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
1234 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
1235
1236 if ((R != 0 || UX) && (R != 3 || KX) &&
1237 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) {
1238 offset = 0x080;
1239 } else {
1240 #endif
1241 offset = 0x000;
1242 #if defined(TARGET_MIPS64)
1243 }
1244 #endif
1245 }
1246 goto set_EPC;
1247 case EXCP_TLBS:
1248 cause = 3;
1249 update_badinstr = 1;
1250 if ((env->error_code & EXCP_TLB_NOMATCH) &&
1251 !(env->CP0_Status & (1 << CP0St_EXL))) {
1252 #if defined(TARGET_MIPS64)
1253 int R = env->CP0_BadVAddr >> 62;
1254 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
1255 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
1256
1257 if ((R != 0 || UX) && (R != 3 || KX) &&
1258 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) {
1259 offset = 0x080;
1260 } else {
1261 #endif
1262 offset = 0x000;
1263 #if defined(TARGET_MIPS64)
1264 }
1265 #endif
1266 }
1267 goto set_EPC;
1268 case EXCP_AdEL:
1269 cause = 4;
1270 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
1271 goto set_EPC;
1272 case EXCP_AdES:
1273 cause = 5;
1274 update_badinstr = 1;
1275 goto set_EPC;
1276 case EXCP_IBE:
1277 cause = 6;
1278 goto set_EPC;
1279 case EXCP_DBE:
1280 cause = 7;
1281 goto set_EPC;
1282 case EXCP_SYSCALL:
1283 cause = 8;
1284 update_badinstr = 1;
1285 goto set_EPC;
1286 case EXCP_BREAK:
1287 cause = 9;
1288 update_badinstr = 1;
1289 goto set_EPC;
1290 case EXCP_RI:
1291 cause = 10;
1292 update_badinstr = 1;
1293 goto set_EPC;
1294 case EXCP_CpU:
1295 cause = 11;
1296 update_badinstr = 1;
1297 env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
1298 (env->error_code << CP0Ca_CE);
1299 goto set_EPC;
1300 case EXCP_OVERFLOW:
1301 cause = 12;
1302 update_badinstr = 1;
1303 goto set_EPC;
1304 case EXCP_TRAP:
1305 cause = 13;
1306 update_badinstr = 1;
1307 goto set_EPC;
1308 case EXCP_MSAFPE:
1309 cause = 14;
1310 update_badinstr = 1;
1311 goto set_EPC;
1312 case EXCP_FPE:
1313 cause = 15;
1314 update_badinstr = 1;
1315 goto set_EPC;
1316 case EXCP_C2E:
1317 cause = 18;
1318 goto set_EPC;
1319 case EXCP_TLBRI:
1320 cause = 19;
1321 update_badinstr = 1;
1322 goto set_EPC;
1323 case EXCP_TLBXI:
1324 cause = 20;
1325 goto set_EPC;
1326 case EXCP_MSADIS:
1327 cause = 21;
1328 update_badinstr = 1;
1329 goto set_EPC;
1330 case EXCP_MDMX:
1331 cause = 22;
1332 goto set_EPC;
1333 case EXCP_DWATCH:
1334 cause = 23;
1335 /* XXX: TODO: manage deferred watch exceptions */
1336 goto set_EPC;
1337 case EXCP_MCHECK:
1338 cause = 24;
1339 goto set_EPC;
1340 case EXCP_THREAD:
1341 cause = 25;
1342 goto set_EPC;
1343 case EXCP_DSPDIS:
1344 cause = 26;
1345 goto set_EPC;
1346 case EXCP_CACHE:
1347 cause = 30;
1348 offset = 0x100;
1349 set_EPC:
1350 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
1351 env->CP0_EPC = exception_resume_pc(env);
1352 if (update_badinstr) {
1353 set_badinstr_registers(env);
1354 }
1355 if (env->hflags & MIPS_HFLAG_BMASK) {
1356 env->CP0_Cause |= (1U << CP0Ca_BD);
1357 } else {
1358 env->CP0_Cause &= ~(1U << CP0Ca_BD);
1359 }
1360 env->CP0_Status |= (1 << CP0St_EXL);
1361 if (env->insn_flags & ISA_MIPS3) {
1362 env->hflags |= MIPS_HFLAG_64;
1363 if (!(env->insn_flags & ISA_MIPS64R6) ||
1364 env->CP0_Status & (1 << CP0St_KX)) {
1365 env->hflags &= ~MIPS_HFLAG_AWRAP;
1366 }
1367 }
1368 env->hflags |= MIPS_HFLAG_CP0;
1369 env->hflags &= ~(MIPS_HFLAG_KSU);
1370 }
1371 env->hflags &= ~MIPS_HFLAG_BMASK;
1372 if (env->CP0_Status & (1 << CP0St_BEV)) {
1373 env->active_tc.PC = env->exception_base + 0x200;
1374 } else if (cause == 30 && !(env->CP0_Config3 & (1 << CP0C3_SC) &&
1375 env->CP0_Config5 & (1 << CP0C5_CV))) {
1376 /* Force KSeg1 for cache errors */
1377 env->active_tc.PC = KSEG1_BASE | (env->CP0_EBase & 0x1FFFF000);
1378 } else {
1379 env->active_tc.PC = env->CP0_EBase & ~0xfff;
1380 }
1381
1382 env->active_tc.PC += offset;
1383 set_hflags_for_handler(env);
1384 env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) |
1385 (cause << CP0Ca_EC);
1386 break;
1387 default:
1388 abort();
1389 }
1390 if (qemu_loglevel_mask(CPU_LOG_INT)
1391 && cs->exception_index != EXCP_EXT_INTERRUPT) {
1392 qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
1393 " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
1394 __func__, env->active_tc.PC, env->CP0_EPC, cause,
1395 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
1396 env->CP0_DEPC);
1397 }
1398 #endif
1399 cs->exception_index = EXCP_NONE;
1400 }
1401
1402 bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
1403 {
1404 if (interrupt_request & CPU_INTERRUPT_HARD) {
1405 MIPSCPU *cpu = MIPS_CPU(cs);
1406 CPUMIPSState *env = &cpu->env;
1407
1408 if (cpu_mips_hw_interrupts_enabled(env) &&
1409 cpu_mips_hw_interrupts_pending(env)) {
1410 /* Raise it */
1411 cs->exception_index = EXCP_EXT_INTERRUPT;
1412 env->error_code = 0;
1413 mips_cpu_do_interrupt(cs);
1414 return true;
1415 }
1416 }
1417 return false;
1418 }
1419
1420 #if !defined(CONFIG_USER_ONLY)
1421 void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
1422 {
1423 CPUState *cs = env_cpu(env);
1424 r4k_tlb_t *tlb;
1425 target_ulong addr;
1426 target_ulong end;
1427 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
1428 uint32_t MMID = env->CP0_MemoryMapID;
1429 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
1430 uint32_t tlb_mmid;
1431 target_ulong mask;
1432
1433 MMID = mi ? MMID : (uint32_t) ASID;
1434
1435 tlb = &env->tlb->mmu.r4k.tlb[idx];
1436 /*
1437 * The qemu TLB is flushed when the ASID/MMID changes, so no need to
1438 * flush these entries again.
1439 */
1440 tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID;
1441 if (tlb->G == 0 && tlb_mmid != MMID) {
1442 return;
1443 }
1444
1445 if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
1446 /*
1447 * For tlbwr, we can shadow the discarded entry into
1448 * a new (fake) TLB entry, as long as the guest can not
1449 * tell that it's there.
1450 */
1451 env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
1452 env->tlb->tlb_in_use++;
1453 return;
1454 }
1455
1456 /* 1k pages are not supported. */
1457 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1458 if (tlb->V0) {
1459 addr = tlb->VPN & ~mask;
1460 #if defined(TARGET_MIPS64)
1461 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
1462 addr |= 0x3FFFFF0000000000ULL;
1463 }
1464 #endif
1465 end = addr | (mask >> 1);
1466 while (addr < end) {
1467 tlb_flush_page(cs, addr);
1468 addr += TARGET_PAGE_SIZE;
1469 }
1470 }
1471 if (tlb->V1) {
1472 addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
1473 #if defined(TARGET_MIPS64)
1474 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
1475 addr |= 0x3FFFFF0000000000ULL;
1476 }
1477 #endif
1478 end = addr | mask;
1479 while (addr - 1 < end) {
1480 tlb_flush_page(cs, addr);
1481 addr += TARGET_PAGE_SIZE;
1482 }
1483 }
1484 }
1485 #endif
1486
1487 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
1488 uint32_t exception,
1489 int error_code,
1490 uintptr_t pc)
1491 {
1492 CPUState *cs = env_cpu(env);
1493
1494 qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n",
1495 __func__, exception, mips_exception_name(exception),
1496 error_code);
1497 cs->exception_index = exception;
1498 env->error_code = error_code;
1499
1500 cpu_loop_exit_restore(cs, pc);
1501 }
AR7 emulation for QEMU