2 * Q35 chipset based pc system emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2009, 2010
6 * Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
10 * This is based on pc.c, but heavily modified.
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 #include "hw/loader.h"
32 #include "sysemu/arch_init.h"
33 #include "hw/i2c/smbus.h"
34 #include "hw/boards.h"
35 #include "hw/timer/mc146818rtc.h"
36 #include "hw/xen/xen.h"
37 #include "sysemu/kvm.h"
38 #include "hw/kvm/clock.h"
39 #include "hw/pci-host/q35.h"
40 #include "exec/address-spaces.h"
41 #include "hw/i386/ich9.h"
42 #include "hw/i386/smbios.h"
43 #include "hw/ide/pci.h"
44 #include "hw/ide/ahci.h"
46 #include "hw/cpu/icc_bus.h"
47 #include "qemu/error-report.h"
49 /* ICH9 AHCI has 6 ports */
50 #define MAX_SATA_PORTS 6
52 static bool has_acpi_build
= true;
53 static bool smbios_defaults
= true;
54 static bool smbios_legacy_mode
;
55 static bool smbios_uuid_encoded
= true;
56 /* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to
57 * host addresses aligned at 1Gbyte boundaries. This way we can use 1GByte
60 static bool gigabyte_align
= true;
61 static bool has_reserved_memory
= true;
63 /* PC hardware initialisation */
64 static void pc_q35_init(MachineState
*machine
)
66 PCMachineState
*pc_machine
= PC_MACHINE(machine
);
67 ram_addr_t below_4g_mem_size
, above_4g_mem_size
;
72 BusState
*idebus
[MAX_SATA_PORTS
];
75 MemoryRegion
*pci_memory
;
76 MemoryRegion
*rom_memory
;
77 MemoryRegion
*ram_memory
;
85 ICH9LPCState
*ich9_lpc
;
87 DeviceState
*icc_bridge
;
88 PcGuestInfo
*guest_info
;
90 DriveInfo
*hd
[MAX_SATA_PORTS
];
92 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
93 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
94 * also known as MMCFG).
95 * If it doesn't, we need to split it in chunks below and above 4G.
96 * In any case, try to make sure that guest addresses aligned at
97 * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
98 * For old machine types, use whatever split we used historically to avoid
101 if (machine
->ram_size
>= 0xb0000000) {
102 lowmem
= gigabyte_align
? 0x80000000 : 0xb0000000;
107 /* Handle the machine opt max-ram-below-4g. It is basically doing
108 * min(qemu limit, user limit).
110 if (lowmem
> pc_machine
->max_ram_below_4g
) {
111 lowmem
= pc_machine
->max_ram_below_4g
;
112 if (machine
->ram_size
- lowmem
> lowmem
&&
113 lowmem
& ((1ULL << 30) - 1)) {
114 error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64
115 ") not a multiple of 1G; possible bad performance.",
116 pc_machine
->max_ram_below_4g
);
120 if (machine
->ram_size
>= lowmem
) {
121 above_4g_mem_size
= machine
->ram_size
- lowmem
;
122 below_4g_mem_size
= lowmem
;
124 above_4g_mem_size
= 0;
125 below_4g_mem_size
= machine
->ram_size
;
128 if (xen_enabled() && xen_hvm_init(&below_4g_mem_size
, &above_4g_mem_size
,
130 fprintf(stderr
, "xen hardware virtual machine initialisation failed\n");
134 icc_bridge
= qdev_create(NULL
, TYPE_ICC_BRIDGE
);
135 object_property_add_child(qdev_get_machine(), "icc-bridge",
136 OBJECT(icc_bridge
), NULL
);
138 pc_cpus_init(machine
->cpu_model
, icc_bridge
);
139 pc_acpi_init("q35-acpi-dsdt.aml");
145 pci_memory
= g_new(MemoryRegion
, 1);
146 memory_region_init(pci_memory
, NULL
, "pci", UINT64_MAX
);
147 rom_memory
= pci_memory
;
150 rom_memory
= get_system_memory();
153 guest_info
= pc_guest_info_init(below_4g_mem_size
, above_4g_mem_size
);
154 guest_info
->isapc_ram_fw
= false;
155 guest_info
->has_acpi_build
= has_acpi_build
;
156 guest_info
->has_reserved_memory
= has_reserved_memory
;
158 /* Migration was not supported in 2.0 for Q35, so do not bother
159 * with this hack (see hw/i386/acpi-build.c).
161 guest_info
->legacy_acpi_table_size
= 0;
163 if (smbios_defaults
) {
164 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
165 /* These values are guest ABI, do not change */
166 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
167 mc
->name
, smbios_legacy_mode
, smbios_uuid_encoded
);
170 /* allocate ram and load rom/bios */
171 if (!xen_enabled()) {
172 pc_memory_init(machine
, get_system_memory(),
173 below_4g_mem_size
, above_4g_mem_size
,
174 rom_memory
, &ram_memory
, guest_info
);
178 gsi_state
= g_malloc0(sizeof(*gsi_state
));
179 if (kvm_irqchip_in_kernel()) {
180 kvm_pc_setup_irq_routing(pci_enabled
);
181 gsi
= qemu_allocate_irqs(kvm_pc_gsi_handler
, gsi_state
,
184 gsi
= qemu_allocate_irqs(gsi_handler
, gsi_state
, GSI_NUM_PINS
);
187 /* create pci host bus */
188 q35_host
= Q35_HOST_DEVICE(qdev_create(NULL
, TYPE_Q35_HOST_DEVICE
));
190 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host
), NULL
);
191 q35_host
->mch
.ram_memory
= ram_memory
;
192 q35_host
->mch
.pci_address_space
= pci_memory
;
193 q35_host
->mch
.system_memory
= get_system_memory();
194 q35_host
->mch
.address_space_io
= get_system_io();
195 q35_host
->mch
.below_4g_mem_size
= below_4g_mem_size
;
196 q35_host
->mch
.above_4g_mem_size
= above_4g_mem_size
;
197 q35_host
->mch
.guest_info
= guest_info
;
199 qdev_init_nofail(DEVICE(q35_host
));
200 phb
= PCI_HOST_BRIDGE(q35_host
);
203 lpc
= pci_create_simple_multifunction(host_bus
, PCI_DEVFN(ICH9_LPC_DEV
,
204 ICH9_LPC_FUNC
), true,
205 TYPE_ICH9_LPC_DEVICE
);
207 object_property_add_link(OBJECT(machine
), PC_MACHINE_ACPI_DEVICE_PROP
,
208 TYPE_HOTPLUG_HANDLER
,
209 (Object
**)&pc_machine
->acpi_dev
,
210 object_property_allow_set_link
,
211 OBJ_PROP_LINK_UNREF_ON_RELEASE
, &error_abort
);
212 object_property_set_link(OBJECT(machine
), OBJECT(lpc
),
213 PC_MACHINE_ACPI_DEVICE_PROP
, &error_abort
);
215 ich9_lpc
= ICH9_LPC_DEVICE(lpc
);
217 ich9_lpc
->ioapic
= gsi_state
->ioapic_irq
;
218 pci_bus_irqs(host_bus
, ich9_lpc_set_irq
, ich9_lpc_map_irq
, ich9_lpc
,
220 pci_bus_set_route_irq_fn(host_bus
, ich9_route_intx_pin_to_irq
);
221 isa_bus
= ich9_lpc
->isa_bus
;
224 isa_bus_irqs(isa_bus
, gsi
);
226 if (kvm_irqchip_in_kernel()) {
227 i8259
= kvm_i8259_init(isa_bus
);
228 } else if (xen_enabled()) {
229 i8259
= xen_interrupt_controller_init();
231 cpu_irq
= pc_allocate_cpu_irq();
232 i8259
= i8259_init(isa_bus
, cpu_irq
[0]);
235 for (i
= 0; i
< ISA_NUM_IRQS
; i
++) {
236 gsi_state
->i8259_irq
[i
] = i8259
[i
];
239 ioapic_init_gsi(gsi_state
, "q35");
241 qdev_init_nofail(icc_bridge
);
243 pc_register_ferr_irq(gsi
[13]);
245 assert(pc_machine
->vmport
!= ON_OFF_AUTO_MAX
);
246 if (pc_machine
->vmport
== ON_OFF_AUTO_AUTO
) {
247 pc_machine
->vmport
= xen_enabled() ? ON_OFF_AUTO_OFF
: ON_OFF_AUTO_ON
;
250 /* init basic PC hardware */
251 pc_basic_device_init(isa_bus
, gsi
, &rtc_state
, &floppy
,
252 (pc_machine
->vmport
!= ON_OFF_AUTO_ON
), 0xff0104);
254 /* connect pm stuff to lpc */
255 ich9_lpc_pm_init(lpc
);
257 /* ahci and SATA device, for q35 1 ahci controller is built-in */
258 ahci
= pci_create_simple_multifunction(host_bus
,
259 PCI_DEVFN(ICH9_SATA1_DEV
,
262 idebus
[0] = qdev_get_child_bus(&ahci
->qdev
, "ide.0");
263 idebus
[1] = qdev_get_child_bus(&ahci
->qdev
, "ide.1");
264 g_assert(MAX_SATA_PORTS
== ICH_AHCI(ahci
)->ahci
.ports
);
265 ide_drive_get(hd
, ICH_AHCI(ahci
)->ahci
.ports
);
266 ahci_ide_create_devs(ahci
, hd
);
269 /* Should we create 6 UHCI according to ich9 spec? */
270 ehci_create_ich9_with_companions(host_bus
, 0x1d);
273 /* TODO: Populate SPD eeprom data. */
274 smbus_eeprom_init(ich9_smb_init(host_bus
,
275 PCI_DEVFN(ICH9_SMB_DEV
, ICH9_SMB_FUNC
),
279 pc_cmos_init(below_4g_mem_size
, above_4g_mem_size
, machine
->boot_order
,
280 machine
, floppy
, idebus
[0], idebus
[1], rtc_state
);
282 /* the rest devices to which pci devfn is automatically assigned */
283 pc_vga_init(isa_bus
, host_bus
);
284 pc_nic_init(isa_bus
, host_bus
);
286 pc_pci_device_init(host_bus
);
290 static void pc_compat_2_2(MachineState
*machine
)
292 x86_cpu_compat_set_features("kvm64", FEAT_1_EDX
, 0, CPUID_VME
);
293 x86_cpu_compat_set_features("kvm32", FEAT_1_EDX
, 0, CPUID_VME
);
294 x86_cpu_compat_set_features("Conroe", FEAT_1_EDX
, 0, CPUID_VME
);
295 x86_cpu_compat_set_features("Penryn", FEAT_1_EDX
, 0, CPUID_VME
);
296 x86_cpu_compat_set_features("Nehalem", FEAT_1_EDX
, 0, CPUID_VME
);
297 x86_cpu_compat_set_features("Westmere", FEAT_1_EDX
, 0, CPUID_VME
);
298 x86_cpu_compat_set_features("SandyBridge", FEAT_1_EDX
, 0, CPUID_VME
);
299 x86_cpu_compat_set_features("Haswell", FEAT_1_EDX
, 0, CPUID_VME
);
300 x86_cpu_compat_set_features("Broadwell", FEAT_1_EDX
, 0, CPUID_VME
);
301 x86_cpu_compat_set_features("Opteron_G1", FEAT_1_EDX
, 0, CPUID_VME
);
302 x86_cpu_compat_set_features("Opteron_G2", FEAT_1_EDX
, 0, CPUID_VME
);
303 x86_cpu_compat_set_features("Opteron_G3", FEAT_1_EDX
, 0, CPUID_VME
);
304 x86_cpu_compat_set_features("Opteron_G4", FEAT_1_EDX
, 0, CPUID_VME
);
305 x86_cpu_compat_set_features("Opteron_G5", FEAT_1_EDX
, 0, CPUID_VME
);
306 x86_cpu_compat_set_features("Haswell", FEAT_1_ECX
, 0, CPUID_EXT_F16C
);
307 x86_cpu_compat_set_features("Haswell", FEAT_1_ECX
, 0, CPUID_EXT_RDRAND
);
308 x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX
, 0, CPUID_EXT_F16C
);
309 x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX
, 0, CPUID_EXT_RDRAND
);
312 static void pc_compat_2_1(MachineState
*machine
)
314 PCMachineState
*pcms
= PC_MACHINE(machine
);
316 pc_compat_2_2(machine
);
317 pcms
->enforce_aligned_dimm
= false;
318 smbios_uuid_encoded
= false;
319 x86_cpu_compat_set_features("coreduo", FEAT_1_ECX
, CPUID_EXT_VMX
, 0);
320 x86_cpu_compat_set_features("core2duo", FEAT_1_ECX
, CPUID_EXT_VMX
, 0);
321 x86_cpu_compat_kvm_no_autodisable(FEAT_8000_0001_ECX
, CPUID_EXT3_SVM
);
324 static void pc_compat_2_0(MachineState
*machine
)
326 pc_compat_2_1(machine
);
327 smbios_legacy_mode
= true;
328 has_reserved_memory
= false;
329 pc_set_legacy_acpi_data_size();
332 static void pc_compat_1_7(MachineState
*machine
)
334 pc_compat_2_0(machine
);
335 smbios_defaults
= false;
336 gigabyte_align
= false;
337 option_rom_has_mr
= true;
338 x86_cpu_compat_kvm_no_autoenable(FEAT_1_ECX
, CPUID_EXT_X2APIC
);
341 static void pc_compat_1_6(MachineState
*machine
)
343 pc_compat_1_7(machine
);
344 rom_file_has_mr
= false;
345 has_acpi_build
= false;
348 static void pc_compat_1_5(MachineState
*machine
)
350 pc_compat_1_6(machine
);
353 static void pc_compat_1_4(MachineState
*machine
)
355 pc_compat_1_5(machine
);
356 x86_cpu_compat_set_features("n270", FEAT_1_ECX
, 0, CPUID_EXT_MOVBE
);
357 x86_cpu_compat_set_features("Westmere", FEAT_1_ECX
, 0, CPUID_EXT_PCLMULQDQ
);
360 static void pc_q35_init_2_2(MachineState
*machine
)
362 pc_compat_2_2(machine
);
363 pc_q35_init(machine
);
366 static void pc_q35_init_2_1(MachineState
*machine
)
368 pc_compat_2_1(machine
);
369 pc_q35_init(machine
);
372 static void pc_q35_init_2_0(MachineState
*machine
)
374 pc_compat_2_0(machine
);
375 pc_q35_init(machine
);
378 static void pc_q35_init_1_7(MachineState
*machine
)
380 pc_compat_1_7(machine
);
381 pc_q35_init(machine
);
384 static void pc_q35_init_1_6(MachineState
*machine
)
386 pc_compat_1_6(machine
);
387 pc_q35_init(machine
);
390 static void pc_q35_init_1_5(MachineState
*machine
)
392 pc_compat_1_5(machine
);
393 pc_q35_init(machine
);
396 static void pc_q35_init_1_4(MachineState
*machine
)
398 pc_compat_1_4(machine
);
399 pc_q35_init(machine
);
402 #define PC_Q35_MACHINE_OPTIONS \
403 PC_DEFAULT_MACHINE_OPTIONS, \
404 .family = "pc_q35", \
405 .desc = "Standard PC (Q35 + ICH9, 2009)", \
406 .hot_add_cpu = pc_hot_add_cpu, \
407 .units_per_default_bus = 1
409 #define PC_Q35_2_3_MACHINE_OPTIONS \
410 PC_Q35_MACHINE_OPTIONS, \
411 .default_machine_opts = "firmware=bios-256k.bin", \
412 .default_display = "std"
414 static QEMUMachine pc_q35_machine_v2_3
= {
415 PC_Q35_2_3_MACHINE_OPTIONS
,
416 .name
= "pc-q35-2.3",
421 #define PC_Q35_2_2_MACHINE_OPTIONS PC_Q35_2_3_MACHINE_OPTIONS
423 static QEMUMachine pc_q35_machine_v2_2
= {
424 PC_Q35_2_2_MACHINE_OPTIONS
,
425 .name
= "pc-q35-2.2",
426 .init
= pc_q35_init_2_2
,
429 #define PC_Q35_2_1_MACHINE_OPTIONS \
430 PC_Q35_MACHINE_OPTIONS, \
431 .default_machine_opts = "firmware=bios-256k.bin"
433 static QEMUMachine pc_q35_machine_v2_1
= {
434 PC_Q35_2_1_MACHINE_OPTIONS
,
435 .name
= "pc-q35-2.1",
436 .init
= pc_q35_init_2_1
,
437 .compat_props
= (GlobalProperty
[]) {
439 { /* end of list */ }
443 #define PC_Q35_2_0_MACHINE_OPTIONS PC_Q35_2_1_MACHINE_OPTIONS
445 static QEMUMachine pc_q35_machine_v2_0
= {
446 PC_Q35_2_0_MACHINE_OPTIONS
,
447 .name
= "pc-q35-2.0",
448 .init
= pc_q35_init_2_0
,
449 .compat_props
= (GlobalProperty
[]) {
451 { /* end of list */ }
455 #define PC_Q35_1_7_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS
457 static QEMUMachine pc_q35_machine_v1_7
= {
458 PC_Q35_1_7_MACHINE_OPTIONS
,
459 .name
= "pc-q35-1.7",
460 .init
= pc_q35_init_1_7
,
461 .compat_props
= (GlobalProperty
[]) {
463 { /* end of list */ }
467 #define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS
469 static QEMUMachine pc_q35_machine_v1_6
= {
470 PC_Q35_1_6_MACHINE_OPTIONS
,
471 .name
= "pc-q35-1.6",
472 .init
= pc_q35_init_1_6
,
473 .compat_props
= (GlobalProperty
[]) {
475 { /* end of list */ }
479 static QEMUMachine pc_q35_machine_v1_5
= {
480 PC_Q35_1_6_MACHINE_OPTIONS
,
481 .name
= "pc-q35-1.5",
482 .init
= pc_q35_init_1_5
,
483 .compat_props
= (GlobalProperty
[]) {
485 { /* end of list */ }
489 #define PC_Q35_1_4_MACHINE_OPTIONS \
490 PC_Q35_1_6_MACHINE_OPTIONS, \
493 static QEMUMachine pc_q35_machine_v1_4
= {
494 PC_Q35_1_4_MACHINE_OPTIONS
,
495 .name
= "pc-q35-1.4",
496 .init
= pc_q35_init_1_4
,
497 .compat_props
= (GlobalProperty
[]) {
499 { /* end of list */ }
503 static void pc_q35_machine_init(void)
505 qemu_register_pc_machine(&pc_q35_machine_v2_3
);
506 qemu_register_pc_machine(&pc_q35_machine_v2_2
);
507 qemu_register_pc_machine(&pc_q35_machine_v2_1
);
508 qemu_register_pc_machine(&pc_q35_machine_v2_0
);
509 qemu_register_pc_machine(&pc_q35_machine_v1_7
);
510 qemu_register_pc_machine(&pc_q35_machine_v1_6
);
511 qemu_register_pc_machine(&pc_q35_machine_v1_5
);
512 qemu_register_pc_machine(&pc_q35_machine_v1_4
);
515 machine_init(pc_q35_machine_init
);