hw/sparc64/sun4u_iommu.c

   1 /*
   2  * QEMU sun4u IOMMU emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2012,2013 Artyom Tarasenko
   6  * Copyright (c) 2017 Mark Cave-Ayland
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #include "qemu/osdep.h"
  28 #include "hw/sysbus.h"
  29 #include "hw/sparc/sun4u_iommu.h"
  30 #include "exec/address-spaces.h"
  31 #include "qapi/error.h"
  32 #include "qemu/log.h"
  33 #include "trace.h"
  34
  35
  36 #define IOMMU_PAGE_SIZE_8K      (1ULL << 13)
  37 #define IOMMU_PAGE_MASK_8K      (~(IOMMU_PAGE_SIZE_8K - 1))
  38 #define IOMMU_PAGE_SIZE_64K     (1ULL << 16)
  39 #define IOMMU_PAGE_MASK_64K     (~(IOMMU_PAGE_SIZE_64K - 1))
  40
  41 #define IOMMU_CTRL              0x0
  42 #define IOMMU_CTRL_TBW_SIZE     (1ULL << 2)
  43 #define IOMMU_CTRL_MMU_EN       (1ULL)
  44
  45 #define IOMMU_CTRL_TSB_SHIFT    16
  46
  47 #define IOMMU_BASE              0x8
  48 #define IOMMU_FLUSH             0x10
  49
  50 #define IOMMU_TTE_DATA_V        (1ULL << 63)
  51 #define IOMMU_TTE_DATA_SIZE     (1ULL << 61)
  52 #define IOMMU_TTE_DATA_W        (1ULL << 1)
  53
  54 #define IOMMU_TTE_PHYS_MASK_8K  0x1ffffffe000ULL
  55 #define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL
  56
  57 #define IOMMU_TSB_8K_OFFSET_MASK_8M    0x00000000007fe000ULL
  58 #define IOMMU_TSB_8K_OFFSET_MASK_16M   0x0000000000ffe000ULL
  59 #define IOMMU_TSB_8K_OFFSET_MASK_32M   0x0000000001ffe000ULL
  60 #define IOMMU_TSB_8K_OFFSET_MASK_64M   0x0000000003ffe000ULL
  61 #define IOMMU_TSB_8K_OFFSET_MASK_128M  0x0000000007ffe000ULL
  62 #define IOMMU_TSB_8K_OFFSET_MASK_256M  0x000000000fffe000ULL
  63 #define IOMMU_TSB_8K_OFFSET_MASK_512M  0x000000001fffe000ULL
  64 #define IOMMU_TSB_8K_OFFSET_MASK_1G    0x000000003fffe000ULL
  65
  66 #define IOMMU_TSB_64K_OFFSET_MASK_64M  0x0000000003ff0000ULL
  67 #define IOMMU_TSB_64K_OFFSET_MASK_128M 0x0000000007ff0000ULL
  68 #define IOMMU_TSB_64K_OFFSET_MASK_256M 0x000000000fff0000ULL
  69 #define IOMMU_TSB_64K_OFFSET_MASK_512M 0x000000001fff0000ULL
  70 #define IOMMU_TSB_64K_OFFSET_MASK_1G   0x000000003fff0000ULL
  71 #define IOMMU_TSB_64K_OFFSET_MASK_2G   0x000000007fff0000ULL
  72
  73
  74 /* Called from RCU critical section */
  75 static IOMMUTLBEntry sun4u_translate_iommu(IOMMUMemoryRegion *iommu,
  76                                            hwaddr addr,
  77                                            IOMMUAccessFlags flag)
  78 {
  79     IOMMUState *is = container_of(iommu, IOMMUState, iommu);
  80     hwaddr baseaddr, offset;
  81     uint64_t tte;
  82     uint32_t tsbsize;
  83     IOMMUTLBEntry ret = {
  84         .target_as = &address_space_memory,
  85         .iova = 0,
  86         .translated_addr = 0,
  87         .addr_mask = ~(hwaddr)0,
  88         .perm = IOMMU_NONE,
  89     };
  90
  91     if (!(is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_MMU_EN)) {
  92         /* IOMMU disabled, passthrough using standard 8K page */
  93         ret.iova = addr & IOMMU_PAGE_MASK_8K;
  94         ret.translated_addr = addr;
  95         ret.addr_mask = IOMMU_PAGE_MASK_8K;
  96         ret.perm = IOMMU_RW;
  97
  98         return ret;
  99     }
 100
 101     baseaddr = is->regs[IOMMU_BASE >> 3];
 102     tsbsize = (is->regs[IOMMU_CTRL >> 3] >> IOMMU_CTRL_TSB_SHIFT) & 0x7;
 103
 104     if (is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_TBW_SIZE) {
 105         /* 64K */
 106         switch (tsbsize) {
 107         case 0:
 108             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_64M) >> 13;
 109             break;
 110         case 1:
 111             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_128M) >> 13;
 112             break;
 113         case 2:
 114             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_256M) >> 13;
 115             break;
 116         case 3:
 117             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_512M) >> 13;
 118             break;
 119         case 4:
 120             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_1G) >> 13;
 121             break;
 122         case 5:
 123             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_2G) >> 13;
 124             break;
 125         default:
 126             /* Not implemented, error */
 127             return ret;
 128         }
 129     } else {
 130         /* 8K */
 131         switch (tsbsize) {
 132         case 0:
 133             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_8M) >> 10;
 134             break;
 135         case 1:
 136             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_16M) >> 10;
 137             break;
 138         case 2:
 139             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_32M) >> 10;
 140             break;
 141         case 3:
 142             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_64M) >> 10;
 143             break;
 144         case 4:
 145             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_128M) >> 10;
 146             break;
 147         case 5:
 148             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_256M) >> 10;
 149             break;
 150         case 6:
 151             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_512M) >> 10;
 152             break;
 153         case 7:
 154             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_1G) >> 10;
 155             break;
 156         }
 157     }
 158
 159     tte = address_space_ldq_be(&address_space_memory, baseaddr + offset,
 160                                MEMTXATTRS_UNSPECIFIED, NULL);
 161
 162     if (!(tte & IOMMU_TTE_DATA_V)) {
 163         /* Invalid mapping */
 164         return ret;
 165     }
 166
 167     if (tte & IOMMU_TTE_DATA_W) {
 168         /* Writeable */
 169         ret.perm = IOMMU_RW;
 170     } else {
 171         ret.perm = IOMMU_RO;
 172     }
 173
 174     /* Extract phys */
 175     if (tte & IOMMU_TTE_DATA_SIZE) {
 176         /* 64K */
 177         ret.iova = addr & IOMMU_PAGE_MASK_64K;
 178         ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_64K;
 179         ret.addr_mask = (IOMMU_PAGE_SIZE_64K - 1);
 180     } else {
 181         /* 8K */
 182         ret.iova = addr & IOMMU_PAGE_MASK_8K;
 183         ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_8K;
 184         ret.addr_mask = (IOMMU_PAGE_SIZE_8K - 1);
 185     }
 186
 187     return ret;
 188 }
 189
 190 static void iommu_mem_write(void *opaque, hwaddr addr,
 191                             uint64_t val, unsigned size)
 192 {
 193     IOMMUState *is = opaque;
 194
 195     trace_sun4u_iommu_mem_write(addr, val, size);
 196
 197     switch (addr) {
 198     case IOMMU_CTRL:
 199         if (size == 4) {
 200             is->regs[IOMMU_CTRL >> 3] &= 0xffffffffULL;
 201             is->regs[IOMMU_CTRL >> 3] |= val << 32;
 202         } else {
 203             is->regs[IOMMU_CTRL >> 3] = val;
 204         }
 205         break;
 206     case IOMMU_CTRL + 0x4:
 207         is->regs[IOMMU_CTRL >> 3] &= 0xffffffff00000000ULL;
 208         is->regs[IOMMU_CTRL >> 3] |= val & 0xffffffffULL;
 209         break;
 210     case IOMMU_BASE:
 211         if (size == 4) {
 212             is->regs[IOMMU_BASE >> 3] &= 0xffffffffULL;
 213             is->regs[IOMMU_BASE >> 3] |= val << 32;
 214         } else {
 215             is->regs[IOMMU_BASE >> 3] = val;
 216         }
 217         break;
 218     case IOMMU_BASE + 0x4:
 219         is->regs[IOMMU_BASE >> 3] &= 0xffffffff00000000ULL;
 220         is->regs[IOMMU_BASE >> 3] |= val & 0xffffffffULL;
 221         break;
 222     case IOMMU_FLUSH:
 223     case IOMMU_FLUSH + 0x4:
 224         break;
 225     default:
 226         qemu_log_mask(LOG_UNIMP,
 227                   "sun4u-iommu: Unimplemented register write "
 228                   "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",
 229                   addr, size, val);
 230         break;
 231     }
 232 }
 233
 234 static uint64_t iommu_mem_read(void *opaque, hwaddr addr, unsigned size)
 235 {
 236     IOMMUState *is = opaque;
 237     uint64_t val;
 238
 239     switch (addr) {
 240     case IOMMU_CTRL:
 241         if (size == 4) {
 242             val = is->regs[IOMMU_CTRL >> 3] >> 32;
 243         } else {
 244             val = is->regs[IOMMU_CTRL >> 3];
 245         }
 246         break;
 247     case IOMMU_CTRL + 0x4:
 248         val = is->regs[IOMMU_CTRL >> 3] & 0xffffffffULL;
 249         break;
 250     case IOMMU_BASE:
 251         if (size == 4) {
 252             val = is->regs[IOMMU_BASE >> 3] >> 32;
 253         } else {
 254             val = is->regs[IOMMU_BASE >> 3];
 255         }
 256         break;
 257     case IOMMU_BASE + 0x4:
 258         val = is->regs[IOMMU_BASE >> 3] & 0xffffffffULL;
 259         break;
 260     case IOMMU_FLUSH:
 261     case IOMMU_FLUSH + 0x4:
 262         val = 0;
 263         break;
 264     default:
 265         qemu_log_mask(LOG_UNIMP,
 266                       "sun4u-iommu: Unimplemented register read "
 267                       "reg 0x%" HWADDR_PRIx " size 0x%x\n",
 268                       addr, size);
 269         val = 0;
 270         break;
 271     }
 272
 273     trace_sun4u_iommu_mem_read(addr, val, size);
 274
 275     return val;
 276 }
 277
 278 static const MemoryRegionOps iommu_mem_ops = {
 279     .read = iommu_mem_read,
 280     .write = iommu_mem_write,
 281     .endianness = DEVICE_BIG_ENDIAN,
 282 };
 283
 284 static void iommu_reset(DeviceState *d)
 285 {
 286     IOMMUState *s = SUN4U_IOMMU(d);
 287
 288     memset(s->regs, 0, IOMMU_NREGS * sizeof(uint64_t));
 289 }
 290
 291 static void iommu_init(Object *obj)
 292 {
 293     IOMMUState *s = SUN4U_IOMMU(obj);
 294     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 295
 296     memory_region_init_iommu(&s->iommu, sizeof(s->iommu),
 297                              TYPE_SUN4U_IOMMU_MEMORY_REGION, OBJECT(s),
 298                              "iommu-sun4u", UINT64_MAX);
 299     address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "iommu-as");
 300
 301     memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu",
 302                           IOMMU_NREGS * sizeof(uint64_t));
 303     sysbus_init_mmio(sbd, &s->iomem);
 304 }
 305
 306 static void iommu_class_init(ObjectClass *klass, void *data)
 307 {
 308     DeviceClass *dc = DEVICE_CLASS(klass);
 309
 310     dc->reset = iommu_reset;
 311 }
 312
 313 static const TypeInfo iommu_info = {
 314     .name          = TYPE_SUN4U_IOMMU,
 315     .parent        = TYPE_SYS_BUS_DEVICE,
 316     .instance_size = sizeof(IOMMUState),
 317     .instance_init = iommu_init,
 318     .class_init    = iommu_class_init,
 319 };
 320
 321 static void sun4u_iommu_memory_region_class_init(ObjectClass *klass, void *data)
 322 {
 323     IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
 324
 325     imrc->translate = sun4u_translate_iommu;
 326 }
 327
 328 static const TypeInfo sun4u_iommu_memory_region_info = {
 329     .parent = TYPE_IOMMU_MEMORY_REGION,
 330     .name = TYPE_SUN4U_IOMMU_MEMORY_REGION,
 331     .class_init = sun4u_iommu_memory_region_class_init,
 332 };
 333
 334 static void iommu_register_types(void)
 335 {
 336     type_register_static(&iommu_info);
 337     type_register_static(&sun4u_iommu_memory_region_info);
 338 }
 339
 340 type_init(iommu_register_types)