ARM: PL061: Checking register r/w accesses to reserved area
[qemu/ar7.git] / target-i386 / mpx_helper.c
blob4d1785ecefd86a0dbb1e307bd58e808390d2198b
1 /*
2 * x86 MPX helpers
4 * Copyright (c) 2015 Red Hat, Inc.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/helper-proto.h"
23 #include "exec/cpu_ldst.h"
26 void cpu_sync_bndcs_hflags(CPUX86State *env)
28 uint32_t hflags = env->hflags;
29 uint32_t hflags2 = env->hflags2;
30 uint32_t bndcsr;
32 if ((hflags & HF_CPL_MASK) == 3) {
33 bndcsr = env->bndcs_regs.cfgu;
34 } else {
35 bndcsr = env->msr_bndcfgs;
38 if ((env->cr[4] & CR4_OSXSAVE_MASK)
39 && (env->xcr0 & XSTATE_BNDCSR_MASK)
40 && (bndcsr & BNDCFG_ENABLE)) {
41 hflags |= HF_MPX_EN_MASK;
42 } else {
43 hflags &= ~HF_MPX_EN_MASK;
46 if (bndcsr & BNDCFG_BNDPRESERVE) {
47 hflags2 |= HF2_MPX_PR_MASK;
48 } else {
49 hflags2 &= ~HF2_MPX_PR_MASK;
52 env->hflags = hflags;
53 env->hflags2 = hflags2;
56 void helper_bndck(CPUX86State *env, uint32_t fail)
58 if (unlikely(fail)) {
59 env->bndcs_regs.sts = 1;
60 raise_exception_ra(env, EXCP05_BOUND, GETPC());
64 static uint64_t lookup_bte64(CPUX86State *env, uint64_t base, uintptr_t ra)
66 uint64_t bndcsr, bde, bt;
68 if ((env->hflags & HF_CPL_MASK) == 3) {
69 bndcsr = env->bndcs_regs.cfgu;
70 } else {
71 bndcsr = env->msr_bndcfgs;
74 bde = (extract64(base, 20, 28) << 3) + (extract64(bndcsr, 20, 44) << 12);
75 bt = cpu_ldq_data_ra(env, bde, ra);
76 if ((bt & 1) == 0) {
77 env->bndcs_regs.sts = bde | 2;
78 raise_exception_ra(env, EXCP05_BOUND, ra);
81 return (extract64(base, 3, 17) << 5) + (bt & ~7);
84 static uint32_t lookup_bte32(CPUX86State *env, uint32_t base, uintptr_t ra)
86 uint32_t bndcsr, bde, bt;
88 if ((env->hflags & HF_CPL_MASK) == 3) {
89 bndcsr = env->bndcs_regs.cfgu;
90 } else {
91 bndcsr = env->msr_bndcfgs;
94 bde = (extract32(base, 12, 20) << 2) + (bndcsr & TARGET_PAGE_MASK);
95 bt = cpu_ldl_data_ra(env, bde, ra);
96 if ((bt & 1) == 0) {
97 env->bndcs_regs.sts = bde | 2;
98 raise_exception_ra(env, EXCP05_BOUND, ra);
101 return (extract32(base, 2, 10) << 4) + (bt & ~3);
104 uint64_t helper_bndldx64(CPUX86State *env, target_ulong base, target_ulong ptr)
106 uintptr_t ra = GETPC();
107 uint64_t bte, lb, ub, pt;
109 bte = lookup_bte64(env, base, ra);
110 lb = cpu_ldq_data_ra(env, bte, ra);
111 ub = cpu_ldq_data_ra(env, bte + 8, ra);
112 pt = cpu_ldq_data_ra(env, bte + 16, ra);
114 if (pt != ptr) {
115 lb = ub = 0;
117 env->mmx_t0.MMX_Q(0) = ub;
118 return lb;
121 uint64_t helper_bndldx32(CPUX86State *env, target_ulong base, target_ulong ptr)
123 uintptr_t ra = GETPC();
124 uint32_t bte, lb, ub, pt;
126 bte = lookup_bte32(env, base, ra);
127 lb = cpu_ldl_data_ra(env, bte, ra);
128 ub = cpu_ldl_data_ra(env, bte + 4, ra);
129 pt = cpu_ldl_data_ra(env, bte + 8, ra);
131 if (pt != ptr) {
132 lb = ub = 0;
134 return ((uint64_t)ub << 32) | lb;
137 void helper_bndstx64(CPUX86State *env, target_ulong base, target_ulong ptr,
138 uint64_t lb, uint64_t ub)
140 uintptr_t ra = GETPC();
141 uint64_t bte;
143 bte = lookup_bte64(env, base, ra);
144 cpu_stq_data_ra(env, bte, lb, ra);
145 cpu_stq_data_ra(env, bte + 8, ub, ra);
146 cpu_stq_data_ra(env, bte + 16, ptr, ra);
149 void helper_bndstx32(CPUX86State *env, target_ulong base, target_ulong ptr,
150 uint64_t lb, uint64_t ub)
152 uintptr_t ra = GETPC();
153 uint32_t bte;
155 bte = lookup_bte32(env, base, ra);
156 cpu_stl_data_ra(env, bte, lb, ra);
157 cpu_stl_data_ra(env, bte + 4, ub, ra);
158 cpu_stl_data_ra(env, bte + 8, ptr, ra);
161 void helper_bnd_jmp(CPUX86State *env)
163 if (!(env->hflags2 & HF2_MPX_PR_MASK)) {
164 memset(env->bnd_regs, 0, sizeof(env->bnd_regs));
165 env->hflags &= ~HF_MPX_IU_MASK;