target/ppc/ppc-qmp-cmds.c

   1 /*
   2  * QEMU PPC (monitor definitions)
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "cpu.h"
  27 #include "monitor/monitor.h"
  28 #include "qemu/ctype.h"
  29 #include "monitor/hmp-target.h"
  30 #include "monitor/hmp.h"
  31 #include "qapi/qapi-commands-machine-target.h"
  32 #include "cpu-models.h"
  33 #include "cpu-qom.h"
  34
  35 static target_long monitor_get_ccr(Monitor *mon, const struct MonitorDef *md,
  36                                    int val)
  37 {
  38     CPUArchState *env = mon_get_cpu_env(mon);
  39     unsigned int u;
  40
  41     u = ppc_get_cr(env);
  42
  43     return u;
  44 }
  45
  46 static target_long monitor_get_xer(Monitor *mon, const struct MonitorDef *md,
  47                                    int val)
  48 {
  49     CPUArchState *env = mon_get_cpu_env(mon);
  50     return cpu_read_xer(env);
  51 }
  52
  53 static target_long monitor_get_decr(Monitor *mon, const struct MonitorDef *md,
  54                                     int val)
  55 {
  56     CPUArchState *env = mon_get_cpu_env(mon);
  57     if (!env->tb_env) {
  58         return 0;
  59     }
  60     return cpu_ppc_load_decr(env);
  61 }
  62
  63 static target_long monitor_get_tbu(Monitor *mon, const struct MonitorDef *md,
  64                                    int val)
  65 {
  66     CPUArchState *env = mon_get_cpu_env(mon);
  67     if (!env->tb_env) {
  68         return 0;
  69     }
  70     return cpu_ppc_load_tbu(env);
  71 }
  72
  73 static target_long monitor_get_tbl(Monitor *mon, const struct MonitorDef *md,
  74                                    int val)
  75 {
  76     CPUArchState *env = mon_get_cpu_env(mon);
  77     if (!env->tb_env) {
  78         return 0;
  79     }
  80     return cpu_ppc_load_tbl(env);
  81 }
  82
  83 void hmp_info_tlb(Monitor *mon, const QDict *qdict)
  84 {
  85     CPUArchState *env1 = mon_get_cpu_env(mon);
  86
  87     if (!env1) {
  88         monitor_printf(mon, "No CPU available\n");
  89         return;
  90     }
  91     dump_mmu(env1);
  92 }
  93
  94 const MonitorDef monitor_defs[] = {
  95     { "fpscr", offsetof(CPUPPCState, fpscr) },
  96     /* Next instruction pointer */
  97     { "nip|pc", offsetof(CPUPPCState, nip) },
  98     { "lr", offsetof(CPUPPCState, lr) },
  99     { "ctr", offsetof(CPUPPCState, ctr) },
 100     { "decr", 0, &monitor_get_decr, },
 101     { "ccr|cr", 0, &monitor_get_ccr, },
 102     /* Machine state register */
 103     { "xer", 0, &monitor_get_xer },
 104     { "msr", offsetof(CPUPPCState, msr) },
 105     { "tbu", 0, &monitor_get_tbu, },
 106     { "tbl", 0, &monitor_get_tbl, },
 107     { NULL },
 108 };
 109
 110 const MonitorDef *target_monitor_defs(void)
 111 {
 112     return monitor_defs;
 113 }
 114
 115 static int ppc_cpu_get_reg_num(const char *numstr, int maxnum, int *pregnum)
 116 {
 117     int regnum;
 118     char *endptr = NULL;
 119
 120     if (!*numstr) {
 121         return false;
 122     }
 123
 124     regnum = strtoul(numstr, &endptr, 10);
 125     if (*endptr || (regnum >= maxnum)) {
 126         return false;
 127     }
 128     *pregnum = regnum;
 129
 130     return true;
 131 }
 132
 133 int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
 134 {
 135     int i, regnum;
 136     PowerPCCPU *cpu = POWERPC_CPU(cs);
 137     CPUPPCState *env = &cpu->env;
 138
 139     /* General purpose registers */
 140     if ((qemu_tolower(name[0]) == 'r') &&
 141         ppc_cpu_get_reg_num(name + 1, ARRAY_SIZE(env->gpr), &regnum)) {
 142         *pval = env->gpr[regnum];
 143         return 0;
 144     }
 145
 146     /* Floating point registers */
 147     if ((qemu_tolower(name[0]) == 'f') &&
 148         ppc_cpu_get_reg_num(name + 1, 32, &regnum)) {
 149         *pval = *cpu_fpr_ptr(env, regnum);
 150         return 0;
 151     }
 152
 153     /* Special purpose registers */
 154     for (i = 0; i < ARRAY_SIZE(env->spr_cb); ++i) {
 155         ppc_spr_t *spr = &env->spr_cb[i];
 156
 157         if (spr->name && (strcasecmp(name, spr->name) == 0)) {
 158             *pval = env->spr[i];
 159             return 0;
 160         }
 161     }
 162
 163     /* Segment registers */
 164 #if !defined(CONFIG_USER_ONLY)
 165     if ((strncasecmp(name, "sr", 2) == 0) &&
 166         ppc_cpu_get_reg_num(name + 2, ARRAY_SIZE(env->sr), &regnum)) {
 167         *pval = env->sr[regnum];
 168         return 0;
 169     }
 170 #endif
 171
 172     return -EINVAL;
 173 }
 174
 175 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
 176 {
 177     ObjectClass *oc = data;
 178     CpuDefinitionInfoList **first = user_data;
 179     const char *typename;
 180     CpuDefinitionInfo *info;
 181
 182     typename = object_class_get_name(oc);
 183     info = g_malloc0(sizeof(*info));
 184     info->name = g_strndup(typename,
 185                            strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
 186
 187     QAPI_LIST_PREPEND(*first, info);
 188 }
 189
 190 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
 191 {
 192     CpuDefinitionInfoList *cpu_list = NULL;
 193     GSList *list;
 194     int i;
 195
 196     list = object_class_get_list(TYPE_POWERPC_CPU, false);
 197     g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
 198     g_slist_free(list);
 199
 200     for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
 201         PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
 202         ObjectClass *oc;
 203         CpuDefinitionInfo *info;
 204
 205         oc = ppc_cpu_class_by_name(alias->model);
 206         if (oc == NULL) {
 207             continue;
 208         }
 209
 210         info = g_malloc0(sizeof(*info));
 211         info->name = g_strdup(alias->alias);
 212         info->q_typename = g_strdup(object_class_get_name(oc));
 213
 214         QAPI_LIST_PREPEND(cpu_list, info);
 215     }
 216
 217     return cpu_list;
 218 }