2 * QEMU USB EHCI Emulation
4 * This library is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU Lesser General Public
6 * License as published by the Free Software Foundation; either
7 * version 2.1 of the License, or (at your option) any later version.
9 * This library is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * Lesser General Public License for more details.
14 * You should have received a copy of the GNU Lesser General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 #include "qemu/osdep.h"
19 #include "hw/qdev-properties.h"
20 #include "hw/usb/hcd-ehci.h"
21 #include "migration/vmstate.h"
22 #include "qemu/module.h"
24 static const VMStateDescription vmstate_ehci_sysbus
= {
25 .name
= "ehci-sysbus",
27 .minimum_version_id
= 1,
28 .fields
= (VMStateField
[]) {
29 VMSTATE_STRUCT(ehci
, EHCISysBusState
, 2, vmstate_ehci
, EHCIState
),
34 static Property ehci_sysbus_properties
[] = {
35 DEFINE_PROP_UINT32("maxframes", EHCISysBusState
, ehci
.maxframes
, 128),
36 DEFINE_PROP_BOOL("companion-enable", EHCISysBusState
, ehci
.companion_enable
,
38 DEFINE_PROP_END_OF_LIST(),
41 static void usb_ehci_sysbus_realize(DeviceState
*dev
, Error
**errp
)
43 SysBusDevice
*d
= SYS_BUS_DEVICE(dev
);
44 EHCISysBusState
*i
= SYS_BUS_EHCI(dev
);
45 EHCIState
*s
= &i
->ehci
;
47 usb_ehci_realize(s
, dev
, errp
);
48 sysbus_init_irq(d
, &s
->irq
);
51 static void usb_ehci_sysbus_reset(DeviceState
*dev
)
53 SysBusDevice
*d
= SYS_BUS_DEVICE(dev
);
54 EHCISysBusState
*i
= SYS_BUS_EHCI(d
);
55 EHCIState
*s
= &i
->ehci
;
60 static void ehci_sysbus_init(Object
*obj
)
62 SysBusDevice
*d
= SYS_BUS_DEVICE(obj
);
63 EHCISysBusState
*i
= SYS_BUS_EHCI(obj
);
64 SysBusEHCIClass
*sec
= SYS_BUS_EHCI_GET_CLASS(obj
);
65 EHCIState
*s
= &i
->ehci
;
67 s
->capsbase
= sec
->capsbase
;
68 s
->opregbase
= sec
->opregbase
;
69 s
->portscbase
= sec
->portscbase
;
70 s
->portnr
= sec
->portnr
;
71 s
->as
= &address_space_memory
;
73 usb_ehci_init(s
, DEVICE(obj
));
74 sysbus_init_mmio(d
, &s
->mem
);
77 static void ehci_sysbus_class_init(ObjectClass
*klass
, void *data
)
79 DeviceClass
*dc
= DEVICE_CLASS(klass
);
80 SysBusEHCIClass
*sec
= SYS_BUS_EHCI_CLASS(klass
);
82 sec
->portscbase
= 0x44;
83 sec
->portnr
= NB_PORTS
;
85 dc
->realize
= usb_ehci_sysbus_realize
;
86 dc
->vmsd
= &vmstate_ehci_sysbus
;
87 device_class_set_props(dc
, ehci_sysbus_properties
);
88 dc
->reset
= usb_ehci_sysbus_reset
;
89 set_bit(DEVICE_CATEGORY_USB
, dc
->categories
);
92 static const TypeInfo ehci_type_info
= {
93 .name
= TYPE_SYS_BUS_EHCI
,
94 .parent
= TYPE_SYS_BUS_DEVICE
,
95 .instance_size
= sizeof(EHCISysBusState
),
96 .instance_init
= ehci_sysbus_init
,
98 .class_init
= ehci_sysbus_class_init
,
99 .class_size
= sizeof(SysBusEHCIClass
),
102 static void ehci_platform_class_init(ObjectClass
*oc
, void *data
)
104 SysBusEHCIClass
*sec
= SYS_BUS_EHCI_CLASS(oc
);
105 DeviceClass
*dc
= DEVICE_CLASS(oc
);
108 sec
->opregbase
= 0x20;
109 set_bit(DEVICE_CATEGORY_USB
, dc
->categories
);
112 static const TypeInfo ehci_platform_type_info
= {
113 .name
= TYPE_PLATFORM_EHCI
,
114 .parent
= TYPE_SYS_BUS_EHCI
,
115 .class_init
= ehci_platform_class_init
,
118 static void ehci_exynos4210_class_init(ObjectClass
*oc
, void *data
)
120 SysBusEHCIClass
*sec
= SYS_BUS_EHCI_CLASS(oc
);
121 DeviceClass
*dc
= DEVICE_CLASS(oc
);
124 sec
->opregbase
= 0x10;
125 set_bit(DEVICE_CATEGORY_USB
, dc
->categories
);
128 static const TypeInfo ehci_exynos4210_type_info
= {
129 .name
= TYPE_EXYNOS4210_EHCI
,
130 .parent
= TYPE_SYS_BUS_EHCI
,
131 .class_init
= ehci_exynos4210_class_init
,
134 static void ehci_tegra2_class_init(ObjectClass
*oc
, void *data
)
136 SysBusEHCIClass
*sec
= SYS_BUS_EHCI_CLASS(oc
);
137 DeviceClass
*dc
= DEVICE_CLASS(oc
);
139 sec
->capsbase
= 0x100;
140 sec
->opregbase
= 0x140;
141 set_bit(DEVICE_CATEGORY_USB
, dc
->categories
);
144 static const TypeInfo ehci_tegra2_type_info
= {
145 .name
= TYPE_TEGRA2_EHCI
,
146 .parent
= TYPE_SYS_BUS_EHCI
,
147 .class_init
= ehci_tegra2_class_init
,
150 static void ehci_ppc4xx_init(Object
*o
)
152 EHCISysBusState
*s
= SYS_BUS_EHCI(o
);
154 s
->ehci
.companion_enable
= true;
157 static void ehci_ppc4xx_class_init(ObjectClass
*oc
, void *data
)
159 SysBusEHCIClass
*sec
= SYS_BUS_EHCI_CLASS(oc
);
160 DeviceClass
*dc
= DEVICE_CLASS(oc
);
163 sec
->opregbase
= 0x10;
164 set_bit(DEVICE_CATEGORY_USB
, dc
->categories
);
167 static const TypeInfo ehci_ppc4xx_type_info
= {
168 .name
= TYPE_PPC4xx_EHCI
,
169 .parent
= TYPE_SYS_BUS_EHCI
,
170 .class_init
= ehci_ppc4xx_class_init
,
171 .instance_init
= ehci_ppc4xx_init
,
175 * Faraday FUSBH200 USB 2.0 EHCI
180 * @FUSBH200_REG_EOF_ASTR: EOF/Async. Sleep Timer Register
181 * @FUSBH200_REG_BMCSR: Bus Monitor Control/Status Register
183 enum FUSBH200EHCIRegs
{
184 FUSBH200_REG_EOF_ASTR
= 0x34,
185 FUSBH200_REG_BMCSR
= 0x40,
188 static uint64_t fusbh200_ehci_read(void *opaque
, hwaddr addr
, unsigned size
)
190 EHCIState
*s
= opaque
;
191 hwaddr off
= s
->opregbase
+ s
->portscbase
+ 4 * s
->portnr
+ addr
;
194 case FUSBH200_REG_EOF_ASTR
:
196 case FUSBH200_REG_BMCSR
:
197 /* High-Speed, VBUS valid, interrupt level-high active */
198 return (2 << 9) | (1 << 8) | (1 << 3);
204 static void fusbh200_ehci_write(void *opaque
, hwaddr addr
, uint64_t val
,
209 static const MemoryRegionOps fusbh200_ehci_mmio_ops
= {
210 .read
= fusbh200_ehci_read
,
211 .write
= fusbh200_ehci_write
,
212 .valid
.min_access_size
= 4,
213 .valid
.max_access_size
= 4,
214 .endianness
= DEVICE_LITTLE_ENDIAN
,
217 static void fusbh200_ehci_init(Object
*obj
)
219 EHCISysBusState
*i
= SYS_BUS_EHCI(obj
);
220 FUSBH200EHCIState
*f
= FUSBH200_EHCI(obj
);
221 EHCIState
*s
= &i
->ehci
;
223 memory_region_init_io(&f
->mem_vendor
, OBJECT(f
), &fusbh200_ehci_mmio_ops
, s
,
225 memory_region_add_subregion(&s
->mem
,
226 s
->opregbase
+ s
->portscbase
+ 4 * s
->portnr
,
230 static void fusbh200_ehci_class_init(ObjectClass
*oc
, void *data
)
232 SysBusEHCIClass
*sec
= SYS_BUS_EHCI_CLASS(oc
);
233 DeviceClass
*dc
= DEVICE_CLASS(oc
);
236 sec
->opregbase
= 0x10;
237 sec
->portscbase
= 0x20;
239 set_bit(DEVICE_CATEGORY_USB
, dc
->categories
);
242 static const TypeInfo ehci_fusbh200_type_info
= {
243 .name
= TYPE_FUSBH200_EHCI
,
244 .parent
= TYPE_SYS_BUS_EHCI
,
245 .instance_size
= sizeof(FUSBH200EHCIState
),
246 .instance_init
= fusbh200_ehci_init
,
247 .class_init
= fusbh200_ehci_class_init
,
250 static void ehci_sysbus_register_types(void)
252 type_register_static(&ehci_type_info
);
253 type_register_static(&ehci_platform_type_info
);
254 type_register_static(&ehci_exynos4210_type_info
);
255 type_register_static(&ehci_tegra2_type_info
);
256 type_register_static(&ehci_ppc4xx_type_info
);
257 type_register_static(&ehci_fusbh200_type_info
);
260 type_init(ehci_sysbus_register_types
)