hw/net/xgmac.c

   1 /*
   2  * QEMU model of XGMAC Ethernet.
   3  *
   4  * derived from the Xilinx AXI-Ethernet by Edgar E. Iglesias.
   5  *
   6  * Copyright (c) 2011 Calxeda, Inc.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #include "qemu/osdep.h"
  28 #include "hw/sysbus.h"
  29 #include "qemu/log.h"
  30 #include "net/net.h"
  31
  32 #ifdef DEBUG_XGMAC
  33 #define DEBUGF_BRK(message, args...) do { \
  34                                          fprintf(stderr, (message), ## args); \
  35                                      } while (0)
  36 #else
  37 #define DEBUGF_BRK(message, args...) do { } while (0)
  38 #endif
  39
  40 #define XGMAC_CONTROL           0x00000000   /* MAC Configuration */
  41 #define XGMAC_FRAME_FILTER      0x00000001   /* MAC Frame Filter */
  42 #define XGMAC_FLOW_CTRL         0x00000006   /* MAC Flow Control */
  43 #define XGMAC_VLAN_TAG          0x00000007   /* VLAN Tags */
  44 #define XGMAC_VERSION           0x00000008   /* Version */
  45 /* VLAN tag for insertion or replacement into tx frames */
  46 #define XGMAC_VLAN_INCL         0x00000009
  47 #define XGMAC_LPI_CTRL          0x0000000a   /* LPI Control and Status */
  48 #define XGMAC_LPI_TIMER         0x0000000b   /* LPI Timers Control */
  49 #define XGMAC_TX_PACE           0x0000000c   /* Transmit Pace and Stretch */
  50 #define XGMAC_VLAN_HASH         0x0000000d   /* VLAN Hash Table */
  51 #define XGMAC_DEBUG             0x0000000e   /* Debug */
  52 #define XGMAC_INT_STATUS        0x0000000f   /* Interrupt and Control */
  53 /* HASH table registers */
  54 #define XGMAC_HASH(n)           ((0x00000300/4) + (n))
  55 #define XGMAC_NUM_HASH          16
  56 /* Operation Mode */
  57 #define XGMAC_OPMODE            (0x00000400/4)
  58 /* Remote Wake-Up Frame Filter */
  59 #define XGMAC_REMOTE_WAKE       (0x00000700/4)
  60 /* PMT Control and Status */
  61 #define XGMAC_PMT               (0x00000704/4)
  62
  63 #define XGMAC_ADDR_HIGH(reg)    (0x00000010+((reg) * 2))
  64 #define XGMAC_ADDR_LOW(reg)     (0x00000011+((reg) * 2))
  65
  66 #define DMA_BUS_MODE            0x000003c0   /* Bus Mode */
  67 #define DMA_XMT_POLL_DEMAND     0x000003c1   /* Transmit Poll Demand */
  68 #define DMA_RCV_POLL_DEMAND     0x000003c2   /* Received Poll Demand */
  69 #define DMA_RCV_BASE_ADDR       0x000003c3   /* Receive List Base */
  70 #define DMA_TX_BASE_ADDR        0x000003c4   /* Transmit List Base */
  71 #define DMA_STATUS              0x000003c5   /* Status Register */
  72 #define DMA_CONTROL             0x000003c6   /* Ctrl (Operational Mode) */
  73 #define DMA_INTR_ENA            0x000003c7   /* Interrupt Enable */
  74 #define DMA_MISSED_FRAME_CTR    0x000003c8   /* Missed Frame Counter */
  75 /* Receive Interrupt Watchdog Timer */
  76 #define DMA_RI_WATCHDOG_TIMER   0x000003c9
  77 #define DMA_AXI_BUS             0x000003ca   /* AXI Bus Mode */
  78 #define DMA_AXI_STATUS          0x000003cb   /* AXI Status */
  79 #define DMA_CUR_TX_DESC_ADDR    0x000003d2   /* Current Host Tx Descriptor */
  80 #define DMA_CUR_RX_DESC_ADDR    0x000003d3   /* Current Host Rx Descriptor */
  81 #define DMA_CUR_TX_BUF_ADDR     0x000003d4   /* Current Host Tx Buffer */
  82 #define DMA_CUR_RX_BUF_ADDR     0x000003d5   /* Current Host Rx Buffer */
  83 #define DMA_HW_FEATURE          0x000003d6   /* Enabled Hardware Features */
  84
  85 /* DMA Status register defines */
  86 #define DMA_STATUS_GMI          0x08000000   /* MMC interrupt */
  87 #define DMA_STATUS_GLI          0x04000000   /* GMAC Line interface int */
  88 #define DMA_STATUS_EB_MASK      0x00380000   /* Error Bits Mask */
  89 #define DMA_STATUS_EB_TX_ABORT  0x00080000   /* Error Bits - TX Abort */
  90 #define DMA_STATUS_EB_RX_ABORT  0x00100000   /* Error Bits - RX Abort */
  91 #define DMA_STATUS_TS_MASK      0x00700000   /* Transmit Process State */
  92 #define DMA_STATUS_TS_SHIFT     20
  93 #define DMA_STATUS_RS_MASK      0x000e0000   /* Receive Process State */
  94 #define DMA_STATUS_RS_SHIFT     17
  95 #define DMA_STATUS_NIS          0x00010000   /* Normal Interrupt Summary */
  96 #define DMA_STATUS_AIS          0x00008000   /* Abnormal Interrupt Summary */
  97 #define DMA_STATUS_ERI          0x00004000   /* Early Receive Interrupt */
  98 #define DMA_STATUS_FBI          0x00002000   /* Fatal Bus Error Interrupt */
  99 #define DMA_STATUS_ETI          0x00000400   /* Early Transmit Interrupt */
 100 #define DMA_STATUS_RWT          0x00000200   /* Receive Watchdog Timeout */
 101 #define DMA_STATUS_RPS          0x00000100   /* Receive Process Stopped */
 102 #define DMA_STATUS_RU           0x00000080   /* Receive Buffer Unavailable */
 103 #define DMA_STATUS_RI           0x00000040   /* Receive Interrupt */
 104 #define DMA_STATUS_UNF          0x00000020   /* Transmit Underflow */
 105 #define DMA_STATUS_OVF          0x00000010   /* Receive Overflow */
 106 #define DMA_STATUS_TJT          0x00000008   /* Transmit Jabber Timeout */
 107 #define DMA_STATUS_TU           0x00000004   /* Transmit Buffer Unavailable */
 108 #define DMA_STATUS_TPS          0x00000002   /* Transmit Process Stopped */
 109 #define DMA_STATUS_TI           0x00000001   /* Transmit Interrupt */
 110
 111 /* DMA Control register defines */
 112 #define DMA_CONTROL_ST          0x00002000   /* Start/Stop Transmission */
 113 #define DMA_CONTROL_SR          0x00000002   /* Start/Stop Receive */
 114 #define DMA_CONTROL_DFF         0x01000000   /* Disable flush of rx frames */
 115
 116 struct desc {
 117     uint32_t ctl_stat;
 118     uint16_t buffer1_size;
 119     uint16_t buffer2_size;
 120     uint32_t buffer1_addr;
 121     uint32_t buffer2_addr;
 122     uint32_t ext_stat;
 123     uint32_t res[3];
 124 };
 125
 126 #define R_MAX 0x400
 127
 128 typedef struct RxTxStats {
 129     uint64_t rx_bytes;
 130     uint64_t tx_bytes;
 131
 132     uint64_t rx;
 133     uint64_t rx_bcast;
 134     uint64_t rx_mcast;
 135 } RxTxStats;
 136
 137 #define TYPE_XGMAC "xgmac"
 138 #define XGMAC(obj) OBJECT_CHECK(XgmacState, (obj), TYPE_XGMAC)
 139
 140 typedef struct XgmacState {
 141     SysBusDevice parent_obj;
 142
 143     MemoryRegion iomem;
 144     qemu_irq sbd_irq;
 145     qemu_irq pmt_irq;
 146     qemu_irq mci_irq;
 147     NICState *nic;
 148     NICConf conf;
 149
 150     struct RxTxStats stats;
 151     uint32_t regs[R_MAX];
 152 } XgmacState;
 153
 154 static const VMStateDescription vmstate_rxtx_stats = {
 155     .name = "xgmac_stats",
 156     .version_id = 1,
 157     .minimum_version_id = 1,
 158     .fields = (VMStateField[]) {
 159         VMSTATE_UINT64(rx_bytes, RxTxStats),
 160         VMSTATE_UINT64(tx_bytes, RxTxStats),
 161         VMSTATE_UINT64(rx, RxTxStats),
 162         VMSTATE_UINT64(rx_bcast, RxTxStats),
 163         VMSTATE_UINT64(rx_mcast, RxTxStats),
 164         VMSTATE_END_OF_LIST()
 165     }
 166 };
 167
 168 static const VMStateDescription vmstate_xgmac = {
 169     .name = "xgmac",
 170     .version_id = 1,
 171     .minimum_version_id = 1,
 172     .fields = (VMStateField[]) {
 173         VMSTATE_STRUCT(stats, XgmacState, 0, vmstate_rxtx_stats, RxTxStats),
 174         VMSTATE_UINT32_ARRAY(regs, XgmacState, R_MAX),
 175         VMSTATE_END_OF_LIST()
 176     }
 177 };
 178
 179 static void xgmac_read_desc(XgmacState *s, struct desc *d, int rx)
 180 {
 181     uint32_t addr = rx ? s->regs[DMA_CUR_RX_DESC_ADDR] :
 182         s->regs[DMA_CUR_TX_DESC_ADDR];
 183     cpu_physical_memory_read(addr, d, sizeof(*d));
 184 }
 185
 186 static void xgmac_write_desc(XgmacState *s, struct desc *d, int rx)
 187 {
 188     int reg = rx ? DMA_CUR_RX_DESC_ADDR : DMA_CUR_TX_DESC_ADDR;
 189     uint32_t addr = s->regs[reg];
 190
 191     if (!rx && (d->ctl_stat & 0x00200000)) {
 192         s->regs[reg] = s->regs[DMA_TX_BASE_ADDR];
 193     } else if (rx && (d->buffer1_size & 0x8000)) {
 194         s->regs[reg] = s->regs[DMA_RCV_BASE_ADDR];
 195     } else {
 196         s->regs[reg] += sizeof(*d);
 197     }
 198     cpu_physical_memory_write(addr, d, sizeof(*d));
 199 }
 200
 201 static void xgmac_enet_send(XgmacState *s)
 202 {
 203     struct desc bd;
 204     int frame_size;
 205     int len;
 206     uint8_t frame[8192];
 207     uint8_t *ptr;
 208
 209     ptr = frame;
 210     frame_size = 0;
 211     while (1) {
 212         xgmac_read_desc(s, &bd, 0);
 213         if ((bd.ctl_stat & 0x80000000) == 0) {
 214             /* Run out of descriptors to transmit.  */
 215             break;
 216         }
 217         len = (bd.buffer1_size & 0xfff) + (bd.buffer2_size & 0xfff);
 218
 219         if ((bd.buffer1_size & 0xfff) > 2048) {
 220             DEBUGF_BRK("qemu:%s:ERROR...ERROR...ERROR... -- "
 221                         "xgmac buffer 1 len on send > 2048 (0x%x)\n",
 222                          __func__, bd.buffer1_size & 0xfff);
 223         }
 224         if ((bd.buffer2_size & 0xfff) != 0) {
 225             DEBUGF_BRK("qemu:%s:ERROR...ERROR...ERROR... -- "
 226                         "xgmac buffer 2 len on send != 0 (0x%x)\n",
 227                         __func__, bd.buffer2_size & 0xfff);
 228         }
 229         if (len >= sizeof(frame)) {
 230             DEBUGF_BRK("qemu:%s: buffer overflow %d read into %zu "
 231                         "buffer\n" , __func__, len, sizeof(frame));
 232             DEBUGF_BRK("qemu:%s: buffer1.size=%d; buffer2.size=%d\n",
 233                         __func__, bd.buffer1_size, bd.buffer2_size);
 234         }
 235
 236         cpu_physical_memory_read(bd.buffer1_addr, ptr, len);
 237         ptr += len;
 238         frame_size += len;
 239         if (bd.ctl_stat & 0x20000000) {
 240             /* Last buffer in frame.  */
 241             qemu_send_packet(qemu_get_queue(s->nic), frame, len);
 242             ptr = frame;
 243             frame_size = 0;
 244             s->regs[DMA_STATUS] |= DMA_STATUS_TI | DMA_STATUS_NIS;
 245         }
 246         bd.ctl_stat &= ~0x80000000;
 247         /* Write back the modified descriptor.  */
 248         xgmac_write_desc(s, &bd, 0);
 249     }
 250 }
 251
 252 static void enet_update_irq(XgmacState *s)
 253 {
 254     int stat = s->regs[DMA_STATUS] & s->regs[DMA_INTR_ENA];
 255     qemu_set_irq(s->sbd_irq, !!stat);
 256 }
 257
 258 static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
 259 {
 260     XgmacState *s = opaque;
 261     uint64_t r = 0;
 262     addr >>= 2;
 263
 264     switch (addr) {
 265     case XGMAC_VERSION:
 266         r = 0x1012;
 267         break;
 268     default:
 269         if (addr < ARRAY_SIZE(s->regs)) {
 270             r = s->regs[addr];
 271         }
 272         break;
 273     }
 274     return r;
 275 }
 276
 277 static void enet_write(void *opaque, hwaddr addr,
 278                        uint64_t value, unsigned size)
 279 {
 280     XgmacState *s = opaque;
 281
 282     addr >>= 2;
 283     switch (addr) {
 284     case DMA_BUS_MODE:
 285         s->regs[DMA_BUS_MODE] = value & ~0x1;
 286         break;
 287     case DMA_XMT_POLL_DEMAND:
 288         xgmac_enet_send(s);
 289         break;
 290     case DMA_STATUS:
 291         s->regs[DMA_STATUS] = s->regs[DMA_STATUS] & ~value;
 292         break;
 293     case DMA_RCV_BASE_ADDR:
 294         s->regs[DMA_RCV_BASE_ADDR] = s->regs[DMA_CUR_RX_DESC_ADDR] = value;
 295         break;
 296     case DMA_TX_BASE_ADDR:
 297         s->regs[DMA_TX_BASE_ADDR] = s->regs[DMA_CUR_TX_DESC_ADDR] = value;
 298         break;
 299     default:
 300         if (addr < ARRAY_SIZE(s->regs)) {
 301             s->regs[addr] = value;
 302         }
 303         break;
 304     }
 305     enet_update_irq(s);
 306 }
 307
 308 static const MemoryRegionOps enet_mem_ops = {
 309     .read = enet_read,
 310     .write = enet_write,
 311     .endianness = DEVICE_LITTLE_ENDIAN,
 312 };
 313
 314 static int eth_can_rx(XgmacState *s)
 315 {
 316     /* RX enabled?  */
 317     return s->regs[DMA_CONTROL] & DMA_CONTROL_SR;
 318 }
 319
 320 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
 321 {
 322     XgmacState *s = qemu_get_nic_opaque(nc);
 323     static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff,
 324                                               0xff, 0xff, 0xff};
 325     int unicast, broadcast, multicast;
 326     struct desc bd;
 327     ssize_t ret;
 328
 329     if (!eth_can_rx(s)) {
 330         return -1;
 331     }
 332     unicast = ~buf[0] & 0x1;
 333     broadcast = memcmp(buf, sa_bcast, 6) == 0;
 334     multicast = !unicast && !broadcast;
 335     if (size < 12) {
 336         s->regs[DMA_STATUS] |= DMA_STATUS_RI | DMA_STATUS_NIS;
 337         ret = -1;
 338         goto out;
 339     }
 340
 341     xgmac_read_desc(s, &bd, 1);
 342     if ((bd.ctl_stat & 0x80000000) == 0) {
 343         s->regs[DMA_STATUS] |= DMA_STATUS_RU | DMA_STATUS_AIS;
 344         ret = size;
 345         goto out;
 346     }
 347
 348     cpu_physical_memory_write(bd.buffer1_addr, buf, size);
 349
 350     /* Add in the 4 bytes for crc (the real hw returns length incl crc) */
 351     size += 4;
 352     bd.ctl_stat = (size << 16) | 0x300;
 353     xgmac_write_desc(s, &bd, 1);
 354
 355     s->stats.rx_bytes += size;
 356     s->stats.rx++;
 357     if (multicast) {
 358         s->stats.rx_mcast++;
 359     } else if (broadcast) {
 360         s->stats.rx_bcast++;
 361     }
 362
 363     s->regs[DMA_STATUS] |= DMA_STATUS_RI | DMA_STATUS_NIS;
 364     ret = size;
 365
 366 out:
 367     enet_update_irq(s);
 368     return ret;
 369 }
 370
 371 static NetClientInfo net_xgmac_enet_info = {
 372     .type = NET_CLIENT_DRIVER_NIC,
 373     .size = sizeof(NICState),
 374     .receive = eth_rx,
 375 };
 376
 377 static void xgmac_enet_realize(DeviceState *dev, Error **errp)
 378 {
 379     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 380     XgmacState *s = XGMAC(dev);
 381
 382     memory_region_init_io(&s->iomem, OBJECT(s), &enet_mem_ops, s,
 383                           "xgmac", 0x1000);
 384     sysbus_init_mmio(sbd, &s->iomem);
 385     sysbus_init_irq(sbd, &s->sbd_irq);
 386     sysbus_init_irq(sbd, &s->pmt_irq);
 387     sysbus_init_irq(sbd, &s->mci_irq);
 388
 389     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 390     s->nic = qemu_new_nic(&net_xgmac_enet_info, &s->conf,
 391                           object_get_typename(OBJECT(dev)), dev->id, s);
 392     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 393
 394     s->regs[XGMAC_ADDR_HIGH(0)] = (s->conf.macaddr.a[5] << 8) |
 395                                    s->conf.macaddr.a[4];
 396     s->regs[XGMAC_ADDR_LOW(0)] = (s->conf.macaddr.a[3] << 24) |
 397                                  (s->conf.macaddr.a[2] << 16) |
 398                                  (s->conf.macaddr.a[1] << 8) |
 399                                   s->conf.macaddr.a[0];
 400 }
 401
 402 static Property xgmac_properties[] = {
 403     DEFINE_NIC_PROPERTIES(XgmacState, conf),
 404     DEFINE_PROP_END_OF_LIST(),
 405 };
 406
 407 static void xgmac_enet_class_init(ObjectClass *klass, void *data)
 408 {
 409     DeviceClass *dc = DEVICE_CLASS(klass);
 410
 411     dc->realize = xgmac_enet_realize;
 412     dc->vmsd = &vmstate_xgmac;
 413     dc->props = xgmac_properties;
 414 }
 415
 416 static const TypeInfo xgmac_enet_info = {
 417     .name          = TYPE_XGMAC,
 418     .parent        = TYPE_SYS_BUS_DEVICE,
 419     .instance_size = sizeof(XgmacState),
 420     .class_init    = xgmac_enet_class_init,
 421 };
 422
 423 static void xgmac_enet_register_types(void)
 424 {
 425     type_register_static(&xgmac_enet_info);
 426 }
 427
 428 type_init(xgmac_enet_register_types)