hw/misc/iotkit-sysctl.c

   1 /*
   2  * ARM IoTKit system control element
   3  *
   4  * Copyright (c) 2018 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License version 2 or
   9  *  (at your option) any later version.
  10  */
  11
  12 /*
  13  * This is a model of the "system control element" which is part of the
  14  * Arm IoTKit and documented in
  15  * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
  16  * Specifically, it implements the "system control register" blocks.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "qemu/log.h"
  21 #include "trace.h"
  22 #include "qapi/error.h"
  23 #include "sysemu/sysemu.h"
  24 #include "hw/sysbus.h"
  25 #include "hw/registerfields.h"
  26 #include "hw/misc/iotkit-sysctl.h"
  27
  28 REG32(SECDBGSTAT, 0x0)
  29 REG32(SECDBGSET, 0x4)
  30 REG32(SECDBGCLR, 0x8)
  31 REG32(RESET_SYNDROME, 0x100)
  32 REG32(RESET_MASK, 0x104)
  33 REG32(SWRESET, 0x108)
  34     FIELD(SWRESET, SWRESETREQ, 9, 1)
  35 REG32(GRETREG, 0x10c)
  36 REG32(INITSVRTOR0, 0x110)
  37 REG32(CPUWAIT, 0x118)
  38 REG32(BUSWAIT, 0x11c)
  39 REG32(WICCTRL, 0x120)
  40 REG32(PID4, 0xfd0)
  41 REG32(PID5, 0xfd4)
  42 REG32(PID6, 0xfd8)
  43 REG32(PID7, 0xfdc)
  44 REG32(PID0, 0xfe0)
  45 REG32(PID1, 0xfe4)
  46 REG32(PID2, 0xfe8)
  47 REG32(PID3, 0xfec)
  48 REG32(CID0, 0xff0)
  49 REG32(CID1, 0xff4)
  50 REG32(CID2, 0xff8)
  51 REG32(CID3, 0xffc)
  52
  53 /* PID/CID values */
  54 static const int sysctl_id[] = {
  55     0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
  56     0x54, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
  57     0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
  58 };
  59
  60 static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
  61                                     unsigned size)
  62 {
  63     IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque);
  64     uint64_t r;
  65
  66     switch (offset) {
  67     case A_SECDBGSTAT:
  68         r = s->secure_debug;
  69         break;
  70     case A_RESET_SYNDROME:
  71         r = s->reset_syndrome;
  72         break;
  73     case A_RESET_MASK:
  74         r = s->reset_mask;
  75         break;
  76     case A_GRETREG:
  77         r = s->gretreg;
  78         break;
  79     case A_INITSVRTOR0:
  80         r = s->initsvrtor0;
  81         break;
  82     case A_CPUWAIT:
  83         r = s->cpuwait;
  84         break;
  85     case A_BUSWAIT:
  86         /* In IoTKit BUSWAIT is reserved, R/O, zero */
  87         r = 0;
  88         break;
  89     case A_WICCTRL:
  90         r = s->wicctrl;
  91         break;
  92     case A_PID4 ... A_CID3:
  93         r = sysctl_id[(offset - A_PID4) / 4];
  94         break;
  95     case A_SECDBGSET:
  96     case A_SECDBGCLR:
  97     case A_SWRESET:
  98         qemu_log_mask(LOG_GUEST_ERROR,
  99                       "IoTKit SysCtl read: read of WO offset %x\n",
 100                       (int)offset);
 101         r = 0;
 102         break;
 103     default:
 104         qemu_log_mask(LOG_GUEST_ERROR,
 105                       "IoTKit SysCtl read: bad offset %x\n", (int)offset);
 106         r = 0;
 107         break;
 108     }
 109     trace_iotkit_sysctl_read(offset, r, size);
 110     return r;
 111 }
 112
 113 static void iotkit_sysctl_write(void *opaque, hwaddr offset,
 114                                  uint64_t value, unsigned size)
 115 {
 116     IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque);
 117
 118     trace_iotkit_sysctl_write(offset, value, size);
 119
 120     /*
 121      * Most of the state here has to do with control of reset and
 122      * similar kinds of power up -- for instance the guest can ask
 123      * what the reason for the last reset was, or forbid reset for
 124      * some causes (like the non-secure watchdog). Most of this is
 125      * not relevant to QEMU, which doesn't really model anything other
 126      * than a full power-on reset.
 127      * We just model the registers as reads-as-written.
 128      */
 129
 130     switch (offset) {
 131     case A_RESET_SYNDROME:
 132         qemu_log_mask(LOG_UNIMP,
 133                       "IoTKit SysCtl RESET_SYNDROME unimplemented\n");
 134         s->reset_syndrome = value;
 135         break;
 136     case A_RESET_MASK:
 137         qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl RESET_MASK unimplemented\n");
 138         s->reset_mask = value;
 139         break;
 140     case A_GRETREG:
 141         /*
 142          * General retention register, which is only reset by a power-on
 143          * reset. Technically this implementation is complete, since
 144          * QEMU only supports power-on resets...
 145          */
 146         s->gretreg = value;
 147         break;
 148     case A_INITSVRTOR0:
 149         qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVRTOR0 unimplemented\n");
 150         s->initsvrtor0 = value;
 151         break;
 152     case A_CPUWAIT:
 153         qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CPUWAIT unimplemented\n");
 154         s->cpuwait = value;
 155         break;
 156     case A_WICCTRL:
 157         qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl WICCTRL unimplemented\n");
 158         s->wicctrl = value;
 159         break;
 160     case A_SECDBGSET:
 161         /* write-1-to-set */
 162         qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SECDBGSET unimplemented\n");
 163         s->secure_debug |= value;
 164         break;
 165     case A_SECDBGCLR:
 166         /* write-1-to-clear */
 167         s->secure_debug &= ~value;
 168         break;
 169     case A_SWRESET:
 170         /* One w/o bit to request a reset; all other bits reserved */
 171         if (value & R_SWRESET_SWRESETREQ_MASK) {
 172             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 173         }
 174         break;
 175     case A_BUSWAIT:        /* In IoTKit BUSWAIT is reserved, R/O, zero */
 176     case A_SECDBGSTAT:
 177     case A_PID4 ... A_CID3:
 178         qemu_log_mask(LOG_GUEST_ERROR,
 179                       "IoTKit SysCtl write: write of RO offset %x\n",
 180                       (int)offset);
 181         break;
 182     default:
 183         qemu_log_mask(LOG_GUEST_ERROR,
 184                       "IoTKit SysCtl write: bad offset %x\n", (int)offset);
 185         break;
 186     }
 187 }
 188
 189 static const MemoryRegionOps iotkit_sysctl_ops = {
 190     .read = iotkit_sysctl_read,
 191     .write = iotkit_sysctl_write,
 192     .endianness = DEVICE_LITTLE_ENDIAN,
 193     /* byte/halfword accesses are just zero-padded on reads and writes */
 194     .impl.min_access_size = 4,
 195     .impl.max_access_size = 4,
 196     .valid.min_access_size = 1,
 197     .valid.max_access_size = 4,
 198 };
 199
 200 static void iotkit_sysctl_reset(DeviceState *dev)
 201 {
 202     IoTKitSysCtl *s = IOTKIT_SYSCTL(dev);
 203
 204     trace_iotkit_sysctl_reset();
 205     s->secure_debug = 0;
 206     s->reset_syndrome = 1;
 207     s->reset_mask = 0;
 208     s->gretreg = 0;
 209     s->initsvrtor0 = 0x10000000;
 210     s->cpuwait = 0;
 211     s->wicctrl = 0;
 212 }
 213
 214 static void iotkit_sysctl_init(Object *obj)
 215 {
 216     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 217     IoTKitSysCtl *s = IOTKIT_SYSCTL(obj);
 218
 219     memory_region_init_io(&s->iomem, obj, &iotkit_sysctl_ops,
 220                           s, "iotkit-sysctl", 0x1000);
 221     sysbus_init_mmio(sbd, &s->iomem);
 222 }
 223
 224 static const VMStateDescription iotkit_sysctl_vmstate = {
 225     .name = "iotkit-sysctl",
 226     .version_id = 1,
 227     .minimum_version_id = 1,
 228     .fields = (VMStateField[]) {
 229         VMSTATE_UINT32(secure_debug, IoTKitSysCtl),
 230         VMSTATE_UINT32(reset_syndrome, IoTKitSysCtl),
 231         VMSTATE_UINT32(reset_mask, IoTKitSysCtl),
 232         VMSTATE_UINT32(gretreg, IoTKitSysCtl),
 233         VMSTATE_UINT32(initsvrtor0, IoTKitSysCtl),
 234         VMSTATE_UINT32(cpuwait, IoTKitSysCtl),
 235         VMSTATE_UINT32(wicctrl, IoTKitSysCtl),
 236         VMSTATE_END_OF_LIST()
 237     }
 238 };
 239
 240 static void iotkit_sysctl_class_init(ObjectClass *klass, void *data)
 241 {
 242     DeviceClass *dc = DEVICE_CLASS(klass);
 243
 244     dc->vmsd = &iotkit_sysctl_vmstate;
 245     dc->reset = iotkit_sysctl_reset;
 246 }
 247
 248 static const TypeInfo iotkit_sysctl_info = {
 249     .name = TYPE_IOTKIT_SYSCTL,
 250     .parent = TYPE_SYS_BUS_DEVICE,
 251     .instance_size = sizeof(IoTKitSysCtl),
 252     .instance_init = iotkit_sysctl_init,
 253     .class_init = iotkit_sysctl_class_init,
 254 };
 255
 256 static void iotkit_sysctl_register_types(void)
 257 {
 258     type_register_static(&iotkit_sysctl_info);
 259 }
 260
 261 type_init(iotkit_sysctl_register_types);