hw/m68k/mcf_intc.c

   1 /*
   2  * ColdFire Interrupt Controller emulation.
   3  *
   4  * Copyright (c) 2007 CodeSourcery.
   5  *
   6  * This code is licensed under the GPL
   7  */
   8 #include "qemu/osdep.h"
   9 #include "qemu-common.h"
  10 #include "cpu.h"
  11 #include "hw/hw.h"
  12 #include "hw/sysbus.h"
  13 #include "hw/m68k/mcf.h"
  14
  15 #define TYPE_MCF_INTC "mcf-intc"
  16 #define MCF_INTC(obj) OBJECT_CHECK(mcf_intc_state, (obj), TYPE_MCF_INTC)
  17
  18 typedef struct {
  19     SysBusDevice parent_obj;
  20
  21     MemoryRegion iomem;
  22     uint64_t ipr;
  23     uint64_t imr;
  24     uint64_t ifr;
  25     uint64_t enabled;
  26     uint8_t icr[64];
  27     M68kCPU *cpu;
  28     int active_vector;
  29 } mcf_intc_state;
  30
  31 static void mcf_intc_update(mcf_intc_state *s)
  32 {
  33     uint64_t active;
  34     int i;
  35     int best;
  36     int best_level;
  37
  38     active = (s->ipr | s->ifr) & s->enabled & ~s->imr;
  39     best_level = 0;
  40     best = 64;
  41     if (active) {
  42         for (i = 0; i < 64; i++) {
  43             if ((active & 1) != 0 && s->icr[i] >= best_level) {
  44                 best_level = s->icr[i];
  45                 best = i;
  46             }
  47             active >>= 1;
  48         }
  49     }
  50     s->active_vector = ((best == 64) ? 24 : (best + 64));
  51     m68k_set_irq_level(s->cpu, best_level, s->active_vector);
  52 }
  53
  54 static uint64_t mcf_intc_read(void *opaque, hwaddr addr,
  55                               unsigned size)
  56 {
  57     int offset;
  58     mcf_intc_state *s = (mcf_intc_state *)opaque;
  59     offset = addr & 0xff;
  60     if (offset >= 0x40 && offset < 0x80) {
  61         return s->icr[offset - 0x40];
  62     }
  63     switch (offset) {
  64     case 0x00:
  65         return (uint32_t)(s->ipr >> 32);
  66     case 0x04:
  67         return (uint32_t)s->ipr;
  68     case 0x08:
  69         return (uint32_t)(s->imr >> 32);
  70     case 0x0c:
  71         return (uint32_t)s->imr;
  72     case 0x10:
  73         return (uint32_t)(s->ifr >> 32);
  74     case 0x14:
  75         return (uint32_t)s->ifr;
  76     case 0xe0: /* SWIACK.  */
  77         return s->active_vector;
  78     case 0xe1: case 0xe2: case 0xe3: case 0xe4:
  79     case 0xe5: case 0xe6: case 0xe7:
  80         /* LnIACK */
  81         hw_error("mcf_intc_read: LnIACK not implemented\n");
  82     default:
  83         return 0;
  84     }
  85 }
  86
  87 static void mcf_intc_write(void *opaque, hwaddr addr,
  88                            uint64_t val, unsigned size)
  89 {
  90     int offset;
  91     mcf_intc_state *s = (mcf_intc_state *)opaque;
  92     offset = addr & 0xff;
  93     if (offset >= 0x40 && offset < 0x80) {
  94         int n = offset - 0x40;
  95         s->icr[n] = val;
  96         if (val == 0)
  97             s->enabled &= ~(1ull << n);
  98         else
  99             s->enabled |= (1ull << n);
 100         mcf_intc_update(s);
 101         return;
 102     }
 103     switch (offset) {
 104     case 0x00: case 0x04:
 105         /* Ignore IPR writes.  */
 106         return;
 107     case 0x08:
 108         s->imr = (s->imr & 0xffffffff) | ((uint64_t)val << 32);
 109         break;
 110     case 0x0c:
 111         s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val;
 112         break;
 113     case 0x1c:
 114         if (val & 0x40) {
 115             s->imr = ~0ull;
 116         } else {
 117             s->imr |= (0x1ull << (val & 0x3f));
 118         }
 119         break;
 120     case 0x1d:
 121         if (val & 0x40) {
 122             s->imr = 0ull;
 123         } else {
 124             s->imr &= ~(0x1ull << (val & 0x3f));
 125         }
 126         break;
 127     default:
 128         hw_error("mcf_intc_write: Bad write offset %d\n", offset);
 129         break;
 130     }
 131     mcf_intc_update(s);
 132 }
 133
 134 static void mcf_intc_set_irq(void *opaque, int irq, int level)
 135 {
 136     mcf_intc_state *s = (mcf_intc_state *)opaque;
 137     if (irq >= 64)
 138         return;
 139     if (level)
 140         s->ipr |= 1ull << irq;
 141     else
 142         s->ipr &= ~(1ull << irq);
 143     mcf_intc_update(s);
 144 }
 145
 146 static void mcf_intc_reset(DeviceState *dev)
 147 {
 148     mcf_intc_state *s = MCF_INTC(dev);
 149
 150     s->imr = ~0ull;
 151     s->ipr = 0;
 152     s->ifr = 0;
 153     s->enabled = 0;
 154     memset(s->icr, 0, 64);
 155     s->active_vector = 24;
 156 }
 157
 158 static const MemoryRegionOps mcf_intc_ops = {
 159     .read = mcf_intc_read,
 160     .write = mcf_intc_write,
 161     .endianness = DEVICE_NATIVE_ENDIAN,
 162 };
 163
 164 static void mcf_intc_instance_init(Object *obj)
 165 {
 166     mcf_intc_state *s = MCF_INTC(obj);
 167
 168     memory_region_init_io(&s->iomem, obj, &mcf_intc_ops, s, "mcf", 0x100);
 169 }
 170
 171 static void mcf_intc_class_init(ObjectClass *oc, void *data)
 172 {
 173     DeviceClass *dc = DEVICE_CLASS(oc);
 174
 175     set_bit(DEVICE_CATEGORY_MISC, dc->categories);
 176     dc->reset = mcf_intc_reset;
 177 }
 178
 179 static const TypeInfo mcf_intc_gate_info = {
 180     .name          = TYPE_MCF_INTC,
 181     .parent        = TYPE_SYS_BUS_DEVICE,
 182     .instance_size = sizeof(mcf_intc_state),
 183     .instance_init = mcf_intc_instance_init,
 184     .class_init    = mcf_intc_class_init,
 185 };
 186
 187 static void mcf_intc_register_types(void)
 188 {
 189     type_register_static(&mcf_intc_gate_info);
 190 }
 191
 192 type_init(mcf_intc_register_types)
 193
 194 qemu_irq *mcf_intc_init(MemoryRegion *sysmem,
 195                         hwaddr base,
 196                         M68kCPU *cpu)
 197 {
 198     DeviceState  *dev;
 199     mcf_intc_state *s;
 200
 201     dev = qdev_create(NULL, TYPE_MCF_INTC);
 202     qdev_init_nofail(dev);
 203
 204     s = MCF_INTC(dev);
 205     s->cpu = cpu;
 206
 207     memory_region_add_subregion(sysmem, base, &s->iomem);
 208
 209     return qemu_allocate_irqs(mcf_intc_set_irq, s, 64);
 210 }