2 * QEMU PowerPC sPAPR XIVE interrupt controller model
4 * Copyright (c) 2017-2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qapi/error.h"
13 #include "qemu/error-report.h"
14 #include "target/ppc/cpu.h"
15 #include "sysemu/cpus.h"
16 #include "monitor/monitor.h"
17 #include "hw/ppc/fdt.h"
18 #include "hw/ppc/spapr.h"
19 #include "hw/ppc/spapr_cpu_core.h"
20 #include "hw/ppc/spapr_xive.h"
21 #include "hw/ppc/xive.h"
22 #include "hw/ppc/xive_regs.h"
25 * XIVE Virtualization Controller BAR and Thread Managment BAR that we
26 * use for the ESB pages and the TIMA pages
28 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull
29 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull
32 * The allocation of VP blocks is a complex operation in OPAL and the
33 * VP identifiers have a relation with the number of HW chips, the
34 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE
35 * controller model does not have the same constraints and can use a
36 * simple mapping scheme of the CPU vcpu_id
38 * These identifiers are never returned to the OS.
41 #define SPAPR_XIVE_NVT_BASE 0x400
44 * The sPAPR machine has a unique XIVE IC device. Assign a fixed value
45 * to the controller block id value. It can nevertheless be changed
46 * for testing purpose.
48 #define SPAPR_XIVE_BLOCK_ID 0x0
51 * sPAPR NVT and END indexing helpers
53 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk
, uint32_t nvt_idx
)
55 return nvt_idx
- SPAPR_XIVE_NVT_BASE
;
58 static void spapr_xive_cpu_to_nvt(PowerPCCPU
*cpu
,
59 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
64 *out_nvt_blk
= SPAPR_XIVE_BLOCK_ID
;
68 *out_nvt_idx
= SPAPR_XIVE_NVT_BASE
+ cpu
->vcpu_id
;
72 static int spapr_xive_target_to_nvt(uint32_t target
,
73 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
75 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
81 spapr_xive_cpu_to_nvt(cpu
, out_nvt_blk
, out_nvt_idx
);
86 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8
89 static void spapr_xive_cpu_to_end(PowerPCCPU
*cpu
, uint8_t prio
,
90 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
95 *out_end_blk
= SPAPR_XIVE_BLOCK_ID
;
99 *out_end_idx
= (cpu
->vcpu_id
<< 3) + prio
;
103 static int spapr_xive_target_to_end(uint32_t target
, uint8_t prio
,
104 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
106 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
112 spapr_xive_cpu_to_end(cpu
, prio
, out_end_blk
, out_end_idx
);
117 * On sPAPR machines, use a simplified output for the XIVE END
118 * structure dumping only the information related to the OS EQ.
120 static void spapr_xive_end_pic_print_info(sPAPRXive
*xive
, XiveEND
*end
,
123 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
124 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
125 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
126 uint32_t qentries
= 1 << (qsize
+ 10);
127 uint32_t nvt
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
128 uint8_t priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
130 monitor_printf(mon
, "%3d/%d % 6d/%5d ^%d",
131 spapr_xive_nvt_to_target(0, nvt
),
132 priority
, qindex
, qentries
, qgen
);
134 xive_end_queue_pic_print_info(end
, 6, mon
);
135 monitor_printf(mon
, "]");
138 void spapr_xive_pic_print_info(sPAPRXive
*xive
, Monitor
*mon
)
140 XiveSource
*xsrc
= &xive
->source
;
143 monitor_printf(mon
, " LSIN PQ EISN CPU/PRIO EQ\n");
145 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
146 uint8_t pq
= xive_source_esb_get(xsrc
, i
);
147 XiveEAS
*eas
= &xive
->eat
[i
];
149 if (!xive_eas_is_valid(eas
)) {
153 monitor_printf(mon
, " %08x %s %c%c%c %s %08x ", i
,
154 xive_source_irq_is_lsi(xsrc
, i
) ? "LSI" : "MSI",
155 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
156 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
157 xsrc
->status
[i
] & XIVE_STATUS_ASSERTED
? 'A' : ' ',
158 xive_eas_is_masked(eas
) ? "M" : " ",
159 (int) xive_get_field64(EAS_END_DATA
, eas
->w
));
161 if (!xive_eas_is_masked(eas
)) {
162 uint32_t end_idx
= xive_get_field64(EAS_END_INDEX
, eas
->w
);
165 assert(end_idx
< xive
->nr_ends
);
166 end
= &xive
->endt
[end_idx
];
168 if (xive_end_is_valid(end
)) {
169 spapr_xive_end_pic_print_info(xive
, end
, mon
);
172 monitor_printf(mon
, "\n");
176 static void spapr_xive_map_mmio(sPAPRXive
*xive
)
178 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 0, xive
->vc_base
);
179 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 1, xive
->end_base
);
180 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 2, xive
->tm_base
);
183 void spapr_xive_mmio_set_enabled(sPAPRXive
*xive
, bool enable
)
185 memory_region_set_enabled(&xive
->source
.esb_mmio
, enable
);
186 memory_region_set_enabled(&xive
->tm_mmio
, enable
);
188 /* Disable the END ESBs until a guest OS makes use of them */
189 memory_region_set_enabled(&xive
->end_source
.esb_mmio
, false);
193 * When a Virtual Processor is scheduled to run on a HW thread, the
194 * hypervisor pushes its identifier in the OS CAM line. Emulate the
195 * same behavior under QEMU.
197 void spapr_xive_set_tctx_os_cam(XiveTCTX
*tctx
)
203 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx
->cs
), &nvt_blk
, &nvt_idx
);
205 nvt_cam
= cpu_to_be32(TM_QW1W2_VO
| xive_nvt_cam_line(nvt_blk
, nvt_idx
));
206 memcpy(&tctx
->regs
[TM_QW1_OS
+ TM_WORD2
], &nvt_cam
, 4);
209 static void spapr_xive_end_reset(XiveEND
*end
)
211 memset(end
, 0, sizeof(*end
));
213 /* switch off the escalation and notification ESBs */
214 end
->w1
= cpu_to_be32(END_W1_ESe_Q
| END_W1_ESn_Q
);
217 static void spapr_xive_reset(void *dev
)
219 sPAPRXive
*xive
= SPAPR_XIVE(dev
);
223 * The XiveSource has its own reset handler, which mask off all
227 /* Mask all valid EASs in the IRQ number space. */
228 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
229 XiveEAS
*eas
= &xive
->eat
[i
];
230 if (xive_eas_is_valid(eas
)) {
231 eas
->w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
238 for (i
= 0; i
< xive
->nr_ends
; i
++) {
239 spapr_xive_end_reset(&xive
->endt
[i
]);
243 static void spapr_xive_instance_init(Object
*obj
)
245 sPAPRXive
*xive
= SPAPR_XIVE(obj
);
247 object_initialize(&xive
->source
, sizeof(xive
->source
), TYPE_XIVE_SOURCE
);
248 object_property_add_child(obj
, "source", OBJECT(&xive
->source
), NULL
);
250 object_initialize(&xive
->end_source
, sizeof(xive
->end_source
),
251 TYPE_XIVE_END_SOURCE
);
252 object_property_add_child(obj
, "end_source", OBJECT(&xive
->end_source
),
256 static void spapr_xive_realize(DeviceState
*dev
, Error
**errp
)
258 sPAPRXive
*xive
= SPAPR_XIVE(dev
);
259 XiveSource
*xsrc
= &xive
->source
;
260 XiveENDSource
*end_xsrc
= &xive
->end_source
;
261 Error
*local_err
= NULL
;
263 if (!xive
->nr_irqs
) {
264 error_setg(errp
, "Number of interrupt needs to be greater 0");
268 if (!xive
->nr_ends
) {
269 error_setg(errp
, "Number of interrupt needs to be greater 0");
274 * Initialize the internal sources, for IPIs and virtual devices.
276 object_property_set_int(OBJECT(xsrc
), xive
->nr_irqs
, "nr-irqs",
278 object_property_add_const_link(OBJECT(xsrc
), "xive", OBJECT(xive
),
280 object_property_set_bool(OBJECT(xsrc
), true, "realized", &local_err
);
282 error_propagate(errp
, local_err
);
287 * Initialize the END ESB source
289 object_property_set_int(OBJECT(end_xsrc
), xive
->nr_irqs
, "nr-ends",
291 object_property_add_const_link(OBJECT(end_xsrc
), "xive", OBJECT(xive
),
293 object_property_set_bool(OBJECT(end_xsrc
), true, "realized", &local_err
);
295 error_propagate(errp
, local_err
);
299 /* Set the mapping address of the END ESB pages after the source ESBs */
300 xive
->end_base
= xive
->vc_base
+ (1ull << xsrc
->esb_shift
) * xsrc
->nr_irqs
;
303 * Allocate the routing tables
305 xive
->eat
= g_new0(XiveEAS
, xive
->nr_irqs
);
306 xive
->endt
= g_new0(XiveEND
, xive
->nr_ends
);
308 /* TIMA initialization */
309 memory_region_init_io(&xive
->tm_mmio
, OBJECT(xive
), &xive_tm_ops
, xive
,
310 "xive.tima", 4ull << TM_SHIFT
);
312 /* Define all XIVE MMIO regions on SysBus */
313 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xsrc
->esb_mmio
);
314 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &end_xsrc
->esb_mmio
);
315 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xive
->tm_mmio
);
317 /* Map all regions */
318 spapr_xive_map_mmio(xive
);
320 qemu_register_reset(spapr_xive_reset
, dev
);
323 static int spapr_xive_get_eas(XiveRouter
*xrtr
, uint8_t eas_blk
,
324 uint32_t eas_idx
, XiveEAS
*eas
)
326 sPAPRXive
*xive
= SPAPR_XIVE(xrtr
);
328 if (eas_idx
>= xive
->nr_irqs
) {
332 *eas
= xive
->eat
[eas_idx
];
336 static int spapr_xive_get_end(XiveRouter
*xrtr
,
337 uint8_t end_blk
, uint32_t end_idx
, XiveEND
*end
)
339 sPAPRXive
*xive
= SPAPR_XIVE(xrtr
);
341 if (end_idx
>= xive
->nr_ends
) {
345 memcpy(end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
349 static int spapr_xive_write_end(XiveRouter
*xrtr
, uint8_t end_blk
,
350 uint32_t end_idx
, XiveEND
*end
,
353 sPAPRXive
*xive
= SPAPR_XIVE(xrtr
);
355 if (end_idx
>= xive
->nr_ends
) {
359 memcpy(&xive
->endt
[end_idx
], end
, sizeof(XiveEND
));
363 static int spapr_xive_get_nvt(XiveRouter
*xrtr
,
364 uint8_t nvt_blk
, uint32_t nvt_idx
, XiveNVT
*nvt
)
366 uint32_t vcpu_id
= spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
367 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
370 /* TODO: should we assert() if we can find a NVT ? */
375 * sPAPR does not maintain a NVT table. Return that the NVT is
376 * valid if we have found a matching CPU
378 nvt
->w0
= cpu_to_be32(NVT_W0_VALID
);
382 static int spapr_xive_write_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
,
383 uint32_t nvt_idx
, XiveNVT
*nvt
,
387 * We don't need to write back to the NVTs because the sPAPR
388 * machine should never hit a non-scheduled NVT. It should never
391 g_assert_not_reached();
394 static XiveTCTX
*spapr_xive_get_tctx(XiveRouter
*xrtr
, CPUState
*cs
)
396 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
398 return spapr_cpu_state(cpu
)->tctx
;
401 static const VMStateDescription vmstate_spapr_xive_end
= {
402 .name
= TYPE_SPAPR_XIVE
"/end",
404 .minimum_version_id
= 1,
405 .fields
= (VMStateField
[]) {
406 VMSTATE_UINT32(w0
, XiveEND
),
407 VMSTATE_UINT32(w1
, XiveEND
),
408 VMSTATE_UINT32(w2
, XiveEND
),
409 VMSTATE_UINT32(w3
, XiveEND
),
410 VMSTATE_UINT32(w4
, XiveEND
),
411 VMSTATE_UINT32(w5
, XiveEND
),
412 VMSTATE_UINT32(w6
, XiveEND
),
413 VMSTATE_UINT32(w7
, XiveEND
),
414 VMSTATE_END_OF_LIST()
418 static const VMStateDescription vmstate_spapr_xive_eas
= {
419 .name
= TYPE_SPAPR_XIVE
"/eas",
421 .minimum_version_id
= 1,
422 .fields
= (VMStateField
[]) {
423 VMSTATE_UINT64(w
, XiveEAS
),
424 VMSTATE_END_OF_LIST()
428 static const VMStateDescription vmstate_spapr_xive
= {
429 .name
= TYPE_SPAPR_XIVE
,
431 .minimum_version_id
= 1,
432 .fields
= (VMStateField
[]) {
433 VMSTATE_UINT32_EQUAL(nr_irqs
, sPAPRXive
, NULL
),
434 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat
, sPAPRXive
, nr_irqs
,
435 vmstate_spapr_xive_eas
, XiveEAS
),
436 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt
, sPAPRXive
, nr_ends
,
437 vmstate_spapr_xive_end
, XiveEND
),
438 VMSTATE_END_OF_LIST()
442 static Property spapr_xive_properties
[] = {
443 DEFINE_PROP_UINT32("nr-irqs", sPAPRXive
, nr_irqs
, 0),
444 DEFINE_PROP_UINT32("nr-ends", sPAPRXive
, nr_ends
, 0),
445 DEFINE_PROP_UINT64("vc-base", sPAPRXive
, vc_base
, SPAPR_XIVE_VC_BASE
),
446 DEFINE_PROP_UINT64("tm-base", sPAPRXive
, tm_base
, SPAPR_XIVE_TM_BASE
),
447 DEFINE_PROP_END_OF_LIST(),
450 static void spapr_xive_class_init(ObjectClass
*klass
, void *data
)
452 DeviceClass
*dc
= DEVICE_CLASS(klass
);
453 XiveRouterClass
*xrc
= XIVE_ROUTER_CLASS(klass
);
455 dc
->desc
= "sPAPR XIVE Interrupt Controller";
456 dc
->props
= spapr_xive_properties
;
457 dc
->realize
= spapr_xive_realize
;
458 dc
->vmsd
= &vmstate_spapr_xive
;
460 xrc
->get_eas
= spapr_xive_get_eas
;
461 xrc
->get_end
= spapr_xive_get_end
;
462 xrc
->write_end
= spapr_xive_write_end
;
463 xrc
->get_nvt
= spapr_xive_get_nvt
;
464 xrc
->write_nvt
= spapr_xive_write_nvt
;
465 xrc
->get_tctx
= spapr_xive_get_tctx
;
468 static const TypeInfo spapr_xive_info
= {
469 .name
= TYPE_SPAPR_XIVE
,
470 .parent
= TYPE_XIVE_ROUTER
,
471 .instance_init
= spapr_xive_instance_init
,
472 .instance_size
= sizeof(sPAPRXive
),
473 .class_init
= spapr_xive_class_init
,
476 static void spapr_xive_register_types(void)
478 type_register_static(&spapr_xive_info
);
481 type_init(spapr_xive_register_types
)
483 bool spapr_xive_irq_claim(sPAPRXive
*xive
, uint32_t lisn
, bool lsi
)
485 XiveSource
*xsrc
= &xive
->source
;
487 if (lisn
>= xive
->nr_irqs
) {
491 xive
->eat
[lisn
].w
|= cpu_to_be64(EAS_VALID
);
492 xive_source_irq_set(xsrc
, lisn
, lsi
);
496 bool spapr_xive_irq_free(sPAPRXive
*xive
, uint32_t lisn
)
498 XiveSource
*xsrc
= &xive
->source
;
500 if (lisn
>= xive
->nr_irqs
) {
504 xive
->eat
[lisn
].w
&= cpu_to_be64(~EAS_VALID
);
505 xive_source_irq_set(xsrc
, lisn
, false);
512 * The terminology used by the XIVE hcalls is the following :
515 * EQ Event Queue assigned by OS to receive event data
516 * ESB page for source interrupt management
517 * LISN Logical Interrupt Source Number identifying a source in the
519 * EISN Effective Interrupt Source Number used by guest OS to
520 * identify source in the guest
522 * The EAS, END, NVT structures are not exposed.
526 * Linux hosts under OPAL reserve priority 7 for their own escalation
527 * interrupts (DD2.X POWER9). So we only allow the guest to use
530 static bool spapr_xive_priority_is_reserved(uint8_t priority
)
535 case 7: /* OPAL escalation queue */
542 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical
543 * real address of the MMIO page through which the Event State Buffer
544 * entry associated with the value of the "lisn" parameter is managed.
550 * - R5: "lisn" is per "interrupts", "interrupt-map", or
551 * "ibm,xive-lisn-ranges" properties, or as returned by the
552 * ibm,query-interrupt-source-number RTAS call, or as returned
553 * by the H_ALLOCATE_VAS_WINDOW hcall
557 * Bits 0-59: Reserved
558 * Bit 60: H_INT_ESB must be used for Event State Buffer
560 * Bit 61: 1 == LSI 0 == MSI
561 * Bit 62: the full function page supports trigger
562 * Bit 63: Store EOI Supported
563 * - R5: Logical Real address of full function Event State Buffer
564 * management page, -1 if H_INT_ESB hcall flag is set to 1.
565 * - R6: Logical Real Address of trigger only Event State Buffer
566 * management page or -1.
567 * - R7: Power of 2 page size for the ESB management pages returned in
571 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */
572 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */
573 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management
575 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */
577 static target_ulong
h_int_get_source_info(PowerPCCPU
*cpu
,
578 sPAPRMachineState
*spapr
,
582 sPAPRXive
*xive
= spapr
->xive
;
583 XiveSource
*xsrc
= &xive
->source
;
584 target_ulong flags
= args
[0];
585 target_ulong lisn
= args
[1];
587 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
595 if (lisn
>= xive
->nr_irqs
) {
596 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
601 if (!xive_eas_is_valid(&xive
->eat
[lisn
])) {
602 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
608 * All sources are emulated under the main XIVE object and share
609 * the same characteristics.
612 if (!xive_source_esb_has_2page(xsrc
)) {
613 args
[0] |= SPAPR_XIVE_SRC_TRIGGER
;
615 if (xsrc
->esb_flags
& XIVE_SRC_STORE_EOI
) {
616 args
[0] |= SPAPR_XIVE_SRC_STORE_EOI
;
620 * Force the use of the H_INT_ESB hcall in case of an LSI
621 * interrupt. This is necessary under KVM to re-trigger the
622 * interrupt if the level is still asserted
624 if (xive_source_irq_is_lsi(xsrc
, lisn
)) {
625 args
[0] |= SPAPR_XIVE_SRC_H_INT_ESB
| SPAPR_XIVE_SRC_LSI
;
628 if (!(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
629 args
[1] = xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
);
634 if (xive_source_esb_has_2page(xsrc
) &&
635 !(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
636 args
[2] = xive
->vc_base
+ xive_source_esb_page(xsrc
, lisn
);
641 if (xive_source_esb_has_2page(xsrc
)) {
642 args
[3] = xsrc
->esb_shift
- 1;
644 args
[3] = xsrc
->esb_shift
;
651 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical
652 * Interrupt Source to a target. The Logical Interrupt Source is
653 * designated with the "lisn" parameter and the target is designated
654 * with the "target" and "priority" parameters. Upon return from the
655 * hcall(), no additional interrupts will be directed to the old EQ.
660 * Bits 0-61: Reserved
661 * Bit 62: set the "eisn" in the EAS
662 * Bit 63: masks the interrupt source in the hardware interrupt
663 * control structure. An interrupt masked by this mechanism will
664 * be dropped, but it's source state bits will still be
665 * set. There is no race-free way of unmasking and restoring the
666 * source. Thus this should only be used in interrupts that are
667 * also masked at the source, and only in cases where the
668 * interrupt is not meant to be used for a large amount of time
669 * because no valid target exists for it for example
670 * - R5: "lisn" is per "interrupts", "interrupt-map", or
671 * "ibm,xive-lisn-ranges" properties, or as returned by the
672 * ibm,query-interrupt-source-number RTAS call, or as returned by
673 * the H_ALLOCATE_VAS_WINDOW hcall
674 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or
675 * "ibm,ppc-interrupt-gserver#s"
676 * - R7: "priority" is a valid priority not in
677 * "ibm,plat-res-int-priorities"
678 * - R8: "eisn" is the guest EISN associated with the "lisn"
684 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62)
685 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63)
687 static target_ulong
h_int_set_source_config(PowerPCCPU
*cpu
,
688 sPAPRMachineState
*spapr
,
692 sPAPRXive
*xive
= spapr
->xive
;
693 XiveEAS eas
, new_eas
;
694 target_ulong flags
= args
[0];
695 target_ulong lisn
= args
[1];
696 target_ulong target
= args
[2];
697 target_ulong priority
= args
[3];
698 target_ulong eisn
= args
[4];
702 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
706 if (flags
& ~(SPAPR_XIVE_SRC_SET_EISN
| SPAPR_XIVE_SRC_MASK
)) {
710 if (lisn
>= xive
->nr_irqs
) {
711 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
716 eas
= xive
->eat
[lisn
];
717 if (!xive_eas_is_valid(&eas
)) {
718 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
723 /* priority 0xff is used to reset the EAS */
724 if (priority
== 0xff) {
725 new_eas
.w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
729 if (flags
& SPAPR_XIVE_SRC_MASK
) {
730 new_eas
.w
= eas
.w
| cpu_to_be64(EAS_MASKED
);
732 new_eas
.w
= eas
.w
& cpu_to_be64(~EAS_MASKED
);
735 if (spapr_xive_priority_is_reserved(priority
)) {
736 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
737 " is reserved\n", priority
);
742 * Validate that "target" is part of the list of threads allocated
743 * to the partition. For that, find the END corresponding to the
746 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
750 new_eas
.w
= xive_set_field64(EAS_END_BLOCK
, new_eas
.w
, end_blk
);
751 new_eas
.w
= xive_set_field64(EAS_END_INDEX
, new_eas
.w
, end_idx
);
753 if (flags
& SPAPR_XIVE_SRC_SET_EISN
) {
754 new_eas
.w
= xive_set_field64(EAS_END_DATA
, new_eas
.w
, eisn
);
758 xive
->eat
[lisn
] = new_eas
;
763 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which
764 * target/priority pair is assigned to the specified Logical Interrupt
771 * - R5: "lisn" is per "interrupts", "interrupt-map", or
772 * "ibm,xive-lisn-ranges" properties, or as returned by the
773 * ibm,query-interrupt-source-number RTAS call, or as
774 * returned by the H_ALLOCATE_VAS_WINDOW hcall
777 * - R4: Target to which the specified Logical Interrupt Source is
779 * - R5: Priority to which the specified Logical Interrupt Source is
781 * - R6: EISN for the specified Logical Interrupt Source (this will be
782 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG)
784 static target_ulong
h_int_get_source_config(PowerPCCPU
*cpu
,
785 sPAPRMachineState
*spapr
,
789 sPAPRXive
*xive
= spapr
->xive
;
790 target_ulong flags
= args
[0];
791 target_ulong lisn
= args
[1];
795 uint32_t end_idx
, nvt_idx
;
797 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
805 if (lisn
>= xive
->nr_irqs
) {
806 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
811 eas
= xive
->eat
[lisn
];
812 if (!xive_eas_is_valid(&eas
)) {
813 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
818 /* EAS_END_BLOCK is unused on sPAPR */
819 end_idx
= xive_get_field64(EAS_END_INDEX
, eas
.w
);
821 assert(end_idx
< xive
->nr_ends
);
822 end
= &xive
->endt
[end_idx
];
824 nvt_blk
= xive_get_field32(END_W6_NVT_BLOCK
, end
->w6
);
825 nvt_idx
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
826 args
[0] = spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
828 if (xive_eas_is_masked(&eas
)) {
831 args
[1] = xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
834 args
[2] = xive_get_field64(EAS_END_DATA
, eas
.w
);
840 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real
841 * address of the notification management page associated with the
842 * specified target and priority.
848 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
849 * "ibm,ppc-interrupt-gserver#s"
850 * - R6: "priority" is a valid priority not in
851 * "ibm,plat-res-int-priorities"
854 * - R4: Logical real address of notification page
855 * - R5: Power of 2 page size of the notification page
857 static target_ulong
h_int_get_queue_info(PowerPCCPU
*cpu
,
858 sPAPRMachineState
*spapr
,
862 sPAPRXive
*xive
= spapr
->xive
;
863 XiveENDSource
*end_xsrc
= &xive
->end_source
;
864 target_ulong flags
= args
[0];
865 target_ulong target
= args
[1];
866 target_ulong priority
= args
[2];
871 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
880 * H_STATE should be returned if a H_INT_RESET is in progress.
881 * This is not needed when running the emulation under QEMU
884 if (spapr_xive_priority_is_reserved(priority
)) {
885 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
886 " is reserved\n", priority
);
891 * Validate that "target" is part of the list of threads allocated
892 * to the partition. For that, find the END corresponding to the
895 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
899 assert(end_idx
< xive
->nr_ends
);
900 end
= &xive
->endt
[end_idx
];
902 args
[0] = xive
->end_base
+ (1ull << (end_xsrc
->esb_shift
+ 1)) * end_idx
;
903 if (xive_end_is_enqueue(end
)) {
904 args
[1] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
913 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for
914 * a given "target" and "priority". It is also used to set the
915 * notification config associated with the EQ. An EQ size of 0 is
916 * used to reset the EQ config for a given target and priority. If
917 * resetting the EQ config, the END associated with the given "target"
918 * and "priority" will be changed to disable queueing.
920 * Upon return from the hcall(), no additional interrupts will be
921 * directed to the old EQ (if one was set). The old EQ (if one was
922 * set) should be investigated for interrupts that occurred prior to
923 * or during the hcall().
928 * Bits 0-62: Reserved
929 * Bit 63: Unconditional Notify (n) per the XIVE spec
930 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
931 * "ibm,ppc-interrupt-gserver#s"
932 * - R6: "priority" is a valid priority not in
933 * "ibm,plat-res-int-priorities"
934 * - R7: "eventQueue": The logical real address of the start of the EQ
935 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes"
941 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63)
943 static target_ulong
h_int_set_queue_config(PowerPCCPU
*cpu
,
944 sPAPRMachineState
*spapr
,
948 sPAPRXive
*xive
= spapr
->xive
;
949 target_ulong flags
= args
[0];
950 target_ulong target
= args
[1];
951 target_ulong priority
= args
[2];
952 target_ulong qpage
= args
[3];
953 target_ulong qsize
= args
[4];
955 uint8_t end_blk
, nvt_blk
;
956 uint32_t end_idx
, nvt_idx
;
958 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
962 if (flags
& ~SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
967 * H_STATE should be returned if a H_INT_RESET is in progress.
968 * This is not needed when running the emulation under QEMU
971 if (spapr_xive_priority_is_reserved(priority
)) {
972 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
973 " is reserved\n", priority
);
978 * Validate that "target" is part of the list of threads allocated
979 * to the partition. For that, find the END corresponding to the
983 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
987 assert(end_idx
< xive
->nr_ends
);
988 memcpy(&end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
995 end
.w2
= cpu_to_be32((qpage
>> 32) & 0x0fffffff);
996 end
.w3
= cpu_to_be32(qpage
& 0xffffffff);
997 end
.w0
|= cpu_to_be32(END_W0_ENQUEUE
);
998 end
.w0
= xive_set_field32(END_W0_QSIZE
, end
.w0
, qsize
- 12);
1001 /* reset queue and disable queueing */
1002 spapr_xive_end_reset(&end
);
1006 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid EQ size %"PRIx64
"\n",
1012 hwaddr plen
= 1 << qsize
;
1016 * Validate the guest EQ. We should also check that the queue
1017 * has been zeroed by the OS.
1019 eq
= address_space_map(CPU(cpu
)->as
, qpage
, &plen
, true,
1020 MEMTXATTRS_UNSPECIFIED
);
1021 if (plen
!= 1 << qsize
) {
1022 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to map EQ @0x%"
1023 HWADDR_PRIx
"\n", qpage
);
1026 address_space_unmap(CPU(cpu
)->as
, eq
, plen
, true, plen
);
1029 /* "target" should have been validated above */
1030 if (spapr_xive_target_to_nvt(target
, &nvt_blk
, &nvt_idx
)) {
1031 g_assert_not_reached();
1035 * Ensure the priority and target are correctly set (they will not
1036 * be right after allocation)
1038 end
.w6
= xive_set_field32(END_W6_NVT_BLOCK
, 0ul, nvt_blk
) |
1039 xive_set_field32(END_W6_NVT_INDEX
, 0ul, nvt_idx
);
1040 end
.w7
= xive_set_field32(END_W7_F0_PRIORITY
, 0ul, priority
);
1042 if (flags
& SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
1043 end
.w0
|= cpu_to_be32(END_W0_UCOND_NOTIFY
);
1045 end
.w0
&= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY
);
1049 * The generation bit for the END starts at 1 and The END page
1050 * offset counter starts at 0.
1052 end
.w1
= cpu_to_be32(END_W1_GENERATION
) |
1053 xive_set_field32(END_W1_PAGE_OFF
, 0ul, 0ul);
1054 end
.w0
|= cpu_to_be32(END_W0_VALID
);
1057 * TODO: issue syncs required to ensure all in-flight interrupts
1058 * are complete on the old END
1063 memcpy(&xive
->endt
[end_idx
], &end
, sizeof(XiveEND
));
1068 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given
1069 * target and priority.
1074 * Bits 0-62: Reserved
1075 * Bit 63: Debug: Return debug data
1076 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1077 * "ibm,ppc-interrupt-gserver#s"
1078 * - R6: "priority" is a valid priority not in
1079 * "ibm,plat-res-int-priorities"
1083 * Bits 0-61: Reserved
1084 * Bit 62: The value of Event Queue Generation Number (g) per
1085 * the XIVE spec if "Debug" = 1
1086 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec
1087 * - R5: The logical real address of the start of the EQ
1088 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes"
1089 * - R7: The value of Event Queue Offset Counter per XIVE spec
1090 * if "Debug" = 1, else 0
1094 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63)
1096 static target_ulong
h_int_get_queue_config(PowerPCCPU
*cpu
,
1097 sPAPRMachineState
*spapr
,
1098 target_ulong opcode
,
1101 sPAPRXive
*xive
= spapr
->xive
;
1102 target_ulong flags
= args
[0];
1103 target_ulong target
= args
[1];
1104 target_ulong priority
= args
[2];
1109 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1113 if (flags
& ~SPAPR_XIVE_END_DEBUG
) {
1118 * H_STATE should be returned if a H_INT_RESET is in progress.
1119 * This is not needed when running the emulation under QEMU
1122 if (spapr_xive_priority_is_reserved(priority
)) {
1123 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1124 " is reserved\n", priority
);
1129 * Validate that "target" is part of the list of threads allocated
1130 * to the partition. For that, find the END corresponding to the
1133 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1137 assert(end_idx
< xive
->nr_ends
);
1138 end
= &xive
->endt
[end_idx
];
1141 if (xive_end_is_notify(end
)) {
1142 args
[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY
;
1145 if (xive_end_is_enqueue(end
)) {
1146 args
[1] = (uint64_t) be32_to_cpu(end
->w2
& 0x0fffffff) << 32
1147 | be32_to_cpu(end
->w3
);
1148 args
[2] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
1154 /* TODO: do we need any locking on the END ? */
1155 if (flags
& SPAPR_XIVE_END_DEBUG
) {
1156 /* Load the event queue generation number into the return flags */
1157 args
[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION
, end
->w1
) << 62;
1159 /* Load R7 with the event queue offset counter */
1160 args
[3] = xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1169 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the
1170 * reporting cache line pair for the calling thread. The reporting
1171 * cache lines will contain the OS interrupt context when the OS
1172 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS
1173 * interrupt. The reporting cache lines can be reset by inputting -1
1174 * in "reportingLine". Issuing the CI store byte without reporting
1175 * cache lines registered will result in the data not being accessible
1181 * Bits 0-63: Reserved
1182 * - R5: "reportingLine": The logical real address of the reporting cache
1188 static target_ulong
h_int_set_os_reporting_line(PowerPCCPU
*cpu
,
1189 sPAPRMachineState
*spapr
,
1190 target_ulong opcode
,
1193 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1198 * H_STATE should be returned if a H_INT_RESET is in progress.
1199 * This is not needed when running the emulation under QEMU
1202 /* TODO: H_INT_SET_OS_REPORTING_LINE */
1207 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical
1208 * real address of the reporting cache line pair set for the input
1209 * "target". If no reporting cache line pair has been set, -1 is
1215 * Bits 0-63: Reserved
1216 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1217 * "ibm,ppc-interrupt-gserver#s"
1218 * - R6: "reportingLine": The logical real address of the reporting
1222 * - R4: The logical real address of the reporting line if set, else -1
1224 static target_ulong
h_int_get_os_reporting_line(PowerPCCPU
*cpu
,
1225 sPAPRMachineState
*spapr
,
1226 target_ulong opcode
,
1229 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1234 * H_STATE should be returned if a H_INT_RESET is in progress.
1235 * This is not needed when running the emulation under QEMU
1238 /* TODO: H_INT_GET_OS_REPORTING_LINE */
1243 * The H_INT_ESB hcall() is used to issue a load or store to the ESB
1244 * page for the input "lisn". This hcall is only supported for LISNs
1245 * that have the ESB hcall flag set to 1 when returned from hcall()
1246 * H_INT_GET_SOURCE_INFO.
1251 * Bits 0-62: Reserved
1252 * bit 63: Store: Store=1, store operation, else load operation
1253 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1254 * "ibm,xive-lisn-ranges" properties, or as returned by the
1255 * ibm,query-interrupt-source-number RTAS call, or as
1256 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1257 * - R6: "esbOffset" is the offset into the ESB page for the load or
1259 * - R7: "storeData" is the data to write for a store operation
1262 * - R4: The value of the load if load operation, else -1
1265 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63)
1267 static target_ulong
h_int_esb(PowerPCCPU
*cpu
,
1268 sPAPRMachineState
*spapr
,
1269 target_ulong opcode
,
1272 sPAPRXive
*xive
= spapr
->xive
;
1274 target_ulong flags
= args
[0];
1275 target_ulong lisn
= args
[1];
1276 target_ulong offset
= args
[2];
1277 target_ulong data
= args
[3];
1279 XiveSource
*xsrc
= &xive
->source
;
1281 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1285 if (flags
& ~SPAPR_XIVE_ESB_STORE
) {
1289 if (lisn
>= xive
->nr_irqs
) {
1290 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1295 eas
= xive
->eat
[lisn
];
1296 if (!xive_eas_is_valid(&eas
)) {
1297 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1302 if (offset
> (1ull << xsrc
->esb_shift
)) {
1306 mmio_addr
= xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
) + offset
;
1308 if (dma_memory_rw(&address_space_memory
, mmio_addr
, &data
, 8,
1309 (flags
& SPAPR_XIVE_ESB_STORE
))) {
1310 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to access ESB @0x%"
1311 HWADDR_PRIx
"\n", mmio_addr
);
1314 args
[0] = (flags
& SPAPR_XIVE_ESB_STORE
) ? -1 : data
;
1319 * The H_INT_SYNC hcall() is used to issue hardware syncs that will
1320 * ensure any in flight events for the input lisn are in the event
1326 * Bits 0-63: Reserved
1327 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1328 * "ibm,xive-lisn-ranges" properties, or as returned by the
1329 * ibm,query-interrupt-source-number RTAS call, or as
1330 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1335 static target_ulong
h_int_sync(PowerPCCPU
*cpu
,
1336 sPAPRMachineState
*spapr
,
1337 target_ulong opcode
,
1340 sPAPRXive
*xive
= spapr
->xive
;
1342 target_ulong flags
= args
[0];
1343 target_ulong lisn
= args
[1];
1345 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1353 if (lisn
>= xive
->nr_irqs
) {
1354 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1359 eas
= xive
->eat
[lisn
];
1360 if (!xive_eas_is_valid(&eas
)) {
1361 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1367 * H_STATE should be returned if a H_INT_RESET is in progress.
1368 * This is not needed when running the emulation under QEMU
1371 /* This is not real hardware. Nothing to be done */
1376 * The H_INT_RESET hcall() is used to reset all of the partition's
1377 * interrupt exploitation structures to their initial state. This
1378 * means losing all previously set interrupt state set via
1379 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG.
1384 * Bits 0-63: Reserved
1389 static target_ulong
h_int_reset(PowerPCCPU
*cpu
,
1390 sPAPRMachineState
*spapr
,
1391 target_ulong opcode
,
1394 sPAPRXive
*xive
= spapr
->xive
;
1395 target_ulong flags
= args
[0];
1397 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1405 device_reset(DEVICE(xive
));
1409 void spapr_xive_hcall_init(sPAPRMachineState
*spapr
)
1411 spapr_register_hypercall(H_INT_GET_SOURCE_INFO
, h_int_get_source_info
);
1412 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG
, h_int_set_source_config
);
1413 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG
, h_int_get_source_config
);
1414 spapr_register_hypercall(H_INT_GET_QUEUE_INFO
, h_int_get_queue_info
);
1415 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG
, h_int_set_queue_config
);
1416 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG
, h_int_get_queue_config
);
1417 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE
,
1418 h_int_set_os_reporting_line
);
1419 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE
,
1420 h_int_get_os_reporting_line
);
1421 spapr_register_hypercall(H_INT_ESB
, h_int_esb
);
1422 spapr_register_hypercall(H_INT_SYNC
, h_int_sync
);
1423 spapr_register_hypercall(H_INT_RESET
, h_int_reset
);
1426 void spapr_dt_xive(sPAPRMachineState
*spapr
, uint32_t nr_servers
, void *fdt
,
1429 sPAPRXive
*xive
= spapr
->xive
;
1431 uint64_t timas
[2 * 2];
1432 /* Interrupt number ranges for the IPIs */
1433 uint32_t lisn_ranges
[] = {
1435 cpu_to_be32(nr_servers
),
1438 * EQ size - the sizes of pages supported by the system 4K, 64K,
1439 * 2M, 16M. We only advertise 64K for the moment.
1441 uint32_t eq_sizes
[] = {
1442 cpu_to_be32(16), /* 64K */
1445 * The following array is in sync with the reserved priorities
1446 * defined by the 'spapr_xive_priority_is_reserved' routine.
1448 uint32_t plat_res_int_priorities
[] = {
1449 cpu_to_be32(7), /* start */
1450 cpu_to_be32(0xf8), /* count */
1454 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */
1455 timas
[0] = cpu_to_be64(xive
->tm_base
+
1456 XIVE_TM_USER_PAGE
* (1ull << TM_SHIFT
));
1457 timas
[1] = cpu_to_be64(1ull << TM_SHIFT
);
1458 timas
[2] = cpu_to_be64(xive
->tm_base
+
1459 XIVE_TM_OS_PAGE
* (1ull << TM_SHIFT
));
1460 timas
[3] = cpu_to_be64(1ull << TM_SHIFT
);
1462 nodename
= g_strdup_printf("interrupt-controller@%" PRIx64
,
1463 xive
->tm_base
+ XIVE_TM_USER_PAGE
* (1 << TM_SHIFT
));
1464 _FDT(node
= fdt_add_subnode(fdt
, 0, nodename
));
1467 _FDT(fdt_setprop_string(fdt
, node
, "device_type", "power-ivpe"));
1468 _FDT(fdt_setprop(fdt
, node
, "reg", timas
, sizeof(timas
)));
1470 _FDT(fdt_setprop_string(fdt
, node
, "compatible", "ibm,power-ivpe"));
1471 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-eq-sizes", eq_sizes
,
1473 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-lisn-ranges", lisn_ranges
,
1474 sizeof(lisn_ranges
)));
1476 /* For Linux to link the LSIs to the interrupt controller. */
1477 _FDT(fdt_setprop(fdt
, node
, "interrupt-controller", NULL
, 0));
1478 _FDT(fdt_setprop_cell(fdt
, node
, "#interrupt-cells", 2));
1481 _FDT(fdt_setprop_cell(fdt
, node
, "linux,phandle", phandle
));
1482 _FDT(fdt_setprop_cell(fdt
, node
, "phandle", phandle
));
1485 * The "ibm,plat-res-int-priorities" property defines the priority
1486 * ranges reserved by the hypervisor
1488 _FDT(fdt_setprop(fdt
, 0, "ibm,plat-res-int-priorities",
1489 plat_res_int_priorities
, sizeof(plat_res_int_priorities
)));