hw/char/imx_serial.c

   1 /*
   2  * IMX31 UARTS
   3  *
   4  * Copyright (c) 2008 OKL
   5  * Originally Written by Hans Jiang
   6  * Copyright (c) 2011 NICTA Pty Ltd.
   7  * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10  * See the COPYING file in the top-level directory.
  11  *
  12  * This is a `bare-bones' implementation of the IMX series serial ports.
  13  * TODO:
  14  *  -- implement FIFOs.  The real hardware has 32 word transmit
  15  *                       and receive FIFOs; we currently use a 1-char buffer
  16  *  -- implement DMA
  17  *  -- implement BAUD-rate and modem lines, for when the backend
  18  *     is a real serial device.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "hw/char/imx_serial.h"
  23 #include "sysemu/sysemu.h"
  24 #include "qemu/log.h"
  25
  26 #ifndef DEBUG_IMX_UART
  27 #define DEBUG_IMX_UART 0
  28 #endif
  29
  30 #define DPRINTF(fmt, args...) \
  31     do { \
  32         if (DEBUG_IMX_UART) { \
  33             fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \
  34                                              __func__, ##args); \
  35         } \
  36     } while (0)
  37
  38 static const VMStateDescription vmstate_imx_serial = {
  39     .name = TYPE_IMX_SERIAL,
  40     .version_id = 2,
  41     .minimum_version_id = 2,
  42     .fields = (VMStateField[]) {
  43         VMSTATE_INT32(readbuff, IMXSerialState),
  44         VMSTATE_UINT32(usr1, IMXSerialState),
  45         VMSTATE_UINT32(usr2, IMXSerialState),
  46         VMSTATE_UINT32(ucr1, IMXSerialState),
  47         VMSTATE_UINT32(uts1, IMXSerialState),
  48         VMSTATE_UINT32(onems, IMXSerialState),
  49         VMSTATE_UINT32(ufcr, IMXSerialState),
  50         VMSTATE_UINT32(ubmr, IMXSerialState),
  51         VMSTATE_UINT32(ubrc, IMXSerialState),
  52         VMSTATE_UINT32(ucr3, IMXSerialState),
  53         VMSTATE_UINT32(ucr4, IMXSerialState),
  54         VMSTATE_END_OF_LIST()
  55     },
  56 };
  57
  58 static void imx_update(IMXSerialState *s)
  59 {
  60     uint32_t usr1;
  61     uint32_t usr2;
  62     uint32_t mask;
  63
  64     /*
  65      * Lucky for us TRDY and RRDY has the same offset in both USR1 and
  66      * UCR1, so we can get away with something as simple as the
  67      * following:
  68      */
  69     usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
  70     /*
  71      * Bits that we want in USR2 are not as conveniently laid out,
  72      * unfortunately.
  73      */
  74     mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
  75     /*
  76      * TCEN and TXDC are both bit 3
  77      * RDR and DREN are both bit 0
  78      */
  79     mask |= s->ucr4 & (UCR4_TCEN | UCR4_DREN);
  80
  81     usr2 = s->usr2 & mask;
  82
  83     qemu_set_irq(s->irq, usr1 || usr2);
  84 }
  85
  86 static void imx_serial_reset(IMXSerialState *s)
  87 {
  88
  89     s->usr1 = USR1_TRDY | USR1_RXDS;
  90     /*
  91      * Fake attachment of a terminal: assert RTS.
  92      */
  93     s->usr1 |= USR1_RTSS;
  94     s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN;
  95     s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY;
  96     s->ucr1 = 0;
  97     s->ucr2 = UCR2_SRST;
  98     s->ucr3 = 0x700;
  99     s->ubmr = 0;
 100     s->ubrc = 4;
 101     s->readbuff = URXD_ERR;
 102 }
 103
 104 static void imx_serial_reset_at_boot(DeviceState *dev)
 105 {
 106     IMXSerialState *s = IMX_SERIAL(dev);
 107
 108     imx_serial_reset(s);
 109
 110     /*
 111      * enable the uart on boot, so messages from the linux decompresser
 112      * are visible.  On real hardware this is done by the boot rom
 113      * before anything else is loaded.
 114      */
 115     s->ucr1 = UCR1_UARTEN;
 116     s->ucr2 = UCR2_TXEN;
 117
 118 }
 119
 120 static uint64_t imx_serial_read(void *opaque, hwaddr offset,
 121                                 unsigned size)
 122 {
 123     IMXSerialState *s = (IMXSerialState *)opaque;
 124     uint32_t c;
 125
 126     DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset);
 127
 128     switch (offset >> 2) {
 129     case 0x0: /* URXD */
 130         c = s->readbuff;
 131         if (!(s->uts1 & UTS1_RXEMPTY)) {
 132             /* Character is valid */
 133             c |= URXD_CHARRDY;
 134             s->usr1 &= ~USR1_RRDY;
 135             s->usr2 &= ~USR2_RDR;
 136             s->uts1 |= UTS1_RXEMPTY;
 137             imx_update(s);
 138             qemu_chr_fe_accept_input(&s->chr);
 139         }
 140         return c;
 141
 142     case 0x20: /* UCR1 */
 143         return s->ucr1;
 144
 145     case 0x21: /* UCR2 */
 146         return s->ucr2;
 147
 148     case 0x25: /* USR1 */
 149         return s->usr1;
 150
 151     case 0x26: /* USR2 */
 152         return s->usr2;
 153
 154     case 0x2A: /* BRM Modulator */
 155         return s->ubmr;
 156
 157     case 0x2B: /* Baud Rate Count */
 158         return s->ubrc;
 159
 160     case 0x2d: /* Test register */
 161         return s->uts1;
 162
 163     case 0x24: /* UFCR */
 164         return s->ufcr;
 165
 166     case 0x2c:
 167         return s->onems;
 168
 169     case 0x22: /* UCR3 */
 170         return s->ucr3;
 171
 172     case 0x23: /* UCR4 */
 173         return s->ucr4;
 174
 175     case 0x29: /* BRM Incremental */
 176         return 0x0; /* TODO */
 177
 178     default:
 179         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 180                       HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
 181         return 0;
 182     }
 183 }
 184
 185 static void imx_serial_write(void *opaque, hwaddr offset,
 186                              uint64_t value, unsigned size)
 187 {
 188     IMXSerialState *s = (IMXSerialState *)opaque;
 189     Chardev *chr = qemu_chr_fe_get_driver(&s->chr);
 190     unsigned char ch;
 191
 192     DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n",
 193             offset, (unsigned int)value, chr ? chr->label : "NODEV");
 194
 195     switch (offset >> 2) {
 196     case 0x10: /* UTXD */
 197         ch = value;
 198         if (s->ucr2 & UCR2_TXEN) {
 199             /* XXX this blocks entire thread. Rewrite to use
 200              * qemu_chr_fe_write and background I/O callbacks */
 201             qemu_chr_fe_write_all(&s->chr, &ch, 1);
 202             s->usr1 &= ~USR1_TRDY;
 203             s->usr2 &= ~USR2_TXDC;
 204             imx_update(s);
 205             s->usr1 |= USR1_TRDY;
 206             s->usr2 |= USR2_TXDC;
 207             imx_update(s);
 208         }
 209         break;
 210
 211     case 0x20: /* UCR1 */
 212         s->ucr1 = value & 0xffff;
 213
 214         DPRINTF("write(ucr1=%x)\n", (unsigned int)value);
 215
 216         imx_update(s);
 217         break;
 218
 219     case 0x21: /* UCR2 */
 220         /*
 221          * Only a few bits in control register 2 are implemented as yet.
 222          * If it's intended to use a real serial device as a back-end, this
 223          * register will have to be implemented more fully.
 224          */
 225         if (!(value & UCR2_SRST)) {
 226             imx_serial_reset(s);
 227             imx_update(s);
 228             value |= UCR2_SRST;
 229         }
 230         if (value & UCR2_RXEN) {
 231             if (!(s->ucr2 & UCR2_RXEN)) {
 232                 qemu_chr_fe_accept_input(&s->chr);
 233             }
 234         }
 235         s->ucr2 = value & 0xffff;
 236         break;
 237
 238     case 0x25: /* USR1 */
 239         value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM |
 240                  USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER;
 241         s->usr1 &= ~value;
 242         break;
 243
 244     case 0x26: /* USR2 */
 245         /*
 246          * Writing 1 to some bits clears them; all other
 247          * values are ignored
 248          */
 249         value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST |
 250                  USR2_RIDELT | USR2_IRINT | USR2_WAKE |
 251                  USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE;
 252         s->usr2 &= ~value;
 253         break;
 254
 255     /*
 256      * Linux expects to see what it writes to these registers
 257      * We don't currently alter the baud rate
 258      */
 259     case 0x29: /* UBIR */
 260         s->ubrc = value & 0xffff;
 261         break;
 262
 263     case 0x2a: /* UBMR */
 264         s->ubmr = value & 0xffff;
 265         break;
 266
 267     case 0x2c: /* One ms reg */
 268         s->onems = value & 0xffff;
 269         break;
 270
 271     case 0x24: /* FIFO control register */
 272         s->ufcr = value & 0xffff;
 273         break;
 274
 275     case 0x22: /* UCR3 */
 276         s->ucr3 = value & 0xffff;
 277         break;
 278
 279     case 0x23: /* UCR4 */
 280         s->ucr4 = value & 0xffff;
 281         imx_update(s);
 282         break;
 283
 284     case 0x2d: /* UTS1 */
 285         qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
 286                       HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
 287         /* TODO */
 288         break;
 289
 290     default:
 291         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 292                       HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
 293     }
 294 }
 295
 296 static int imx_can_receive(void *opaque)
 297 {
 298     IMXSerialState *s = (IMXSerialState *)opaque;
 299     return !(s->usr1 & USR1_RRDY);
 300 }
 301
 302 static void imx_put_data(void *opaque, uint32_t value)
 303 {
 304     IMXSerialState *s = (IMXSerialState *)opaque;
 305
 306     DPRINTF("received char\n");
 307
 308     s->usr1 |= USR1_RRDY;
 309     s->usr2 |= USR2_RDR;
 310     s->uts1 &= ~UTS1_RXEMPTY;
 311     s->readbuff = value;
 312     if (value & URXD_BRK) {
 313         s->usr2 |= USR2_BRCD;
 314     }
 315     imx_update(s);
 316 }
 317
 318 static void imx_receive(void *opaque, const uint8_t *buf, int size)
 319 {
 320     imx_put_data(opaque, *buf);
 321 }
 322
 323 static void imx_event(void *opaque, int event)
 324 {
 325     if (event == CHR_EVENT_BREAK) {
 326         imx_put_data(opaque, URXD_BRK | URXD_FRMERR | URXD_ERR);
 327     }
 328 }
 329
 330
 331 static const struct MemoryRegionOps imx_serial_ops = {
 332     .read = imx_serial_read,
 333     .write = imx_serial_write,
 334     .endianness = DEVICE_NATIVE_ENDIAN,
 335 };
 336
 337 static void imx_serial_realize(DeviceState *dev, Error **errp)
 338 {
 339     IMXSerialState *s = IMX_SERIAL(dev);
 340
 341     DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr));
 342
 343     qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive,
 344                              imx_event, NULL, s, NULL, true);
 345 }
 346
 347 static void imx_serial_init(Object *obj)
 348 {
 349     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 350     IMXSerialState *s = IMX_SERIAL(obj);
 351
 352     memory_region_init_io(&s->iomem, obj, &imx_serial_ops, s,
 353                           TYPE_IMX_SERIAL, 0x1000);
 354     sysbus_init_mmio(sbd, &s->iomem);
 355     sysbus_init_irq(sbd, &s->irq);
 356 }
 357
 358 static Property imx_serial_properties[] = {
 359     DEFINE_PROP_CHR("chardev", IMXSerialState, chr),
 360     DEFINE_PROP_END_OF_LIST(),
 361 };
 362
 363 static void imx_serial_class_init(ObjectClass *klass, void *data)
 364 {
 365     DeviceClass *dc = DEVICE_CLASS(klass);
 366
 367     dc->realize = imx_serial_realize;
 368     dc->vmsd = &vmstate_imx_serial;
 369     dc->reset = imx_serial_reset_at_boot;
 370     set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 371     dc->desc = "i.MX series UART";
 372     dc->props = imx_serial_properties;
 373 }
 374
 375 static const TypeInfo imx_serial_info = {
 376     .name           = TYPE_IMX_SERIAL,
 377     .parent         = TYPE_SYS_BUS_DEVICE,
 378     .instance_size  = sizeof(IMXSerialState),
 379     .instance_init  = imx_serial_init,
 380     .class_init     = imx_serial_class_init,
 381 };
 382
 383 static void imx_serial_register_types(void)
 384 {
 385     type_register_static(&imx_serial_info);
 386 }
 387
 388 type_init(imx_serial_register_types)