4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu-common.h"
27 #include "qemu/datadir.h"
28 #include "qemu/units.h"
30 #include "hw/pci/pci.h"
31 #include "hw/pci/pci_bridge.h"
32 #include "hw/pci/pci_bus.h"
33 #include "hw/pci/pci_host.h"
34 #include "hw/qdev-properties.h"
35 #include "hw/qdev-properties-system.h"
36 #include "migration/qemu-file-types.h"
37 #include "migration/vmstate.h"
38 #include "monitor/monitor.h"
40 #include "sysemu/numa.h"
41 #include "sysemu/sysemu.h"
42 #include "hw/loader.h"
43 #include "qemu/error-report.h"
44 #include "qemu/range.h"
46 #include "hw/pci/msi.h"
47 #include "hw/pci/msix.h"
48 #include "exec/address-spaces.h"
49 #include "hw/hotplug.h"
50 #include "hw/boards.h"
51 #include "qapi/error.h"
52 #include "qapi/qapi-commands-pci.h"
53 #include "qemu/cutils.h"
57 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
59 # define PCI_DPRINTF(format, ...) do { } while (0)
62 bool pci_available
= true;
64 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
65 static char *pcibus_get_dev_path(DeviceState
*dev
);
66 static char *pcibus_get_fw_dev_path(DeviceState
*dev
);
67 static void pcibus_reset(BusState
*qbus
);
69 static Property pci_props
[] = {
70 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
71 DEFINE_PROP_STRING("romfile", PCIDevice
, romfile
),
72 DEFINE_PROP_UINT32("romsize", PCIDevice
, romsize
, -1),
73 DEFINE_PROP_UINT32("rombar", PCIDevice
, rom_bar
, 1),
74 DEFINE_PROP_BIT("multifunction", PCIDevice
, cap_present
,
75 QEMU_PCI_CAP_MULTIFUNCTION_BITNR
, false),
76 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice
, cap_present
,
77 QEMU_PCIE_LNKSTA_DLLLA_BITNR
, true),
78 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice
, cap_present
,
79 QEMU_PCIE_EXTCAP_INIT_BITNR
, true),
80 DEFINE_PROP_STRING("failover_pair_id", PCIDevice
,
82 DEFINE_PROP_END_OF_LIST()
85 static const VMStateDescription vmstate_pcibus
= {
88 .minimum_version_id
= 1,
89 .fields
= (VMStateField
[]) {
90 VMSTATE_INT32_EQUAL(nirq
, PCIBus
, NULL
),
91 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
,
92 nirq
, 0, vmstate_info_int32
,
98 static void pci_init_bus_master(PCIDevice
*pci_dev
)
100 AddressSpace
*dma_as
= pci_device_iommu_address_space(pci_dev
);
102 memory_region_init_alias(&pci_dev
->bus_master_enable_region
,
103 OBJECT(pci_dev
), "bus master",
104 dma_as
->root
, 0, memory_region_size(dma_as
->root
));
105 memory_region_set_enabled(&pci_dev
->bus_master_enable_region
, false);
106 memory_region_add_subregion(&pci_dev
->bus_master_container_region
, 0,
107 &pci_dev
->bus_master_enable_region
);
110 static void pcibus_machine_done(Notifier
*notifier
, void *data
)
112 PCIBus
*bus
= container_of(notifier
, PCIBus
, machine_done
);
115 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
116 if (bus
->devices
[i
]) {
117 pci_init_bus_master(bus
->devices
[i
]);
122 static void pci_bus_realize(BusState
*qbus
, Error
**errp
)
124 PCIBus
*bus
= PCI_BUS(qbus
);
126 bus
->machine_done
.notify
= pcibus_machine_done
;
127 qemu_add_machine_init_done_notifier(&bus
->machine_done
);
129 vmstate_register(NULL
, VMSTATE_INSTANCE_ID_ANY
, &vmstate_pcibus
, bus
);
132 static void pcie_bus_realize(BusState
*qbus
, Error
**errp
)
134 PCIBus
*bus
= PCI_BUS(qbus
);
136 pci_bus_realize(qbus
, errp
);
139 * A PCI-E bus can support extended config space if it's the root
140 * bus, or if the bus/bridge above it does as well
142 if (pci_bus_is_root(bus
)) {
143 bus
->flags
|= PCI_BUS_EXTENDED_CONFIG_SPACE
;
145 PCIBus
*parent_bus
= pci_get_bus(bus
->parent_dev
);
147 if (pci_bus_allows_extended_config_space(parent_bus
)) {
148 bus
->flags
|= PCI_BUS_EXTENDED_CONFIG_SPACE
;
153 static void pci_bus_unrealize(BusState
*qbus
)
155 PCIBus
*bus
= PCI_BUS(qbus
);
157 qemu_remove_machine_init_done_notifier(&bus
->machine_done
);
159 vmstate_unregister(NULL
, &vmstate_pcibus
, bus
);
162 static int pcibus_num(PCIBus
*bus
)
164 if (pci_bus_is_root(bus
)) {
165 return 0; /* pci host bridge */
167 return bus
->parent_dev
->config
[PCI_SECONDARY_BUS
];
170 static uint16_t pcibus_numa_node(PCIBus
*bus
)
172 return NUMA_NODE_UNASSIGNED
;
175 static void pci_bus_class_init(ObjectClass
*klass
, void *data
)
177 BusClass
*k
= BUS_CLASS(klass
);
178 PCIBusClass
*pbc
= PCI_BUS_CLASS(klass
);
180 k
->print_dev
= pcibus_dev_print
;
181 k
->get_dev_path
= pcibus_get_dev_path
;
182 k
->get_fw_dev_path
= pcibus_get_fw_dev_path
;
183 k
->realize
= pci_bus_realize
;
184 k
->unrealize
= pci_bus_unrealize
;
185 k
->reset
= pcibus_reset
;
187 pbc
->bus_num
= pcibus_num
;
188 pbc
->numa_node
= pcibus_numa_node
;
191 static const TypeInfo pci_bus_info
= {
192 .name
= TYPE_PCI_BUS
,
194 .instance_size
= sizeof(PCIBus
),
195 .class_size
= sizeof(PCIBusClass
),
196 .class_init
= pci_bus_class_init
,
199 static const TypeInfo pcie_interface_info
= {
200 .name
= INTERFACE_PCIE_DEVICE
,
201 .parent
= TYPE_INTERFACE
,
204 static const TypeInfo conventional_pci_interface_info
= {
205 .name
= INTERFACE_CONVENTIONAL_PCI_DEVICE
,
206 .parent
= TYPE_INTERFACE
,
209 static void pcie_bus_class_init(ObjectClass
*klass
, void *data
)
211 BusClass
*k
= BUS_CLASS(klass
);
213 k
->realize
= pcie_bus_realize
;
216 static const TypeInfo pcie_bus_info
= {
217 .name
= TYPE_PCIE_BUS
,
218 .parent
= TYPE_PCI_BUS
,
219 .class_init
= pcie_bus_class_init
,
222 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
);
223 static void pci_update_mappings(PCIDevice
*d
);
224 static void pci_irq_handler(void *opaque
, int irq_num
, int level
);
225 static void pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
, Error
**);
226 static void pci_del_option_rom(PCIDevice
*pdev
);
228 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
229 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
231 static QLIST_HEAD(, PCIHostState
) pci_host_bridges
;
233 int pci_bar(PCIDevice
*d
, int reg
)
237 if (reg
!= PCI_ROM_SLOT
)
238 return PCI_BASE_ADDRESS_0
+ reg
* 4;
240 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
241 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
244 static inline int pci_irq_state(PCIDevice
*d
, int irq_num
)
246 return (d
->irq_state
>> irq_num
) & 0x1;
249 static inline void pci_set_irq_state(PCIDevice
*d
, int irq_num
, int level
)
251 d
->irq_state
&= ~(0x1 << irq_num
);
252 d
->irq_state
|= level
<< irq_num
;
255 static void pci_bus_change_irq_level(PCIBus
*bus
, int irq_num
, int change
)
257 assert(irq_num
>= 0);
258 assert(irq_num
< bus
->nirq
);
259 bus
->irq_count
[irq_num
] += change
;
260 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
263 static void pci_change_irq_level(PCIDevice
*pci_dev
, int irq_num
, int change
)
267 bus
= pci_get_bus(pci_dev
);
268 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
271 pci_dev
= bus
->parent_dev
;
273 pci_bus_change_irq_level(bus
, irq_num
, change
);
276 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
)
278 assert(irq_num
>= 0);
279 assert(irq_num
< bus
->nirq
);
280 return !!bus
->irq_count
[irq_num
];
283 /* Update interrupt status bit in config space on interrupt
285 static void pci_update_irq_status(PCIDevice
*dev
)
287 if (dev
->irq_state
) {
288 dev
->config
[PCI_STATUS
] |= PCI_STATUS_INTERRUPT
;
290 dev
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
294 void pci_device_deassert_intx(PCIDevice
*dev
)
297 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
298 pci_irq_handler(dev
, i
, 0);
302 static void pci_do_device_reset(PCIDevice
*dev
)
306 pci_device_deassert_intx(dev
);
307 assert(dev
->irq_state
== 0);
309 /* Clear all writable bits */
310 pci_word_test_and_clear_mask(dev
->config
+ PCI_COMMAND
,
311 pci_get_word(dev
->wmask
+ PCI_COMMAND
) |
312 pci_get_word(dev
->w1cmask
+ PCI_COMMAND
));
313 pci_word_test_and_clear_mask(dev
->config
+ PCI_STATUS
,
314 pci_get_word(dev
->wmask
+ PCI_STATUS
) |
315 pci_get_word(dev
->w1cmask
+ PCI_STATUS
));
316 /* Some devices make bits of PCI_INTERRUPT_LINE read only */
317 pci_byte_test_and_clear_mask(dev
->config
+ PCI_INTERRUPT_LINE
,
318 pci_get_word(dev
->wmask
+ PCI_INTERRUPT_LINE
) |
319 pci_get_word(dev
->w1cmask
+ PCI_INTERRUPT_LINE
));
320 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
321 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
322 PCIIORegion
*region
= &dev
->io_regions
[r
];
327 if (!(region
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
328 region
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
329 pci_set_quad(dev
->config
+ pci_bar(dev
, r
), region
->type
);
331 pci_set_long(dev
->config
+ pci_bar(dev
, r
), region
->type
);
334 pci_update_mappings(dev
);
341 * This function is called on #RST and FLR.
342 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
344 void pci_device_reset(PCIDevice
*dev
)
346 qdev_reset_all(&dev
->qdev
);
347 pci_do_device_reset(dev
);
351 * Trigger pci bus reset under a given bus.
352 * Called via qbus_reset_all on RST# assert, after the devices
353 * have been reset qdev_reset_all-ed already.
355 static void pcibus_reset(BusState
*qbus
)
357 PCIBus
*bus
= DO_UPCAST(PCIBus
, qbus
, qbus
);
360 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
361 if (bus
->devices
[i
]) {
362 pci_do_device_reset(bus
->devices
[i
]);
366 for (i
= 0; i
< bus
->nirq
; i
++) {
367 assert(bus
->irq_count
[i
] == 0);
371 static void pci_host_bus_register(DeviceState
*host
)
373 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(host
);
375 QLIST_INSERT_HEAD(&pci_host_bridges
, host_bridge
, next
);
378 static void pci_host_bus_unregister(DeviceState
*host
)
380 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(host
);
382 QLIST_REMOVE(host_bridge
, next
);
385 PCIBus
*pci_device_root_bus(const PCIDevice
*d
)
387 PCIBus
*bus
= pci_get_bus(d
);
389 while (!pci_bus_is_root(bus
)) {
393 bus
= pci_get_bus(d
);
399 const char *pci_root_bus_path(PCIDevice
*dev
)
401 PCIBus
*rootbus
= pci_device_root_bus(dev
);
402 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(rootbus
->qbus
.parent
);
403 PCIHostBridgeClass
*hc
= PCI_HOST_BRIDGE_GET_CLASS(host_bridge
);
405 assert(host_bridge
->bus
== rootbus
);
407 if (hc
->root_bus_path
) {
408 return (*hc
->root_bus_path
)(host_bridge
, rootbus
);
411 return rootbus
->qbus
.name
;
414 static void pci_root_bus_init(PCIBus
*bus
, DeviceState
*parent
,
415 MemoryRegion
*address_space_mem
,
416 MemoryRegion
*address_space_io
,
419 assert(PCI_FUNC(devfn_min
) == 0);
420 bus
->devfn_min
= devfn_min
;
421 bus
->slot_reserved_mask
= 0x0;
422 bus
->address_space_mem
= address_space_mem
;
423 bus
->address_space_io
= address_space_io
;
424 bus
->flags
|= PCI_BUS_IS_ROOT
;
427 QLIST_INIT(&bus
->child
);
429 pci_host_bus_register(parent
);
432 static void pci_bus_uninit(PCIBus
*bus
)
434 pci_host_bus_unregister(BUS(bus
)->parent
);
437 bool pci_bus_is_express(PCIBus
*bus
)
439 return object_dynamic_cast(OBJECT(bus
), TYPE_PCIE_BUS
);
442 void pci_root_bus_new_inplace(PCIBus
*bus
, size_t bus_size
, DeviceState
*parent
,
444 MemoryRegion
*address_space_mem
,
445 MemoryRegion
*address_space_io
,
446 uint8_t devfn_min
, const char *typename
)
448 qbus_create_inplace(bus
, bus_size
, typename
, parent
, name
);
449 pci_root_bus_init(bus
, parent
, address_space_mem
, address_space_io
,
453 PCIBus
*pci_root_bus_new(DeviceState
*parent
, const char *name
,
454 MemoryRegion
*address_space_mem
,
455 MemoryRegion
*address_space_io
,
456 uint8_t devfn_min
, const char *typename
)
460 bus
= PCI_BUS(qbus_create(typename
, parent
, name
));
461 pci_root_bus_init(bus
, parent
, address_space_mem
, address_space_io
,
466 void pci_root_bus_cleanup(PCIBus
*bus
)
469 /* the caller of the unplug hotplug handler will delete this device */
470 qbus_unrealize(BUS(bus
));
473 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
474 void *irq_opaque
, int nirq
)
476 bus
->set_irq
= set_irq
;
477 bus
->map_irq
= map_irq
;
478 bus
->irq_opaque
= irq_opaque
;
480 bus
->irq_count
= g_malloc0(nirq
* sizeof(bus
->irq_count
[0]));
483 void pci_bus_irqs_cleanup(PCIBus
*bus
)
487 bus
->irq_opaque
= NULL
;
489 g_free(bus
->irq_count
);
492 PCIBus
*pci_register_root_bus(DeviceState
*parent
, const char *name
,
493 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
495 MemoryRegion
*address_space_mem
,
496 MemoryRegion
*address_space_io
,
497 uint8_t devfn_min
, int nirq
,
498 const char *typename
)
502 bus
= pci_root_bus_new(parent
, name
, address_space_mem
,
503 address_space_io
, devfn_min
, typename
);
504 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
508 void pci_unregister_root_bus(PCIBus
*bus
)
510 pci_bus_irqs_cleanup(bus
);
511 pci_root_bus_cleanup(bus
);
514 int pci_bus_num(PCIBus
*s
)
516 return PCI_BUS_GET_CLASS(s
)->bus_num(s
);
519 int pci_bus_numa_node(PCIBus
*bus
)
521 return PCI_BUS_GET_CLASS(bus
)->numa_node(bus
);
524 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
,
525 const VMStateField
*field
)
527 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
528 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(s
);
532 assert(size
== pci_config_size(s
));
533 config
= g_malloc(size
);
535 qemu_get_buffer(f
, config
, size
);
536 for (i
= 0; i
< size
; ++i
) {
537 if ((config
[i
] ^ s
->config
[i
]) &
538 s
->cmask
[i
] & ~s
->wmask
[i
] & ~s
->w1cmask
[i
]) {
539 error_report("%s: Bad config data: i=0x%x read: %x device: %x "
540 "cmask: %x wmask: %x w1cmask:%x", __func__
,
541 i
, config
[i
], s
->config
[i
],
542 s
->cmask
[i
], s
->wmask
[i
], s
->w1cmask
[i
]);
547 memcpy(s
->config
, config
, size
);
549 pci_update_mappings(s
);
551 PCIBridge
*b
= PCI_BRIDGE(s
);
552 pci_bridge_update_mappings(b
);
555 memory_region_set_enabled(&s
->bus_master_enable_region
,
556 pci_get_word(s
->config
+ PCI_COMMAND
)
557 & PCI_COMMAND_MASTER
);
563 /* just put buffer */
564 static int put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
,
565 const VMStateField
*field
, JSONWriter
*vmdesc
)
567 const uint8_t **v
= pv
;
568 assert(size
== pci_config_size(container_of(pv
, PCIDevice
, config
)));
569 qemu_put_buffer(f
, *v
, size
);
574 static VMStateInfo vmstate_info_pci_config
= {
575 .name
= "pci config",
576 .get
= get_pci_config_device
,
577 .put
= put_pci_config_device
,
580 static int get_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
,
581 const VMStateField
*field
)
583 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
584 uint32_t irq_state
[PCI_NUM_PINS
];
586 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
587 irq_state
[i
] = qemu_get_be32(f
);
588 if (irq_state
[i
] != 0x1 && irq_state
[i
] != 0) {
589 fprintf(stderr
, "irq state %d: must be 0 or 1.\n",
595 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
596 pci_set_irq_state(s
, i
, irq_state
[i
]);
602 static int put_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
,
603 const VMStateField
*field
, JSONWriter
*vmdesc
)
606 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
608 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
609 qemu_put_be32(f
, pci_irq_state(s
, i
));
615 static VMStateInfo vmstate_info_pci_irq_state
= {
616 .name
= "pci irq state",
617 .get
= get_pci_irq_state
,
618 .put
= put_pci_irq_state
,
621 static bool migrate_is_pcie(void *opaque
, int version_id
)
623 return pci_is_express((PCIDevice
*)opaque
);
626 static bool migrate_is_not_pcie(void *opaque
, int version_id
)
628 return !pci_is_express((PCIDevice
*)opaque
);
631 const VMStateDescription vmstate_pci_device
= {
634 .minimum_version_id
= 1,
635 .fields
= (VMStateField
[]) {
636 VMSTATE_INT32_POSITIVE_LE(version_id
, PCIDevice
),
637 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config
, PCIDevice
,
639 0, vmstate_info_pci_config
,
640 PCI_CONFIG_SPACE_SIZE
),
641 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config
, PCIDevice
,
643 0, vmstate_info_pci_config
,
644 PCIE_CONFIG_SPACE_SIZE
),
645 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
646 vmstate_info_pci_irq_state
,
647 PCI_NUM_PINS
* sizeof(int32_t)),
648 VMSTATE_END_OF_LIST()
653 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
655 /* Clear interrupt status bit: it is implicit
656 * in irq_state which we are saving.
657 * This makes us compatible with old devices
658 * which never set or clear this bit. */
659 s
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
660 vmstate_save_state(f
, &vmstate_pci_device
, s
, NULL
);
661 /* Restore the interrupt status bit. */
662 pci_update_irq_status(s
);
665 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
668 ret
= vmstate_load_state(f
, &vmstate_pci_device
, s
, s
->version_id
);
669 /* Restore the interrupt status bit. */
670 pci_update_irq_status(s
);
674 static void pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
676 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
677 pci_default_sub_vendor_id
);
678 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
679 pci_default_sub_device_id
);
683 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
684 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
686 static int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
,
687 unsigned int *slotp
, unsigned int *funcp
)
692 unsigned long dom
= 0, bus
= 0;
693 unsigned int slot
= 0;
694 unsigned int func
= 0;
697 val
= strtoul(p
, &e
, 16);
703 val
= strtoul(p
, &e
, 16);
710 val
= strtoul(p
, &e
, 16);
723 val
= strtoul(p
, &e
, 16);
730 /* if funcp == NULL func is 0 */
731 if (dom
> 0xffff || bus
> 0xff || slot
> 0x1f || func
> 7)
745 static void pci_init_cmask(PCIDevice
*dev
)
747 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
748 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
749 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
750 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
751 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
752 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
753 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
754 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
757 static void pci_init_wmask(PCIDevice
*dev
)
759 int config_size
= pci_config_size(dev
);
761 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
762 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
763 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
764 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
765 PCI_COMMAND_INTX_DISABLE
);
766 pci_word_test_and_set_mask(dev
->wmask
+ PCI_COMMAND
, PCI_COMMAND_SERR
);
768 memset(dev
->wmask
+ PCI_CONFIG_HEADER_SIZE
, 0xff,
769 config_size
- PCI_CONFIG_HEADER_SIZE
);
772 static void pci_init_w1cmask(PCIDevice
*dev
)
775 * Note: It's okay to set w1cmask even for readonly bits as
776 * long as their value is hardwired to 0.
778 pci_set_word(dev
->w1cmask
+ PCI_STATUS
,
779 PCI_STATUS_PARITY
| PCI_STATUS_SIG_TARGET_ABORT
|
780 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_REC_MASTER_ABORT
|
781 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_DETECTED_PARITY
);
784 static void pci_init_mask_bridge(PCIDevice
*d
)
786 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
787 PCI_SEC_LETENCY_TIMER */
788 memset(d
->wmask
+ PCI_PRIMARY_BUS
, 0xff, 4);
791 d
->wmask
[PCI_IO_BASE
] = PCI_IO_RANGE_MASK
& 0xff;
792 d
->wmask
[PCI_IO_LIMIT
] = PCI_IO_RANGE_MASK
& 0xff;
793 pci_set_word(d
->wmask
+ PCI_MEMORY_BASE
,
794 PCI_MEMORY_RANGE_MASK
& 0xffff);
795 pci_set_word(d
->wmask
+ PCI_MEMORY_LIMIT
,
796 PCI_MEMORY_RANGE_MASK
& 0xffff);
797 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_BASE
,
798 PCI_PREF_RANGE_MASK
& 0xffff);
799 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_LIMIT
,
800 PCI_PREF_RANGE_MASK
& 0xffff);
802 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
803 memset(d
->wmask
+ PCI_PREF_BASE_UPPER32
, 0xff, 8);
805 /* Supported memory and i/o types */
806 d
->config
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_16
;
807 d
->config
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_16
;
808 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_BASE
,
809 PCI_PREF_RANGE_TYPE_64
);
810 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_LIMIT
,
811 PCI_PREF_RANGE_TYPE_64
);
814 * TODO: Bridges default to 10-bit VGA decoding but we currently only
815 * implement 16-bit decoding (no alias support).
817 pci_set_word(d
->wmask
+ PCI_BRIDGE_CONTROL
,
818 PCI_BRIDGE_CTL_PARITY
|
819 PCI_BRIDGE_CTL_SERR
|
822 PCI_BRIDGE_CTL_VGA_16BIT
|
823 PCI_BRIDGE_CTL_MASTER_ABORT
|
824 PCI_BRIDGE_CTL_BUS_RESET
|
825 PCI_BRIDGE_CTL_FAST_BACK
|
826 PCI_BRIDGE_CTL_DISCARD
|
827 PCI_BRIDGE_CTL_SEC_DISCARD
|
828 PCI_BRIDGE_CTL_DISCARD_SERR
);
829 /* Below does not do anything as we never set this bit, put here for
831 pci_set_word(d
->w1cmask
+ PCI_BRIDGE_CONTROL
,
832 PCI_BRIDGE_CTL_DISCARD_STATUS
);
833 d
->cmask
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_MASK
;
834 d
->cmask
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_MASK
;
835 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_BASE
,
836 PCI_PREF_RANGE_TYPE_MASK
);
837 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_LIMIT
,
838 PCI_PREF_RANGE_TYPE_MASK
);
841 static void pci_init_multifunction(PCIBus
*bus
, PCIDevice
*dev
, Error
**errp
)
843 uint8_t slot
= PCI_SLOT(dev
->devfn
);
846 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
847 dev
->config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
851 * multifunction bit is interpreted in two ways as follows.
852 * - all functions must set the bit to 1.
854 * - function 0 must set the bit, but the rest function (> 0)
855 * is allowed to leave the bit to 0.
856 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
858 * So OS (at least Linux) checks the bit of only function 0,
859 * and doesn't see the bit of function > 0.
861 * The below check allows both interpretation.
863 if (PCI_FUNC(dev
->devfn
)) {
864 PCIDevice
*f0
= bus
->devices
[PCI_DEVFN(slot
, 0)];
865 if (f0
&& !(f0
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)) {
866 /* function 0 should set multifunction bit */
867 error_setg(errp
, "PCI: single function device can't be populated "
868 "in function %x.%x", slot
, PCI_FUNC(dev
->devfn
));
874 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
877 /* function 0 indicates single function, so function > 0 must be NULL */
878 for (func
= 1; func
< PCI_FUNC_MAX
; ++func
) {
879 if (bus
->devices
[PCI_DEVFN(slot
, func
)]) {
880 error_setg(errp
, "PCI: %x.0 indicates single function, "
881 "but %x.%x is already populated.",
888 static void pci_config_alloc(PCIDevice
*pci_dev
)
890 int config_size
= pci_config_size(pci_dev
);
892 pci_dev
->config
= g_malloc0(config_size
);
893 pci_dev
->cmask
= g_malloc0(config_size
);
894 pci_dev
->wmask
= g_malloc0(config_size
);
895 pci_dev
->w1cmask
= g_malloc0(config_size
);
896 pci_dev
->used
= g_malloc0(config_size
);
899 static void pci_config_free(PCIDevice
*pci_dev
)
901 g_free(pci_dev
->config
);
902 g_free(pci_dev
->cmask
);
903 g_free(pci_dev
->wmask
);
904 g_free(pci_dev
->w1cmask
);
905 g_free(pci_dev
->used
);
908 static void do_pci_unregister_device(PCIDevice
*pci_dev
)
910 pci_get_bus(pci_dev
)->devices
[pci_dev
->devfn
] = NULL
;
911 pci_config_free(pci_dev
);
913 if (memory_region_is_mapped(&pci_dev
->bus_master_enable_region
)) {
914 memory_region_del_subregion(&pci_dev
->bus_master_container_region
,
915 &pci_dev
->bus_master_enable_region
);
917 address_space_destroy(&pci_dev
->bus_master_as
);
920 /* Extract PCIReqIDCache into BDF format */
921 static uint16_t pci_req_id_cache_extract(PCIReqIDCache
*cache
)
926 switch (cache
->type
) {
928 result
= pci_get_bdf(cache
->dev
);
930 case PCI_REQ_ID_SECONDARY_BUS
:
931 bus_n
= pci_dev_bus_num(cache
->dev
);
932 result
= PCI_BUILD_BDF(bus_n
, 0);
935 error_report("Invalid PCI requester ID cache type: %d",
944 /* Parse bridges up to the root complex and return requester ID
945 * cache for specific device. For full PCIe topology, the cache
946 * result would be exactly the same as getting BDF of the device.
947 * However, several tricks are required when system mixed up with
948 * legacy PCI devices and PCIe-to-PCI bridges.
950 * Here we cache the proxy device (and type) not requester ID since
951 * bus number might change from time to time.
953 static PCIReqIDCache
pci_req_id_cache_get(PCIDevice
*dev
)
956 PCIReqIDCache cache
= {
958 .type
= PCI_REQ_ID_BDF
,
961 while (!pci_bus_is_root(pci_get_bus(dev
))) {
962 /* We are under PCI/PCIe bridges */
963 parent
= pci_get_bus(dev
)->parent_dev
;
964 if (pci_is_express(parent
)) {
965 if (pcie_cap_get_type(parent
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
966 /* When we pass through PCIe-to-PCI/PCIX bridges, we
967 * override the requester ID using secondary bus
968 * number of parent bridge with zeroed devfn
969 * (pcie-to-pci bridge spec chap 2.3). */
970 cache
.type
= PCI_REQ_ID_SECONDARY_BUS
;
974 /* Legacy PCI, override requester ID with the bridge's
975 * BDF upstream. When the root complex connects to
976 * legacy PCI devices (including buses), it can only
977 * obtain requester ID info from directly attached
978 * devices. If devices are attached under bridges, only
979 * the requester ID of the bridge that is directly
980 * attached to the root complex can be recognized. */
981 cache
.type
= PCI_REQ_ID_BDF
;
990 uint16_t pci_requester_id(PCIDevice
*dev
)
992 return pci_req_id_cache_extract(&dev
->requester_id_cache
);
995 static bool pci_bus_devfn_available(PCIBus
*bus
, int devfn
)
997 return !(bus
->devices
[devfn
]);
1000 static bool pci_bus_devfn_reserved(PCIBus
*bus
, int devfn
)
1002 return bus
->slot_reserved_mask
& (1UL << PCI_SLOT(devfn
));
1005 /* -1 for devfn means auto assign */
1006 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
,
1007 const char *name
, int devfn
,
1010 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
1011 PCIConfigReadFunc
*config_read
= pc
->config_read
;
1012 PCIConfigWriteFunc
*config_write
= pc
->config_write
;
1013 Error
*local_err
= NULL
;
1014 DeviceState
*dev
= DEVICE(pci_dev
);
1015 PCIBus
*bus
= pci_get_bus(pci_dev
);
1017 /* Only pci bridges can be attached to extra PCI root buses */
1018 if (pci_bus_is_root(bus
) && bus
->parent_dev
&& !pc
->is_bridge
) {
1020 "PCI: Only PCI/PCIe bridges can be plugged into %s",
1021 bus
->parent_dev
->name
);
1026 for(devfn
= bus
->devfn_min
; devfn
< ARRAY_SIZE(bus
->devices
);
1027 devfn
+= PCI_FUNC_MAX
) {
1028 if (pci_bus_devfn_available(bus
, devfn
) &&
1029 !pci_bus_devfn_reserved(bus
, devfn
)) {
1033 error_setg(errp
, "PCI: no slot/function available for %s, all in use "
1034 "or reserved", name
);
1037 } else if (pci_bus_devfn_reserved(bus
, devfn
)) {
1038 error_setg(errp
, "PCI: slot %d function %d not available for %s,"
1040 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
);
1042 } else if (!pci_bus_devfn_available(bus
, devfn
)) {
1043 error_setg(errp
, "PCI: slot %d function %d not available for %s,"
1045 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
,
1046 bus
->devices
[devfn
]->name
);
1048 } else if (dev
->hotplugged
&&
1049 pci_get_function_0(pci_dev
)) {
1050 error_setg(errp
, "PCI: slot %d function 0 already occupied by %s,"
1051 " new func %s cannot be exposed to guest.",
1052 PCI_SLOT(pci_get_function_0(pci_dev
)->devfn
),
1053 pci_get_function_0(pci_dev
)->name
,
1059 pci_dev
->devfn
= devfn
;
1060 pci_dev
->requester_id_cache
= pci_req_id_cache_get(pci_dev
);
1061 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
1063 memory_region_init(&pci_dev
->bus_master_container_region
, OBJECT(pci_dev
),
1064 "bus master container", UINT64_MAX
);
1065 address_space_init(&pci_dev
->bus_master_as
,
1066 &pci_dev
->bus_master_container_region
, pci_dev
->name
);
1068 if (phase_check(PHASE_MACHINE_READY
)) {
1069 pci_init_bus_master(pci_dev
);
1071 pci_dev
->irq_state
= 0;
1072 pci_config_alloc(pci_dev
);
1074 pci_config_set_vendor_id(pci_dev
->config
, pc
->vendor_id
);
1075 pci_config_set_device_id(pci_dev
->config
, pc
->device_id
);
1076 pci_config_set_revision(pci_dev
->config
, pc
->revision
);
1077 pci_config_set_class(pci_dev
->config
, pc
->class_id
);
1079 if (!pc
->is_bridge
) {
1080 if (pc
->subsystem_vendor_id
|| pc
->subsystem_id
) {
1081 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
1082 pc
->subsystem_vendor_id
);
1083 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
1086 pci_set_default_subsystem_id(pci_dev
);
1089 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
1090 assert(!pc
->subsystem_vendor_id
);
1091 assert(!pc
->subsystem_id
);
1093 pci_init_cmask(pci_dev
);
1094 pci_init_wmask(pci_dev
);
1095 pci_init_w1cmask(pci_dev
);
1096 if (pc
->is_bridge
) {
1097 pci_init_mask_bridge(pci_dev
);
1099 pci_init_multifunction(bus
, pci_dev
, &local_err
);
1101 error_propagate(errp
, local_err
);
1102 do_pci_unregister_device(pci_dev
);
1107 config_read
= pci_default_read_config
;
1109 config_write
= pci_default_write_config
;
1110 pci_dev
->config_read
= config_read
;
1111 pci_dev
->config_write
= config_write
;
1112 bus
->devices
[devfn
] = pci_dev
;
1113 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
1117 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
1122 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1123 r
= &pci_dev
->io_regions
[i
];
1124 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
1126 memory_region_del_subregion(r
->address_space
, r
->memory
);
1129 pci_unregister_vga(pci_dev
);
1132 static void pci_qdev_unrealize(DeviceState
*dev
)
1134 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
1135 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
1137 pci_unregister_io_regions(pci_dev
);
1138 pci_del_option_rom(pci_dev
);
1144 pci_device_deassert_intx(pci_dev
);
1145 do_pci_unregister_device(pci_dev
);
1148 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
1149 uint8_t type
, MemoryRegion
*memory
)
1152 uint32_t addr
; /* offset in pci config space */
1154 pcibus_t size
= memory_region_size(memory
);
1157 assert(region_num
>= 0);
1158 assert(region_num
< PCI_NUM_REGIONS
);
1159 assert(is_power_of_2(size
));
1161 /* A PCI bridge device (with Type 1 header) may only have at most 2 BARs */
1163 pci_dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1164 assert(hdr_type
!= PCI_HEADER_TYPE_BRIDGE
|| region_num
< 2);
1166 r
= &pci_dev
->io_regions
[region_num
];
1167 r
->addr
= PCI_BAR_UNMAPPED
;
1171 r
->address_space
= type
& PCI_BASE_ADDRESS_SPACE_IO
1172 ? pci_get_bus(pci_dev
)->address_space_io
1173 : pci_get_bus(pci_dev
)->address_space_mem
;
1175 wmask
= ~(size
- 1);
1176 if (region_num
== PCI_ROM_SLOT
) {
1177 /* ROM enable bit is writable */
1178 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
1181 addr
= pci_bar(pci_dev
, region_num
);
1182 pci_set_long(pci_dev
->config
+ addr
, type
);
1184 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
1185 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
1186 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
1187 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
1189 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
1190 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
1194 static void pci_update_vga(PCIDevice
*pci_dev
)
1198 if (!pci_dev
->has_vga
) {
1202 cmd
= pci_get_word(pci_dev
->config
+ PCI_COMMAND
);
1204 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
],
1205 cmd
& PCI_COMMAND_MEMORY
);
1206 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
],
1207 cmd
& PCI_COMMAND_IO
);
1208 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
],
1209 cmd
& PCI_COMMAND_IO
);
1212 void pci_register_vga(PCIDevice
*pci_dev
, MemoryRegion
*mem
,
1213 MemoryRegion
*io_lo
, MemoryRegion
*io_hi
)
1215 PCIBus
*bus
= pci_get_bus(pci_dev
);
1217 assert(!pci_dev
->has_vga
);
1219 assert(memory_region_size(mem
) == QEMU_PCI_VGA_MEM_SIZE
);
1220 pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
] = mem
;
1221 memory_region_add_subregion_overlap(bus
->address_space_mem
,
1222 QEMU_PCI_VGA_MEM_BASE
, mem
, 1);
1224 assert(memory_region_size(io_lo
) == QEMU_PCI_VGA_IO_LO_SIZE
);
1225 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
] = io_lo
;
1226 memory_region_add_subregion_overlap(bus
->address_space_io
,
1227 QEMU_PCI_VGA_IO_LO_BASE
, io_lo
, 1);
1229 assert(memory_region_size(io_hi
) == QEMU_PCI_VGA_IO_HI_SIZE
);
1230 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
] = io_hi
;
1231 memory_region_add_subregion_overlap(bus
->address_space_io
,
1232 QEMU_PCI_VGA_IO_HI_BASE
, io_hi
, 1);
1233 pci_dev
->has_vga
= true;
1235 pci_update_vga(pci_dev
);
1238 void pci_unregister_vga(PCIDevice
*pci_dev
)
1240 PCIBus
*bus
= pci_get_bus(pci_dev
);
1242 if (!pci_dev
->has_vga
) {
1246 memory_region_del_subregion(bus
->address_space_mem
,
1247 pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
]);
1248 memory_region_del_subregion(bus
->address_space_io
,
1249 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
]);
1250 memory_region_del_subregion(bus
->address_space_io
,
1251 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
]);
1252 pci_dev
->has_vga
= false;
1255 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
)
1257 return pci_dev
->io_regions
[region_num
].addr
;
1260 static pcibus_t
pci_bar_address(PCIDevice
*d
,
1261 int reg
, uint8_t type
, pcibus_t size
)
1263 pcibus_t new_addr
, last_addr
;
1264 int bar
= pci_bar(d
, reg
);
1265 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
1266 Object
*machine
= qdev_get_machine();
1267 ObjectClass
*oc
= object_get_class(machine
);
1268 MachineClass
*mc
= MACHINE_CLASS(oc
);
1269 bool allow_0_address
= mc
->pci_allow_0_address
;
1271 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1272 if (!(cmd
& PCI_COMMAND_IO
)) {
1273 return PCI_BAR_UNMAPPED
;
1275 new_addr
= pci_get_long(d
->config
+ bar
) & ~(size
- 1);
1276 last_addr
= new_addr
+ size
- 1;
1277 /* Check if 32 bit BAR wraps around explicitly.
1278 * TODO: make priorities correct and remove this work around.
1280 if (last_addr
<= new_addr
|| last_addr
>= UINT32_MAX
||
1281 (!allow_0_address
&& new_addr
== 0)) {
1282 return PCI_BAR_UNMAPPED
;
1287 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
1288 return PCI_BAR_UNMAPPED
;
1290 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
1291 new_addr
= pci_get_quad(d
->config
+ bar
);
1293 new_addr
= pci_get_long(d
->config
+ bar
);
1295 /* the ROM slot has a specific enable bit */
1296 if (reg
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
)) {
1297 return PCI_BAR_UNMAPPED
;
1299 new_addr
&= ~(size
- 1);
1300 last_addr
= new_addr
+ size
- 1;
1301 /* NOTE: we do not support wrapping */
1302 /* XXX: as we cannot support really dynamic
1303 mappings, we handle specific values as invalid
1305 if (last_addr
<= new_addr
|| last_addr
== PCI_BAR_UNMAPPED
||
1306 (!allow_0_address
&& new_addr
== 0)) {
1307 return PCI_BAR_UNMAPPED
;
1310 /* Now pcibus_t is 64bit.
1311 * Check if 32 bit BAR wraps around explicitly.
1312 * Without this, PC ide doesn't work well.
1313 * TODO: remove this work around.
1315 if (!(type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) && last_addr
>= UINT32_MAX
) {
1316 return PCI_BAR_UNMAPPED
;
1320 * OS is allowed to set BAR beyond its addressable
1321 * bits. For example, 32 bit OS can set 64bit bar
1322 * to >4G. Check it. TODO: we might need to support
1323 * it in the future for e.g. PAE.
1325 if (last_addr
>= HWADDR_MAX
) {
1326 return PCI_BAR_UNMAPPED
;
1332 static void pci_update_mappings(PCIDevice
*d
)
1338 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1339 r
= &d
->io_regions
[i
];
1341 /* this region isn't registered */
1345 new_addr
= pci_bar_address(d
, i
, r
->type
, r
->size
);
1347 /* This bar isn't changed */
1348 if (new_addr
== r
->addr
)
1351 /* now do the real mapping */
1352 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1353 trace_pci_update_mappings_del(d
, pci_dev_bus_num(d
),
1356 i
, r
->addr
, r
->size
);
1357 memory_region_del_subregion(r
->address_space
, r
->memory
);
1360 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1361 trace_pci_update_mappings_add(d
, pci_dev_bus_num(d
),
1364 i
, r
->addr
, r
->size
);
1365 memory_region_add_subregion_overlap(r
->address_space
,
1366 r
->addr
, r
->memory
, 1);
1373 static inline int pci_irq_disabled(PCIDevice
*d
)
1375 return pci_get_word(d
->config
+ PCI_COMMAND
) & PCI_COMMAND_INTX_DISABLE
;
1378 /* Called after interrupt disabled field update in config space,
1379 * assert/deassert interrupts if necessary.
1380 * Gets original interrupt disable bit value (before update). */
1381 static void pci_update_irq_disabled(PCIDevice
*d
, int was_irq_disabled
)
1383 int i
, disabled
= pci_irq_disabled(d
);
1384 if (disabled
== was_irq_disabled
)
1386 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
1387 int state
= pci_irq_state(d
, i
);
1388 pci_change_irq_level(d
, i
, disabled
? -state
: state
);
1392 uint32_t pci_default_read_config(PCIDevice
*d
,
1393 uint32_t address
, int len
)
1397 assert(address
+ len
<= pci_config_size(d
));
1399 if (pci_is_express_downstream_port(d
) &&
1400 ranges_overlap(address
, len
, d
->exp
.exp_cap
+ PCI_EXP_LNKSTA
, 2)) {
1401 pcie_sync_bridge_lnk(d
);
1403 memcpy(&val
, d
->config
+ address
, len
);
1404 return le32_to_cpu(val
);
1407 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val_in
, int l
)
1409 int i
, was_irq_disabled
= pci_irq_disabled(d
);
1410 uint32_t val
= val_in
;
1412 assert(addr
+ l
<= pci_config_size(d
));
1414 for (i
= 0; i
< l
; val
>>= 8, ++i
) {
1415 uint8_t wmask
= d
->wmask
[addr
+ i
];
1416 uint8_t w1cmask
= d
->w1cmask
[addr
+ i
];
1417 assert(!(wmask
& w1cmask
));
1418 d
->config
[addr
+ i
] = (d
->config
[addr
+ i
] & ~wmask
) | (val
& wmask
);
1419 d
->config
[addr
+ i
] &= ~(val
& w1cmask
); /* W1C: Write 1 to Clear */
1421 if (ranges_overlap(addr
, l
, PCI_BASE_ADDRESS_0
, 24) ||
1422 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS
, 4) ||
1423 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS1
, 4) ||
1424 range_covers_byte(addr
, l
, PCI_COMMAND
))
1425 pci_update_mappings(d
);
1427 if (range_covers_byte(addr
, l
, PCI_COMMAND
)) {
1428 pci_update_irq_disabled(d
, was_irq_disabled
);
1429 memory_region_set_enabled(&d
->bus_master_enable_region
,
1430 pci_get_word(d
->config
+ PCI_COMMAND
)
1431 & PCI_COMMAND_MASTER
);
1434 msi_write_config(d
, addr
, val_in
, l
);
1435 msix_write_config(d
, addr
, val_in
, l
);
1438 /***********************************************************/
1439 /* generic PCI irq support */
1441 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1442 static void pci_irq_handler(void *opaque
, int irq_num
, int level
)
1444 PCIDevice
*pci_dev
= opaque
;
1447 change
= level
- pci_irq_state(pci_dev
, irq_num
);
1451 pci_set_irq_state(pci_dev
, irq_num
, level
);
1452 pci_update_irq_status(pci_dev
);
1453 if (pci_irq_disabled(pci_dev
))
1455 pci_change_irq_level(pci_dev
, irq_num
, change
);
1458 static inline int pci_intx(PCIDevice
*pci_dev
)
1460 return pci_get_byte(pci_dev
->config
+ PCI_INTERRUPT_PIN
) - 1;
1463 qemu_irq
pci_allocate_irq(PCIDevice
*pci_dev
)
1465 int intx
= pci_intx(pci_dev
);
1467 return qemu_allocate_irq(pci_irq_handler
, pci_dev
, intx
);
1470 void pci_set_irq(PCIDevice
*pci_dev
, int level
)
1472 int intx
= pci_intx(pci_dev
);
1473 pci_irq_handler(pci_dev
, intx
, level
);
1476 /* Special hooks used by device assignment */
1477 void pci_bus_set_route_irq_fn(PCIBus
*bus
, pci_route_irq_fn route_intx_to_irq
)
1479 assert(pci_bus_is_root(bus
));
1480 bus
->route_intx_to_irq
= route_intx_to_irq
;
1483 PCIINTxRoute
pci_device_route_intx_to_irq(PCIDevice
*dev
, int pin
)
1488 bus
= pci_get_bus(dev
);
1489 pin
= bus
->map_irq(dev
, pin
);
1490 dev
= bus
->parent_dev
;
1493 if (!bus
->route_intx_to_irq
) {
1494 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1495 object_get_typename(OBJECT(bus
->qbus
.parent
)));
1496 return (PCIINTxRoute
) { PCI_INTX_DISABLED
, -1 };
1499 return bus
->route_intx_to_irq(bus
->irq_opaque
, pin
);
1502 bool pci_intx_route_changed(PCIINTxRoute
*old
, PCIINTxRoute
*new)
1504 return old
->mode
!= new->mode
|| old
->irq
!= new->irq
;
1507 void pci_bus_fire_intx_routing_notifier(PCIBus
*bus
)
1513 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
1514 dev
= bus
->devices
[i
];
1515 if (dev
&& dev
->intx_routing_notifier
) {
1516 dev
->intx_routing_notifier(dev
);
1520 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1521 pci_bus_fire_intx_routing_notifier(sec
);
1525 void pci_device_set_intx_routing_notifier(PCIDevice
*dev
,
1526 PCIINTxRoutingNotifier notifier
)
1528 dev
->intx_routing_notifier
= notifier
;
1532 * PCI-to-PCI bridge specification
1533 * 9.1: Interrupt routing. Table 9-1
1535 * the PCI Express Base Specification, Revision 2.1
1536 * 2.2.8.1: INTx interrutp signaling - Rules
1537 * the Implementation Note
1541 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1542 * 0-origin unlike PCI interrupt pin register.
1544 int pci_swizzle_map_irq_fn(PCIDevice
*pci_dev
, int pin
)
1546 return pci_swizzle(PCI_SLOT(pci_dev
->devfn
), pin
);
1549 /***********************************************************/
1550 /* monitor info on PCI */
1555 const char *fw_name
;
1556 uint16_t fw_ign_bits
;
1559 static const pci_class_desc pci_class_descriptions
[] =
1561 { 0x0001, "VGA controller", "display"},
1562 { 0x0100, "SCSI controller", "scsi"},
1563 { 0x0101, "IDE controller", "ide"},
1564 { 0x0102, "Floppy controller", "fdc"},
1565 { 0x0103, "IPI controller", "ipi"},
1566 { 0x0104, "RAID controller", "raid"},
1567 { 0x0106, "SATA controller"},
1568 { 0x0107, "SAS controller"},
1569 { 0x0180, "Storage controller"},
1570 { 0x0200, "Ethernet controller", "ethernet"},
1571 { 0x0201, "Token Ring controller", "token-ring"},
1572 { 0x0202, "FDDI controller", "fddi"},
1573 { 0x0203, "ATM controller", "atm"},
1574 { 0x0280, "Network controller"},
1575 { 0x0300, "VGA controller", "display", 0x00ff},
1576 { 0x0301, "XGA controller"},
1577 { 0x0302, "3D controller"},
1578 { 0x0380, "Display controller"},
1579 { 0x0400, "Video controller", "video"},
1580 { 0x0401, "Audio controller", "sound"},
1582 { 0x0403, "Audio controller", "sound"},
1583 { 0x0480, "Multimedia controller"},
1584 { 0x0500, "RAM controller", "memory"},
1585 { 0x0501, "Flash controller", "flash"},
1586 { 0x0580, "Memory controller"},
1587 { 0x0600, "Host bridge", "host"},
1588 { 0x0601, "ISA bridge", "isa"},
1589 { 0x0602, "EISA bridge", "eisa"},
1590 { 0x0603, "MC bridge", "mca"},
1591 { 0x0604, "PCI bridge", "pci-bridge"},
1592 { 0x0605, "PCMCIA bridge", "pcmcia"},
1593 { 0x0606, "NUBUS bridge", "nubus"},
1594 { 0x0607, "CARDBUS bridge", "cardbus"},
1595 { 0x0608, "RACEWAY bridge"},
1596 { 0x0680, "Bridge"},
1597 { 0x0700, "Serial port", "serial"},
1598 { 0x0701, "Parallel port", "parallel"},
1599 { 0x0800, "Interrupt controller", "interrupt-controller"},
1600 { 0x0801, "DMA controller", "dma-controller"},
1601 { 0x0802, "Timer", "timer"},
1602 { 0x0803, "RTC", "rtc"},
1603 { 0x0900, "Keyboard", "keyboard"},
1604 { 0x0901, "Pen", "pen"},
1605 { 0x0902, "Mouse", "mouse"},
1606 { 0x0A00, "Dock station", "dock", 0x00ff},
1607 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1608 { 0x0c00, "Fireware contorller", "fireware"},
1609 { 0x0c01, "Access bus controller", "access-bus"},
1610 { 0x0c02, "SSA controller", "ssa"},
1611 { 0x0c03, "USB controller", "usb"},
1612 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1617 static void pci_for_each_device_under_bus_reverse(PCIBus
*bus
,
1618 void (*fn
)(PCIBus
*b
,
1626 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1627 d
= bus
->devices
[ARRAY_SIZE(bus
->devices
) - 1 - devfn
];
1634 void pci_for_each_device_reverse(PCIBus
*bus
, int bus_num
,
1635 void (*fn
)(PCIBus
*b
, PCIDevice
*d
, void *opaque
),
1638 bus
= pci_find_bus_nr(bus
, bus_num
);
1641 pci_for_each_device_under_bus_reverse(bus
, fn
, opaque
);
1645 static void pci_for_each_device_under_bus(PCIBus
*bus
,
1646 void (*fn
)(PCIBus
*b
, PCIDevice
*d
,
1653 for(devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1654 d
= bus
->devices
[devfn
];
1661 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
1662 void (*fn
)(PCIBus
*b
, PCIDevice
*d
, void *opaque
),
1665 bus
= pci_find_bus_nr(bus
, bus_num
);
1668 pci_for_each_device_under_bus(bus
, fn
, opaque
);
1672 static const pci_class_desc
*get_class_desc(int class)
1674 const pci_class_desc
*desc
;
1676 desc
= pci_class_descriptions
;
1677 while (desc
->desc
&& class != desc
->class) {
1684 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
);
1686 static PciMemoryRegionList
*qmp_query_pci_regions(const PCIDevice
*dev
)
1688 PciMemoryRegionList
*head
= NULL
, **tail
= &head
;
1691 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1692 const PCIIORegion
*r
= &dev
->io_regions
[i
];
1693 PciMemoryRegion
*region
;
1699 region
= g_malloc0(sizeof(*region
));
1701 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1702 region
->type
= g_strdup("io");
1704 region
->type
= g_strdup("memory");
1705 region
->has_prefetch
= true;
1706 region
->prefetch
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_PREFETCH
);
1707 region
->has_mem_type_64
= true;
1708 region
->mem_type_64
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
);
1712 region
->address
= r
->addr
;
1713 region
->size
= r
->size
;
1715 QAPI_LIST_APPEND(tail
, region
);
1721 static PciBridgeInfo
*qmp_query_pci_bridge(PCIDevice
*dev
, PCIBus
*bus
,
1724 PciBridgeInfo
*info
;
1725 PciMemoryRange
*range
;
1727 info
= g_new0(PciBridgeInfo
, 1);
1729 info
->bus
= g_new0(PciBusInfo
, 1);
1730 info
->bus
->number
= dev
->config
[PCI_PRIMARY_BUS
];
1731 info
->bus
->secondary
= dev
->config
[PCI_SECONDARY_BUS
];
1732 info
->bus
->subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
1734 range
= info
->bus
->io_range
= g_new0(PciMemoryRange
, 1);
1735 range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1736 range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1738 range
= info
->bus
->memory_range
= g_new0(PciMemoryRange
, 1);
1739 range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1740 range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1742 range
= info
->bus
->prefetchable_range
= g_new0(PciMemoryRange
, 1);
1743 range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1744 range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1746 if (dev
->config
[PCI_SECONDARY_BUS
] != 0) {
1747 PCIBus
*child_bus
= pci_find_bus_nr(bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1749 info
->has_devices
= true;
1750 info
->devices
= qmp_query_pci_devices(child_bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1757 static PciDeviceInfo
*qmp_query_pci_device(PCIDevice
*dev
, PCIBus
*bus
,
1760 const pci_class_desc
*desc
;
1761 PciDeviceInfo
*info
;
1765 info
= g_new0(PciDeviceInfo
, 1);
1766 info
->bus
= bus_num
;
1767 info
->slot
= PCI_SLOT(dev
->devfn
);
1768 info
->function
= PCI_FUNC(dev
->devfn
);
1770 info
->class_info
= g_new0(PciDeviceClass
, 1);
1771 class = pci_get_word(dev
->config
+ PCI_CLASS_DEVICE
);
1772 info
->class_info
->q_class
= class;
1773 desc
= get_class_desc(class);
1775 info
->class_info
->has_desc
= true;
1776 info
->class_info
->desc
= g_strdup(desc
->desc
);
1779 info
->id
= g_new0(PciDeviceId
, 1);
1780 info
->id
->vendor
= pci_get_word(dev
->config
+ PCI_VENDOR_ID
);
1781 info
->id
->device
= pci_get_word(dev
->config
+ PCI_DEVICE_ID
);
1782 info
->regions
= qmp_query_pci_regions(dev
);
1783 info
->qdev_id
= g_strdup(dev
->qdev
.id
? dev
->qdev
.id
: "");
1785 info
->irq_pin
= dev
->config
[PCI_INTERRUPT_PIN
];
1786 if (dev
->config
[PCI_INTERRUPT_PIN
] != 0) {
1787 info
->has_irq
= true;
1788 info
->irq
= dev
->config
[PCI_INTERRUPT_LINE
];
1791 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1792 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
1793 info
->has_pci_bridge
= true;
1794 info
->pci_bridge
= qmp_query_pci_bridge(dev
, bus
, bus_num
);
1795 } else if (type
== PCI_HEADER_TYPE_NORMAL
) {
1796 info
->id
->has_subsystem
= info
->id
->has_subsystem_vendor
= true;
1797 info
->id
->subsystem
= pci_get_word(dev
->config
+ PCI_SUBSYSTEM_ID
);
1798 info
->id
->subsystem_vendor
=
1799 pci_get_word(dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
);
1800 } else if (type
== PCI_HEADER_TYPE_CARDBUS
) {
1801 info
->id
->has_subsystem
= info
->id
->has_subsystem_vendor
= true;
1802 info
->id
->subsystem
= pci_get_word(dev
->config
+ PCI_CB_SUBSYSTEM_ID
);
1803 info
->id
->subsystem_vendor
=
1804 pci_get_word(dev
->config
+ PCI_CB_SUBSYSTEM_VENDOR_ID
);
1810 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
)
1812 PciDeviceInfoList
*head
= NULL
, **tail
= &head
;
1816 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1817 dev
= bus
->devices
[devfn
];
1819 QAPI_LIST_APPEND(tail
, qmp_query_pci_device(dev
, bus
, bus_num
));
1826 static PciInfo
*qmp_query_pci_bus(PCIBus
*bus
, int bus_num
)
1828 PciInfo
*info
= NULL
;
1830 bus
= pci_find_bus_nr(bus
, bus_num
);
1832 info
= g_malloc0(sizeof(*info
));
1833 info
->bus
= bus_num
;
1834 info
->devices
= qmp_query_pci_devices(bus
, bus_num
);
1840 PciInfoList
*qmp_query_pci(Error
**errp
)
1842 PciInfoList
*head
= NULL
, **tail
= &head
;
1843 PCIHostState
*host_bridge
;
1845 QLIST_FOREACH(host_bridge
, &pci_host_bridges
, next
) {
1846 QAPI_LIST_APPEND(tail
,
1847 qmp_query_pci_bus(host_bridge
->bus
,
1848 pci_bus_num(host_bridge
->bus
)));
1854 /* Initialize a PCI NIC. */
1855 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, PCIBus
*rootbus
,
1856 const char *default_model
,
1857 const char *default_devaddr
)
1859 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
1861 GPtrArray
*pci_nic_models
;
1870 if (nd
->model
&& !strcmp(nd
->model
, "virtio")) {
1872 nd
->model
= g_strdup("virtio-net-pci");
1875 list
= object_class_get_list_sorted(TYPE_PCI_DEVICE
, false);
1876 pci_nic_models
= g_ptr_array_new();
1878 DeviceClass
*dc
= OBJECT_CLASS_CHECK(DeviceClass
, list
->data
,
1881 if (test_bit(DEVICE_CATEGORY_NETWORK
, dc
->categories
) &&
1882 dc
->user_creatable
) {
1883 const char *name
= object_class_get_name(list
->data
);
1885 * A network device might also be something else than a NIC, see
1886 * e.g. the "rocker" device. Thus we have to look for the "netdev"
1887 * property, too. Unfortunately, some devices like virtio-net only
1888 * create this property during instance_init, so we have to create
1889 * a temporary instance here to be able to check it.
1891 Object
*obj
= object_new_with_class(OBJECT_CLASS(dc
));
1892 if (object_property_find(obj
, "netdev")) {
1893 g_ptr_array_add(pci_nic_models
, (gpointer
)name
);
1898 g_slist_free_1(list
);
1901 g_ptr_array_add(pci_nic_models
, NULL
);
1903 if (qemu_show_nic_models(nd
->model
, (const char **)pci_nic_models
->pdata
)) {
1907 i
= qemu_find_nic_model(nd
, (const char **)pci_nic_models
->pdata
,
1914 error_report("No primary PCI bus");
1918 assert(!rootbus
->parent_dev
);
1924 if (pci_parse_devaddr(devaddr
, &dom
, &busnr
, &slot
, NULL
) < 0) {
1925 error_report("Invalid PCI device address %s for device %s",
1926 devaddr
, nd
->model
);
1931 error_report("No support for non-zero PCI domains");
1935 devfn
= PCI_DEVFN(slot
, 0);
1938 bus
= pci_find_bus_nr(rootbus
, busnr
);
1940 error_report("Invalid PCI device address %s for device %s",
1941 devaddr
, nd
->model
);
1945 pci_dev
= pci_new(devfn
, nd
->model
);
1946 dev
= &pci_dev
->qdev
;
1947 qdev_set_nic_properties(dev
, nd
);
1948 pci_realize_and_unref(pci_dev
, bus
, &error_fatal
);
1949 g_ptr_array_free(pci_nic_models
, true);
1953 PCIDevice
*pci_vga_init(PCIBus
*bus
)
1955 switch (vga_interface_type
) {
1957 return pci_create_simple(bus
, -1, "cirrus-vga");
1959 return pci_create_simple(bus
, -1, "qxl-vga");
1961 return pci_create_simple(bus
, -1, "VGA");
1963 return pci_create_simple(bus
, -1, "vmware-svga");
1965 return pci_create_simple(bus
, -1, "virtio-vga");
1967 default: /* Other non-PCI types. Checking for unsupported types is already
1973 /* Whether a given bus number is in range of the secondary
1974 * bus of the given bridge device. */
1975 static bool pci_secondary_bus_in_range(PCIDevice
*dev
, int bus_num
)
1977 return !(pci_get_word(dev
->config
+ PCI_BRIDGE_CONTROL
) &
1978 PCI_BRIDGE_CTL_BUS_RESET
) /* Don't walk the bus if it's reset. */ &&
1979 dev
->config
[PCI_SECONDARY_BUS
] <= bus_num
&&
1980 bus_num
<= dev
->config
[PCI_SUBORDINATE_BUS
];
1983 /* Whether a given bus number is in a range of a root bus */
1984 static bool pci_root_bus_in_range(PCIBus
*bus
, int bus_num
)
1988 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
1989 PCIDevice
*dev
= bus
->devices
[i
];
1991 if (dev
&& PCI_DEVICE_GET_CLASS(dev
)->is_bridge
) {
1992 if (pci_secondary_bus_in_range(dev
, bus_num
)) {
2001 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
)
2009 if (pci_bus_num(bus
) == bus_num
) {
2013 /* Consider all bus numbers in range for the host pci bridge. */
2014 if (!pci_bus_is_root(bus
) &&
2015 !pci_secondary_bus_in_range(bus
->parent_dev
, bus_num
)) {
2020 for (; bus
; bus
= sec
) {
2021 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
2022 if (pci_bus_num(sec
) == bus_num
) {
2025 /* PXB buses assumed to be children of bus 0 */
2026 if (pci_bus_is_root(sec
)) {
2027 if (pci_root_bus_in_range(sec
, bus_num
)) {
2031 if (pci_secondary_bus_in_range(sec
->parent_dev
, bus_num
)) {
2041 void pci_for_each_bus_depth_first(PCIBus
*bus
,
2042 void *(*begin
)(PCIBus
*bus
, void *parent_state
),
2043 void (*end
)(PCIBus
*bus
, void *state
),
2054 state
= begin(bus
, parent_state
);
2056 state
= parent_state
;
2059 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
2060 pci_for_each_bus_depth_first(sec
, begin
, end
, state
);
2069 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
)
2071 bus
= pci_find_bus_nr(bus
, bus_num
);
2076 return bus
->devices
[devfn
];
2079 static void pci_qdev_realize(DeviceState
*qdev
, Error
**errp
)
2081 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
2082 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
2083 ObjectClass
*klass
= OBJECT_CLASS(pc
);
2084 Error
*local_err
= NULL
;
2085 bool is_default_rom
;
2088 if (pci_dev
->romsize
!= -1 && !is_power_of_2(pci_dev
->romsize
)) {
2089 error_setg(errp
, "ROM size %u is not a power of two", pci_dev
->romsize
);
2093 /* initialize cap_present for pci_is_express() and pci_config_size(),
2094 * Note that hybrid PCIs are not set automatically and need to manage
2095 * QEMU_PCI_CAP_EXPRESS manually */
2096 if (object_class_dynamic_cast(klass
, INTERFACE_PCIE_DEVICE
) &&
2097 !object_class_dynamic_cast(klass
, INTERFACE_CONVENTIONAL_PCI_DEVICE
)) {
2098 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
2101 pci_dev
= do_pci_register_device(pci_dev
,
2102 object_get_typename(OBJECT(qdev
)),
2103 pci_dev
->devfn
, errp
);
2104 if (pci_dev
== NULL
)
2108 pc
->realize(pci_dev
, &local_err
);
2110 error_propagate(errp
, local_err
);
2111 do_pci_unregister_device(pci_dev
);
2116 if (pci_dev
->failover_pair_id
) {
2117 if (!pci_bus_is_express(pci_get_bus(pci_dev
))) {
2118 error_setg(errp
, "failover primary device must be on "
2120 pci_qdev_unrealize(DEVICE(pci_dev
));
2123 class_id
= pci_get_word(pci_dev
->config
+ PCI_CLASS_DEVICE
);
2124 if (class_id
!= PCI_CLASS_NETWORK_ETHERNET
) {
2125 error_setg(errp
, "failover primary device is not an "
2127 pci_qdev_unrealize(DEVICE(pci_dev
));
2130 if (!(pci_dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)
2131 && (PCI_FUNC(pci_dev
->devfn
) == 0)) {
2132 qdev
->allow_unplug_during_migration
= true;
2134 error_setg(errp
, "failover: primary device must be in its own "
2136 pci_qdev_unrealize(DEVICE(pci_dev
));
2139 qdev
->allow_unplug_during_migration
= true;
2143 is_default_rom
= false;
2144 if (pci_dev
->romfile
== NULL
&& pc
->romfile
!= NULL
) {
2145 pci_dev
->romfile
= g_strdup(pc
->romfile
);
2146 is_default_rom
= true;
2149 pci_add_option_rom(pci_dev
, is_default_rom
, &local_err
);
2151 error_propagate(errp
, local_err
);
2152 pci_qdev_unrealize(DEVICE(pci_dev
));
2157 PCIDevice
*pci_new_multifunction(int devfn
, bool multifunction
,
2162 dev
= qdev_new(name
);
2163 qdev_prop_set_int32(dev
, "addr", devfn
);
2164 qdev_prop_set_bit(dev
, "multifunction", multifunction
);
2165 return PCI_DEVICE(dev
);
2168 PCIDevice
*pci_new(int devfn
, const char *name
)
2170 return pci_new_multifunction(devfn
, false, name
);
2173 bool pci_realize_and_unref(PCIDevice
*dev
, PCIBus
*bus
, Error
**errp
)
2175 return qdev_realize_and_unref(&dev
->qdev
, &bus
->qbus
, errp
);
2178 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
2182 PCIDevice
*dev
= pci_new_multifunction(devfn
, multifunction
, name
);
2183 pci_realize_and_unref(dev
, bus
, &error_fatal
);
2187 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
2189 return pci_create_simple_multifunction(bus
, devfn
, false, name
);
2192 static uint8_t pci_find_space(PCIDevice
*pdev
, uint8_t size
)
2194 int offset
= PCI_CONFIG_HEADER_SIZE
;
2196 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< PCI_CONFIG_SPACE_SIZE
; ++i
) {
2199 else if (i
- offset
+ 1 == size
)
2205 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
2210 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
2213 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
2214 prev
= next
+ PCI_CAP_LIST_NEXT
)
2215 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
2223 static uint8_t pci_find_capability_at_offset(PCIDevice
*pdev
, uint8_t offset
)
2225 uint8_t next
, prev
, found
= 0;
2227 if (!(pdev
->used
[offset
])) {
2231 assert(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
);
2233 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
2234 prev
= next
+ PCI_CAP_LIST_NEXT
) {
2235 if (next
<= offset
&& next
> found
) {
2242 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
2243 This is needed for an option rom which is used for more than one device. */
2244 static void pci_patch_ids(PCIDevice
*pdev
, uint8_t *ptr
, uint32_t size
)
2248 uint16_t rom_vendor_id
;
2249 uint16_t rom_device_id
;
2251 uint16_t pcir_offset
;
2254 /* Words in rom data are little endian (like in PCI configuration),
2255 so they can be read / written with pci_get_word / pci_set_word. */
2257 /* Only a valid rom will be patched. */
2258 rom_magic
= pci_get_word(ptr
);
2259 if (rom_magic
!= 0xaa55) {
2260 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic
);
2263 pcir_offset
= pci_get_word(ptr
+ 0x18);
2264 if (pcir_offset
+ 8 >= size
|| memcmp(ptr
+ pcir_offset
, "PCIR", 4)) {
2265 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset
);
2269 vendor_id
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
2270 device_id
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
2271 rom_vendor_id
= pci_get_word(ptr
+ pcir_offset
+ 4);
2272 rom_device_id
= pci_get_word(ptr
+ pcir_offset
+ 6);
2274 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev
->romfile
,
2275 vendor_id
, device_id
, rom_vendor_id
, rom_device_id
);
2279 if (vendor_id
!= rom_vendor_id
) {
2280 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
2281 checksum
+= (uint8_t)rom_vendor_id
+ (uint8_t)(rom_vendor_id
>> 8);
2282 checksum
-= (uint8_t)vendor_id
+ (uint8_t)(vendor_id
>> 8);
2283 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
2285 pci_set_word(ptr
+ pcir_offset
+ 4, vendor_id
);
2288 if (device_id
!= rom_device_id
) {
2289 /* Patch device id and checksum (at offset 6 for etherboot roms). */
2290 checksum
+= (uint8_t)rom_device_id
+ (uint8_t)(rom_device_id
>> 8);
2291 checksum
-= (uint8_t)device_id
+ (uint8_t)(device_id
>> 8);
2292 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
2294 pci_set_word(ptr
+ pcir_offset
+ 6, device_id
);
2298 /* Add an option rom for the device */
2299 static void pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
,
2306 const VMStateDescription
*vmsd
;
2310 if (strlen(pdev
->romfile
) == 0)
2313 if (!pdev
->rom_bar
) {
2315 * Load rom via fw_cfg instead of creating a rom bar,
2316 * for 0.11 compatibility.
2318 int class = pci_get_word(pdev
->config
+ PCI_CLASS_DEVICE
);
2321 * Hot-plugged devices can't use the option ROM
2322 * if the rom bar is disabled.
2324 if (DEVICE(pdev
)->hotplugged
) {
2325 error_setg(errp
, "Hot-plugged device without ROM bar"
2326 " can't have an option ROM");
2330 if (class == 0x0300) {
2331 rom_add_vga(pdev
->romfile
);
2333 rom_add_option(pdev
->romfile
, -1);
2338 path
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, pdev
->romfile
);
2340 path
= g_strdup(pdev
->romfile
);
2343 size
= get_image_size(path
);
2345 error_setg(errp
, "failed to find romfile \"%s\"", pdev
->romfile
);
2348 } else if (size
== 0) {
2349 error_setg(errp
, "romfile \"%s\" is empty", pdev
->romfile
);
2352 } else if (size
> 2 * GiB
) {
2353 error_setg(errp
, "romfile \"%s\" too large (size cannot exceed 2 GiB)",
2358 if (pdev
->romsize
!= -1) {
2359 if (size
> pdev
->romsize
) {
2360 error_setg(errp
, "romfile \"%s\" (%u bytes) is too large for ROM size %u",
2361 pdev
->romfile
, (uint32_t)size
, pdev
->romsize
);
2366 pdev
->romsize
= pow2ceil(size
);
2369 vmsd
= qdev_get_vmsd(DEVICE(pdev
));
2372 snprintf(name
, sizeof(name
), "%s.rom", vmsd
->name
);
2374 snprintf(name
, sizeof(name
), "%s.rom", object_get_typename(OBJECT(pdev
)));
2376 pdev
->has_rom
= true;
2377 memory_region_init_rom(&pdev
->rom
, OBJECT(pdev
), name
, pdev
->romsize
, &error_fatal
);
2378 ptr
= memory_region_get_ram_ptr(&pdev
->rom
);
2379 if (load_image_size(path
, ptr
, size
) < 0) {
2380 error_setg(errp
, "failed to load romfile \"%s\"", pdev
->romfile
);
2386 if (is_default_rom
) {
2387 /* Only the default rom images will be patched (if needed). */
2388 pci_patch_ids(pdev
, ptr
, size
);
2391 pci_register_bar(pdev
, PCI_ROM_SLOT
, 0, &pdev
->rom
);
2394 static void pci_del_option_rom(PCIDevice
*pdev
)
2399 vmstate_unregister_ram(&pdev
->rom
, &pdev
->qdev
);
2400 pdev
->has_rom
= false;
2404 * On success, pci_add_capability() returns a positive value
2405 * that the offset of the pci capability.
2406 * On failure, it sets an error and returns a negative error
2409 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
2410 uint8_t offset
, uint8_t size
,
2414 int i
, overlapping_cap
;
2417 offset
= pci_find_space(pdev
, size
);
2418 /* out of PCI config space is programming error */
2421 /* Verify that capabilities don't overlap. Note: device assignment
2422 * depends on this check to verify that the device is not broken.
2423 * Should never trigger for emulated devices, but it's helpful
2424 * for debugging these. */
2425 for (i
= offset
; i
< offset
+ size
; i
++) {
2426 overlapping_cap
= pci_find_capability_at_offset(pdev
, i
);
2427 if (overlapping_cap
) {
2428 error_setg(errp
, "%s:%02x:%02x.%x "
2429 "Attempt to add PCI capability %x at offset "
2430 "%x overlaps existing capability %x at offset %x",
2431 pci_root_bus_path(pdev
), pci_dev_bus_num(pdev
),
2432 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
),
2433 cap_id
, offset
, overlapping_cap
, i
);
2439 config
= pdev
->config
+ offset
;
2440 config
[PCI_CAP_LIST_ID
] = cap_id
;
2441 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
2442 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
2443 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
2444 memset(pdev
->used
+ offset
, 0xFF, QEMU_ALIGN_UP(size
, 4));
2445 /* Make capability read-only by default */
2446 memset(pdev
->wmask
+ offset
, 0, size
);
2447 /* Check capability by default */
2448 memset(pdev
->cmask
+ offset
, 0xFF, size
);
2452 /* Unlink capability from the pci config space. */
2453 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
2455 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
2458 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
2459 /* Make capability writable again */
2460 memset(pdev
->wmask
+ offset
, 0xff, size
);
2461 memset(pdev
->w1cmask
+ offset
, 0, size
);
2462 /* Clear cmask as device-specific registers can't be checked */
2463 memset(pdev
->cmask
+ offset
, 0, size
);
2464 memset(pdev
->used
+ offset
, 0, QEMU_ALIGN_UP(size
, 4));
2466 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
2467 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
2470 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
2472 return pci_find_capability_list(pdev
, cap_id
, NULL
);
2475 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
2477 PCIDevice
*d
= (PCIDevice
*)dev
;
2478 const pci_class_desc
*desc
;
2483 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2484 desc
= pci_class_descriptions
;
2485 while (desc
->desc
&& class != desc
->class)
2488 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
2490 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
2493 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
2494 "pci id %04x:%04x (sub %04x:%04x)\n",
2495 indent
, "", ctxt
, pci_dev_bus_num(d
),
2496 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
),
2497 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2498 pci_get_word(d
->config
+ PCI_DEVICE_ID
),
2499 pci_get_word(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
),
2500 pci_get_word(d
->config
+ PCI_SUBSYSTEM_ID
));
2501 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
2502 r
= &d
->io_regions
[i
];
2505 monitor_printf(mon
, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2506 " [0x%"FMT_PCIBUS
"]\n",
2508 i
, r
->type
& PCI_BASE_ADDRESS_SPACE_IO
? "i/o" : "mem",
2509 r
->addr
, r
->addr
+ r
->size
- 1);
2513 static char *pci_dev_fw_name(DeviceState
*dev
, char *buf
, int len
)
2515 PCIDevice
*d
= (PCIDevice
*)dev
;
2516 const char *name
= NULL
;
2517 const pci_class_desc
*desc
= pci_class_descriptions
;
2518 int class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2520 while (desc
->desc
&&
2521 (class & ~desc
->fw_ign_bits
) !=
2522 (desc
->class & ~desc
->fw_ign_bits
)) {
2527 name
= desc
->fw_name
;
2531 pstrcpy(buf
, len
, name
);
2533 snprintf(buf
, len
, "pci%04x,%04x",
2534 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2535 pci_get_word(d
->config
+ PCI_DEVICE_ID
));
2541 static char *pcibus_get_fw_dev_path(DeviceState
*dev
)
2543 PCIDevice
*d
= (PCIDevice
*)dev
;
2544 char path
[50], name
[33];
2547 off
= snprintf(path
, sizeof(path
), "%s@%x",
2548 pci_dev_fw_name(dev
, name
, sizeof name
),
2549 PCI_SLOT(d
->devfn
));
2550 if (PCI_FUNC(d
->devfn
))
2551 snprintf(path
+ off
, sizeof(path
) + off
, ",%x", PCI_FUNC(d
->devfn
));
2552 return g_strdup(path
);
2555 static char *pcibus_get_dev_path(DeviceState
*dev
)
2557 PCIDevice
*d
= container_of(dev
, PCIDevice
, qdev
);
2560 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2561 * 00 is added here to make this format compatible with
2562 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2563 * Slot.Function list specifies the slot and function numbers for all
2564 * devices on the path from root to the specific device. */
2565 const char *root_bus_path
;
2567 char slot
[] = ":SS.F";
2568 int slot_len
= sizeof slot
- 1 /* For '\0' */;
2573 root_bus_path
= pci_root_bus_path(d
);
2574 root_bus_len
= strlen(root_bus_path
);
2576 /* Calculate # of slots on path between device and root. */;
2578 for (t
= d
; t
; t
= pci_get_bus(t
)->parent_dev
) {
2582 path_len
= root_bus_len
+ slot_len
* slot_depth
;
2584 /* Allocate memory, fill in the terminating null byte. */
2585 path
= g_malloc(path_len
+ 1 /* For '\0' */);
2586 path
[path_len
] = '\0';
2588 memcpy(path
, root_bus_path
, root_bus_len
);
2590 /* Fill in slot numbers. We walk up from device to root, so need to print
2591 * them in the reverse order, last to first. */
2592 p
= path
+ path_len
;
2593 for (t
= d
; t
; t
= pci_get_bus(t
)->parent_dev
) {
2595 s
= snprintf(slot
, sizeof slot
, ":%02x.%x",
2596 PCI_SLOT(t
->devfn
), PCI_FUNC(t
->devfn
));
2597 assert(s
== slot_len
);
2598 memcpy(p
, slot
, slot_len
);
2604 static int pci_qdev_find_recursive(PCIBus
*bus
,
2605 const char *id
, PCIDevice
**pdev
)
2607 DeviceState
*qdev
= qdev_find_recursive(&bus
->qbus
, id
);
2612 /* roughly check if given qdev is pci device */
2613 if (object_dynamic_cast(OBJECT(qdev
), TYPE_PCI_DEVICE
)) {
2614 *pdev
= PCI_DEVICE(qdev
);
2620 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
)
2622 PCIHostState
*host_bridge
;
2625 QLIST_FOREACH(host_bridge
, &pci_host_bridges
, next
) {
2626 int tmp
= pci_qdev_find_recursive(host_bridge
->bus
, id
, pdev
);
2631 if (tmp
!= -ENODEV
) {
2639 MemoryRegion
*pci_address_space(PCIDevice
*dev
)
2641 return pci_get_bus(dev
)->address_space_mem
;
2644 MemoryRegion
*pci_address_space_io(PCIDevice
*dev
)
2646 return pci_get_bus(dev
)->address_space_io
;
2649 static void pci_device_class_init(ObjectClass
*klass
, void *data
)
2651 DeviceClass
*k
= DEVICE_CLASS(klass
);
2653 k
->realize
= pci_qdev_realize
;
2654 k
->unrealize
= pci_qdev_unrealize
;
2655 k
->bus_type
= TYPE_PCI_BUS
;
2656 device_class_set_props(k
, pci_props
);
2659 static void pci_device_class_base_init(ObjectClass
*klass
, void *data
)
2661 if (!object_class_is_abstract(klass
)) {
2662 ObjectClass
*conventional
=
2663 object_class_dynamic_cast(klass
, INTERFACE_CONVENTIONAL_PCI_DEVICE
);
2665 object_class_dynamic_cast(klass
, INTERFACE_PCIE_DEVICE
);
2666 assert(conventional
|| pcie
);
2670 AddressSpace
*pci_device_iommu_address_space(PCIDevice
*dev
)
2672 PCIBus
*bus
= pci_get_bus(dev
);
2673 PCIBus
*iommu_bus
= bus
;
2674 uint8_t devfn
= dev
->devfn
;
2676 while (iommu_bus
&& !iommu_bus
->iommu_fn
&& iommu_bus
->parent_dev
) {
2677 PCIBus
*parent_bus
= pci_get_bus(iommu_bus
->parent_dev
);
2680 * The requester ID of the provided device may be aliased, as seen from
2681 * the IOMMU, due to topology limitations. The IOMMU relies on a
2682 * requester ID to provide a unique AddressSpace for devices, but
2683 * conventional PCI buses pre-date such concepts. Instead, the PCIe-
2684 * to-PCI bridge creates and accepts transactions on behalf of down-
2685 * stream devices. When doing so, all downstream devices are masked
2686 * (aliased) behind a single requester ID. The requester ID used
2687 * depends on the format of the bridge devices. Proper PCIe-to-PCI
2688 * bridges, with a PCIe capability indicating such, follow the
2689 * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification,
2690 * where the bridge uses the seconary bus as the bridge portion of the
2691 * requester ID and devfn of 00.0. For other bridges, typically those
2692 * found on the root complex such as the dmi-to-pci-bridge, we follow
2693 * the convention of typical bare-metal hardware, which uses the
2694 * requester ID of the bridge itself. There are device specific
2695 * exceptions to these rules, but these are the defaults that the
2696 * Linux kernel uses when determining DMA aliases itself and believed
2697 * to be true for the bare metal equivalents of the devices emulated
2700 if (!pci_bus_is_express(iommu_bus
)) {
2701 PCIDevice
*parent
= iommu_bus
->parent_dev
;
2703 if (pci_is_express(parent
) &&
2704 pcie_cap_get_type(parent
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
2705 devfn
= PCI_DEVFN(0, 0);
2708 devfn
= parent
->devfn
;
2713 iommu_bus
= parent_bus
;
2715 if (iommu_bus
&& iommu_bus
->iommu_fn
) {
2716 return iommu_bus
->iommu_fn(bus
, iommu_bus
->iommu_opaque
, devfn
);
2718 return &address_space_memory
;
2721 void pci_setup_iommu(PCIBus
*bus
, PCIIOMMUFunc fn
, void *opaque
)
2724 bus
->iommu_opaque
= opaque
;
2727 static void pci_dev_get_w64(PCIBus
*b
, PCIDevice
*dev
, void *opaque
)
2729 Range
*range
= opaque
;
2730 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
2731 uint16_t cmd
= pci_get_word(dev
->config
+ PCI_COMMAND
);
2734 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
2738 if (pc
->is_bridge
) {
2739 pcibus_t base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
2740 pcibus_t limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
2742 base
= MAX(base
, 0x1ULL
<< 32);
2744 if (limit
>= base
) {
2746 range_set_bounds(&pref_range
, base
, limit
);
2747 range_extend(range
, &pref_range
);
2750 for (i
= 0; i
< PCI_NUM_REGIONS
; ++i
) {
2751 PCIIORegion
*r
= &dev
->io_regions
[i
];
2756 (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) ||
2757 !(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
)) {
2761 lob
= pci_bar_address(dev
, i
, r
->type
, r
->size
);
2762 upb
= lob
+ r
->size
- 1;
2763 if (lob
== PCI_BAR_UNMAPPED
) {
2767 lob
= MAX(lob
, 0x1ULL
<< 32);
2770 range_set_bounds(®ion_range
, lob
, upb
);
2771 range_extend(range
, ®ion_range
);
2776 void pci_bus_get_w64_range(PCIBus
*bus
, Range
*range
)
2778 range_make_empty(range
);
2779 pci_for_each_device_under_bus(bus
, pci_dev_get_w64
, range
);
2782 static bool pcie_has_upstream_port(PCIDevice
*dev
)
2784 PCIDevice
*parent_dev
= pci_bridge_get_device(pci_get_bus(dev
));
2786 /* Device associated with an upstream port.
2787 * As there are several types of these, it's easier to check the
2788 * parent device: upstream ports are always connected to
2789 * root or downstream ports.
2791 return parent_dev
&&
2792 pci_is_express(parent_dev
) &&
2793 parent_dev
->exp
.exp_cap
&&
2794 (pcie_cap_get_type(parent_dev
) == PCI_EXP_TYPE_ROOT_PORT
||
2795 pcie_cap_get_type(parent_dev
) == PCI_EXP_TYPE_DOWNSTREAM
);
2798 PCIDevice
*pci_get_function_0(PCIDevice
*pci_dev
)
2800 PCIBus
*bus
= pci_get_bus(pci_dev
);
2802 if(pcie_has_upstream_port(pci_dev
)) {
2803 /* With an upstream PCIe port, we only support 1 device at slot 0 */
2804 return bus
->devices
[0];
2806 /* Other bus types might support multiple devices at slots 0-31 */
2807 return bus
->devices
[PCI_DEVFN(PCI_SLOT(pci_dev
->devfn
), 0)];
2811 MSIMessage
pci_get_msi_message(PCIDevice
*dev
, int vector
)
2814 if (msix_enabled(dev
)) {
2815 msg
= msix_get_message(dev
, vector
);
2816 } else if (msi_enabled(dev
)) {
2817 msg
= msi_get_message(dev
, vector
);
2819 /* Should never happen */
2820 error_report("%s: unknown interrupt type", __func__
);
2826 static const TypeInfo pci_device_type_info
= {
2827 .name
= TYPE_PCI_DEVICE
,
2828 .parent
= TYPE_DEVICE
,
2829 .instance_size
= sizeof(PCIDevice
),
2831 .class_size
= sizeof(PCIDeviceClass
),
2832 .class_init
= pci_device_class_init
,
2833 .class_base_init
= pci_device_class_base_init
,
2836 static void pci_register_types(void)
2838 type_register_static(&pci_bus_info
);
2839 type_register_static(&pcie_bus_info
);
2840 type_register_static(&conventional_pci_interface_info
);
2841 type_register_static(&pcie_interface_info
);
2842 type_register_static(&pci_device_type_info
);
2845 type_init(pci_register_types
)