hw/xilinx_spips.c

   1 /*
   2  * QEMU model of the Xilinx Zynq SPI controller
   3  *
   4  * Copyright (c) 2012 Peter A. G. Crosthwaite
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/sysbus.h"
  26 #include "sysemu/sysemu.h"
  27 #include "hw/ptimer.h"
  28 #include "qemu/log.h"
  29 #include "qemu/fifo8.h"
  30 #include "hw/ssi.h"
  31 #include "qemu/bitops.h"
  32
  33 #ifdef XILINX_SPIPS_ERR_DEBUG
  34 #define DB_PRINT(...) do { \
  35     fprintf(stderr,  ": %s: ", __func__); \
  36     fprintf(stderr, ## __VA_ARGS__); \
  37     } while (0);
  38 #else
  39     #define DB_PRINT(...)
  40 #endif
  41
  42 /* config register */
  43 #define R_CONFIG            (0x00 / 4)
  44 #define IFMODE              (1 << 31)
  45 #define ENDIAN              (1 << 26)
  46 #define MODEFAIL_GEN_EN     (1 << 17)
  47 #define MAN_START_COM       (1 << 16)
  48 #define MAN_START_EN        (1 << 15)
  49 #define MANUAL_CS           (1 << 14)
  50 #define CS                  (0xF << 10)
  51 #define CS_SHIFT            (10)
  52 #define PERI_SEL            (1 << 9)
  53 #define REF_CLK             (1 << 8)
  54 #define FIFO_WIDTH          (3 << 6)
  55 #define BAUD_RATE_DIV       (7 << 3)
  56 #define CLK_PH              (1 << 2)
  57 #define CLK_POL             (1 << 1)
  58 #define MODE_SEL            (1 << 0)
  59
  60 /* interrupt mechanism */
  61 #define R_INTR_STATUS       (0x04 / 4)
  62 #define R_INTR_EN           (0x08 / 4)
  63 #define R_INTR_DIS          (0x0C / 4)
  64 #define R_INTR_MASK         (0x10 / 4)
  65 #define IXR_TX_FIFO_UNDERFLOW   (1 << 6)
  66 #define IXR_RX_FIFO_FULL        (1 << 5)
  67 #define IXR_RX_FIFO_NOT_EMPTY   (1 << 4)
  68 #define IXR_TX_FIFO_FULL        (1 << 3)
  69 #define IXR_TX_FIFO_NOT_FULL    (1 << 2)
  70 #define IXR_TX_FIFO_MODE_FAIL   (1 << 1)
  71 #define IXR_RX_FIFO_OVERFLOW    (1 << 0)
  72 #define IXR_ALL                 ((IXR_TX_FIFO_UNDERFLOW<<1)-1)
  73
  74 #define R_EN                (0x14 / 4)
  75 #define R_DELAY             (0x18 / 4)
  76 #define R_TX_DATA           (0x1C / 4)
  77 #define R_RX_DATA           (0x20 / 4)
  78 #define R_SLAVE_IDLE_COUNT  (0x24 / 4)
  79 #define R_TX_THRES          (0x28 / 4)
  80 #define R_RX_THRES          (0x2C / 4)
  81 #define R_TXD1              (0x80 / 4)
  82 #define R_TXD2              (0x84 / 4)
  83 #define R_TXD3              (0x88 / 4)
  84
  85 #define R_LQSPI_CFG         (0xa0 / 4)
  86 #define R_LQSPI_CFG_RESET       0x03A002EB
  87 #define LQSPI_CFG_LQ_MODE       (1 << 31)
  88 #define LQSPI_CFG_TWO_MEM       (1 << 30)
  89 #define LQSPI_CFG_SEP_BUS       (1 << 30)
  90 #define LQSPI_CFG_U_PAGE        (1 << 28)
  91 #define LQSPI_CFG_MODE_EN       (1 << 25)
  92 #define LQSPI_CFG_MODE_WIDTH    8
  93 #define LQSPI_CFG_MODE_SHIFT    16
  94 #define LQSPI_CFG_DUMMY_WIDTH   3
  95 #define LQSPI_CFG_DUMMY_SHIFT   8
  96 #define LQSPI_CFG_INST_CODE     0xFF
  97
  98 #define R_LQSPI_STS         (0xA4 / 4)
  99 #define LQSPI_STS_WR_RECVD      (1 << 1)
 100
 101 #define R_MOD_ID            (0xFC / 4)
 102
 103 #define R_MAX (R_MOD_ID+1)
 104
 105 /* size of TXRX FIFOs */
 106 #define RXFF_A          32
 107 #define TXFF_A          32
 108
 109 /* 16MB per linear region */
 110 #define LQSPI_ADDRESS_BITS 24
 111 /* Bite off 4k chunks at a time */
 112 #define LQSPI_CACHE_SIZE 1024
 113
 114 #define SNOOP_CHECKING 0xFF
 115 #define SNOOP_NONE 0xFE
 116 #define SNOOP_STRIPING 0
 117
 118 typedef enum {
 119     READ = 0x3,
 120     FAST_READ = 0xb,
 121     DOR = 0x3b,
 122     QOR = 0x6b,
 123     DIOR = 0xbb,
 124     QIOR = 0xeb,
 125
 126     PP = 0x2,
 127     DPP = 0xa2,
 128     QPP = 0x32,
 129 } FlashCMD;
 130
 131 typedef struct {
 132     SysBusDevice busdev;
 133     MemoryRegion iomem;
 134     MemoryRegion mmlqspi;
 135
 136     qemu_irq irq;
 137     int irqline;
 138
 139     uint8_t num_cs;
 140     uint8_t num_busses;
 141
 142     uint8_t snoop_state;
 143     qemu_irq *cs_lines;
 144     SSIBus **spi;
 145
 146     Fifo8 rx_fifo;
 147     Fifo8 tx_fifo;
 148
 149     uint8_t num_txrx_bytes;
 150
 151     uint32_t regs[R_MAX];
 152
 153     uint32_t lqspi_buf[LQSPI_CACHE_SIZE];
 154     hwaddr lqspi_cached_addr;
 155 } XilinxSPIPS;
 156
 157 static inline int num_effective_busses(XilinxSPIPS *s)
 158 {
 159     return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS &&
 160             s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1;
 161 }
 162
 163 static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
 164 {
 165     int i, j;
 166     bool found = false;
 167     int field = s->regs[R_CONFIG] >> CS_SHIFT;
 168
 169     for (i = 0; i < s->num_cs; i++) {
 170         for (j = 0; j < num_effective_busses(s); j++) {
 171             int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE);
 172             int cs_to_set = (j * s->num_cs + i + upage) %
 173                                 (s->num_cs * s->num_busses);
 174
 175             if (~field & (1 << i) && !found) {
 176                 DB_PRINT("selecting slave %d\n", i);
 177                 qemu_set_irq(s->cs_lines[cs_to_set], 0);
 178             } else {
 179                 qemu_set_irq(s->cs_lines[cs_to_set], 1);
 180             }
 181         }
 182         if (~field & (1 << i)) {
 183             found = true;
 184         }
 185     }
 186     if (!found) {
 187         s->snoop_state = SNOOP_CHECKING;
 188     }
 189 }
 190
 191 static void xilinx_spips_update_ixr(XilinxSPIPS *s)
 192 {
 193     /* These are set/cleared as they occur */
 194     s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW |
 195                                 IXR_TX_FIFO_MODE_FAIL);
 196     /* these are pure functions of fifo state, set them here */
 197     s->regs[R_INTR_STATUS] |=
 198         (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) |
 199         (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) |
 200         (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) |
 201         (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0);
 202     /* drive external interrupt pin */
 203     int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] &
 204                                                                 IXR_ALL);
 205     if (new_irqline != s->irqline) {
 206         s->irqline = new_irqline;
 207         qemu_set_irq(s->irq, s->irqline);
 208     }
 209 }
 210
 211 static void xilinx_spips_reset(DeviceState *d)
 212 {
 213     XilinxSPIPS *s = DO_UPCAST(XilinxSPIPS, busdev.qdev, d);
 214
 215     int i;
 216     for (i = 0; i < R_MAX; i++) {
 217         s->regs[i] = 0;
 218     }
 219
 220     fifo8_reset(&s->rx_fifo);
 221     fifo8_reset(&s->rx_fifo);
 222     /* non zero resets */
 223     s->regs[R_CONFIG] |= MODEFAIL_GEN_EN;
 224     s->regs[R_SLAVE_IDLE_COUNT] = 0xFF;
 225     s->regs[R_TX_THRES] = 1;
 226     s->regs[R_RX_THRES] = 1;
 227     /* FIXME: move magic number definition somewhere sensible */
 228     s->regs[R_MOD_ID] = 0x01090106;
 229     s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET;
 230     s->snoop_state = SNOOP_CHECKING;
 231     xilinx_spips_update_ixr(s);
 232     xilinx_spips_update_cs_lines(s);
 233 }
 234
 235 static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
 236 {
 237     for (;;) {
 238         int i;
 239         uint8_t rx;
 240         uint8_t tx = 0;
 241
 242         for (i = 0; i < num_effective_busses(s); ++i) {
 243             if (!i || s->snoop_state == SNOOP_STRIPING) {
 244                 if (fifo8_is_empty(&s->tx_fifo)) {
 245                     s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
 246                     xilinx_spips_update_ixr(s);
 247                     return;
 248                 } else {
 249                     tx = fifo8_pop(&s->tx_fifo);
 250                 }
 251             }
 252             rx = ssi_transfer(s->spi[i], (uint32_t)tx);
 253             DB_PRINT("tx = %02x rx = %02x\n", tx, rx);
 254             if (!i || s->snoop_state == SNOOP_STRIPING) {
 255                 if (fifo8_is_full(&s->rx_fifo)) {
 256                     s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW;
 257                     DB_PRINT("rx FIFO overflow");
 258                 } else {
 259                     fifo8_push(&s->rx_fifo, (uint8_t)rx);
 260                 }
 261             }
 262         }
 263
 264         switch (s->snoop_state) {
 265         case (SNOOP_CHECKING):
 266             switch (tx) { /* new instruction code */
 267             case READ: /* 3 address bytes, no dummy bytes/cycles */
 268             case PP:
 269             case DPP:
 270             case QPP:
 271                 s->snoop_state = 3;
 272                 break;
 273             case FAST_READ: /* 3 address bytes, 1 dummy byte */
 274             case DOR:
 275             case QOR:
 276             case DIOR: /* FIXME: these vary between vendor - set to spansion */
 277                 s->snoop_state = 4;
 278                 break;
 279             case QIOR: /* 3 address bytes, 2 dummy bytes */
 280                 s->snoop_state = 6;
 281                 break;
 282             default:
 283                 s->snoop_state = SNOOP_NONE;
 284             }
 285             break;
 286         case (SNOOP_STRIPING):
 287         case (SNOOP_NONE):
 288             break;
 289         default:
 290             s->snoop_state--;
 291         }
 292     }
 293 }
 294
 295 static inline void rx_data_bytes(XilinxSPIPS *s, uint32_t *value, int max)
 296 {
 297     int i;
 298
 299     *value = 0;
 300     for (i = 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) {
 301         uint32_t next = fifo8_pop(&s->rx_fifo) & 0xFF;
 302         *value |= next << 8 * (s->regs[R_CONFIG] & ENDIAN ? 3-i : i);
 303     }
 304 }
 305
 306 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
 307                                                         unsigned size)
 308 {
 309     XilinxSPIPS *s = opaque;
 310     uint32_t mask = ~0;
 311     uint32_t ret;
 312
 313     addr >>= 2;
 314     switch (addr) {
 315     case R_CONFIG:
 316         mask = 0x0002FFFF;
 317         break;
 318     case R_INTR_STATUS:
 319     case R_INTR_MASK:
 320         mask = IXR_ALL;
 321         break;
 322     case  R_EN:
 323         mask = 0x1;
 324         break;
 325     case R_SLAVE_IDLE_COUNT:
 326         mask = 0xFF;
 327         break;
 328     case R_MOD_ID:
 329         mask = 0x01FFFFFF;
 330         break;
 331     case R_INTR_EN:
 332     case R_INTR_DIS:
 333     case R_TX_DATA:
 334         mask = 0;
 335         break;
 336     case R_RX_DATA:
 337         rx_data_bytes(s, &ret, s->num_txrx_bytes);
 338         DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
 339         xilinx_spips_update_ixr(s);
 340         return ret;
 341     }
 342     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, s->regs[addr] & mask);
 343     return s->regs[addr] & mask;
 344
 345 }
 346
 347 static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num)
 348 {
 349     int i;
 350     for (i = 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) {
 351         if (s->regs[R_CONFIG] & ENDIAN) {
 352             fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24));
 353             value <<= 8;
 354         } else {
 355             fifo8_push(&s->tx_fifo, (uint8_t)value);
 356             value >>= 8;
 357         }
 358     }
 359 }
 360
 361 static void xilinx_spips_write(void *opaque, hwaddr addr,
 362                                         uint64_t value, unsigned size)
 363 {
 364     int mask = ~0;
 365     int man_start_com = 0;
 366     XilinxSPIPS *s = opaque;
 367
 368     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
 369     addr >>= 2;
 370     switch (addr) {
 371     case R_CONFIG:
 372         mask = 0x0002FFFF;
 373         if (value & MAN_START_COM) {
 374             man_start_com = 1;
 375         }
 376         break;
 377     case R_INTR_STATUS:
 378         mask = IXR_ALL;
 379         s->regs[R_INTR_STATUS] &= ~(mask & value);
 380         goto no_reg_update;
 381     case R_INTR_DIS:
 382         mask = IXR_ALL;
 383         s->regs[R_INTR_MASK] &= ~(mask & value);
 384         goto no_reg_update;
 385     case R_INTR_EN:
 386         mask = IXR_ALL;
 387         s->regs[R_INTR_MASK] |= mask & value;
 388         goto no_reg_update;
 389     case R_EN:
 390         mask = 0x1;
 391         break;
 392     case R_SLAVE_IDLE_COUNT:
 393         mask = 0xFF;
 394         break;
 395     case R_RX_DATA:
 396     case R_INTR_MASK:
 397     case R_MOD_ID:
 398         mask = 0;
 399         break;
 400     case R_TX_DATA:
 401         tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes);
 402         goto no_reg_update;
 403     case R_TXD1:
 404         tx_data_bytes(s, (uint32_t)value, 1);
 405         goto no_reg_update;
 406     case R_TXD2:
 407         tx_data_bytes(s, (uint32_t)value, 2);
 408         goto no_reg_update;
 409     case R_TXD3:
 410         tx_data_bytes(s, (uint32_t)value, 3);
 411         goto no_reg_update;
 412     }
 413     s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
 414 no_reg_update:
 415     if (man_start_com) {
 416         xilinx_spips_flush_txfifo(s);
 417     }
 418     xilinx_spips_update_ixr(s);
 419     xilinx_spips_update_cs_lines(s);
 420 }
 421
 422 static const MemoryRegionOps spips_ops = {
 423     .read = xilinx_spips_read,
 424     .write = xilinx_spips_write,
 425     .endianness = DEVICE_LITTLE_ENDIAN,
 426 };
 427
 428 #define LQSPI_CACHE_SIZE 1024
 429
 430 static uint64_t
 431 lqspi_read(void *opaque, hwaddr addr, unsigned int size)
 432 {
 433     int i;
 434     XilinxSPIPS *s = opaque;
 435
 436     if (addr >= s->lqspi_cached_addr &&
 437             addr <= s->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
 438         return s->lqspi_buf[(addr - s->lqspi_cached_addr) >> 2];
 439     } else {
 440         int flash_addr = (addr / num_effective_busses(s));
 441         int slave = flash_addr >> LQSPI_ADDRESS_BITS;
 442         int cache_entry = 0;
 443
 444         DB_PRINT("config reg status: %08x\n", s->regs[R_LQSPI_CFG]);
 445
 446         fifo8_reset(&s->tx_fifo);
 447         fifo8_reset(&s->rx_fifo);
 448
 449         s->regs[R_CONFIG] &= ~CS;
 450         s->regs[R_CONFIG] |= (~(1 << slave) << CS_SHIFT) & CS;
 451         xilinx_spips_update_cs_lines(s);
 452
 453         /* instruction */
 454         DB_PRINT("pushing read instruction: %02x\n",
 455                  (uint8_t)(s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE));
 456         fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE);
 457         /* read address */
 458         DB_PRINT("pushing read address %06x\n", flash_addr);
 459         fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16));
 460         fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8));
 461         fifo8_push(&s->tx_fifo, (uint8_t)flash_addr);
 462         /* mode bits */
 463         if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) {
 464             fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG],
 465                                               LQSPI_CFG_MODE_SHIFT,
 466                                               LQSPI_CFG_MODE_WIDTH));
 467         }
 468         /* dummy bytes */
 469         for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT,
 470                                    LQSPI_CFG_DUMMY_WIDTH)); ++i) {
 471             DB_PRINT("pushing dummy byte\n");
 472             fifo8_push(&s->tx_fifo, 0);
 473         }
 474         xilinx_spips_flush_txfifo(s);
 475         fifo8_reset(&s->rx_fifo);
 476
 477         DB_PRINT("starting QSPI data read\n");
 478
 479         for (i = 0; i < LQSPI_CACHE_SIZE / 4; ++i) {
 480             tx_data_bytes(s, 0, 4);
 481             xilinx_spips_flush_txfifo(s);
 482             rx_data_bytes(s, &s->lqspi_buf[cache_entry], 4);
 483             cache_entry++;
 484         }
 485
 486         s->regs[R_CONFIG] |= CS;
 487         xilinx_spips_update_cs_lines(s);
 488
 489         s->lqspi_cached_addr = addr;
 490         return lqspi_read(opaque, addr, size);
 491     }
 492 }
 493
 494 static const MemoryRegionOps lqspi_ops = {
 495     .read = lqspi_read,
 496     .endianness = DEVICE_NATIVE_ENDIAN,
 497     .valid = {
 498         .min_access_size = 4,
 499         .max_access_size = 4
 500     }
 501 };
 502
 503 static int xilinx_spips_init(SysBusDevice *dev)
 504 {
 505     XilinxSPIPS *s = FROM_SYSBUS(typeof(*s), dev);
 506     int i;
 507
 508     DB_PRINT("inited device model\n");
 509
 510     s->spi = g_new(SSIBus *, s->num_busses);
 511     for (i = 0; i < s->num_busses; ++i) {
 512         char bus_name[16];
 513         snprintf(bus_name, 16, "spi%d", i);
 514         s->spi[i] = ssi_create_bus(&dev->qdev, bus_name);
 515     }
 516
 517     s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses);
 518     ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[0]);
 519     ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[1]);
 520     sysbus_init_irq(dev, &s->irq);
 521     for (i = 0; i < s->num_cs * s->num_busses; ++i) {
 522         sysbus_init_irq(dev, &s->cs_lines[i]);
 523     }
 524
 525     memory_region_init_io(&s->iomem, &spips_ops, s, "spi", R_MAX*4);
 526     sysbus_init_mmio(dev, &s->iomem);
 527
 528     memory_region_init_io(&s->mmlqspi, &lqspi_ops, s, "lqspi",
 529                           (1 << LQSPI_ADDRESS_BITS) * 2);
 530     sysbus_init_mmio(dev, &s->mmlqspi);
 531
 532     s->irqline = -1;
 533     s->lqspi_cached_addr = ~0ULL;
 534
 535     fifo8_create(&s->rx_fifo, RXFF_A);
 536     fifo8_create(&s->tx_fifo, TXFF_A);
 537
 538     return 0;
 539 }
 540
 541 static int xilinx_spips_post_load(void *opaque, int version_id)
 542 {
 543     xilinx_spips_update_ixr((XilinxSPIPS *)opaque);
 544     xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque);
 545     return 0;
 546 }
 547
 548 static const VMStateDescription vmstate_xilinx_spips = {
 549     .name = "xilinx_spips",
 550     .version_id = 2,
 551     .minimum_version_id = 2,
 552     .minimum_version_id_old = 2,
 553     .post_load = xilinx_spips_post_load,
 554     .fields = (VMStateField[]) {
 555         VMSTATE_FIFO8(tx_fifo, XilinxSPIPS),
 556         VMSTATE_FIFO8(rx_fifo, XilinxSPIPS),
 557         VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, R_MAX),
 558         VMSTATE_UINT8(snoop_state, XilinxSPIPS),
 559         VMSTATE_END_OF_LIST()
 560     }
 561 };
 562
 563 static Property xilinx_spips_properties[] = {
 564     DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1),
 565     DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4),
 566     DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1),
 567     DEFINE_PROP_END_OF_LIST(),
 568 };
 569 static void xilinx_spips_class_init(ObjectClass *klass, void *data)
 570 {
 571     DeviceClass *dc = DEVICE_CLASS(klass);
 572     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 573
 574     sdc->init = xilinx_spips_init;
 575     dc->reset = xilinx_spips_reset;
 576     dc->props = xilinx_spips_properties;
 577     dc->vmsd = &vmstate_xilinx_spips;
 578 }
 579
 580 static const TypeInfo xilinx_spips_info = {
 581     .name  = "xilinx,spips",
 582     .parent = TYPE_SYS_BUS_DEVICE,
 583     .instance_size  = sizeof(XilinxSPIPS),
 584     .class_init = xilinx_spips_class_init,
 585 };
 586
 587 static void xilinx_spips_register_types(void)
 588 {
 589     type_register_static(&xilinx_spips_info);
 590 }
 591
 592 type_init(xilinx_spips_register_types)