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ati-vga: Implement fallback for pixman routines
[qemu/ar7.git] / target / riscv / cpu_helper.c
blob8c28241c1839dc9bab61d86f9cee1bf01b732559
1 /*
2 * RISC-V CPU helpers for qemu.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "qemu/main-loop.h"
23 #include "cpu.h"
24 #include "internals.h"
25 #include "pmu.h"
26 #include "exec/exec-all.h"
27 #include "instmap.h"
28 #include "tcg/tcg-op.h"
29 #include "trace.h"
30 #include "semihosting/common-semi.h"
31 #include "sysemu/cpu-timers.h"
32 #include "cpu_bits.h"
33 #include "debug.h"
34 #include "tcg/oversized-guest.h"
35
36 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
37 {
38 #ifdef CONFIG_USER_ONLY
39 return 0;
40 #else
41 bool virt = env->virt_enabled;
42 int mode = env->priv;
43
44 /* All priv -> mmu_idx mapping are here */
45 if (!ifetch) {
46 uint64_t status = env->mstatus;
47
48 if (mode == PRV_M && get_field(status, MSTATUS_MPRV)) {
49 mode = get_field(env->mstatus, MSTATUS_MPP);
50 virt = get_field(env->mstatus, MSTATUS_MPV) &&
51 (mode != PRV_M);
52 if (virt) {
53 status = env->vsstatus;
54 }
55 }
56 if (mode == PRV_S && get_field(status, MSTATUS_SUM)) {
57 mode = MMUIdx_S_SUM;
58 }
59 }
60
61 return mode | (virt ? MMU_2STAGE_BIT : 0);
62 #endif
63 }
64
65 void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
66 uint64_t *cs_base, uint32_t *pflags)
67 {
68 RISCVCPU *cpu = env_archcpu(env);
69 RISCVExtStatus fs, vs;
70 uint32_t flags = 0;
71
72 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
73 *cs_base = 0;
74
75 if (cpu->cfg.ext_zve32f) {
76 /*
77 * If env->vl equals to VLMAX, we can use generic vector operation
78 * expanders (GVEC) to accerlate the vector operations.
79 * However, as LMUL could be a fractional number. The maximum
80 * vector size can be operated might be less than 8 bytes,
81 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true
82 * only when maxsz >= 8 bytes.
83 */
84 uint32_t vlmax = vext_get_vlmax(cpu, env->vtype);
85 uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW);
86 uint32_t maxsz = vlmax << sew;
87 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
88 (maxsz >= 8);
89 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
90 flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew);
91 flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
92 FIELD_EX64(env->vtype, VTYPE, VLMUL));
93 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
94 flags = FIELD_DP32(flags, TB_FLAGS, VTA,
95 FIELD_EX64(env->vtype, VTYPE, VTA));
96 flags = FIELD_DP32(flags, TB_FLAGS, VMA,
97 FIELD_EX64(env->vtype, VTYPE, VMA));
98 flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0);
99 } else {
100 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
101 }
102
103 #ifdef CONFIG_USER_ONLY
104 fs = EXT_STATUS_DIRTY;
105 vs = EXT_STATUS_DIRTY;
106 #else
107 flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv);
108
109 flags |= cpu_mmu_index(env, 0);
110 fs = get_field(env->mstatus, MSTATUS_FS);
111 vs = get_field(env->mstatus, MSTATUS_VS);
112
113 if (env->virt_enabled) {
114 flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1);
115 /*
116 * Merge DISABLED and !DIRTY states using MIN.
117 * We will set both fields when dirtying.
118 */
119 fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS));
120 vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS));
121 }
122
123 /* With Zfinx, floating point is enabled/disabled by Smstateen. */
124 if (!riscv_has_ext(env, RVF)) {
125 fs = (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE)
126 ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED;
127 }
128
129 if (cpu->cfg.debug && !icount_enabled()) {
130 flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
131 }
132 #endif
133
134 flags = FIELD_DP32(flags, TB_FLAGS, FS, fs);
135 flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
136 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
137 flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env));
138 if (env->cur_pmmask != 0) {
139 flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
140 }
141 if (env->cur_pmbase != 0) {
142 flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
143 }
144
145 *pflags = flags;
146 }
147
148 void riscv_cpu_update_mask(CPURISCVState *env)
149 {
150 target_ulong mask = 0, base = 0;
151 RISCVMXL xl = env->xl;
152 /*
153 * TODO: Current RVJ spec does not specify
154 * how the extension interacts with XLEN.
155 */
156 #ifndef CONFIG_USER_ONLY
157 int mode = cpu_address_mode(env);
158 xl = cpu_get_xl(env, mode);
159 if (riscv_has_ext(env, RVJ)) {
160 switch (mode) {
161 case PRV_M:
162 if (env->mmte & M_PM_ENABLE) {
163 mask = env->mpmmask;
164 base = env->mpmbase;
165 }
166 break;
167 case PRV_S:
168 if (env->mmte & S_PM_ENABLE) {
169 mask = env->spmmask;
170 base = env->spmbase;
171 }
172 break;
173 case PRV_U:
174 if (env->mmte & U_PM_ENABLE) {
175 mask = env->upmmask;
176 base = env->upmbase;
177 }
178 break;
179 default:
180 g_assert_not_reached();
181 }
182 }
183 #endif
184 if (xl == MXL_RV32) {
185 env->cur_pmmask = mask & UINT32_MAX;
186 env->cur_pmbase = base & UINT32_MAX;
187 } else {
188 env->cur_pmmask = mask;
189 env->cur_pmbase = base;
190 }
191 }
192
193 #ifndef CONFIG_USER_ONLY
194
195 /*
196 * The HS-mode is allowed to configure priority only for the
197 * following VS-mode local interrupts:
198 *
199 * 0 (Reserved interrupt, reads as zero)
200 * 1 Supervisor software interrupt
201 * 4 (Reserved interrupt, reads as zero)
202 * 5 Supervisor timer interrupt
203 * 8 (Reserved interrupt, reads as zero)
204 * 13 (Reserved interrupt)
205 * 14 "
206 * 15 "
207 * 16 "
208 * 17 "
209 * 18 "
210 * 19 "
211 * 20 "
212 * 21 "
213 * 22 "
214 * 23 "
215 */
216
217 static const int hviprio_index2irq[] = {
218 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 };
219 static const int hviprio_index2rdzero[] = {
220 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
221
222 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero)
223 {
224 if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) {
225 return -EINVAL;
226 }
227
228 if (out_irq) {
229 *out_irq = hviprio_index2irq[index];
230 }
231
232 if (out_rdzero) {
233 *out_rdzero = hviprio_index2rdzero[index];
234 }
235
236 return 0;
237 }
238
239 /*
240 * Default priorities of local interrupts are defined in the
241 * RISC-V Advanced Interrupt Architecture specification.
242 *
243 * ----------------------------------------------------------------
244 * Default |
245 * Priority | Major Interrupt Numbers
246 * ----------------------------------------------------------------
247 * Highest | 47, 23, 46, 45, 22, 44,
248 * | 43, 21, 42, 41, 20, 40
249 * |
250 * | 11 (0b), 3 (03), 7 (07)
251 * | 9 (09), 1 (01), 5 (05)
252 * | 12 (0c)
253 * | 10 (0a), 2 (02), 6 (06)
254 * |
255 * | 39, 19, 38, 37, 18, 36,
256 * Lowest | 35, 17, 34, 33, 16, 32
257 * ----------------------------------------------------------------
258 */
259 static const uint8_t default_iprio[64] = {
260 /* Custom interrupts 48 to 63 */
261 [63] = IPRIO_MMAXIPRIO,
262 [62] = IPRIO_MMAXIPRIO,
263 [61] = IPRIO_MMAXIPRIO,
264 [60] = IPRIO_MMAXIPRIO,
265 [59] = IPRIO_MMAXIPRIO,
266 [58] = IPRIO_MMAXIPRIO,
267 [57] = IPRIO_MMAXIPRIO,
268 [56] = IPRIO_MMAXIPRIO,
269 [55] = IPRIO_MMAXIPRIO,
270 [54] = IPRIO_MMAXIPRIO,
271 [53] = IPRIO_MMAXIPRIO,
272 [52] = IPRIO_MMAXIPRIO,
273 [51] = IPRIO_MMAXIPRIO,
274 [50] = IPRIO_MMAXIPRIO,
275 [49] = IPRIO_MMAXIPRIO,
276 [48] = IPRIO_MMAXIPRIO,
277
278 /* Custom interrupts 24 to 31 */
279 [31] = IPRIO_MMAXIPRIO,
280 [30] = IPRIO_MMAXIPRIO,
281 [29] = IPRIO_MMAXIPRIO,
282 [28] = IPRIO_MMAXIPRIO,
283 [27] = IPRIO_MMAXIPRIO,
284 [26] = IPRIO_MMAXIPRIO,
285 [25] = IPRIO_MMAXIPRIO,
286 [24] = IPRIO_MMAXIPRIO,
287
288 [47] = IPRIO_DEFAULT_UPPER,
289 [23] = IPRIO_DEFAULT_UPPER + 1,
290 [46] = IPRIO_DEFAULT_UPPER + 2,
291 [45] = IPRIO_DEFAULT_UPPER + 3,
292 [22] = IPRIO_DEFAULT_UPPER + 4,
293 [44] = IPRIO_DEFAULT_UPPER + 5,
294
295 [43] = IPRIO_DEFAULT_UPPER + 6,
296 [21] = IPRIO_DEFAULT_UPPER + 7,
297 [42] = IPRIO_DEFAULT_UPPER + 8,
298 [41] = IPRIO_DEFAULT_UPPER + 9,
299 [20] = IPRIO_DEFAULT_UPPER + 10,
300 [40] = IPRIO_DEFAULT_UPPER + 11,
301
302 [11] = IPRIO_DEFAULT_M,
303 [3] = IPRIO_DEFAULT_M + 1,
304 [7] = IPRIO_DEFAULT_M + 2,
305
306 [9] = IPRIO_DEFAULT_S,
307 [1] = IPRIO_DEFAULT_S + 1,
308 [5] = IPRIO_DEFAULT_S + 2,
309
310 [12] = IPRIO_DEFAULT_SGEXT,
311
312 [10] = IPRIO_DEFAULT_VS,
313 [2] = IPRIO_DEFAULT_VS + 1,
314 [6] = IPRIO_DEFAULT_VS + 2,
315
316 [39] = IPRIO_DEFAULT_LOWER,
317 [19] = IPRIO_DEFAULT_LOWER + 1,
318 [38] = IPRIO_DEFAULT_LOWER + 2,
319 [37] = IPRIO_DEFAULT_LOWER + 3,
320 [18] = IPRIO_DEFAULT_LOWER + 4,
321 [36] = IPRIO_DEFAULT_LOWER + 5,
322
323 [35] = IPRIO_DEFAULT_LOWER + 6,
324 [17] = IPRIO_DEFAULT_LOWER + 7,
325 [34] = IPRIO_DEFAULT_LOWER + 8,
326 [33] = IPRIO_DEFAULT_LOWER + 9,
327 [16] = IPRIO_DEFAULT_LOWER + 10,
328 [32] = IPRIO_DEFAULT_LOWER + 11,
329 };
330
331 uint8_t riscv_cpu_default_priority(int irq)
332 {
333 if (irq < 0 || irq > 63) {
334 return IPRIO_MMAXIPRIO;
335 }
336
337 return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO;
338 };
339
340 static int riscv_cpu_pending_to_irq(CPURISCVState *env,
341 int extirq, unsigned int extirq_def_prio,
342 uint64_t pending, uint8_t *iprio)
343 {
344 int irq, best_irq = RISCV_EXCP_NONE;
345 unsigned int prio, best_prio = UINT_MAX;
346
347 if (!pending) {
348 return RISCV_EXCP_NONE;
349 }
350
351 irq = ctz64(pending);
352 if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia :
353 riscv_cpu_cfg(env)->ext_ssaia)) {
354 return irq;
355 }
356
357 pending = pending >> irq;
358 while (pending) {
359 prio = iprio[irq];
360 if (!prio) {
361 if (irq == extirq) {
362 prio = extirq_def_prio;
363 } else {
364 prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ?
365 1 : IPRIO_MMAXIPRIO;
366 }
367 }
368 if ((pending & 0x1) && (prio <= best_prio)) {
369 best_irq = irq;
370 best_prio = prio;
371 }
372 irq++;
373 pending = pending >> 1;
374 }
375
376 return best_irq;
377 }
378
379 uint64_t riscv_cpu_all_pending(CPURISCVState *env)
380 {
381 uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN);
382 uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
383 uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0;
384
385 return (env->mip | vsgein | vstip) & env->mie;
386 }
387
388 int riscv_cpu_mirq_pending(CPURISCVState *env)
389 {
390 uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg &
391 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
392
393 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M,
394 irqs, env->miprio);
395 }
396
397 int riscv_cpu_sirq_pending(CPURISCVState *env)
398 {
399 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
400 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
401
402 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
403 irqs, env->siprio);
404 }
405
406 int riscv_cpu_vsirq_pending(CPURISCVState *env)
407 {
408 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
409 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
410
411 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
412 irqs >> 1, env->hviprio);
413 }
414
415 static int riscv_cpu_local_irq_pending(CPURISCVState *env)
416 {
417 int virq;
418 uint64_t irqs, pending, mie, hsie, vsie;
419
420 /* Determine interrupt enable state of all privilege modes */
421 if (env->virt_enabled) {
422 mie = 1;
423 hsie = 1;
424 vsie = (env->priv < PRV_S) ||
425 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
426 } else {
427 mie = (env->priv < PRV_M) ||
428 (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE));
429 hsie = (env->priv < PRV_S) ||
430 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
431 vsie = 0;
432 }
433
434 /* Determine all pending interrupts */
435 pending = riscv_cpu_all_pending(env);
436
437 /* Check M-mode interrupts */
438 irqs = pending & ~env->mideleg & -mie;
439 if (irqs) {
440 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M,
441 irqs, env->miprio);
442 }
443
444 /* Check HS-mode interrupts */
445 irqs = pending & env->mideleg & ~env->hideleg & -hsie;
446 if (irqs) {
447 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
448 irqs, env->siprio);
449 }
450
451 /* Check VS-mode interrupts */
452 irqs = pending & env->mideleg & env->hideleg & -vsie;
453 if (irqs) {
454 virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
455 irqs >> 1, env->hviprio);
456 return (virq <= 0) ? virq : virq + 1;
457 }
458
459 /* Indicate no pending interrupt */
460 return RISCV_EXCP_NONE;
461 }
462
463 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
464 {
465 if (interrupt_request & CPU_INTERRUPT_HARD) {
466 RISCVCPU *cpu = RISCV_CPU(cs);
467 CPURISCVState *env = &cpu->env;
468 int interruptno = riscv_cpu_local_irq_pending(env);
469 if (interruptno >= 0) {
470 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno;
471 riscv_cpu_do_interrupt(cs);
472 return true;
473 }
474 }
475 return false;
476 }
477
478 /* Return true is floating point support is currently enabled */
479 bool riscv_cpu_fp_enabled(CPURISCVState *env)
480 {
481 if (env->mstatus & MSTATUS_FS) {
482 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) {
483 return false;
484 }
485 return true;
486 }
487
488 return false;
489 }
490
491 /* Return true is vector support is currently enabled */
492 bool riscv_cpu_vector_enabled(CPURISCVState *env)
493 {
494 if (env->mstatus & MSTATUS_VS) {
495 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) {
496 return false;
497 }
498 return true;
499 }
500
501 return false;
502 }
503
504 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
505 {
506 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM |
507 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
508 MSTATUS64_UXL | MSTATUS_VS;
509
510 if (riscv_has_ext(env, RVF)) {
511 mstatus_mask |= MSTATUS_FS;
512 }
513 bool current_virt = env->virt_enabled;
514
515 g_assert(riscv_has_ext(env, RVH));
516
517 if (current_virt) {
518 /* Current V=1 and we are about to change to V=0 */
519 env->vsstatus = env->mstatus & mstatus_mask;
520 env->mstatus &= ~mstatus_mask;
521 env->mstatus |= env->mstatus_hs;
522
523 env->vstvec = env->stvec;
524 env->stvec = env->stvec_hs;
525
526 env->vsscratch = env->sscratch;
527 env->sscratch = env->sscratch_hs;
528
529 env->vsepc = env->sepc;
530 env->sepc = env->sepc_hs;
531
532 env->vscause = env->scause;
533 env->scause = env->scause_hs;
534
535 env->vstval = env->stval;
536 env->stval = env->stval_hs;
537
538 env->vsatp = env->satp;
539 env->satp = env->satp_hs;
540 } else {
541 /* Current V=0 and we are about to change to V=1 */
542 env->mstatus_hs = env->mstatus & mstatus_mask;
543 env->mstatus &= ~mstatus_mask;
544 env->mstatus |= env->vsstatus;
545
546 env->stvec_hs = env->stvec;
547 env->stvec = env->vstvec;
548
549 env->sscratch_hs = env->sscratch;
550 env->sscratch = env->vsscratch;
551
552 env->sepc_hs = env->sepc;
553 env->sepc = env->vsepc;
554
555 env->scause_hs = env->scause;
556 env->scause = env->vscause;
557
558 env->stval_hs = env->stval;
559 env->stval = env->vstval;
560
561 env->satp_hs = env->satp;
562 env->satp = env->vsatp;
563 }
564 }
565
566 target_ulong riscv_cpu_get_geilen(CPURISCVState *env)
567 {
568 if (!riscv_has_ext(env, RVH)) {
569 return 0;
570 }
571
572 return env->geilen;
573 }
574
575 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen)
576 {
577 if (!riscv_has_ext(env, RVH)) {
578 return;
579 }
580
581 if (geilen > (TARGET_LONG_BITS - 1)) {
582 return;
583 }
584
585 env->geilen = geilen;
586 }
587
588 /* This function can only be called to set virt when RVH is enabled */
589 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
590 {
591 /* Flush the TLB on all virt mode changes. */
592 if (env->virt_enabled != enable) {
593 tlb_flush(env_cpu(env));
594 }
595
596 env->virt_enabled = enable;
597
598 if (enable) {
599 /*
600 * The guest external interrupts from an interrupt controller are
601 * delivered only when the Guest/VM is running (i.e. V=1). This means
602 * any guest external interrupt which is triggered while the Guest/VM
603 * is not running (i.e. V=0) will be missed on QEMU resulting in guest
604 * with sluggish response to serial console input and other I/O events.
605 *
606 * To solve this, we check and inject interrupt after setting V=1.
607 */
608 riscv_cpu_update_mip(env, 0, 0);
609 }
610 }
611
612 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
613 {
614 CPURISCVState *env = &cpu->env;
615 if (env->miclaim & interrupts) {
616 return -1;
617 } else {
618 env->miclaim |= interrupts;
619 return 0;
620 }
621 }
622
623 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
624 uint64_t value)
625 {
626 CPUState *cs = env_cpu(env);
627 uint64_t gein, vsgein = 0, vstip = 0, old = env->mip;
628
629 if (env->virt_enabled) {
630 gein = get_field(env->hstatus, HSTATUS_VGEIN);
631 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
632 }
633
634 vstip = env->vstime_irq ? MIP_VSTIP : 0;
635
636 QEMU_IOTHREAD_LOCK_GUARD();
637
638 env->mip = (env->mip & ~mask) | (value & mask);
639
640 if (env->mip | vsgein | vstip) {
641 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
642 } else {
643 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
644 }
645
646 return old;
647 }
648
649 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
650 void *arg)
651 {
652 env->rdtime_fn = fn;
653 env->rdtime_fn_arg = arg;
654 }
655
656 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
657 int (*rmw_fn)(void *arg,
658 target_ulong reg,
659 target_ulong *val,
660 target_ulong new_val,
661 target_ulong write_mask),
662 void *rmw_fn_arg)
663 {
664 if (priv <= PRV_M) {
665 env->aia_ireg_rmw_fn[priv] = rmw_fn;
666 env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg;
667 }
668 }
669
670 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
671 {
672 g_assert(newpriv <= PRV_M && newpriv != PRV_RESERVED);
673
674 if (icount_enabled() && newpriv != env->priv) {
675 riscv_itrigger_update_priv(env);
676 }
677 /* tlb_flush is unnecessary as mode is contained in mmu_idx */
678 env->priv = newpriv;
679 env->xl = cpu_recompute_xl(env);
680 riscv_cpu_update_mask(env);
681
682 /*
683 * Clear the load reservation - otherwise a reservation placed in one
684 * context/process can be used by another, resulting in an SC succeeding
685 * incorrectly. Version 2.2 of the ISA specification explicitly requires
686 * this behaviour, while later revisions say that the kernel "should" use
687 * an SC instruction to force the yielding of a load reservation on a
688 * preemptive context switch. As a result, do both.
689 */
690 env->load_res = -1;
691 }
692
693 /*
694 * get_physical_address_pmp - check PMP permission for this physical address
695 *
696 * Match the PMP region and check permission for this physical address and it's
697 * TLB page. Returns 0 if the permission checking was successful
698 *
699 * @env: CPURISCVState
700 * @prot: The returned protection attributes
701 * @addr: The physical address to be checked permission
702 * @access_type: The type of MMU access
703 * @mode: Indicates current privilege level.
704 */
705 static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr addr,
706 int size, MMUAccessType access_type,
707 int mode)
708 {
709 pmp_priv_t pmp_priv;
710 bool pmp_has_privs;
711
712 if (!riscv_cpu_cfg(env)->pmp) {
713 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
714 return TRANSLATE_SUCCESS;
715 }
716
717 pmp_has_privs = pmp_hart_has_privs(env, addr, size, 1 << access_type,
718 &pmp_priv, mode);
719 if (!pmp_has_privs) {
720 *prot = 0;
721 return TRANSLATE_PMP_FAIL;
722 }
723
724 *prot = pmp_priv_to_page_prot(pmp_priv);
725
726 return TRANSLATE_SUCCESS;
727 }
728
729 /*
730 * get_physical_address - get the physical address for this virtual address
731 *
732 * Do a page table walk to obtain the physical address corresponding to a
733 * virtual address. Returns 0 if the translation was successful
734 *
735 * Adapted from Spike's mmu_t::translate and mmu_t::walk
736 *
737 * @env: CPURISCVState
738 * @physical: This will be set to the calculated physical address
739 * @prot: The returned protection attributes
740 * @addr: The virtual address or guest physical address to be translated
741 * @fault_pte_addr: If not NULL, this will be set to fault pte address
742 * when a error occurs on pte address translation.
743 * This will already be shifted to match htval.
744 * @access_type: The type of MMU access
745 * @mmu_idx: Indicates current privilege level
746 * @first_stage: Are we in first stage translation?
747 * Second stage is used for hypervisor guest translation
748 * @two_stage: Are we going to perform two stage translation
749 * @is_debug: Is this access from a debugger or the monitor?
750 */
751 static int get_physical_address(CPURISCVState *env, hwaddr *physical,
752 int *ret_prot, vaddr addr,
753 target_ulong *fault_pte_addr,
754 int access_type, int mmu_idx,
755 bool first_stage, bool two_stage,
756 bool is_debug)
757 {
758 /*
759 * NOTE: the env->pc value visible here will not be
760 * correct, but the value visible to the exception handler
761 * (riscv_cpu_do_interrupt) is correct
762 */
763 MemTxResult res;
764 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
765 int mode = mmuidx_priv(mmu_idx);
766 bool use_background = false;
767 hwaddr ppn;
768 int napot_bits = 0;
769 target_ulong napot_mask;
770
771 /*
772 * Check if we should use the background registers for the two
773 * stage translation. We don't need to check if we actually need
774 * two stage translation as that happened before this function
775 * was called. Background registers will be used if the guest has
776 * forced a two stage translation to be on (in HS or M mode).
777 */
778 if (!env->virt_enabled && two_stage) {
779 use_background = true;
780 }
781
782 if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) {
783 *physical = addr;
784 *ret_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
785 return TRANSLATE_SUCCESS;
786 }
787
788 *ret_prot = 0;
789
790 hwaddr base;
791 int levels, ptidxbits, ptesize, vm, widened;
792
793 if (first_stage == true) {
794 if (use_background) {
795 if (riscv_cpu_mxl(env) == MXL_RV32) {
796 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
797 vm = get_field(env->vsatp, SATP32_MODE);
798 } else {
799 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT;
800 vm = get_field(env->vsatp, SATP64_MODE);
801 }
802 } else {
803 if (riscv_cpu_mxl(env) == MXL_RV32) {
804 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
805 vm = get_field(env->satp, SATP32_MODE);
806 } else {
807 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
808 vm = get_field(env->satp, SATP64_MODE);
809 }
810 }
811 widened = 0;
812 } else {
813 if (riscv_cpu_mxl(env) == MXL_RV32) {
814 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
815 vm = get_field(env->hgatp, SATP32_MODE);
816 } else {
817 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT;
818 vm = get_field(env->hgatp, SATP64_MODE);
819 }
820 widened = 2;
821 }
822
823 switch (vm) {
824 case VM_1_10_SV32:
825 levels = 2; ptidxbits = 10; ptesize = 4; break;
826 case VM_1_10_SV39:
827 levels = 3; ptidxbits = 9; ptesize = 8; break;
828 case VM_1_10_SV48:
829 levels = 4; ptidxbits = 9; ptesize = 8; break;
830 case VM_1_10_SV57:
831 levels = 5; ptidxbits = 9; ptesize = 8; break;
832 case VM_1_10_MBARE:
833 *physical = addr;
834 *ret_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
835 return TRANSLATE_SUCCESS;
836 default:
837 g_assert_not_reached();
838 }
839
840 CPUState *cs = env_cpu(env);
841 int va_bits = PGSHIFT + levels * ptidxbits + widened;
842
843 if (first_stage == true) {
844 target_ulong mask, masked_msbs;
845
846 if (TARGET_LONG_BITS > (va_bits - 1)) {
847 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
848 } else {
849 mask = 0;
850 }
851 masked_msbs = (addr >> (va_bits - 1)) & mask;
852
853 if (masked_msbs != 0 && masked_msbs != mask) {
854 return TRANSLATE_FAIL;
855 }
856 } else {
857 if (vm != VM_1_10_SV32 && addr >> va_bits != 0) {
858 return TRANSLATE_FAIL;
859 }
860 }
861
862 bool pbmte = env->menvcfg & MENVCFG_PBMTE;
863 bool adue = env->menvcfg & MENVCFG_ADUE;
864
865 if (first_stage && two_stage && env->virt_enabled) {
866 pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
867 adue = adue && (env->henvcfg & HENVCFG_ADUE);
868 }
869
870 int ptshift = (levels - 1) * ptidxbits;
871 target_ulong pte;
872 hwaddr pte_addr;
873 int i;
874
875 #if !TCG_OVERSIZED_GUEST
876 restart:
877 #endif
878 for (i = 0; i < levels; i++, ptshift -= ptidxbits) {
879 target_ulong idx;
880 if (i == 0) {
881 idx = (addr >> (PGSHIFT + ptshift)) &
882 ((1 << (ptidxbits + widened)) - 1);
883 } else {
884 idx = (addr >> (PGSHIFT + ptshift)) &
885 ((1 << ptidxbits) - 1);
886 }
887
888 /* check that physical address of PTE is legal */
889
890 if (two_stage && first_stage) {
891 int vbase_prot;
892 hwaddr vbase;
893
894 /* Do the second stage translation on the base PTE address. */
895 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
896 base, NULL, MMU_DATA_LOAD,
897 MMUIdx_U, false, true,
898 is_debug);
899
900 if (vbase_ret != TRANSLATE_SUCCESS) {
901 if (fault_pte_addr) {
902 *fault_pte_addr = (base + idx * ptesize) >> 2;
903 }
904 return TRANSLATE_G_STAGE_FAIL;
905 }
906
907 pte_addr = vbase + idx * ptesize;
908 } else {
909 pte_addr = base + idx * ptesize;
910 }
911
912 int pmp_prot;
913 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, pte_addr,
914 sizeof(target_ulong),
915 MMU_DATA_LOAD, PRV_S);
916 if (pmp_ret != TRANSLATE_SUCCESS) {
917 return TRANSLATE_PMP_FAIL;
918 }
919
920 if (riscv_cpu_mxl(env) == MXL_RV32) {
921 pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
922 } else {
923 pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
924 }
925
926 if (res != MEMTX_OK) {
927 return TRANSLATE_FAIL;
928 }
929
930 if (riscv_cpu_sxl(env) == MXL_RV32) {
931 ppn = pte >> PTE_PPN_SHIFT;
932 } else {
933 if (pte & PTE_RESERVED) {
934 return TRANSLATE_FAIL;
935 }
936
937 if (!pbmte && (pte & PTE_PBMT)) {
938 return TRANSLATE_FAIL;
939 }
940
941 if (!riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
942 return TRANSLATE_FAIL;
943 }
944
945 ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
946 }
947
948 if (!(pte & PTE_V)) {
949 /* Invalid PTE */
950 return TRANSLATE_FAIL;
951 }
952 if (pte & (PTE_R | PTE_W | PTE_X)) {
953 goto leaf;
954 }
955
956 /* Inner PTE, continue walking */
957 if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
958 return TRANSLATE_FAIL;
959 }
960 base = ppn << PGSHIFT;
961 }
962
963 /* No leaf pte at any translation level. */
964 return TRANSLATE_FAIL;
965
966 leaf:
967 if (ppn & ((1ULL << ptshift) - 1)) {
968 /* Misaligned PPN */
969 return TRANSLATE_FAIL;
970 }
971 if (!pbmte && (pte & PTE_PBMT)) {
972 /* Reserved without Svpbmt. */
973 return TRANSLATE_FAIL;
974 }
975
976 /* Check for reserved combinations of RWX flags. */
977 switch (pte & (PTE_R | PTE_W | PTE_X)) {
978 case PTE_W:
979 case PTE_W | PTE_X:
980 return TRANSLATE_FAIL;
981 }
982
983 int prot = 0;
984 if (pte & PTE_R) {
985 prot |= PAGE_READ;
986 }
987 if (pte & PTE_W) {
988 prot |= PAGE_WRITE;
989 }
990 if (pte & PTE_X) {
991 bool mxr;
992
993 if (first_stage == true) {
994 mxr = get_field(env->mstatus, MSTATUS_MXR);
995 } else {
996 mxr = get_field(env->vsstatus, MSTATUS_MXR);
997 }
998 if (mxr) {
999 prot |= PAGE_READ;
1000 }
1001 prot |= PAGE_EXEC;
1002 }
1003
1004 if (pte & PTE_U) {
1005 if (mode != PRV_U) {
1006 if (!mmuidx_sum(mmu_idx)) {
1007 return TRANSLATE_FAIL;
1008 }
1009 /* SUM allows only read+write, not execute. */
1010 prot &= PAGE_READ | PAGE_WRITE;
1011 }
1012 } else if (mode != PRV_S) {
1013 /* Supervisor PTE flags when not S mode */
1014 return TRANSLATE_FAIL;
1015 }
1016
1017 if (!((prot >> access_type) & 1)) {
1018 /* Access check failed */
1019 return TRANSLATE_FAIL;
1020 }
1021
1022 /* If necessary, set accessed and dirty bits. */
1023 target_ulong updated_pte = pte | PTE_A |
1024 (access_type == MMU_DATA_STORE ? PTE_D : 0);
1025
1026 /* Page table updates need to be atomic with MTTCG enabled */
1027 if (updated_pte != pte && !is_debug) {
1028 if (!adue) {
1029 return TRANSLATE_FAIL;
1030 }
1031
1032 /*
1033 * - if accessed or dirty bits need updating, and the PTE is
1034 * in RAM, then we do so atomically with a compare and swap.
1035 * - if the PTE is in IO space or ROM, then it can't be updated
1036 * and we return TRANSLATE_FAIL.
1037 * - if the PTE changed by the time we went to update it, then
1038 * it is no longer valid and we must re-walk the page table.
1039 */
1040 MemoryRegion *mr;
1041 hwaddr l = sizeof(target_ulong), addr1;
1042 mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
1043 false, MEMTXATTRS_UNSPECIFIED);
1044 if (memory_region_is_ram(mr)) {
1045 target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1);
1046 #if TCG_OVERSIZED_GUEST
1047 /*
1048 * MTTCG is not enabled on oversized TCG guests so
1049 * page table updates do not need to be atomic
1050 */
1051 *pte_pa = pte = updated_pte;
1052 #else
1053 target_ulong old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte);
1054 if (old_pte != pte) {
1055 goto restart;
1056 }
1057 pte = updated_pte;
1058 #endif
1059 } else {
1060 /*
1061 * Misconfigured PTE in ROM (AD bits are not preset) or
1062 * PTE is in IO space and can't be updated atomically.
1063 */
1064 return TRANSLATE_FAIL;
1065 }
1066 }
1067
1068 /* For superpage mappings, make a fake leaf PTE for the TLB's benefit. */
1069 target_ulong vpn = addr >> PGSHIFT;
1070
1071 if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
1072 napot_bits = ctzl(ppn) + 1;
1073 if ((i != (levels - 1)) || (napot_bits != 4)) {
1074 return TRANSLATE_FAIL;
1075 }
1076 }
1077
1078 napot_mask = (1 << napot_bits) - 1;
1079 *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) |
1080 (vpn & (((target_ulong)1 << ptshift) - 1))
1081 ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
1082
1083 /*
1084 * Remove write permission unless this is a store, or the page is
1085 * already dirty, so that we TLB miss on later writes to update
1086 * the dirty bit.
1087 */
1088 if (access_type != MMU_DATA_STORE && !(pte & PTE_D)) {
1089 prot &= ~PAGE_WRITE;
1090 }
1091 *ret_prot = prot;
1092
1093 return TRANSLATE_SUCCESS;
1094 }
1095
1096 static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
1097 MMUAccessType access_type, bool pmp_violation,
1098 bool first_stage, bool two_stage,
1099 bool two_stage_indirect)
1100 {
1101 CPUState *cs = env_cpu(env);
1102 int page_fault_exceptions, vm;
1103 uint64_t stap_mode;
1104
1105 if (riscv_cpu_mxl(env) == MXL_RV32) {
1106 stap_mode = SATP32_MODE;
1107 } else {
1108 stap_mode = SATP64_MODE;
1109 }
1110
1111 if (first_stage) {
1112 vm = get_field(env->satp, stap_mode);
1113 } else {
1114 vm = get_field(env->hgatp, stap_mode);
1115 }
1116
1117 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
1118
1119 switch (access_type) {
1120 case MMU_INST_FETCH:
1121 if (env->virt_enabled && !first_stage) {
1122 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
1123 } else {
1124 cs->exception_index = page_fault_exceptions ?
1125 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT;
1126 }
1127 break;
1128 case MMU_DATA_LOAD:
1129 if (two_stage && !first_stage) {
1130 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
1131 } else {
1132 cs->exception_index = page_fault_exceptions ?
1133 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT;
1134 }
1135 break;
1136 case MMU_DATA_STORE:
1137 if (two_stage && !first_stage) {
1138 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
1139 } else {
1140 cs->exception_index = page_fault_exceptions ?
1141 RISCV_EXCP_STORE_PAGE_FAULT :
1142 RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
1143 }
1144 break;
1145 default:
1146 g_assert_not_reached();
1147 }
1148 env->badaddr = address;
1149 env->two_stage_lookup = two_stage;
1150 env->two_stage_indirect_lookup = two_stage_indirect;
1151 }
1152
1153 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
1154 {
1155 RISCVCPU *cpu = RISCV_CPU(cs);
1156 CPURISCVState *env = &cpu->env;
1157 hwaddr phys_addr;
1158 int prot;
1159 int mmu_idx = cpu_mmu_index(&cpu->env, false);
1160
1161 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx,
1162 true, env->virt_enabled, true)) {
1163 return -1;
1164 }
1165
1166 if (env->virt_enabled) {
1167 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,
1168 0, mmu_idx, false, true, true)) {
1169 return -1;
1170 }
1171 }
1172
1173 return phys_addr & TARGET_PAGE_MASK;
1174 }
1175
1176 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
1177 vaddr addr, unsigned size,
1178 MMUAccessType access_type,
1179 int mmu_idx, MemTxAttrs attrs,
1180 MemTxResult response, uintptr_t retaddr)
1181 {
1182 RISCVCPU *cpu = RISCV_CPU(cs);
1183 CPURISCVState *env = &cpu->env;
1184
1185 if (access_type == MMU_DATA_STORE) {
1186 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
1187 } else if (access_type == MMU_DATA_LOAD) {
1188 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
1189 } else {
1190 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
1191 }
1192
1193 env->badaddr = addr;
1194 env->two_stage_lookup = mmuidx_2stage(mmu_idx);
1195 env->two_stage_indirect_lookup = false;
1196 cpu_loop_exit_restore(cs, retaddr);
1197 }
1198
1199 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
1200 MMUAccessType access_type, int mmu_idx,
1201 uintptr_t retaddr)
1202 {
1203 RISCVCPU *cpu = RISCV_CPU(cs);
1204 CPURISCVState *env = &cpu->env;
1205 switch (access_type) {
1206 case MMU_INST_FETCH:
1207 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS;
1208 break;
1209 case MMU_DATA_LOAD:
1210 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS;
1211 break;
1212 case MMU_DATA_STORE:
1213 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS;
1214 break;
1215 default:
1216 g_assert_not_reached();
1217 }
1218 env->badaddr = addr;
1219 env->two_stage_lookup = mmuidx_2stage(mmu_idx);
1220 env->two_stage_indirect_lookup = false;
1221 cpu_loop_exit_restore(cs, retaddr);
1222 }
1223
1224
1225 static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type)
1226 {
1227 enum riscv_pmu_event_idx pmu_event_type;
1228
1229 switch (access_type) {
1230 case MMU_INST_FETCH:
1231 pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS;
1232 break;
1233 case MMU_DATA_LOAD:
1234 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS;
1235 break;
1236 case MMU_DATA_STORE:
1237 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS;
1238 break;
1239 default:
1240 return;
1241 }
1242
1243 riscv_pmu_incr_ctr(cpu, pmu_event_type);
1244 }
1245
1246 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
1247 MMUAccessType access_type, int mmu_idx,
1248 bool probe, uintptr_t retaddr)
1249 {
1250 RISCVCPU *cpu = RISCV_CPU(cs);
1251 CPURISCVState *env = &cpu->env;
1252 vaddr im_address;
1253 hwaddr pa = 0;
1254 int prot, prot2, prot_pmp;
1255 bool pmp_violation = false;
1256 bool first_stage_error = true;
1257 bool two_stage_lookup = mmuidx_2stage(mmu_idx);
1258 bool two_stage_indirect_error = false;
1259 int ret = TRANSLATE_FAIL;
1260 int mode = mmu_idx;
1261 /* default TLB page size */
1262 target_ulong tlb_size = TARGET_PAGE_SIZE;
1263
1264 env->guest_phys_fault_addr = 0;
1265
1266 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
1267 __func__, address, access_type, mmu_idx);
1268
1269 pmu_tlb_fill_incr_ctr(cpu, access_type);
1270 if (two_stage_lookup) {
1271 /* Two stage lookup */
1272 ret = get_physical_address(env, &pa, &prot, address,
1273 &env->guest_phys_fault_addr, access_type,
1274 mmu_idx, true, true, false);
1275
1276 /*
1277 * A G-stage exception may be triggered during two state lookup.
1278 * And the env->guest_phys_fault_addr has already been set in
1279 * get_physical_address().
1280 */
1281 if (ret == TRANSLATE_G_STAGE_FAIL) {
1282 first_stage_error = false;
1283 two_stage_indirect_error = true;
1284 }
1285
1286 qemu_log_mask(CPU_LOG_MMU,
1287 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical "
1288 HWADDR_FMT_plx " prot %d\n",
1289 __func__, address, ret, pa, prot);
1290
1291 if (ret == TRANSLATE_SUCCESS) {
1292 /* Second stage lookup */
1293 im_address = pa;
1294
1295 ret = get_physical_address(env, &pa, &prot2, im_address, NULL,
1296 access_type, MMUIdx_U, false, true,
1297 false);
1298
1299 qemu_log_mask(CPU_LOG_MMU,
1300 "%s 2nd-stage address=%" VADDR_PRIx
1301 " ret %d physical "
1302 HWADDR_FMT_plx " prot %d\n",
1303 __func__, im_address, ret, pa, prot2);
1304
1305 prot &= prot2;
1306
1307 if (ret == TRANSLATE_SUCCESS) {
1308 ret = get_physical_address_pmp(env, &prot_pmp, pa,
1309 size, access_type, mode);
1310 tlb_size = pmp_get_tlb_size(env, pa);
1311
1312 qemu_log_mask(CPU_LOG_MMU,
1313 "%s PMP address=" HWADDR_FMT_plx " ret %d prot"
1314 " %d tlb_size " TARGET_FMT_lu "\n",
1315 __func__, pa, ret, prot_pmp, tlb_size);
1316
1317 prot &= prot_pmp;
1318 }
1319
1320 if (ret != TRANSLATE_SUCCESS) {
1321 /*
1322 * Guest physical address translation failed, this is a HS
1323 * level exception
1324 */
1325 first_stage_error = false;
1326 env->guest_phys_fault_addr = (im_address |
1327 (address &
1328 (TARGET_PAGE_SIZE - 1))) >> 2;
1329 }
1330 }
1331 } else {
1332 /* Single stage lookup */
1333 ret = get_physical_address(env, &pa, &prot, address, NULL,
1334 access_type, mmu_idx, true, false, false);
1335
1336 qemu_log_mask(CPU_LOG_MMU,
1337 "%s address=%" VADDR_PRIx " ret %d physical "
1338 HWADDR_FMT_plx " prot %d\n",
1339 __func__, address, ret, pa, prot);
1340
1341 if (ret == TRANSLATE_SUCCESS) {
1342 ret = get_physical_address_pmp(env, &prot_pmp, pa,
1343 size, access_type, mode);
1344 tlb_size = pmp_get_tlb_size(env, pa);
1345
1346 qemu_log_mask(CPU_LOG_MMU,
1347 "%s PMP address=" HWADDR_FMT_plx " ret %d prot"
1348 " %d tlb_size " TARGET_FMT_lu "\n",
1349 __func__, pa, ret, prot_pmp, tlb_size);
1350
1351 prot &= prot_pmp;
1352 }
1353 }
1354
1355 if (ret == TRANSLATE_PMP_FAIL) {
1356 pmp_violation = true;
1357 }
1358
1359 if (ret == TRANSLATE_SUCCESS) {
1360 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
1361 prot, mmu_idx, tlb_size);
1362 return true;
1363 } else if (probe) {
1364 return false;
1365 } else {
1366 raise_mmu_exception(env, address, access_type, pmp_violation,
1367 first_stage_error, two_stage_lookup,
1368 two_stage_indirect_error);
1369 cpu_loop_exit_restore(cs, retaddr);
1370 }
1371
1372 return true;
1373 }
1374
1375 static target_ulong riscv_transformed_insn(CPURISCVState *env,
1376 target_ulong insn,
1377 target_ulong taddr)
1378 {
1379 target_ulong xinsn = 0;
1380 target_ulong access_rs1 = 0, access_imm = 0, access_size = 0;
1381
1382 /*
1383 * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to
1384 * be uncompressed. The Quadrant 1 of RVC instruction space need
1385 * not be transformed because these instructions won't generate
1386 * any load/store trap.
1387 */
1388
1389 if ((insn & 0x3) != 0x3) {
1390 /* Transform 16bit instruction into 32bit instruction */
1391 switch (GET_C_OP(insn)) {
1392 case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */
1393 switch (GET_C_FUNC(insn)) {
1394 case OPC_RISC_C_FUNC_FLD_LQ:
1395 if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */
1396 xinsn = OPC_RISC_FLD;
1397 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1398 access_rs1 = GET_C_RS1S(insn);
1399 access_imm = GET_C_LD_IMM(insn);
1400 access_size = 8;
1401 }
1402 break;
1403 case OPC_RISC_C_FUNC_LW: /* C.LW */
1404 xinsn = OPC_RISC_LW;
1405 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1406 access_rs1 = GET_C_RS1S(insn);
1407 access_imm = GET_C_LW_IMM(insn);
1408 access_size = 4;
1409 break;
1410 case OPC_RISC_C_FUNC_FLW_LD:
1411 if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */
1412 xinsn = OPC_RISC_FLW;
1413 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1414 access_rs1 = GET_C_RS1S(insn);
1415 access_imm = GET_C_LW_IMM(insn);
1416 access_size = 4;
1417 } else { /* C.LD (RV64/RV128) */
1418 xinsn = OPC_RISC_LD;
1419 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1420 access_rs1 = GET_C_RS1S(insn);
1421 access_imm = GET_C_LD_IMM(insn);
1422 access_size = 8;
1423 }
1424 break;
1425 case OPC_RISC_C_FUNC_FSD_SQ:
1426 if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */
1427 xinsn = OPC_RISC_FSD;
1428 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1429 access_rs1 = GET_C_RS1S(insn);
1430 access_imm = GET_C_SD_IMM(insn);
1431 access_size = 8;
1432 }
1433 break;
1434 case OPC_RISC_C_FUNC_SW: /* C.SW */
1435 xinsn = OPC_RISC_SW;
1436 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1437 access_rs1 = GET_C_RS1S(insn);
1438 access_imm = GET_C_SW_IMM(insn);
1439 access_size = 4;
1440 break;
1441 case OPC_RISC_C_FUNC_FSW_SD:
1442 if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */
1443 xinsn = OPC_RISC_FSW;
1444 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1445 access_rs1 = GET_C_RS1S(insn);
1446 access_imm = GET_C_SW_IMM(insn);
1447 access_size = 4;
1448 } else { /* C.SD (RV64/RV128) */
1449 xinsn = OPC_RISC_SD;
1450 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1451 access_rs1 = GET_C_RS1S(insn);
1452 access_imm = GET_C_SD_IMM(insn);
1453 access_size = 8;
1454 }
1455 break;
1456 default:
1457 break;
1458 }
1459 break;
1460 case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */
1461 switch (GET_C_FUNC(insn)) {
1462 case OPC_RISC_C_FUNC_FLDSP_LQSP:
1463 if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */
1464 xinsn = OPC_RISC_FLD;
1465 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1466 access_rs1 = 2;
1467 access_imm = GET_C_LDSP_IMM(insn);
1468 access_size = 8;
1469 }
1470 break;
1471 case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */
1472 xinsn = OPC_RISC_LW;
1473 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1474 access_rs1 = 2;
1475 access_imm = GET_C_LWSP_IMM(insn);
1476 access_size = 4;
1477 break;
1478 case OPC_RISC_C_FUNC_FLWSP_LDSP:
1479 if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */
1480 xinsn = OPC_RISC_FLW;
1481 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1482 access_rs1 = 2;
1483 access_imm = GET_C_LWSP_IMM(insn);
1484 access_size = 4;
1485 } else { /* C.LDSP (RV64/RV128) */
1486 xinsn = OPC_RISC_LD;
1487 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1488 access_rs1 = 2;
1489 access_imm = GET_C_LDSP_IMM(insn);
1490 access_size = 8;
1491 }
1492 break;
1493 case OPC_RISC_C_FUNC_FSDSP_SQSP:
1494 if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */
1495 xinsn = OPC_RISC_FSD;
1496 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1497 access_rs1 = 2;
1498 access_imm = GET_C_SDSP_IMM(insn);
1499 access_size = 8;
1500 }
1501 break;
1502 case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */
1503 xinsn = OPC_RISC_SW;
1504 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1505 access_rs1 = 2;
1506 access_imm = GET_C_SWSP_IMM(insn);
1507 access_size = 4;
1508 break;
1509 case 7:
1510 if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */
1511 xinsn = OPC_RISC_FSW;
1512 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1513 access_rs1 = 2;
1514 access_imm = GET_C_SWSP_IMM(insn);
1515 access_size = 4;
1516 } else { /* C.SDSP (RV64/RV128) */
1517 xinsn = OPC_RISC_SD;
1518 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1519 access_rs1 = 2;
1520 access_imm = GET_C_SDSP_IMM(insn);
1521 access_size = 8;
1522 }
1523 break;
1524 default:
1525 break;
1526 }
1527 break;
1528 default:
1529 break;
1530 }
1531
1532 /*
1533 * Clear Bit1 of transformed instruction to indicate that
1534 * original insruction was a 16bit instruction
1535 */
1536 xinsn &= ~((target_ulong)0x2);
1537 } else {
1538 /* Transform 32bit (or wider) instructions */
1539 switch (MASK_OP_MAJOR(insn)) {
1540 case OPC_RISC_ATOMIC:
1541 xinsn = insn;
1542 access_rs1 = GET_RS1(insn);
1543 access_size = 1 << GET_FUNCT3(insn);
1544 break;
1545 case OPC_RISC_LOAD:
1546 case OPC_RISC_FP_LOAD:
1547 xinsn = SET_I_IMM(insn, 0);
1548 access_rs1 = GET_RS1(insn);
1549 access_imm = GET_IMM(insn);
1550 access_size = 1 << GET_FUNCT3(insn);
1551 break;
1552 case OPC_RISC_STORE:
1553 case OPC_RISC_FP_STORE:
1554 xinsn = SET_S_IMM(insn, 0);
1555 access_rs1 = GET_RS1(insn);
1556 access_imm = GET_STORE_IMM(insn);
1557 access_size = 1 << GET_FUNCT3(insn);
1558 break;
1559 case OPC_RISC_SYSTEM:
1560 if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) {
1561 xinsn = insn;
1562 access_rs1 = GET_RS1(insn);
1563 access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3);
1564 access_size = 1 << access_size;
1565 }
1566 break;
1567 default:
1568 break;
1569 }
1570 }
1571
1572 if (access_size) {
1573 xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) &
1574 (access_size - 1));
1575 }
1576
1577 return xinsn;
1578 }
1579 #endif /* !CONFIG_USER_ONLY */
1580
1581 /*
1582 * Handle Traps
1583 *
1584 * Adapted from Spike's processor_t::take_trap.
1585 *
1586 */
1587 void riscv_cpu_do_interrupt(CPUState *cs)
1588 {
1589 #if !defined(CONFIG_USER_ONLY)
1590
1591 RISCVCPU *cpu = RISCV_CPU(cs);
1592 CPURISCVState *env = &cpu->env;
1593 bool write_gva = false;
1594 uint64_t s;
1595
1596 /*
1597 * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
1598 * so we mask off the MSB and separate into trap type and cause.
1599 */
1600 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
1601 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
1602 uint64_t deleg = async ? env->mideleg : env->medeleg;
1603 target_ulong tval = 0;
1604 target_ulong tinst = 0;
1605 target_ulong htval = 0;
1606 target_ulong mtval2 = 0;
1607
1608 if (cause == RISCV_EXCP_SEMIHOST) {
1609 do_common_semihosting(cs);
1610 env->pc += 4;
1611 return;
1612 }
1613
1614 if (!async) {
1615 /* set tval to badaddr for traps with address information */
1616 switch (cause) {
1617 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
1618 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
1619 case RISCV_EXCP_LOAD_ADDR_MIS:
1620 case RISCV_EXCP_STORE_AMO_ADDR_MIS:
1621 case RISCV_EXCP_LOAD_ACCESS_FAULT:
1622 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT:
1623 case RISCV_EXCP_LOAD_PAGE_FAULT:
1624 case RISCV_EXCP_STORE_PAGE_FAULT:
1625 write_gva = env->two_stage_lookup;
1626 tval = env->badaddr;
1627 if (env->two_stage_indirect_lookup) {
1628 /*
1629 * special pseudoinstruction for G-stage fault taken while
1630 * doing VS-stage page table walk.
1631 */
1632 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000;
1633 } else {
1634 /*
1635 * The "Addr. Offset" field in transformed instruction is
1636 * non-zero only for misaligned access.
1637 */
1638 tinst = riscv_transformed_insn(env, env->bins, tval);
1639 }
1640 break;
1641 case RISCV_EXCP_INST_GUEST_PAGE_FAULT:
1642 case RISCV_EXCP_INST_ADDR_MIS:
1643 case RISCV_EXCP_INST_ACCESS_FAULT:
1644 case RISCV_EXCP_INST_PAGE_FAULT:
1645 write_gva = env->two_stage_lookup;
1646 tval = env->badaddr;
1647 if (env->two_stage_indirect_lookup) {
1648 /*
1649 * special pseudoinstruction for G-stage fault taken while
1650 * doing VS-stage page table walk.
1651 */
1652 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000;
1653 }
1654 break;
1655 case RISCV_EXCP_ILLEGAL_INST:
1656 case RISCV_EXCP_VIRT_INSTRUCTION_FAULT:
1657 tval = env->bins;
1658 break;
1659 case RISCV_EXCP_BREAKPOINT:
1660 if (cs->watchpoint_hit) {
1661 tval = cs->watchpoint_hit->hitaddr;
1662 cs->watchpoint_hit = NULL;
1663 }
1664 break;
1665 default:
1666 break;
1667 }
1668 /* ecall is dispatched as one cause so translate based on mode */
1669 if (cause == RISCV_EXCP_U_ECALL) {
1670 assert(env->priv <= 3);
1671
1672 if (env->priv == PRV_M) {
1673 cause = RISCV_EXCP_M_ECALL;
1674 } else if (env->priv == PRV_S && env->virt_enabled) {
1675 cause = RISCV_EXCP_VS_ECALL;
1676 } else if (env->priv == PRV_S && !env->virt_enabled) {
1677 cause = RISCV_EXCP_S_ECALL;
1678 } else if (env->priv == PRV_U) {
1679 cause = RISCV_EXCP_U_ECALL;
1680 }
1681 }
1682 }
1683
1684 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
1685 riscv_cpu_get_trap_name(cause, async));
1686
1687 qemu_log_mask(CPU_LOG_INT,
1688 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", "
1689 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n",
1690 __func__, env->mhartid, async, cause, env->pc, tval,
1691 riscv_cpu_get_trap_name(cause, async));
1692
1693 if (env->priv <= PRV_S &&
1694 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
1695 /* handle the trap in S-mode */
1696 if (riscv_has_ext(env, RVH)) {
1697 uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
1698
1699 if (env->virt_enabled && ((hdeleg >> cause) & 1)) {
1700 /* Trap to VS mode */
1701 /*
1702 * See if we need to adjust cause. Yes if its VS mode interrupt
1703 * no if hypervisor has delegated one of hs mode's interrupt
1704 */
1705 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
1706 cause == IRQ_VS_EXT) {
1707 cause = cause - 1;
1708 }
1709 write_gva = false;
1710 } else if (env->virt_enabled) {
1711 /* Trap into HS mode, from virt */
1712 riscv_cpu_swap_hypervisor_regs(env);
1713 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP,
1714 env->priv);
1715 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, true);
1716
1717 htval = env->guest_phys_fault_addr;
1718
1719 riscv_cpu_set_virt_enabled(env, 0);
1720 } else {
1721 /* Trap into HS mode */
1722 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
1723 htval = env->guest_phys_fault_addr;
1724 }
1725 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva);
1726 }
1727
1728 s = env->mstatus;
1729 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
1730 s = set_field(s, MSTATUS_SPP, env->priv);
1731 s = set_field(s, MSTATUS_SIE, 0);
1732 env->mstatus = s;
1733 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
1734 env->sepc = env->pc;
1735 env->stval = tval;
1736 env->htval = htval;
1737 env->htinst = tinst;
1738 env->pc = (env->stvec >> 2 << 2) +
1739 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
1740 riscv_cpu_set_mode(env, PRV_S);
1741 } else {
1742 /* handle the trap in M-mode */
1743 if (riscv_has_ext(env, RVH)) {
1744 if (env->virt_enabled) {
1745 riscv_cpu_swap_hypervisor_regs(env);
1746 }
1747 env->mstatus = set_field(env->mstatus, MSTATUS_MPV,
1748 env->virt_enabled);
1749 if (env->virt_enabled && tval) {
1750 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1);
1751 }
1752
1753 mtval2 = env->guest_phys_fault_addr;
1754
1755 /* Trapping to M mode, virt is disabled */
1756 riscv_cpu_set_virt_enabled(env, 0);
1757 }
1758
1759 s = env->mstatus;
1760 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
1761 s = set_field(s, MSTATUS_MPP, env->priv);
1762 s = set_field(s, MSTATUS_MIE, 0);
1763 env->mstatus = s;
1764 env->mcause = cause | ~(((target_ulong)-1) >> async);
1765 env->mepc = env->pc;
1766 env->mtval = tval;
1767 env->mtval2 = mtval2;
1768 env->mtinst = tinst;
1769 env->pc = (env->mtvec >> 2 << 2) +
1770 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
1771 riscv_cpu_set_mode(env, PRV_M);
1772 }
1773
1774 /*
1775 * NOTE: it is not necessary to yield load reservations here. It is only
1776 * necessary for an SC from "another hart" to cause a load reservation
1777 * to be yielded. Refer to the memory consistency model section of the
1778 * RISC-V ISA Specification.
1779 */
1780
1781 env->two_stage_lookup = false;
1782 env->two_stage_indirect_lookup = false;
1783 #endif
1784 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */
1785 }
AR7 emulation for QEMU