riscv: sifive_e: Manually define the machine
[qemu/ar7.git] / hw / misc / aspeed_sdmc.c
blob25e1e58356035cd8b304998fceb6944563be18b0
1 /*
2 * ASPEED SDRAM Memory Controller
4 * Copyright (C) 2016 IBM Corp.
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 */
10 #include "qemu/osdep.h"
11 #include "qemu/log.h"
12 #include "qemu/module.h"
13 #include "qemu/error-report.h"
14 #include "hw/misc/aspeed_sdmc.h"
15 #include "hw/misc/aspeed_scu.h"
16 #include "hw/qdev-properties.h"
17 #include "migration/vmstate.h"
18 #include "qapi/error.h"
19 #include "trace.h"
20 #include "qemu/units.h"
21 #include "qemu/cutils.h"
22 #include "qapi/visitor.h"
24 /* Protection Key Register */
25 #define R_PROT (0x00 / 4)
26 #define PROT_UNLOCKED 0x01
27 #define PROT_HARDLOCKED 0x10 /* AST2600 */
28 #define PROT_SOFTLOCKED 0x00
30 #define PROT_KEY_UNLOCK 0xFC600309
31 #define PROT_KEY_HARDLOCK 0xDEADDEAD /* AST2600 */
33 /* Configuration Register */
34 #define R_CONF (0x04 / 4)
36 /* Control/Status Register #1 (ast2500) */
37 #define R_STATUS1 (0x60 / 4)
38 #define PHY_BUSY_STATE BIT(0)
39 #define PHY_PLL_LOCK_STATUS BIT(4)
41 #define R_ECC_TEST_CTRL (0x70 / 4)
42 #define ECC_TEST_FINISHED BIT(12)
43 #define ECC_TEST_FAIL BIT(13)
46 * Configuration register Ox4 (for Aspeed AST2400 SOC)
48 * These are for the record and future use. ASPEED_SDMC_DRAM_SIZE is
49 * what we care about right now as it is checked by U-Boot to
50 * determine the RAM size.
53 #define ASPEED_SDMC_RESERVED 0xFFFFF800 /* 31:11 reserved */
54 #define ASPEED_SDMC_AST2300_COMPAT (1 << 10)
55 #define ASPEED_SDMC_SCRAMBLE_PATTERN (1 << 9)
56 #define ASPEED_SDMC_DATA_SCRAMBLE (1 << 8)
57 #define ASPEED_SDMC_ECC_ENABLE (1 << 7)
58 #define ASPEED_SDMC_VGA_COMPAT (1 << 6) /* readonly */
59 #define ASPEED_SDMC_DRAM_BANK (1 << 5)
60 #define ASPEED_SDMC_DRAM_BURST (1 << 4)
61 #define ASPEED_SDMC_VGA_APERTURE(x) ((x & 0x3) << 2) /* readonly */
62 #define ASPEED_SDMC_VGA_8MB 0x0
63 #define ASPEED_SDMC_VGA_16MB 0x1
64 #define ASPEED_SDMC_VGA_32MB 0x2
65 #define ASPEED_SDMC_VGA_64MB 0x3
66 #define ASPEED_SDMC_DRAM_SIZE(x) (x & 0x3)
67 #define ASPEED_SDMC_DRAM_64MB 0x0
68 #define ASPEED_SDMC_DRAM_128MB 0x1
69 #define ASPEED_SDMC_DRAM_256MB 0x2
70 #define ASPEED_SDMC_DRAM_512MB 0x3
72 #define ASPEED_SDMC_READONLY_MASK \
73 (ASPEED_SDMC_RESERVED | ASPEED_SDMC_VGA_COMPAT | \
74 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
76 * Configuration register Ox4 (for Aspeed AST2500 SOC and higher)
78 * Incompatibilities are annotated in the list. ASPEED_SDMC_HW_VERSION
79 * should be set to 1 for the AST2500 SOC.
81 #define ASPEED_SDMC_HW_VERSION(x) ((x & 0xf) << 28) /* readonly */
82 #define ASPEED_SDMC_SW_VERSION ((x & 0xff) << 20)
83 #define ASPEED_SDMC_CACHE_INITIAL_DONE (1 << 19) /* readonly */
84 #define ASPEED_SDMC_AST2500_RESERVED 0x7C000 /* 18:14 reserved */
85 #define ASPEED_SDMC_CACHE_DDR4_CONF (1 << 13)
86 #define ASPEED_SDMC_CACHE_INITIAL (1 << 12)
87 #define ASPEED_SDMC_CACHE_RANGE_CTRL (1 << 11)
88 #define ASPEED_SDMC_CACHE_ENABLE (1 << 10) /* differs from AST2400 */
89 #define ASPEED_SDMC_DRAM_TYPE (1 << 4) /* differs from AST2400 */
91 /* DRAM size definitions differs */
92 #define ASPEED_SDMC_AST2500_128MB 0x0
93 #define ASPEED_SDMC_AST2500_256MB 0x1
94 #define ASPEED_SDMC_AST2500_512MB 0x2
95 #define ASPEED_SDMC_AST2500_1024MB 0x3
97 #define ASPEED_SDMC_AST2600_256MB 0x0
98 #define ASPEED_SDMC_AST2600_512MB 0x1
99 #define ASPEED_SDMC_AST2600_1024MB 0x2
100 #define ASPEED_SDMC_AST2600_2048MB 0x3
102 #define ASPEED_SDMC_AST2500_READONLY_MASK \
103 (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE | \
104 ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT | \
105 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
107 static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size)
109 AspeedSDMCState *s = ASPEED_SDMC(opaque);
111 addr >>= 2;
113 if (addr >= ARRAY_SIZE(s->regs)) {
114 qemu_log_mask(LOG_GUEST_ERROR,
115 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
116 __func__, addr);
117 return 0;
120 return s->regs[addr];
123 static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
124 unsigned int size)
126 AspeedSDMCState *s = ASPEED_SDMC(opaque);
127 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
129 addr >>= 2;
131 if (addr >= ARRAY_SIZE(s->regs)) {
132 qemu_log_mask(LOG_GUEST_ERROR,
133 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
134 __func__, addr);
135 return;
138 asc->write(s, addr, data);
141 static const MemoryRegionOps aspeed_sdmc_ops = {
142 .read = aspeed_sdmc_read,
143 .write = aspeed_sdmc_write,
144 .endianness = DEVICE_LITTLE_ENDIAN,
145 .valid.min_access_size = 4,
146 .valid.max_access_size = 4,
149 static int ast2400_rambits(AspeedSDMCState *s)
151 switch (s->ram_size >> 20) {
152 case 64:
153 return ASPEED_SDMC_DRAM_64MB;
154 case 128:
155 return ASPEED_SDMC_DRAM_128MB;
156 case 256:
157 return ASPEED_SDMC_DRAM_256MB;
158 case 512:
159 return ASPEED_SDMC_DRAM_512MB;
160 default:
161 g_assert_not_reached();
162 break;
166 static int ast2500_rambits(AspeedSDMCState *s)
168 switch (s->ram_size >> 20) {
169 case 128:
170 return ASPEED_SDMC_AST2500_128MB;
171 case 256:
172 return ASPEED_SDMC_AST2500_256MB;
173 case 512:
174 return ASPEED_SDMC_AST2500_512MB;
175 case 1024:
176 return ASPEED_SDMC_AST2500_1024MB;
177 default:
178 g_assert_not_reached();
179 break;
183 static int ast2600_rambits(AspeedSDMCState *s)
185 switch (s->ram_size >> 20) {
186 case 256:
187 return ASPEED_SDMC_AST2600_256MB;
188 case 512:
189 return ASPEED_SDMC_AST2600_512MB;
190 case 1024:
191 return ASPEED_SDMC_AST2600_1024MB;
192 case 2048:
193 return ASPEED_SDMC_AST2600_2048MB;
194 default:
195 g_assert_not_reached();
196 break;
200 static void aspeed_sdmc_reset(DeviceState *dev)
202 AspeedSDMCState *s = ASPEED_SDMC(dev);
203 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
205 memset(s->regs, 0, sizeof(s->regs));
207 /* Set ram size bit and defaults values */
208 s->regs[R_CONF] = asc->compute_conf(s, 0);
211 static void aspeed_sdmc_get_ram_size(Object *obj, Visitor *v, const char *name,
212 void *opaque, Error **errp)
214 AspeedSDMCState *s = ASPEED_SDMC(obj);
215 int64_t value = s->ram_size;
217 visit_type_int(v, name, &value, errp);
220 static void aspeed_sdmc_set_ram_size(Object *obj, Visitor *v, const char *name,
221 void *opaque, Error **errp)
223 int i;
224 char *sz;
225 int64_t value;
226 Error *local_err = NULL;
227 AspeedSDMCState *s = ASPEED_SDMC(obj);
228 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
230 visit_type_int(v, name, &value, &local_err);
231 if (local_err) {
232 error_propagate(errp, local_err);
233 return;
236 for (i = 0; asc->valid_ram_sizes[i]; i++) {
237 if (value == asc->valid_ram_sizes[i]) {
238 s->ram_size = value;
239 return;
243 sz = size_to_str(value);
244 error_setg(&local_err, "Invalid RAM size %s", sz);
245 g_free(sz);
246 error_propagate(errp, local_err);
249 static void aspeed_sdmc_initfn(Object *obj)
251 object_property_add(obj, "ram-size", "int",
252 aspeed_sdmc_get_ram_size, aspeed_sdmc_set_ram_size,
253 NULL, NULL);
256 static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
258 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
259 AspeedSDMCState *s = ASPEED_SDMC(dev);
260 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
262 s->max_ram_size = asc->max_ram_size;
264 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s,
265 TYPE_ASPEED_SDMC, 0x1000);
266 sysbus_init_mmio(sbd, &s->iomem);
269 static const VMStateDescription vmstate_aspeed_sdmc = {
270 .name = "aspeed.sdmc",
271 .version_id = 1,
272 .minimum_version_id = 1,
273 .fields = (VMStateField[]) {
274 VMSTATE_UINT32_ARRAY(regs, AspeedSDMCState, ASPEED_SDMC_NR_REGS),
275 VMSTATE_END_OF_LIST()
279 static Property aspeed_sdmc_properties[] = {
280 DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0),
281 DEFINE_PROP_END_OF_LIST(),
284 static void aspeed_sdmc_class_init(ObjectClass *klass, void *data)
286 DeviceClass *dc = DEVICE_CLASS(klass);
287 dc->realize = aspeed_sdmc_realize;
288 dc->reset = aspeed_sdmc_reset;
289 dc->desc = "ASPEED SDRAM Memory Controller";
290 dc->vmsd = &vmstate_aspeed_sdmc;
291 device_class_set_props(dc, aspeed_sdmc_properties);
294 static const TypeInfo aspeed_sdmc_info = {
295 .name = TYPE_ASPEED_SDMC,
296 .parent = TYPE_SYS_BUS_DEVICE,
297 .instance_size = sizeof(AspeedSDMCState),
298 .instance_init = aspeed_sdmc_initfn,
299 .class_init = aspeed_sdmc_class_init,
300 .class_size = sizeof(AspeedSDMCClass),
301 .abstract = true,
304 static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
306 uint32_t fixed_conf = ASPEED_SDMC_VGA_COMPAT |
307 ASPEED_SDMC_DRAM_SIZE(ast2400_rambits(s));
309 /* Make sure readonly bits are kept */
310 data &= ~ASPEED_SDMC_READONLY_MASK;
312 return data | fixed_conf;
315 static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg,
316 uint32_t data)
318 if (reg == R_PROT) {
319 s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
320 return;
323 if (!s->regs[R_PROT]) {
324 qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
325 return;
328 switch (reg) {
329 case R_CONF:
330 data = aspeed_2400_sdmc_compute_conf(s, data);
331 break;
332 default:
333 break;
336 s->regs[reg] = data;
339 static const uint64_t
340 aspeed_2400_ram_sizes[] = { 64 * MiB, 128 * MiB, 256 * MiB, 512 * MiB, 0};
342 static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data)
344 DeviceClass *dc = DEVICE_CLASS(klass);
345 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
347 dc->desc = "ASPEED 2400 SDRAM Memory Controller";
348 asc->max_ram_size = 512 << 20;
349 asc->compute_conf = aspeed_2400_sdmc_compute_conf;
350 asc->write = aspeed_2400_sdmc_write;
351 asc->valid_ram_sizes = aspeed_2400_ram_sizes;
354 static const TypeInfo aspeed_2400_sdmc_info = {
355 .name = TYPE_ASPEED_2400_SDMC,
356 .parent = TYPE_ASPEED_SDMC,
357 .class_init = aspeed_2400_sdmc_class_init,
360 static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
362 uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(1) |
363 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
364 ASPEED_SDMC_CACHE_INITIAL_DONE |
365 ASPEED_SDMC_DRAM_SIZE(ast2500_rambits(s));
367 /* Make sure readonly bits are kept */
368 data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
370 return data | fixed_conf;
373 static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg,
374 uint32_t data)
376 if (reg == R_PROT) {
377 s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
378 return;
381 if (!s->regs[R_PROT]) {
382 qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
383 return;
386 switch (reg) {
387 case R_CONF:
388 data = aspeed_2500_sdmc_compute_conf(s, data);
389 break;
390 case R_STATUS1:
391 /* Will never return 'busy' */
392 data &= ~PHY_BUSY_STATE;
393 break;
394 case R_ECC_TEST_CTRL:
395 /* Always done, always happy */
396 data |= ECC_TEST_FINISHED;
397 data &= ~ECC_TEST_FAIL;
398 break;
399 default:
400 break;
403 s->regs[reg] = data;
406 static const uint64_t
407 aspeed_2500_ram_sizes[] = { 128 * MiB, 256 * MiB, 512 * MiB, 1024 * MiB, 0};
409 static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data)
411 DeviceClass *dc = DEVICE_CLASS(klass);
412 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
414 dc->desc = "ASPEED 2500 SDRAM Memory Controller";
415 asc->max_ram_size = 1024 << 20;
416 asc->compute_conf = aspeed_2500_sdmc_compute_conf;
417 asc->write = aspeed_2500_sdmc_write;
418 asc->valid_ram_sizes = aspeed_2500_ram_sizes;
421 static const TypeInfo aspeed_2500_sdmc_info = {
422 .name = TYPE_ASPEED_2500_SDMC,
423 .parent = TYPE_ASPEED_SDMC,
424 .class_init = aspeed_2500_sdmc_class_init,
427 static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
429 uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(3) |
430 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
431 ASPEED_SDMC_DRAM_SIZE(ast2600_rambits(s));
433 /* Make sure readonly bits are kept (use ast2500 mask) */
434 data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
436 return data | fixed_conf;
439 static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg,
440 uint32_t data)
442 if (s->regs[R_PROT] == PROT_HARDLOCKED) {
443 qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked until system reset!\n",
444 __func__);
445 return;
448 if (reg != R_PROT && s->regs[R_PROT] == PROT_SOFTLOCKED) {
449 qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
450 return;
453 switch (reg) {
454 case R_PROT:
455 if (data == PROT_KEY_UNLOCK) {
456 data = PROT_UNLOCKED;
457 } else if (data == PROT_KEY_HARDLOCK) {
458 data = PROT_HARDLOCKED;
459 } else {
460 data = PROT_SOFTLOCKED;
462 break;
463 case R_CONF:
464 data = aspeed_2600_sdmc_compute_conf(s, data);
465 break;
466 case R_STATUS1:
467 /* Will never return 'busy'. 'lock status' is always set */
468 data &= ~PHY_BUSY_STATE;
469 data |= PHY_PLL_LOCK_STATUS;
470 break;
471 case R_ECC_TEST_CTRL:
472 /* Always done, always happy */
473 data |= ECC_TEST_FINISHED;
474 data &= ~ECC_TEST_FAIL;
475 break;
476 default:
477 break;
480 s->regs[reg] = data;
483 static const uint64_t
484 aspeed_2600_ram_sizes[] = { 256 * MiB, 512 * MiB, 1024 * MiB, 2048 * MiB, 0};
486 static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data)
488 DeviceClass *dc = DEVICE_CLASS(klass);
489 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
491 dc->desc = "ASPEED 2600 SDRAM Memory Controller";
492 asc->max_ram_size = 2048 << 20;
493 asc->compute_conf = aspeed_2600_sdmc_compute_conf;
494 asc->write = aspeed_2600_sdmc_write;
495 asc->valid_ram_sizes = aspeed_2600_ram_sizes;
498 static const TypeInfo aspeed_2600_sdmc_info = {
499 .name = TYPE_ASPEED_2600_SDMC,
500 .parent = TYPE_ASPEED_SDMC,
501 .class_init = aspeed_2600_sdmc_class_init,
504 static void aspeed_sdmc_register_types(void)
506 type_register_static(&aspeed_sdmc_info);
507 type_register_static(&aspeed_2400_sdmc_info);
508 type_register_static(&aspeed_2500_sdmc_info);
509 type_register_static(&aspeed_2600_sdmc_info);
512 type_init(aspeed_sdmc_register_types);