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hw/intc/arm_gicv3: Fix ICC register tracepoints
[qemu/ar7.git] / target-tricore / tricore-opcodes.h
blobdf666b081f77836bc97632fb222b064fd64a8a16
1 /*
2 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
3 *
4 * This library is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU Lesser General Public
6 * License as published by the Free Software Foundation; either
7 * version 2 of the License, or (at your option) any later version.
8 *
9 * This library is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * Lesser General Public License for more details.
13 *
14 * You should have received a copy of the GNU Lesser General Public
15 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
16 */
17
18 /*
19 * Opcode Masks for Tricore
20 * Format MASK_OP_InstrFormatName_Field
21 */
22
23 /* This creates a mask with bits start .. end set to 1 and applies it to op */
24 #define MASK_BITS_SHIFT(op, start, end) (extract32(op, (start), \
25 (end) - (start) + 1))
26 #define MASK_BITS_SHIFT_SEXT(op, start, end) (sextract32(op, (start),\
27 (end) - (start) + 1))
28
29 /* new opcode masks */
30
31 #define MASK_OP_MAJOR(op) MASK_BITS_SHIFT(op, 0, 7)
32
33 /* 16-Bit Formats */
34 #define MASK_OP_SB_DISP8(op) MASK_BITS_SHIFT(op, 8, 15)
35 #define MASK_OP_SB_DISP8_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 8, 15)
36
37 #define MASK_OP_SBC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
38 #define MASK_OP_SBC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
39 #define MASK_OP_SBC_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
40
41 #define MASK_OP_SBR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
42 #define MASK_OP_SBR_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
43
44 #define MASK_OP_SBRN_N(op) MASK_BITS_SHIFT(op, 12, 15)
45 #define MASK_OP_SBRN_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
46
47 #define MASK_OP_SC_CONST8(op) MASK_BITS_SHIFT(op, 8, 15)
48
49 #define MASK_OP_SLR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
50 #define MASK_OP_SLR_D(op) MASK_BITS_SHIFT(op, 8, 11)
51
52 #define MASK_OP_SLRO_OFF4(op) MASK_BITS_SHIFT(op, 12, 15)
53 #define MASK_OP_SLRO_D(op) MASK_BITS_SHIFT(op, 8, 11)
54
55 #define MASK_OP_SR_OP2(op) MASK_BITS_SHIFT(op, 12, 15)
56 #define MASK_OP_SR_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
57
58 #define MASK_OP_SRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
59 #define MASK_OP_SRC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
60 #define MASK_OP_SRC_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
61
62 #define MASK_OP_SRO_S2(op) MASK_BITS_SHIFT(op, 12, 15)
63 #define MASK_OP_SRO_OFF4(op) MASK_BITS_SHIFT(op, 8, 11)
64
65 #define MASK_OP_SRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
66 #define MASK_OP_SRR_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
67
68 #define MASK_OP_SRRS_S2(op) MASK_BITS_SHIFT(op, 12, 15)
69 #define MASK_OP_SRRS_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
70 #define MASK_OP_SRRS_N(op) MASK_BITS_SHIFT(op, 6, 7)
71
72 #define MASK_OP_SSR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
73 #define MASK_OP_SSR_S1(op) MASK_BITS_SHIFT(op, 8, 11)
74
75 #define MASK_OP_SSRO_OFF4(op) MASK_BITS_SHIFT(op, 12, 15)
76 #define MASK_OP_SSRO_S1(op) MASK_BITS_SHIFT(op, 8, 11)
77
78 /* 32-Bit Formats */
79
80 /* ABS Format */
81 #define MASK_OP_ABS_OFF18(op) (MASK_BITS_SHIFT(op, 16, 21) + \
82 (MASK_BITS_SHIFT(op, 28, 31) << 6) + \
83 (MASK_BITS_SHIFT(op, 22, 25) << 10) +\
84 (MASK_BITS_SHIFT(op, 12, 15) << 14))
85 #define MASK_OP_ABS_OP2(op) MASK_BITS_SHIFT(op, 26, 27)
86 #define MASK_OP_ABS_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
87
88 /* ABSB Format */
89 #define MASK_OP_ABSB_OFF18(op) MASK_OP_ABS_OFF18(op)
90 #define MASK_OP_ABSB_OP2(op) MASK_BITS_SHIFT(op, 26, 27)
91 #define MASK_OP_ABSB_B(op) MASK_BITS_SHIFT(op, 11, 11)
92 #define MASK_OP_ABSB_BPOS(op) MASK_BITS_SHIFT(op, 8, 10)
93
94 /* B Format */
95 #define MASK_OP_B_DISP24(op) (MASK_BITS_SHIFT(op, 16, 31) + \
96 (MASK_BITS_SHIFT(op, 8, 15) << 16))
97 #define MASK_OP_B_DISP24_SEXT(op) (MASK_BITS_SHIFT(op, 16, 31) + \
98 (MASK_BITS_SHIFT_SEXT(op, 8, 15) << 16))
99 /* BIT Format */
100 #define MASK_OP_BIT_D(op) MASK_BITS_SHIFT(op, 28, 31)
101 #define MASK_OP_BIT_POS2(op) MASK_BITS_SHIFT(op, 23, 27)
102 #define MASK_OP_BIT_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
103 #define MASK_OP_BIT_POS1(op) MASK_BITS_SHIFT(op, 16, 20)
104 #define MASK_OP_BIT_S2(op) MASK_BITS_SHIFT(op, 12, 15)
105 #define MASK_OP_BIT_S1(op) MASK_BITS_SHIFT(op, 8, 11)
106
107 /* BO Format */
108 #define MASK_OP_BO_OFF10(op) (MASK_BITS_SHIFT(op, 16, 21) + \
109 (MASK_BITS_SHIFT(op, 28, 31) << 6))
110 #define MASK_OP_BO_OFF10_SEXT(op) (MASK_BITS_SHIFT(op, 16, 21) + \
111 (MASK_BITS_SHIFT_SEXT(op, 28, 31) << 6))
112 #define MASK_OP_BO_OP2(op) MASK_BITS_SHIFT(op, 22, 27)
113 #define MASK_OP_BO_S2(op) MASK_BITS_SHIFT(op, 12, 15)
114 #define MASK_OP_BO_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
115
116 /* BOL Format */
117 #define MASK_OP_BOL_OFF16(op) ((MASK_BITS_SHIFT(op, 16, 21) + \
118 (MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
119 (MASK_BITS_SHIFT(op, 22, 27) << 10))
120 #define MASK_OP_BOL_OFF16_SEXT(op) ((MASK_BITS_SHIFT(op, 16, 21) + \
121 (MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
122 (MASK_BITS_SHIFT_SEXT(op, 22, 27) << 10))
123 #define MASK_OP_BOL_S2(op) MASK_BITS_SHIFT(op, 12, 15)
124 #define MASK_OP_BOL_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
125
126 /* BRC Format */
127 #define MASK_OP_BRC_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
128 #define MASK_OP_BRC_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
129 #define MASK_OP_BRC_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30)
130 #define MASK_OP_BRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
131 #define MASK_OP_BRC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
132 #define MASK_OP_BRC_S1(op) MASK_BITS_SHIFT(op, 8, 11)
133
134 /* BRN Format */
135 #define MASK_OP_BRN_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
136 #define MASK_OP_BRN_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
137 #define MASK_OP_BRN_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30)
138 #define MASK_OP_BRN_N(op) (MASK_BITS_SHIFT(op, 12, 15) + \
139 (MASK_BITS_SHIFT(op, 7, 7) << 4))
140 #define MASK_OP_BRN_S1(op) MASK_BITS_SHIFT(op, 8, 11)
141 /* BRR Format */
142 #define MASK_OP_BRR_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
143 #define MASK_OP_BRR_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
144 #define MASK_OP_BRR_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30)
145 #define MASK_OP_BRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
146 #define MASK_OP_BRR_S1(op) MASK_BITS_SHIFT(op, 8, 11)
147
148 /* META MASK for similar instr Formats */
149 #define MASK_OP_META_D(op) MASK_BITS_SHIFT(op, 28, 31)
150 #define MASK_OP_META_S1(op) MASK_BITS_SHIFT(op, 8, 11)
151
152 /* RC Format */
153 #define MASK_OP_RC_D(op) MASK_OP_META_D(op)
154 #define MASK_OP_RC_OP2(op) MASK_BITS_SHIFT(op, 21, 27)
155 #define MASK_OP_RC_CONST9(op) MASK_BITS_SHIFT(op, 12, 20)
156 #define MASK_OP_RC_CONST9_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 20)
157 #define MASK_OP_RC_S1(op) MASK_OP_META_S1(op)
158
159 /* RCPW Format */
160
161 #define MASK_OP_RCPW_D(op) MASK_OP_META_D(op)
162 #define MASK_OP_RCPW_POS(op) MASK_BITS_SHIFT(op, 23, 27)
163 #define MASK_OP_RCPW_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
164 #define MASK_OP_RCPW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
165 #define MASK_OP_RCPW_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
166 #define MASK_OP_RCPW_S1(op) MASK_OP_META_S1(op)
167
168 /* RCR Format */
169
170 #define MASK_OP_RCR_D(op) MASK_OP_META_D(op)
171 #define MASK_OP_RCR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
172 #define MASK_OP_RCR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
173 #define MASK_OP_RCR_CONST9(op) MASK_BITS_SHIFT(op, 12, 20)
174 #define MASK_OP_RCR_CONST9_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 20)
175 #define MASK_OP_RCR_S1(op) MASK_OP_META_S1(op)
176
177 /* RCRR Format */
178
179 #define MASK_OP_RCRR_D(op) MASK_OP_META_D(op)
180 #define MASK_OP_RCRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
181 #define MASK_OP_RCRR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
182 #define MASK_OP_RCRR_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
183 #define MASK_OP_RCRR_S1(op) MASK_OP_META_S1(op)
184
185 /* RCRW Format */
186
187 #define MASK_OP_RCRW_D(op) MASK_OP_META_D(op)
188 #define MASK_OP_RCRW_S3(op) MASK_BITS_SHIFT(op, 24, 27)
189 #define MASK_OP_RCRW_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
190 #define MASK_OP_RCRW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
191 #define MASK_OP_RCRW_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
192 #define MASK_OP_RCRW_S1(op) MASK_OP_META_S1(op)
193
194 /* RLC Format */
195
196 #define MASK_OP_RLC_D(op) MASK_OP_META_D(op)
197 #define MASK_OP_RLC_CONST16(op) MASK_BITS_SHIFT(op, 12, 27)
198 #define MASK_OP_RLC_CONST16_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 27)
199 #define MASK_OP_RLC_S1(op) MASK_OP_META_S1(op)
200
201 /* RR Format */
202 #define MASK_OP_RR_D(op) MASK_OP_META_D(op)
203 #define MASK_OP_RR_OP2(op) MASK_BITS_SHIFT(op, 20, 27)
204 #define MASK_OP_RR_N(op) MASK_BITS_SHIFT(op, 16, 17)
205 #define MASK_OP_RR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
206 #define MASK_OP_RR_S1(op) MASK_OP_META_S1(op)
207
208 /* RR1 Format */
209 #define MASK_OP_RR1_D(op) MASK_OP_META_D(op)
210 #define MASK_OP_RR1_OP2(op) MASK_BITS_SHIFT(op, 18, 27)
211 #define MASK_OP_RR1_N(op) MASK_BITS_SHIFT(op, 16, 17)
212 #define MASK_OP_RR1_S2(op) MASK_BITS_SHIFT(op, 12, 15)
213 #define MASK_OP_RR1_S1(op) MASK_OP_META_S1(op)
214
215 /* RR2 Format */
216 #define MASK_OP_RR2_D(op) MASK_OP_META_D(op)
217 #define MASK_OP_RR2_OP2(op) MASK_BITS_SHIFT(op, 16, 27)
218 #define MASK_OP_RR2_S2(op) MASK_BITS_SHIFT(op, 12, 15)
219 #define MASK_OP_RR2_S1(op) MASK_OP_META_S1(op)
220
221 /* RRPW Format */
222 #define MASK_OP_RRPW_D(op) MASK_OP_META_D(op)
223 #define MASK_OP_RRPW_POS(op) MASK_BITS_SHIFT(op, 23, 27)
224 #define MASK_OP_RRPW_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
225 #define MASK_OP_RRPW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
226 #define MASK_OP_RRPW_S2(op) MASK_BITS_SHIFT(op, 12, 15)
227 #define MASK_OP_RRPW_S1(op) MASK_OP_META_S1(op)
228
229 /* RRR Format */
230 #define MASK_OP_RRR_D(op) MASK_OP_META_D(op)
231 #define MASK_OP_RRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
232 #define MASK_OP_RRR_OP2(op) MASK_BITS_SHIFT(op, 20, 23)
233 #define MASK_OP_RRR_N(op) MASK_BITS_SHIFT(op, 16, 17)
234 #define MASK_OP_RRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
235 #define MASK_OP_RRR_S1(op) MASK_OP_META_S1(op)
236
237 /* RRR1 Format */
238 #define MASK_OP_RRR1_D(op) MASK_OP_META_D(op)
239 #define MASK_OP_RRR1_S3(op) MASK_BITS_SHIFT(op, 24, 27)
240 #define MASK_OP_RRR1_OP2(op) MASK_BITS_SHIFT(op, 18, 23)
241 #define MASK_OP_RRR1_N(op) MASK_BITS_SHIFT(op, 16, 17)
242 #define MASK_OP_RRR1_S2(op) MASK_BITS_SHIFT(op, 12, 15)
243 #define MASK_OP_RRR1_S1(op) MASK_OP_META_S1(op)
244
245 /* RRR2 Format */
246 #define MASK_OP_RRR2_D(op) MASK_OP_META_D(op)
247 #define MASK_OP_RRR2_S3(op) MASK_BITS_SHIFT(op, 24, 27)
248 #define MASK_OP_RRR2_OP2(op) MASK_BITS_SHIFT(op, 16, 23)
249 #define MASK_OP_RRR2_S2(op) MASK_BITS_SHIFT(op, 12, 15)
250 #define MASK_OP_RRR2_S1(op) MASK_OP_META_S1(op)
251
252 /* RRRR Format */
253 #define MASK_OP_RRRR_D(op) MASK_OP_META_D(op)
254 #define MASK_OP_RRRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
255 #define MASK_OP_RRRR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
256 #define MASK_OP_RRRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
257 #define MASK_OP_RRRR_S1(op) MASK_OP_META_S1(op)
258
259 /* RRRW Format */
260 #define MASK_OP_RRRW_D(op) MASK_OP_META_D(op)
261 #define MASK_OP_RRRW_S3(op) MASK_BITS_SHIFT(op, 24, 27)
262 #define MASK_OP_RRRW_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
263 #define MASK_OP_RRRW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
264 #define MASK_OP_RRRW_S2(op) MASK_BITS_SHIFT(op, 12, 15)
265 #define MASK_OP_RRRW_S1(op) MASK_OP_META_S1(op)
266
267 /* SYS Format */
268 #define MASK_OP_SYS_OP2(op) MASK_BITS_SHIFT(op, 22, 27)
269 #define MASK_OP_SYS_S1D(op) MASK_OP_META_S1(op)
270
271
272
273 /*
274 * Tricore Opcodes Enums
275 *
276 * Format: OPC(1|2|M)_InstrLen_Name
277 * OPC1 = only op1 field is used
278 * OPC2 = op1 and op2 field used part of OPCM
279 * OPCM = op1 field used to group Instr
280 * InstrLen = 16|32
281 * Name = Name of Instr
282 */
283
284 /* 16-Bit */
285 enum {
286
287 OPCM_16_SR_SYSTEM = 0x00,
288 OPCM_16_SR_ACCU = 0x32,
289
290 OPC1_16_SRC_ADD = 0xc2,
291 OPC1_16_SRC_ADD_A15 = 0x92,
292 OPC1_16_SRC_ADD_15A = 0x9a,
293 OPC1_16_SRR_ADD = 0x42,
294 OPC1_16_SRR_ADD_A15 = 0x12,
295 OPC1_16_SRR_ADD_15A = 0x1a,
296 OPC1_16_SRC_ADD_A = 0xb0,
297 OPC1_16_SRR_ADD_A = 0x30,
298 OPC1_16_SRR_ADDS = 0x22,
299 OPC1_16_SRRS_ADDSC_A = 0x10,
300 OPC1_16_SC_AND = 0x16,
301 OPC1_16_SRR_AND = 0x26,
302 OPC1_16_SC_BISR = 0xe0,
303 OPC1_16_SRC_CADD = 0x8a,
304 OPC1_16_SRC_CADDN = 0xca,
305 OPC1_16_SB_CALL = 0x5c,
306 OPC1_16_SRC_CMOV = 0xaa,
307 OPC1_16_SRR_CMOV = 0x2a,
308 OPC1_16_SRC_CMOVN = 0xea,
309 OPC1_16_SRR_CMOVN = 0x6a,
310 OPC1_16_SRC_EQ = 0xba,
311 OPC1_16_SRR_EQ = 0x3a,
312 OPC1_16_SB_J = 0x3c,
313 OPC1_16_SBC_JEQ = 0x1e,
314 OPC1_16_SBR_JEQ = 0x3e,
315 OPC1_16_SBR_JGEZ = 0xce,
316 OPC1_16_SBR_JGTZ = 0x4e,
317 OPC1_16_SR_JI = 0xdc,
318 OPC1_16_SBR_JLEZ = 0x8e,
319 OPC1_16_SBR_JLTZ = 0x0e,
320 OPC1_16_SBC_JNE = 0x5e,
321 OPC1_16_SBR_JNE = 0x7e,
322 OPC1_16_SB_JNZ = 0xee,
323 OPC1_16_SBR_JNZ = 0xf6,
324 OPC1_16_SBR_JNZ_A = 0x7c,
325 OPC1_16_SBRN_JNZ_T = 0xae,
326 OPC1_16_SB_JZ = 0x6e,
327 OPC1_16_SBR_JZ = 0x76,
328 OPC1_16_SBR_JZ_A = 0xbc,
329 OPC1_16_SBRN_JZ_T = 0x2e,
330 OPC1_16_SC_LD_A = 0xd8,
331 OPC1_16_SLR_LD_A = 0xd4,
332 OPC1_16_SLR_LD_A_POSTINC = 0xc4,
333 OPC1_16_SLRO_LD_A = 0xc8,
334 OPC1_16_SRO_LD_A = 0xcc,
335 OPC1_16_SLR_LD_BU = 0x14,
336 OPC1_16_SLR_LD_BU_POSTINC = 0x04,
337 OPC1_16_SLRO_LD_BU = 0x08,
338 OPC1_16_SRO_LD_BU = 0x0c,
339 OPC1_16_SLR_LD_H = 0x94,
340 OPC1_16_SLR_LD_H_POSTINC = 0x84,
341 OPC1_16_SLRO_LD_H = 0x88,
342 OPC1_16_SRO_LD_H = 0x8c,
343 OPC1_16_SC_LD_W = 0x58,
344 OPC1_16_SLR_LD_W = 0x54,
345 OPC1_16_SLR_LD_W_POSTINC = 0x44,
346 OPC1_16_SLRO_LD_W = 0x48,
347 OPC1_16_SRO_LD_W = 0x4c,
348 OPC1_16_SBR_LOOP = 0xfc,
349 OPC1_16_SRC_LT = 0xfa,
350 OPC1_16_SRR_LT = 0x7a,
351 OPC1_16_SC_MOV = 0xda,
352 OPC1_16_SRC_MOV = 0x82,
353 OPC1_16_SRR_MOV = 0x02,
354 OPC1_16_SRC_MOV_E = 0xd2,/* 1.6 only */
355 OPC1_16_SRC_MOV_A = 0xa0,
356 OPC1_16_SRR_MOV_A = 0x60,
357 OPC1_16_SRR_MOV_AA = 0x40,
358 OPC1_16_SRR_MOV_D = 0x80,
359 OPC1_16_SRR_MUL = 0xe2,
360 OPC1_16_SR_NOT = 0x46,
361 OPC1_16_SC_OR = 0x96,
362 OPC1_16_SRR_OR = 0xa6,
363 OPC1_16_SRC_SH = 0x06,
364 OPC1_16_SRC_SHA = 0x86,
365 OPC1_16_SC_ST_A = 0xf8,
366 OPC1_16_SRO_ST_A = 0xec,
367 OPC1_16_SSR_ST_A = 0xf4,
368 OPC1_16_SSR_ST_A_POSTINC = 0xe4,
369 OPC1_16_SSRO_ST_A = 0xe8,
370 OPC1_16_SRO_ST_B = 0x2c,
371 OPC1_16_SSR_ST_B = 0x34,
372 OPC1_16_SSR_ST_B_POSTINC = 0x24,
373 OPC1_16_SSRO_ST_B = 0x28,
374 OPC1_16_SRO_ST_H = 0xac,
375 OPC1_16_SSR_ST_H = 0xb4,
376 OPC1_16_SSR_ST_H_POSTINC = 0xa4,
377 OPC1_16_SSRO_ST_H = 0xa8,
378 OPC1_16_SC_ST_W = 0x78,
379 OPC1_16_SRO_ST_W = 0x6c,
380 OPC1_16_SSR_ST_W = 0x74,
381 OPC1_16_SSR_ST_W_POSTINC = 0x64,
382 OPC1_16_SSRO_ST_W = 0x68,
383 OPC1_16_SRR_SUB = 0xa2,
384 OPC1_16_SRR_SUB_A15B = 0x52,
385 OPC1_16_SRR_SUB_15AB = 0x5a,
386 OPC1_16_SC_SUB_A = 0x20,
387 OPC1_16_SRR_SUBS = 0x62,
388 OPC1_16_SRR_XOR = 0xc6,
389
390 };
391
392 /*
393 * SR Format
394 */
395 /* OPCM_16_SR_SYSTEM */
396 enum {
397
398 OPC2_16_SR_NOP = 0x00,
399 OPC2_16_SR_RET = 0x09,
400 OPC2_16_SR_RFE = 0x08,
401 OPC2_16_SR_DEBUG = 0x0a,
402 OPC2_16_SR_FRET = 0x07,
403 };
404 /* OPCM_16_SR_ACCU */
405 enum {
406 OPC2_16_SR_RSUB = 0x05,
407 OPC2_16_SR_SAT_B = 0x00,
408 OPC2_16_SR_SAT_BU = 0x01,
409 OPC2_16_SR_SAT_H = 0x02,
410 OPC2_16_SR_SAT_HU = 0x03,
411
412 };
413
414 /* 32-Bit */
415
416 enum {
417 /* ABS Format 1, M */
418 OPCM_32_ABS_LDW = 0x85,
419 OPCM_32_ABS_LDB = 0x05,
420 OPCM_32_ABS_LDMST_SWAP = 0xe5,
421 OPCM_32_ABS_LDST_CONTEXT = 0x15,
422 OPCM_32_ABS_STORE = 0xa5,
423 OPCM_32_ABS_STOREB_H = 0x25,
424 OPC1_32_ABS_STOREQ = 0x65,
425 OPC1_32_ABS_LD_Q = 0x45,
426 OPC1_32_ABS_LEA = 0xc5,
427 /* ABSB Format */
428 OPC1_32_ABSB_ST_T = 0xd5,
429 /* B Format */
430 OPC1_32_B_CALL = 0x6d,
431 OPC1_32_B_CALLA = 0xed,
432 OPC1_32_B_FCALL = 0x61,
433 OPC1_32_B_FCALLA = 0xe1,
434 OPC1_32_B_J = 0x1d,
435 OPC1_32_B_JA = 0x9d,
436 OPC1_32_B_JL = 0x5d,
437 OPC1_32_B_JLA = 0xdd,
438 /* Bit Format */
439 OPCM_32_BIT_ANDACC = 0x47,
440 OPCM_32_BIT_LOGICAL_T1 = 0x87,
441 OPCM_32_BIT_INSERT = 0x67,
442 OPCM_32_BIT_LOGICAL_T2 = 0x07,
443 OPCM_32_BIT_ORAND = 0xc7,
444 OPCM_32_BIT_SH_LOGIC1 = 0x27,
445 OPCM_32_BIT_SH_LOGIC2 = 0xa7,
446 /* BO Format */
447 OPCM_32_BO_ADDRMODE_POST_PRE_BASE = 0x89,
448 OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR = 0xa9,
449 OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE = 0x09,
450 OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR = 0x29,
451 OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE = 0x49,
452 OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR = 0x69,
453 /* BOL Format */
454 OPC1_32_BOL_LD_A_LONGOFF = 0x99,
455 OPC1_32_BOL_LD_W_LONGOFF = 0x19,
456 OPC1_32_BOL_LEA_LONGOFF = 0xd9,
457 OPC1_32_BOL_ST_W_LONGOFF = 0x59,
458 OPC1_32_BOL_ST_A_LONGOFF = 0xb5, /* 1.6 only */
459 OPC1_32_BOL_LD_B_LONGOFF = 0x79, /* 1.6 only */
460 OPC1_32_BOL_LD_BU_LONGOFF = 0x39, /* 1.6 only */
461 OPC1_32_BOL_LD_H_LONGOFF = 0xc9, /* 1.6 only */
462 OPC1_32_BOL_LD_HU_LONGOFF = 0xb9, /* 1.6 only */
463 OPC1_32_BOL_ST_B_LONGOFF = 0xe9, /* 1.6 only */
464 OPC1_32_BOL_ST_H_LONGOFF = 0xf9, /* 1.6 only */
465 /* BRC Format */
466 OPCM_32_BRC_EQ_NEQ = 0xdf,
467 OPCM_32_BRC_GE = 0xff,
468 OPCM_32_BRC_JLT = 0xbf,
469 OPCM_32_BRC_JNE = 0x9f,
470 /* BRN Format */
471 OPCM_32_BRN_JTT = 0x6f,
472 /* BRR Format */
473 OPCM_32_BRR_EQ_NEQ = 0x5f,
474 OPCM_32_BRR_ADDR_EQ_NEQ = 0x7d,
475 OPCM_32_BRR_GE = 0x7f,
476 OPCM_32_BRR_JLT = 0x3f,
477 OPCM_32_BRR_JNE = 0x1f,
478 OPCM_32_BRR_JNZ = 0xbd,
479 OPCM_32_BRR_LOOP = 0xfd,
480 /* RC Format */
481 OPCM_32_RC_LOGICAL_SHIFT = 0x8f,
482 OPCM_32_RC_ACCUMULATOR = 0x8b,
483 OPCM_32_RC_SERVICEROUTINE = 0xad,
484 OPCM_32_RC_MUL = 0x53,
485 /* RCPW Format */
486 OPCM_32_RCPW_MASK_INSERT = 0xb7,
487 /* RCR Format */
488 OPCM_32_RCR_COND_SELECT = 0xab,
489 OPCM_32_RCR_MADD = 0x13,
490 OPCM_32_RCR_MSUB = 0x33,
491 /* RCRR Format */
492 OPC1_32_RCRR_INSERT = 0x97,
493 /* RCRW Format */
494 OPCM_32_RCRW_MASK_INSERT = 0xd7,
495 /* RLC Format */
496 OPC1_32_RLC_ADDI = 0x1b,
497 OPC1_32_RLC_ADDIH = 0x9b,
498 OPC1_32_RLC_ADDIH_A = 0x11,
499 OPC1_32_RLC_MFCR = 0x4d,
500 OPC1_32_RLC_MOV = 0x3b,
501 OPC1_32_RLC_MOV_64 = 0xfb, /* 1.6 only */
502 OPC1_32_RLC_MOV_U = 0xbb,
503 OPC1_32_RLC_MOV_H = 0x7b,
504 OPC1_32_RLC_MOVH_A = 0x91,
505 OPC1_32_RLC_MTCR = 0xcd,
506 /* RR Format */
507 OPCM_32_RR_LOGICAL_SHIFT = 0x0f,
508 OPCM_32_RR_ACCUMULATOR = 0x0b,
509 OPCM_32_RR_ADDRESS = 0x01,
510 OPCM_32_RR_DIVIDE = 0x4b,
511 OPCM_32_RR_IDIRECT = 0x2d,
512 /* RR1 Format */
513 OPCM_32_RR1_MUL = 0xb3,
514 OPCM_32_RR1_MULQ = 0x93,
515 /* RR2 Format */
516 OPCM_32_RR2_MUL = 0x73,
517 /* RRPW Format */
518 OPCM_32_RRPW_EXTRACT_INSERT = 0x37,
519 OPC1_32_RRPW_DEXTR = 0x77,
520 /* RRR Format */
521 OPCM_32_RRR_COND_SELECT = 0x2b,
522 OPCM_32_RRR_DIVIDE = 0x6b,
523 /* RRR1 Format */
524 OPCM_32_RRR1_MADD = 0x83,
525 OPCM_32_RRR1_MADDQ_H = 0x43,
526 OPCM_32_RRR1_MADDSU_H = 0xc3,
527 OPCM_32_RRR1_MSUB_H = 0xa3,
528 OPCM_32_RRR1_MSUB_Q = 0x63,
529 OPCM_32_RRR1_MSUBAD_H = 0xe3,
530 /* RRR2 Format */
531 OPCM_32_RRR2_MADD = 0x03,
532 OPCM_32_RRR2_MSUB = 0x23,
533 /* RRRR Format */
534 OPCM_32_RRRR_EXTRACT_INSERT = 0x17,
535 /* RRRW Format */
536 OPCM_32_RRRW_EXTRACT_INSERT = 0x57,
537 /* SYS Format */
538 OPCM_32_SYS_INTERRUPTS = 0x0d,
539 OPC1_32_SYS_RSTV = 0x2f,
540 };
541
542
543
544 /*
545 * ABS Format
546 */
547
548 /* OPCM_32_ABS_LDW */
549 enum {
550
551 OPC2_32_ABS_LD_A = 0x02,
552 OPC2_32_ABS_LD_D = 0x01,
553 OPC2_32_ABS_LD_DA = 0x03,
554 OPC2_32_ABS_LD_W = 0x00,
555 };
556
557 /* OPCM_32_ABS_LDB */
558 enum {
559 OPC2_32_ABS_LD_B = 0x00,
560 OPC2_32_ABS_LD_BU = 0x01,
561 OPC2_32_ABS_LD_H = 0x02,
562 OPC2_32_ABS_LD_HU = 0x03,
563 };
564 /* OPCM_32_ABS_LDMST_SWAP */
565 enum {
566 OPC2_32_ABS_LDMST = 0x01,
567 OPC2_32_ABS_SWAP_W = 0x00,
568 };
569 /* OPCM_32_ABS_LDST_CONTEXT */
570 enum {
571 OPC2_32_ABS_LDLCX = 0x02,
572 OPC2_32_ABS_LDUCX = 0x03,
573 OPC2_32_ABS_STLCX = 0x00,
574 OPC2_32_ABS_STUCX = 0x01,
575 };
576 /* OPCM_32_ABS_STORE */
577 enum {
578 OPC2_32_ABS_ST_A = 0x02,
579 OPC2_32_ABS_ST_D = 0x01,
580 OPC2_32_ABS_ST_DA = 0x03,
581 OPC2_32_ABS_ST_W = 0x00,
582 };
583 /* OPCM_32_ABS_STOREB_H */
584 enum {
585 OPC2_32_ABS_ST_B = 0x00,
586 OPC2_32_ABS_ST_H = 0x02,
587 };
588 /*
589 * Bit Format
590 */
591 /* OPCM_32_BIT_ANDACC */
592 enum {
593 OPC2_32_BIT_AND_AND_T = 0x00,
594 OPC2_32_BIT_AND_ANDN_T = 0x03,
595 OPC2_32_BIT_AND_NOR_T = 0x02,
596 OPC2_32_BIT_AND_OR_T = 0x01,
597 };
598 /* OPCM_32_BIT_LOGICAL_T */
599 enum {
600 OPC2_32_BIT_AND_T = 0x00,
601 OPC2_32_BIT_ANDN_T = 0x03,
602 OPC2_32_BIT_NOR_T = 0x02,
603 OPC2_32_BIT_OR_T = 0x01,
604 };
605 /* OPCM_32_BIT_INSERT */
606 enum {
607 OPC2_32_BIT_INS_T = 0x00,
608 OPC2_32_BIT_INSN_T = 0x01,
609 };
610 /* OPCM_32_BIT_LOGICAL_T2 */
611 enum {
612 OPC2_32_BIT_NAND_T = 0x00,
613 OPC2_32_BIT_ORN_T = 0x01,
614 OPC2_32_BIT_XNOR_T = 0x02,
615 OPC2_32_BIT_XOR_T = 0x03,
616 };
617 /* OPCM_32_BIT_ORAND */
618 enum {
619 OPC2_32_BIT_OR_AND_T = 0x00,
620 OPC2_32_BIT_OR_ANDN_T = 0x03,
621 OPC2_32_BIT_OR_NOR_T = 0x02,
622 OPC2_32_BIT_OR_OR_T = 0x01,
623 };
624 /*OPCM_32_BIT_SH_LOGIC1 */
625 enum {
626 OPC2_32_BIT_SH_AND_T = 0x00,
627 OPC2_32_BIT_SH_ANDN_T = 0x03,
628 OPC2_32_BIT_SH_NOR_T = 0x02,
629 OPC2_32_BIT_SH_OR_T = 0x01,
630 };
631 /* OPCM_32_BIT_SH_LOGIC2 */
632 enum {
633 OPC2_32_BIT_SH_NAND_T = 0x00,
634 OPC2_32_BIT_SH_ORN_T = 0x01,
635 OPC2_32_BIT_SH_XNOR_T = 0x02,
636 OPC2_32_BIT_SH_XOR_T = 0x03,
637 };
638 /*
639 * BO Format
640 */
641 /* OPCM_32_BO_ADDRMODE_POST_PRE_BASE */
642 enum {
643 OPC2_32_BO_CACHEA_I_SHORTOFF = 0x2e,
644 OPC2_32_BO_CACHEA_I_POSTINC = 0x0e,
645 OPC2_32_BO_CACHEA_I_PREINC = 0x1e,
646 OPC2_32_BO_CACHEA_W_SHORTOFF = 0x2c,
647 OPC2_32_BO_CACHEA_W_POSTINC = 0x0c,
648 OPC2_32_BO_CACHEA_W_PREINC = 0x1c,
649 OPC2_32_BO_CACHEA_WI_SHORTOFF = 0x2d,
650 OPC2_32_BO_CACHEA_WI_POSTINC = 0x0d,
651 OPC2_32_BO_CACHEA_WI_PREINC = 0x1d,
652 /* 1.3.1 only */
653 OPC2_32_BO_CACHEI_W_SHORTOFF = 0x2b,
654 OPC2_32_BO_CACHEI_W_POSTINC = 0x0b,
655 OPC2_32_BO_CACHEI_W_PREINC = 0x1b,
656 OPC2_32_BO_CACHEI_WI_SHORTOFF = 0x2f,
657 OPC2_32_BO_CACHEI_WI_POSTINC = 0x0f,
658 OPC2_32_BO_CACHEI_WI_PREINC = 0x1f,
659 /* end 1.3.1 only */
660 OPC2_32_BO_ST_A_SHORTOFF = 0x26,
661 OPC2_32_BO_ST_A_POSTINC = 0x06,
662 OPC2_32_BO_ST_A_PREINC = 0x16,
663 OPC2_32_BO_ST_B_SHORTOFF = 0x20,
664 OPC2_32_BO_ST_B_POSTINC = 0x00,
665 OPC2_32_BO_ST_B_PREINC = 0x10,
666 OPC2_32_BO_ST_D_SHORTOFF = 0x25,
667 OPC2_32_BO_ST_D_POSTINC = 0x05,
668 OPC2_32_BO_ST_D_PREINC = 0x15,
669 OPC2_32_BO_ST_DA_SHORTOFF = 0x27,
670 OPC2_32_BO_ST_DA_POSTINC = 0x07,
671 OPC2_32_BO_ST_DA_PREINC = 0x17,
672 OPC2_32_BO_ST_H_SHORTOFF = 0x22,
673 OPC2_32_BO_ST_H_POSTINC = 0x02,
674 OPC2_32_BO_ST_H_PREINC = 0x12,
675 OPC2_32_BO_ST_Q_SHORTOFF = 0x28,
676 OPC2_32_BO_ST_Q_POSTINC = 0x08,
677 OPC2_32_BO_ST_Q_PREINC = 0x18,
678 OPC2_32_BO_ST_W_SHORTOFF = 0x24,
679 OPC2_32_BO_ST_W_POSTINC = 0x04,
680 OPC2_32_BO_ST_W_PREINC = 0x14,
681 };
682 /* OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR */
683 enum {
684 OPC2_32_BO_CACHEA_I_BR = 0x0e,
685 OPC2_32_BO_CACHEA_I_CIRC = 0x1e,
686 OPC2_32_BO_CACHEA_W_BR = 0x0c,
687 OPC2_32_BO_CACHEA_W_CIRC = 0x1c,
688 OPC2_32_BO_CACHEA_WI_BR = 0x0d,
689 OPC2_32_BO_CACHEA_WI_CIRC = 0x1d,
690 OPC2_32_BO_ST_A_BR = 0x06,
691 OPC2_32_BO_ST_A_CIRC = 0x16,
692 OPC2_32_BO_ST_B_BR = 0x00,
693 OPC2_32_BO_ST_B_CIRC = 0x10,
694 OPC2_32_BO_ST_D_BR = 0x05,
695 OPC2_32_BO_ST_D_CIRC = 0x15,
696 OPC2_32_BO_ST_DA_BR = 0x07,
697 OPC2_32_BO_ST_DA_CIRC = 0x17,
698 OPC2_32_BO_ST_H_BR = 0x02,
699 OPC2_32_BO_ST_H_CIRC = 0x12,
700 OPC2_32_BO_ST_Q_BR = 0x08,
701 OPC2_32_BO_ST_Q_CIRC = 0x18,
702 OPC2_32_BO_ST_W_BR = 0x04,
703 OPC2_32_BO_ST_W_CIRC = 0x14,
704 };
705 /* OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE */
706 enum {
707 OPC2_32_BO_LD_A_SHORTOFF = 0x26,
708 OPC2_32_BO_LD_A_POSTINC = 0x06,
709 OPC2_32_BO_LD_A_PREINC = 0x16,
710 OPC2_32_BO_LD_B_SHORTOFF = 0x20,
711 OPC2_32_BO_LD_B_POSTINC = 0x00,
712 OPC2_32_BO_LD_B_PREINC = 0x10,
713 OPC2_32_BO_LD_BU_SHORTOFF = 0x21,
714 OPC2_32_BO_LD_BU_POSTINC = 0x01,
715 OPC2_32_BO_LD_BU_PREINC = 0x11,
716 OPC2_32_BO_LD_D_SHORTOFF = 0x25,
717 OPC2_32_BO_LD_D_POSTINC = 0x05,
718 OPC2_32_BO_LD_D_PREINC = 0x15,
719 OPC2_32_BO_LD_DA_SHORTOFF = 0x27,
720 OPC2_32_BO_LD_DA_POSTINC = 0x07,
721 OPC2_32_BO_LD_DA_PREINC = 0x17,
722 OPC2_32_BO_LD_H_SHORTOFF = 0x22,
723 OPC2_32_BO_LD_H_POSTINC = 0x02,
724 OPC2_32_BO_LD_H_PREINC = 0x12,
725 OPC2_32_BO_LD_HU_SHORTOFF = 0x23,
726 OPC2_32_BO_LD_HU_POSTINC = 0x03,
727 OPC2_32_BO_LD_HU_PREINC = 0x13,
728 OPC2_32_BO_LD_Q_SHORTOFF = 0x28,
729 OPC2_32_BO_LD_Q_POSTINC = 0x08,
730 OPC2_32_BO_LD_Q_PREINC = 0x18,
731 OPC2_32_BO_LD_W_SHORTOFF = 0x24,
732 OPC2_32_BO_LD_W_POSTINC = 0x04,
733 OPC2_32_BO_LD_W_PREINC = 0x14,
734 };
735 /* OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR */
736 enum {
737 OPC2_32_BO_LD_A_BR = 0x06,
738 OPC2_32_BO_LD_A_CIRC = 0x16,
739 OPC2_32_BO_LD_B_BR = 0x00,
740 OPC2_32_BO_LD_B_CIRC = 0x10,
741 OPC2_32_BO_LD_BU_BR = 0x01,
742 OPC2_32_BO_LD_BU_CIRC = 0x11,
743 OPC2_32_BO_LD_D_BR = 0x05,
744 OPC2_32_BO_LD_D_CIRC = 0x15,
745 OPC2_32_BO_LD_DA_BR = 0x07,
746 OPC2_32_BO_LD_DA_CIRC = 0x17,
747 OPC2_32_BO_LD_H_BR = 0x02,
748 OPC2_32_BO_LD_H_CIRC = 0x12,
749 OPC2_32_BO_LD_HU_BR = 0x03,
750 OPC2_32_BO_LD_HU_CIRC = 0x13,
751 OPC2_32_BO_LD_Q_BR = 0x08,
752 OPC2_32_BO_LD_Q_CIRC = 0x18,
753 OPC2_32_BO_LD_W_BR = 0x04,
754 OPC2_32_BO_LD_W_CIRC = 0x14,
755 };
756 /* OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE */
757 enum {
758 OPC2_32_BO_LDLCX_SHORTOFF = 0x24,
759 OPC2_32_BO_LDMST_SHORTOFF = 0x21,
760 OPC2_32_BO_LDMST_POSTINC = 0x01,
761 OPC2_32_BO_LDMST_PREINC = 0x11,
762 OPC2_32_BO_LDUCX_SHORTOFF = 0x25,
763 OPC2_32_BO_LEA_SHORTOFF = 0x28,
764 OPC2_32_BO_STLCX_SHORTOFF = 0x26,
765 OPC2_32_BO_STUCX_SHORTOFF = 0x27,
766 OPC2_32_BO_SWAP_W_SHORTOFF = 0x20,
767 OPC2_32_BO_SWAP_W_POSTINC = 0x00,
768 OPC2_32_BO_SWAP_W_PREINC = 0x10,
769 OPC2_32_BO_CMPSWAP_W_SHORTOFF = 0x23,
770 OPC2_32_BO_CMPSWAP_W_POSTINC = 0x03,
771 OPC2_32_BO_CMPSWAP_W_PREINC = 0x13,
772 OPC2_32_BO_SWAPMSK_W_SHORTOFF = 0x22,
773 OPC2_32_BO_SWAPMSK_W_POSTINC = 0x02,
774 OPC2_32_BO_SWAPMSK_W_PREINC = 0x12,
775 };
776 /*OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR */
777 enum {
778 OPC2_32_BO_LDMST_BR = 0x01,
779 OPC2_32_BO_LDMST_CIRC = 0x11,
780 OPC2_32_BO_SWAP_W_BR = 0x00,
781 OPC2_32_BO_SWAP_W_CIRC = 0x10,
782 OPC2_32_BO_CMPSWAP_W_BR = 0x03,
783 OPC2_32_BO_CMPSWAP_W_CIRC = 0x13,
784 OPC2_32_BO_SWAPMSK_W_BR = 0x02,
785 OPC2_32_BO_SWAPMSK_W_CIRC = 0x12,
786 };
787 /*
788 * BRC Format
789 */
790 /*OPCM_32_BRC_EQ_NEQ */
791 enum {
792 OPC2_32_BRC_JEQ = 0x00,
793 OPC2_32_BRC_JNE = 0x01,
794 };
795 /* OPCM_32_BRC_GE */
796 enum {
797 OP2_32_BRC_JGE = 0x00,
798 OPC_32_BRC_JGE_U = 0x01,
799 };
800 /* OPCM_32_BRC_JLT */
801 enum {
802 OPC2_32_BRC_JLT = 0x00,
803 OPC2_32_BRC_JLT_U = 0x01,
804 };
805 /* OPCM_32_BRC_JNE */
806 enum {
807 OPC2_32_BRC_JNED = 0x01,
808 OPC2_32_BRC_JNEI = 0x00,
809 };
810 /*
811 * BRN Format
812 */
813 /* OPCM_32_BRN_JTT */
814 enum {
815 OPC2_32_BRN_JNZ_T = 0x01,
816 OPC2_32_BRN_JZ_T = 0x00,
817 };
818 /*
819 * BRR Format
820 */
821 /* OPCM_32_BRR_EQ_NEQ */
822 enum {
823 OPC2_32_BRR_JEQ = 0x00,
824 OPC2_32_BRR_JNE = 0x01,
825 };
826 /* OPCM_32_BRR_ADDR_EQ_NEQ */
827 enum {
828 OPC2_32_BRR_JEQ_A = 0x00,
829 OPC2_32_BRR_JNE_A = 0x01,
830 };
831 /*OPCM_32_BRR_GE */
832 enum {
833 OPC2_32_BRR_JGE = 0x00,
834 OPC2_32_BRR_JGE_U = 0x01,
835 };
836 /* OPCM_32_BRR_JLT */
837 enum {
838 OPC2_32_BRR_JLT = 0x00,
839 OPC2_32_BRR_JLT_U = 0x01,
840 };
841 /* OPCM_32_BRR_JNE */
842 enum {
843 OPC2_32_BRR_JNED = 0x01,
844 OPC2_32_BRR_JNEI = 0x00,
845 };
846 /* OPCM_32_BRR_JNZ */
847 enum {
848 OPC2_32_BRR_JNZ_A = 0x01,
849 OPC2_32_BRR_JZ_A = 0x00,
850 };
851 /* OPCM_32_BRR_LOOP */
852 enum {
853 OPC2_32_BRR_LOOP = 0x00,
854 OPC2_32_BRR_LOOPU = 0x01,
855 };
856 /*
857 * RC Format
858 */
859 /* OPCM_32_RC_LOGICAL_SHIFT */
860 enum {
861 OPC2_32_RC_AND = 0x08,
862 OPC2_32_RC_ANDN = 0x0e,
863 OPC2_32_RC_NAND = 0x09,
864 OPC2_32_RC_NOR = 0x0b,
865 OPC2_32_RC_OR = 0x0a,
866 OPC2_32_RC_ORN = 0x0f,
867 OPC2_32_RC_SH = 0x00,
868 OPC2_32_RC_SH_H = 0x40,
869 OPC2_32_RC_SHA = 0x01,
870 OPC2_32_RC_SHA_H = 0x41,
871 OPC2_32_RC_SHAS = 0x02,
872 OPC2_32_RC_XNOR = 0x0d,
873 OPC2_32_RC_XOR = 0x0c,
874 };
875 /* OPCM_32_RC_ACCUMULATOR */
876 enum {
877 OPC2_32_RC_ABSDIF = 0x0e,
878 OPC2_32_RC_ABSDIFS = 0x0f,
879 OPC2_32_RC_ADD = 0x00,
880 OPC2_32_RC_ADDC = 0x05,
881 OPC2_32_RC_ADDS = 0x02,
882 OPC2_32_RC_ADDS_U = 0x03,
883 OPC2_32_RC_ADDX = 0x04,
884 OPC2_32_RC_AND_EQ = 0x20,
885 OPC2_32_RC_AND_GE = 0x24,
886 OPC2_32_RC_AND_GE_U = 0x25,
887 OPC2_32_RC_AND_LT = 0x22,
888 OPC2_32_RC_AND_LT_U = 0x23,
889 OPC2_32_RC_AND_NE = 0x21,
890 OPC2_32_RC_EQ = 0x10,
891 OPC2_32_RC_EQANY_B = 0x56,
892 OPC2_32_RC_EQANY_H = 0x76,
893 OPC2_32_RC_GE = 0x14,
894 OPC2_32_RC_GE_U = 0x15,
895 OPC2_32_RC_LT = 0x12,
896 OPC2_32_RC_LT_U = 0x13,
897 OPC2_32_RC_MAX = 0x1a,
898 OPC2_32_RC_MAX_U = 0x1b,
899 OPC2_32_RC_MIN = 0x18,
900 OPC2_32_RC_MIN_U = 0x19,
901 OPC2_32_RC_NE = 0x11,
902 OPC2_32_RC_OR_EQ = 0x27,
903 OPC2_32_RC_OR_GE = 0x2b,
904 OPC2_32_RC_OR_GE_U = 0x2c,
905 OPC2_32_RC_OR_LT = 0x29,
906 OPC2_32_RC_OR_LT_U = 0x2a,
907 OPC2_32_RC_OR_NE = 0x28,
908 OPC2_32_RC_RSUB = 0x08,
909 OPC2_32_RC_RSUBS = 0x0a,
910 OPC2_32_RC_RSUBS_U = 0x0b,
911 OPC2_32_RC_SH_EQ = 0x37,
912 OPC2_32_RC_SH_GE = 0x3b,
913 OPC2_32_RC_SH_GE_U = 0x3c,
914 OPC2_32_RC_SH_LT = 0x39,
915 OPC2_32_RC_SH_LT_U = 0x3a,
916 OPC2_32_RC_SH_NE = 0x38,
917 OPC2_32_RC_XOR_EQ = 0x2f,
918 OPC2_32_RC_XOR_GE = 0x33,
919 OPC2_32_RC_XOR_GE_U = 0x34,
920 OPC2_32_RC_XOR_LT = 0x31,
921 OPC2_32_RC_XOR_LT_U = 0x32,
922 OPC2_32_RC_XOR_NE = 0x30,
923 };
924 /* OPCM_32_RC_SERVICEROUTINE */
925 enum {
926 OPC2_32_RC_BISR = 0x00,
927 OPC2_32_RC_SYSCALL = 0x04,
928 };
929 /* OPCM_32_RC_MUL */
930 enum {
931 OPC2_32_RC_MUL_32 = 0x01,
932 OPC2_32_RC_MUL_64 = 0x03,
933 OPC2_32_RC_MULS_32 = 0x05,
934 OPC2_32_RC_MUL_U_64 = 0x02,
935 OPC2_32_RC_MULS_U_32 = 0x04,
936 };
937 /*
938 * RCPW Format
939 */
940 /* OPCM_32_RCPW_MASK_INSERT */
941 enum {
942 OPC2_32_RCPW_IMASK = 0x01,
943 OPC2_32_RCPW_INSERT = 0x00,
944 };
945 /*
946 * RCR Format
947 */
948 /* OPCM_32_RCR_COND_SELECT */
949 enum {
950 OPC2_32_RCR_CADD = 0x00,
951 OPC2_32_RCR_CADDN = 0x01,
952 OPC2_32_RCR_SEL = 0x04,
953 OPC2_32_RCR_SELN = 0x05,
954 };
955 /* OPCM_32_RCR_MADD */
956 enum {
957 OPC2_32_RCR_MADD_32 = 0x01,
958 OPC2_32_RCR_MADD_64 = 0x03,
959 OPC2_32_RCR_MADDS_32 = 0x05,
960 OPC2_32_RCR_MADDS_64 = 0x07,
961 OPC2_32_RCR_MADD_U_64 = 0x02,
962 OPC2_32_RCR_MADDS_U_32 = 0x04,
963 OPC2_32_RCR_MADDS_U_64 = 0x06,
964 };
965 /* OPCM_32_RCR_MSUB */
966 enum {
967 OPC2_32_RCR_MSUB_32 = 0x01,
968 OPC2_32_RCR_MSUB_64 = 0x03,
969 OPC2_32_RCR_MSUBS_32 = 0x05,
970 OPC2_32_RCR_MSUBS_64 = 0x07,
971 OPC2_32_RCR_MSUB_U_64 = 0x02,
972 OPC2_32_RCR_MSUBS_U_32 = 0x04,
973 OPC2_32_RCR_MSUBS_U_64 = 0x06,
974 };
975 /*
976 * RCRW Format
977 */
978 /* OPCM_32_RCRW_MASK_INSERT */
979 enum {
980 OPC2_32_RCRW_IMASK = 0x01,
981 OPC2_32_RCRW_INSERT = 0x00,
982 };
983
984 /*
985 * RR Format
986 */
987 /* OPCM_32_RR_LOGICAL_SHIFT */
988 enum {
989 OPC2_32_RR_AND = 0x08,
990 OPC2_32_RR_ANDN = 0x0e,
991 OPC2_32_RR_CLO = 0x1c,
992 OPC2_32_RR_CLO_H = 0x7d,
993 OPC2_32_RR_CLS = 0x1d,
994 OPC2_32_RR_CLS_H = 0x7e,
995 OPC2_32_RR_CLZ = 0x1b,
996 OPC2_32_RR_CLZ_H = 0x7c,
997 OPC2_32_RR_NAND = 0x09,
998 OPC2_32_RR_NOR = 0x0b,
999 OPC2_32_RR_OR = 0x0a,
1000 OPC2_32_RR_ORN = 0x0f,
1001 OPC2_32_RR_SH = 0x00,
1002 OPC2_32_RR_SH_H = 0x40,
1003 OPC2_32_RR_SHA = 0x01,
1004 OPC2_32_RR_SHA_H = 0x41,
1005 OPC2_32_RR_SHAS = 0x02,
1006 OPC2_32_RR_XNOR = 0x0d,
1007 OPC2_32_RR_XOR = 0x0c,
1008 };
1009 /* OPCM_32_RR_ACCUMULATOR */
1010 enum {
1011 OPC2_32_RR_ABS = 0x1c,
1012 OPC2_32_RR_ABS_B = 0x5c,
1013 OPC2_32_RR_ABS_H = 0x7c,
1014 OPC2_32_RR_ABSDIF = 0x0e,
1015 OPC2_32_RR_ABSDIF_B = 0x4e,
1016 OPC2_32_RR_ABSDIF_H = 0x6e,
1017 OPC2_32_RR_ABSDIFS = 0x0f,
1018 OPC2_32_RR_ABSDIFS_H = 0x6f,
1019 OPC2_32_RR_ABSS = 0x1d,
1020 OPC2_32_RR_ABSS_H = 0x7d,
1021 OPC2_32_RR_ADD = 0x00,
1022 OPC2_32_RR_ADD_B = 0x40,
1023 OPC2_32_RR_ADD_H = 0x60,
1024 OPC2_32_RR_ADDC = 0x05,
1025 OPC2_32_RR_ADDS = 0x02,
1026 OPC2_32_RR_ADDS_H = 0x62,
1027 OPC2_32_RR_ADDS_HU = 0x63,
1028 OPC2_32_RR_ADDS_U = 0x03,
1029 OPC2_32_RR_ADDX = 0x04,
1030 OPC2_32_RR_AND_EQ = 0x20,
1031 OPC2_32_RR_AND_GE = 0x24,
1032 OPC2_32_RR_AND_GE_U = 0x25,
1033 OPC2_32_RR_AND_LT = 0x22,
1034 OPC2_32_RR_AND_LT_U = 0x23,
1035 OPC2_32_RR_AND_NE = 0x21,
1036 OPC2_32_RR_EQ = 0x10,
1037 OPC2_32_RR_EQ_B = 0x50,
1038 OPC2_32_RR_EQ_H = 0x70,
1039 OPC2_32_RR_EQ_W = 0x90,
1040 OPC2_32_RR_EQANY_B = 0x56,
1041 OPC2_32_RR_EQANY_H = 0x76,
1042 OPC2_32_RR_GE = 0x14,
1043 OPC2_32_RR_GE_U = 0x15,
1044 OPC2_32_RR_LT = 0x12,
1045 OPC2_32_RR_LT_U = 0x13,
1046 OPC2_32_RR_LT_B = 0x52,
1047 OPC2_32_RR_LT_BU = 0x53,
1048 OPC2_32_RR_LT_H = 0x72,
1049 OPC2_32_RR_LT_HU = 0x73,
1050 OPC2_32_RR_LT_W = 0x92,
1051 OPC2_32_RR_LT_WU = 0x93,
1052 OPC2_32_RR_MAX = 0x1a,
1053 OPC2_32_RR_MAX_U = 0x1b,
1054 OPC2_32_RR_MAX_B = 0x5a,
1055 OPC2_32_RR_MAX_BU = 0x5b,
1056 OPC2_32_RR_MAX_H = 0x7a,
1057 OPC2_32_RR_MAX_HU = 0x7b,
1058 OPC2_32_RR_MIN = 0x18,
1059 OPC2_32_RR_MIN_U = 0x19,
1060 OPC2_32_RR_MIN_B = 0x58,
1061 OPC2_32_RR_MIN_BU = 0x59,
1062 OPC2_32_RR_MIN_H = 0x78,
1063 OPC2_32_RR_MIN_HU = 0x79,
1064 OPC2_32_RR_MOV = 0x1f,
1065 OPC2_32_RR_NE = 0x11,
1066 OPC2_32_RR_OR_EQ = 0x27,
1067 OPC2_32_RR_OR_GE = 0x2b,
1068 OPC2_32_RR_OR_GE_U = 0x2c,
1069 OPC2_32_RR_OR_LT = 0x29,
1070 OPC2_32_RR_OR_LT_U = 0x2a,
1071 OPC2_32_RR_OR_NE = 0x28,
1072 OPC2_32_RR_SAT_B = 0x5e,
1073 OPC2_32_RR_SAT_BU = 0x5f,
1074 OPC2_32_RR_SAT_H = 0x7e,
1075 OPC2_32_RR_SAT_HU = 0x7f,
1076 OPC2_32_RR_SH_EQ = 0x37,
1077 OPC2_32_RR_SH_GE = 0x3b,
1078 OPC2_32_RR_SH_GE_U = 0x3c,
1079 OPC2_32_RR_SH_LT = 0x39,
1080 OPC2_32_RR_SH_LT_U = 0x3a,
1081 OPC2_32_RR_SH_NE = 0x38,
1082 OPC2_32_RR_SUB = 0x08,
1083 OPC2_32_RR_SUB_B = 0x48,
1084 OPC2_32_RR_SUB_H = 0x68,
1085 OPC2_32_RR_SUBC = 0x0d,
1086 OPC2_32_RR_SUBS = 0x0a,
1087 OPC2_32_RR_SUBS_U = 0x0b,
1088 OPC2_32_RR_SUBS_H = 0x6a,
1089 OPC2_32_RR_SUBS_HU = 0x6b,
1090 OPC2_32_RR_SUBX = 0x0c,
1091 OPC2_32_RR_XOR_EQ = 0x2f,
1092 OPC2_32_RR_XOR_GE = 0x33,
1093 OPC2_32_RR_XOR_GE_U = 0x34,
1094 OPC2_32_RR_XOR_LT = 0x31,
1095 OPC2_32_RR_XOR_LT_U = 0x32,
1096 OPC2_32_RR_XOR_NE = 0x30,
1097 };
1098 /* OPCM_32_RR_ADDRESS */
1099 enum {
1100 OPC2_32_RR_ADD_A = 0x01,
1101 OPC2_32_RR_ADDSC_A = 0x60,
1102 OPC2_32_RR_ADDSC_AT = 0x62,
1103 OPC2_32_RR_EQ_A = 0x40,
1104 OPC2_32_RR_EQZ = 0x48,
1105 OPC2_32_RR_GE_A = 0x43,
1106 OPC2_32_RR_LT_A = 0x42,
1107 OPC2_32_RR_MOV_A = 0x63,
1108 OPC2_32_RR_MOV_AA = 0x00,
1109 OPC2_32_RR_MOV_D = 0x4c,
1110 OPC2_32_RR_NE_A = 0x41,
1111 OPC2_32_RR_NEZ_A = 0x49,
1112 OPC2_32_RR_SUB_A = 0x02,
1113 };
1114 /* OPCM_32_RR_FLOAT */
1115 enum {
1116 OPC2_32_RR_BMERGE = 0x01,
1117 OPC2_32_RR_BSPLIT = 0x09,
1118 OPC2_32_RR_DVINIT_B = 0x5a,
1119 OPC2_32_RR_DVINIT_BU = 0x4a,
1120 OPC2_32_RR_DVINIT_H = 0x3a,
1121 OPC2_32_RR_DVINIT_HU = 0x2a,
1122 OPC2_32_RR_DVINIT = 0x1a,
1123 OPC2_32_RR_DVINIT_U = 0x0a,
1124 OPC2_32_RR_PARITY = 0x02,
1125 OPC2_32_RR_UNPACK = 0x08,
1126 OPC2_32_RR_CRC32 = 0x03,
1127 OPC2_32_RR_DIV = 0x20,
1128 OPC2_32_RR_DIV_U = 0x21,
1129 OPC2_32_RR_MUL_F = 0x04,
1130 OPC2_32_RR_DIV_F = 0x05,
1131 OPC2_32_RR_FTOI = 0x10,
1132 OPC2_32_RR_ITOF = 0x14,
1133 OPC2_32_RR_CMP_F = 0x00,
1134 OPC2_32_RR_FTOIZ = 0x13,
1135 OPC2_32_RR_FTOQ31 = 0x11,
1136 OPC2_32_RR_FTOQ31Z = 0x18,
1137 OPC2_32_RR_FTOU = 0x12,
1138 OPC2_32_RR_FTOUZ = 0x17,
1139 OPC2_32_RR_Q31TOF = 0x15,
1140 OPC2_32_RR_QSEED_F = 0x19,
1141 OPC2_32_RR_UPDFL = 0x0c,
1142 OPC2_32_RR_UTOF = 0x16,
1143 };
1144 /* OPCM_32_RR_IDIRECT */
1145 enum {
1146 OPC2_32_RR_JI = 0x03,
1147 OPC2_32_RR_JLI = 0x02,
1148 OPC2_32_RR_CALLI = 0x00,
1149 OPC2_32_RR_FCALLI = 0x01,
1150 };
1151 /*
1152 * RR1 Format
1153 */
1154 /* OPCM_32_RR1_MUL */
1155 enum {
1156 OPC2_32_RR1_MUL_H_32_LL = 0x1a,
1157 OPC2_32_RR1_MUL_H_32_LU = 0x19,
1158 OPC2_32_RR1_MUL_H_32_UL = 0x18,
1159 OPC2_32_RR1_MUL_H_32_UU = 0x1b,
1160 OPC2_32_RR1_MULM_H_64_LL = 0x1e,
1161 OPC2_32_RR1_MULM_H_64_LU = 0x1d,
1162 OPC2_32_RR1_MULM_H_64_UL = 0x1c,
1163 OPC2_32_RR1_MULM_H_64_UU = 0x1f,
1164 OPC2_32_RR1_MULR_H_16_LL = 0x0e,
1165 OPC2_32_RR1_MULR_H_16_LU = 0x0d,
1166 OPC2_32_RR1_MULR_H_16_UL = 0x0c,
1167 OPC2_32_RR1_MULR_H_16_UU = 0x0f,
1168 };
1169 /* OPCM_32_RR1_MULQ */
1170 enum {
1171 OPC2_32_RR1_MUL_Q_32 = 0x02,
1172 OPC2_32_RR1_MUL_Q_64 = 0x1b,
1173 OPC2_32_RR1_MUL_Q_32_L = 0x01,
1174 OPC2_32_RR1_MUL_Q_64_L = 0x19,
1175 OPC2_32_RR1_MUL_Q_32_U = 0x00,
1176 OPC2_32_RR1_MUL_Q_64_U = 0x18,
1177 OPC2_32_RR1_MUL_Q_32_LL = 0x05,
1178 OPC2_32_RR1_MUL_Q_32_UU = 0x04,
1179 OPC2_32_RR1_MULR_Q_32_L = 0x07,
1180 OPC2_32_RR1_MULR_Q_32_U = 0x06,
1181 };
1182 /*
1183 * RR2 Format
1184 */
1185 /* OPCM_32_RR2_MUL */
1186 enum {
1187 OPC2_32_RR2_MUL_32 = 0x0a,
1188 OPC2_32_RR2_MUL_64 = 0x6a,
1189 OPC2_32_RR2_MULS_32 = 0x8a,
1190 OPC2_32_RR2_MUL_U_64 = 0x68,
1191 OPC2_32_RR2_MULS_U_32 = 0x88,
1192 };
1193 /*
1194 * RRPW Format
1195 */
1196 /* OPCM_32_RRPW_EXTRACT_INSERT */
1197 enum {
1198
1199 OPC2_32_RRPW_EXTR = 0x02,
1200 OPC2_32_RRPW_EXTR_U = 0x03,
1201 OPC2_32_RRPW_IMASK = 0x01,
1202 OPC2_32_RRPW_INSERT = 0x00,
1203 };
1204 /*
1205 * RRR Format
1206 */
1207 /* OPCM_32_RRR_COND_SELECT */
1208 enum {
1209 OPC2_32_RRR_CADD = 0x00,
1210 OPC2_32_RRR_CADDN = 0x01,
1211 OPC2_32_RRR_CSUB = 0x02,
1212 OPC2_32_RRR_CSUBN = 0x03,
1213 OPC2_32_RRR_SEL = 0x04,
1214 OPC2_32_RRR_SELN = 0x05,
1215 };
1216 /* OPCM_32_RRR_FLOAT */
1217 enum {
1218 OPC2_32_RRR_DVADJ = 0x0d,
1219 OPC2_32_RRR_DVSTEP = 0x0f,
1220 OPC2_32_RRR_DVSTEP_U = 0x0e,
1221 OPC2_32_RRR_IXMAX = 0x0a,
1222 OPC2_32_RRR_IXMAX_U = 0x0b,
1223 OPC2_32_RRR_IXMIN = 0x08,
1224 OPC2_32_RRR_IXMIN_U = 0x09,
1225 OPC2_32_RRR_PACK = 0x00,
1226 OPC2_32_RRR_ADD_F = 0x02,
1227 OPC2_32_RRR_SUB_F = 0x03,
1228 OPC2_32_RRR_MADD_F = 0x06,
1229 OPC2_32_RRR_MSUB_F = 0x07,
1230 };
1231 /*
1232 * RRR1 Format
1233 */
1234 /* OPCM_32_RRR1_MADD */
1235 enum {
1236 OPC2_32_RRR1_MADD_H_LL = 0x1a,
1237 OPC2_32_RRR1_MADD_H_LU = 0x19,
1238 OPC2_32_RRR1_MADD_H_UL = 0x18,
1239 OPC2_32_RRR1_MADD_H_UU = 0x1b,
1240 OPC2_32_RRR1_MADDS_H_LL = 0x3a,
1241 OPC2_32_RRR1_MADDS_H_LU = 0x39,
1242 OPC2_32_RRR1_MADDS_H_UL = 0x38,
1243 OPC2_32_RRR1_MADDS_H_UU = 0x3b,
1244 OPC2_32_RRR1_MADDM_H_LL = 0x1e,
1245 OPC2_32_RRR1_MADDM_H_LU = 0x1d,
1246 OPC2_32_RRR1_MADDM_H_UL = 0x1c,
1247 OPC2_32_RRR1_MADDM_H_UU = 0x1f,
1248 OPC2_32_RRR1_MADDMS_H_LL = 0x3e,
1249 OPC2_32_RRR1_MADDMS_H_LU = 0x3d,
1250 OPC2_32_RRR1_MADDMS_H_UL = 0x3c,
1251 OPC2_32_RRR1_MADDMS_H_UU = 0x3f,
1252 OPC2_32_RRR1_MADDR_H_LL = 0x0e,
1253 OPC2_32_RRR1_MADDR_H_LU = 0x0d,
1254 OPC2_32_RRR1_MADDR_H_UL = 0x0c,
1255 OPC2_32_RRR1_MADDR_H_UU = 0x0f,
1256 OPC2_32_RRR1_MADDRS_H_LL = 0x2e,
1257 OPC2_32_RRR1_MADDRS_H_LU = 0x2d,
1258 OPC2_32_RRR1_MADDRS_H_UL = 0x2c,
1259 OPC2_32_RRR1_MADDRS_H_UU = 0x2f,
1260 };
1261 /* OPCM_32_RRR1_MADDQ_H */
1262 enum {
1263 OPC2_32_RRR1_MADD_Q_32 = 0x02,
1264 OPC2_32_RRR1_MADD_Q_64 = 0x1b,
1265 OPC2_32_RRR1_MADD_Q_32_L = 0x01,
1266 OPC2_32_RRR1_MADD_Q_64_L = 0x19,
1267 OPC2_32_RRR1_MADD_Q_32_U = 0x00,
1268 OPC2_32_RRR1_MADD_Q_64_U = 0x18,
1269 OPC2_32_RRR1_MADD_Q_32_LL = 0x05,
1270 OPC2_32_RRR1_MADD_Q_64_LL = 0x1d,
1271 OPC2_32_RRR1_MADD_Q_32_UU = 0x04,
1272 OPC2_32_RRR1_MADD_Q_64_UU = 0x1c,
1273 OPC2_32_RRR1_MADDS_Q_32 = 0x22,
1274 OPC2_32_RRR1_MADDS_Q_64 = 0x3b,
1275 OPC2_32_RRR1_MADDS_Q_32_L = 0x21,
1276 OPC2_32_RRR1_MADDS_Q_64_L = 0x39,
1277 OPC2_32_RRR1_MADDS_Q_32_U = 0x20,
1278 OPC2_32_RRR1_MADDS_Q_64_U = 0x38,
1279 OPC2_32_RRR1_MADDS_Q_32_LL = 0x25,
1280 OPC2_32_RRR1_MADDS_Q_64_LL = 0x3d,
1281 OPC2_32_RRR1_MADDS_Q_32_UU = 0x24,
1282 OPC2_32_RRR1_MADDS_Q_64_UU = 0x3c,
1283 OPC2_32_RRR1_MADDR_H_64_UL = 0x1e,
1284 OPC2_32_RRR1_MADDRS_H_64_UL = 0x3e,
1285 OPC2_32_RRR1_MADDR_Q_32_LL = 0x07,
1286 OPC2_32_RRR1_MADDR_Q_32_UU = 0x06,
1287 OPC2_32_RRR1_MADDRS_Q_32_LL = 0x27,
1288 OPC2_32_RRR1_MADDRS_Q_32_UU = 0x26,
1289 };
1290 /* OPCM_32_RRR1_MADDSU_H */
1291 enum {
1292 OPC2_32_RRR1_MADDSU_H_32_LL = 0x1a,
1293 OPC2_32_RRR1_MADDSU_H_32_LU = 0x19,
1294 OPC2_32_RRR1_MADDSU_H_32_UL = 0x18,
1295 OPC2_32_RRR1_MADDSU_H_32_UU = 0x1b,
1296 OPC2_32_RRR1_MADDSUS_H_32_LL = 0x3a,
1297 OPC2_32_RRR1_MADDSUS_H_32_LU = 0x39,
1298 OPC2_32_RRR1_MADDSUS_H_32_UL = 0x38,
1299 OPC2_32_RRR1_MADDSUS_H_32_UU = 0x3b,
1300 OPC2_32_RRR1_MADDSUM_H_64_LL = 0x1e,
1301 OPC2_32_RRR1_MADDSUM_H_64_LU = 0x1d,
1302 OPC2_32_RRR1_MADDSUM_H_64_UL = 0x1c,
1303 OPC2_32_RRR1_MADDSUM_H_64_UU = 0x1f,
1304 OPC2_32_RRR1_MADDSUMS_H_64_LL = 0x3e,
1305 OPC2_32_RRR1_MADDSUMS_H_64_LU = 0x3d,
1306 OPC2_32_RRR1_MADDSUMS_H_64_UL = 0x3c,
1307 OPC2_32_RRR1_MADDSUMS_H_64_UU = 0x3f,
1308 OPC2_32_RRR1_MADDSUR_H_16_LL = 0x0e,
1309 OPC2_32_RRR1_MADDSUR_H_16_LU = 0x0d,
1310 OPC2_32_RRR1_MADDSUR_H_16_UL = 0x0c,
1311 OPC2_32_RRR1_MADDSUR_H_16_UU = 0x0f,
1312 OPC2_32_RRR1_MADDSURS_H_16_LL = 0x2e,
1313 OPC2_32_RRR1_MADDSURS_H_16_LU = 0x2d,
1314 OPC2_32_RRR1_MADDSURS_H_16_UL = 0x2c,
1315 OPC2_32_RRR1_MADDSURS_H_16_UU = 0x2f,
1316 };
1317 /* OPCM_32_RRR1_MSUB_H */
1318 enum {
1319 OPC2_32_RRR1_MSUB_H_LL = 0x1a,
1320 OPC2_32_RRR1_MSUB_H_LU = 0x19,
1321 OPC2_32_RRR1_MSUB_H_UL = 0x18,
1322 OPC2_32_RRR1_MSUB_H_UU = 0x1b,
1323 OPC2_32_RRR1_MSUBS_H_LL = 0x3a,
1324 OPC2_32_RRR1_MSUBS_H_LU = 0x39,
1325 OPC2_32_RRR1_MSUBS_H_UL = 0x38,
1326 OPC2_32_RRR1_MSUBS_H_UU = 0x3b,
1327 OPC2_32_RRR1_MSUBM_H_LL = 0x1e,
1328 OPC2_32_RRR1_MSUBM_H_LU = 0x1d,
1329 OPC2_32_RRR1_MSUBM_H_UL = 0x1c,
1330 OPC2_32_RRR1_MSUBM_H_UU = 0x1f,
1331 OPC2_32_RRR1_MSUBMS_H_LL = 0x3e,
1332 OPC2_32_RRR1_MSUBMS_H_LU = 0x3d,
1333 OPC2_32_RRR1_MSUBMS_H_UL = 0x3c,
1334 OPC2_32_RRR1_MSUBMS_H_UU = 0x3f,
1335 OPC2_32_RRR1_MSUBR_H_LL = 0x0e,
1336 OPC2_32_RRR1_MSUBR_H_LU = 0x0d,
1337 OPC2_32_RRR1_MSUBR_H_UL = 0x0c,
1338 OPC2_32_RRR1_MSUBR_H_UU = 0x0f,
1339 OPC2_32_RRR1_MSUBRS_H_LL = 0x2e,
1340 OPC2_32_RRR1_MSUBRS_H_LU = 0x2d,
1341 OPC2_32_RRR1_MSUBRS_H_UL = 0x2c,
1342 OPC2_32_RRR1_MSUBRS_H_UU = 0x2f,
1343 };
1344 /* OPCM_32_RRR1_MSUB_Q */
1345 enum {
1346 OPC2_32_RRR1_MSUB_Q_32 = 0x02,
1347 OPC2_32_RRR1_MSUB_Q_64 = 0x1b,
1348 OPC2_32_RRR1_MSUB_Q_32_L = 0x01,
1349 OPC2_32_RRR1_MSUB_Q_64_L = 0x19,
1350 OPC2_32_RRR1_MSUB_Q_32_U = 0x00,
1351 OPC2_32_RRR1_MSUB_Q_64_U = 0x18,
1352 OPC2_32_RRR1_MSUB_Q_32_LL = 0x05,
1353 OPC2_32_RRR1_MSUB_Q_64_LL = 0x1d,
1354 OPC2_32_RRR1_MSUB_Q_32_UU = 0x04,
1355 OPC2_32_RRR1_MSUB_Q_64_UU = 0x1c,
1356 OPC2_32_RRR1_MSUBS_Q_32 = 0x22,
1357 OPC2_32_RRR1_MSUBS_Q_64 = 0x3b,
1358 OPC2_32_RRR1_MSUBS_Q_32_L = 0x21,
1359 OPC2_32_RRR1_MSUBS_Q_64_L = 0x39,
1360 OPC2_32_RRR1_MSUBS_Q_32_U = 0x20,
1361 OPC2_32_RRR1_MSUBS_Q_64_U = 0x38,
1362 OPC2_32_RRR1_MSUBS_Q_32_LL = 0x25,
1363 OPC2_32_RRR1_MSUBS_Q_64_LL = 0x3d,
1364 OPC2_32_RRR1_MSUBS_Q_32_UU = 0x24,
1365 OPC2_32_RRR1_MSUBS_Q_64_UU = 0x3c,
1366 OPC2_32_RRR1_MSUBR_H_64_UL = 0x1e,
1367 OPC2_32_RRR1_MSUBRS_H_64_UL = 0x3e,
1368 OPC2_32_RRR1_MSUBR_Q_32_LL = 0x07,
1369 OPC2_32_RRR1_MSUBR_Q_32_UU = 0x06,
1370 OPC2_32_RRR1_MSUBRS_Q_32_LL = 0x27,
1371 OPC2_32_RRR1_MSUBRS_Q_32_UU = 0x26,
1372 };
1373 /* OPCM_32_RRR1_MSUBADS_H */
1374 enum {
1375 OPC2_32_RRR1_MSUBAD_H_32_LL = 0x1a,
1376 OPC2_32_RRR1_MSUBAD_H_32_LU = 0x19,
1377 OPC2_32_RRR1_MSUBAD_H_32_UL = 0x18,
1378 OPC2_32_RRR1_MSUBAD_H_32_UU = 0x1b,
1379 OPC2_32_RRR1_MSUBADS_H_32_LL = 0x3a,
1380 OPC2_32_RRR1_MSUBADS_H_32_LU = 0x39,
1381 OPC2_32_RRR1_MSUBADS_H_32_UL = 0x38,
1382 OPC2_32_RRR1_MSUBADS_H_32_UU = 0x3b,
1383 OPC2_32_RRR1_MSUBADM_H_64_LL = 0x1e,
1384 OPC2_32_RRR1_MSUBADM_H_64_LU = 0x1d,
1385 OPC2_32_RRR1_MSUBADM_H_64_UL = 0x1c,
1386 OPC2_32_RRR1_MSUBADM_H_64_UU = 0x1f,
1387 OPC2_32_RRR1_MSUBADMS_H_64_LL = 0x3e,
1388 OPC2_32_RRR1_MSUBADMS_H_64_LU = 0x3d,
1389 OPC2_32_RRR1_MSUBADMS_H_64_UL = 0x3c,
1390 OPC2_32_RRR1_MSUBADMS_H_64_UU = 0x3f,
1391 OPC2_32_RRR1_MSUBADR_H_16_LL = 0x0e,
1392 OPC2_32_RRR1_MSUBADR_H_16_LU = 0x0d,
1393 OPC2_32_RRR1_MSUBADR_H_16_UL = 0x0c,
1394 OPC2_32_RRR1_MSUBADR_H_16_UU = 0x0f,
1395 OPC2_32_RRR1_MSUBADRS_H_16_LL = 0x2e,
1396 OPC2_32_RRR1_MSUBADRS_H_16_LU = 0x2d,
1397 OPC2_32_RRR1_MSUBADRS_H_16_UL = 0x2c,
1398 OPC2_32_RRR1_MSUBADRS_H_16_UU = 0x2f,
1399 };
1400 /*
1401 * RRR2 Format
1402 */
1403 /* OPCM_32_RRR2_MADD */
1404 enum {
1405 OPC2_32_RRR2_MADD_32 = 0x0a,
1406 OPC2_32_RRR2_MADD_64 = 0x6a,
1407 OPC2_32_RRR2_MADDS_32 = 0x8a,
1408 OPC2_32_RRR2_MADDS_64 = 0xea,
1409 OPC2_32_RRR2_MADD_U_64 = 0x68,
1410 OPC2_32_RRR2_MADDS_U_32 = 0x88,
1411 OPC2_32_RRR2_MADDS_U_64 = 0xe8,
1412 };
1413 /* OPCM_32_RRR2_MSUB */
1414 enum {
1415 OPC2_32_RRR2_MSUB_32 = 0x0a,
1416 OPC2_32_RRR2_MSUB_64 = 0x6a,
1417 OPC2_32_RRR2_MSUBS_32 = 0x8a,
1418 OPC2_32_RRR2_MSUBS_64 = 0xea,
1419 OPC2_32_RRR2_MSUB_U_64 = 0x68,
1420 OPC2_32_RRR2_MSUBS_U_32 = 0x88,
1421 OPC2_32_RRR2_MSUBS_U_64 = 0xe8,
1422 };
1423 /*
1424 * RRRR Format
1425 */
1426 /* OPCM_32_RRRR_EXTRACT_INSERT */
1427 enum {
1428 OPC2_32_RRRR_DEXTR = 0x04,
1429 OPC2_32_RRRR_EXTR = 0x02,
1430 OPC2_32_RRRR_EXTR_U = 0x03,
1431 OPC2_32_RRRR_INSERT = 0x00,
1432 };
1433 /*
1434 * RRRW Format
1435 */
1436 /* OPCM_32_RRRW_EXTRACT_INSERT */
1437 enum {
1438 OPC2_32_RRRW_EXTR = 0x02,
1439 OPC2_32_RRRW_EXTR_U = 0x03,
1440 OPC2_32_RRRW_IMASK = 0x01,
1441 OPC2_32_RRRW_INSERT = 0x00,
1442 };
1443 /*
1444 * SYS Format
1445 */
1446 /* OPCM_32_SYS_INTERRUPTS */
1447 enum {
1448 OPC2_32_SYS_DEBUG = 0x04,
1449 OPC2_32_SYS_DISABLE = 0x0d,
1450 OPC2_32_SYS_DSYNC = 0x12,
1451 OPC2_32_SYS_ENABLE = 0x0c,
1452 OPC2_32_SYS_ISYNC = 0x13,
1453 OPC2_32_SYS_NOP = 0x00,
1454 OPC2_32_SYS_RET = 0x06,
1455 OPC2_32_SYS_RFE = 0x07,
1456 OPC2_32_SYS_RFM = 0x05,
1457 OPC2_32_SYS_RSLCX = 0x09,
1458 OPC2_32_SYS_SVLCX = 0x08,
1459 OPC2_32_SYS_TRAPSV = 0x15,
1460 OPC2_32_SYS_TRAPV = 0x14,
1461 OPC2_32_SYS_RESTORE = 0x0e,
1462 OPC2_32_SYS_FRET = 0x03,
1463 };
AR7 emulation for QEMU