2 * ARM GICv3 support - common bits of emulated and KVM kernel model
4 * Copyright (c) 2012 Linaro Limited
5 * Copyright (c) 2015 Huawei.
6 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
7 * Written by Peter Maydell
8 * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation, either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
27 #include "hw/intc/arm_gicv3_common.h"
28 #include "gicv3_internal.h"
29 #include "hw/arm/linux-boot-if.h"
31 static void gicv3_pre_save(void *opaque
)
33 GICv3State
*s
= (GICv3State
*)opaque
;
34 ARMGICv3CommonClass
*c
= ARM_GICV3_COMMON_GET_CLASS(s
);
41 static int gicv3_post_load(void *opaque
, int version_id
)
43 GICv3State
*s
= (GICv3State
*)opaque
;
44 ARMGICv3CommonClass
*c
= ARM_GICV3_COMMON_GET_CLASS(s
);
52 static const VMStateDescription vmstate_gicv3
= {
55 .pre_save
= gicv3_pre_save
,
56 .post_load
= gicv3_post_load
,
59 void gicv3_init_irqs_and_mmio(GICv3State
*s
, qemu_irq_handler handler
,
60 const MemoryRegionOps
*ops
)
62 SysBusDevice
*sbd
= SYS_BUS_DEVICE(s
);
65 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
66 * GPIO array layout is thus:
68 * [N..N+31] PPIs for CPU 0
69 * [N+32..N+63] PPIs for CPU 1
72 i
= s
->num_irq
- GIC_INTERNAL
+ GIC_INTERNAL
* s
->num_cpu
;
73 qdev_init_gpio_in(DEVICE(s
), handler
, i
);
75 s
->parent_irq
= g_malloc(s
->num_cpu
* sizeof(qemu_irq
));
76 s
->parent_fiq
= g_malloc(s
->num_cpu
* sizeof(qemu_irq
));
78 for (i
= 0; i
< s
->num_cpu
; i
++) {
79 sysbus_init_irq(sbd
, &s
->parent_irq
[i
]);
81 for (i
= 0; i
< s
->num_cpu
; i
++) {
82 sysbus_init_irq(sbd
, &s
->parent_fiq
[i
]);
85 memory_region_init_io(&s
->iomem_dist
, OBJECT(s
), ops
, s
,
86 "gicv3_dist", 0x10000);
87 memory_region_init_io(&s
->iomem_redist
, OBJECT(s
), ops
? &ops
[1] : NULL
, s
,
88 "gicv3_redist", 0x20000 * s
->num_cpu
);
90 sysbus_init_mmio(sbd
, &s
->iomem_dist
);
91 sysbus_init_mmio(sbd
, &s
->iomem_redist
);
94 static void arm_gicv3_common_realize(DeviceState
*dev
, Error
**errp
)
96 GICv3State
*s
= ARM_GICV3_COMMON(dev
);
99 /* revision property is actually reserved and currently used only in order
100 * to keep the interface compatible with GICv2 code, avoiding extra
101 * conditions. However, in future it could be used, for example, if we
104 if (s
->revision
!= 3) {
105 error_setg(errp
, "unsupported GIC revision %d", s
->revision
);
109 if (s
->num_irq
> GICV3_MAXIRQ
) {
111 "requested %u interrupt lines exceeds GIC maximum %d",
112 s
->num_irq
, GICV3_MAXIRQ
);
115 if (s
->num_irq
< GIC_INTERNAL
) {
117 "requested %u interrupt lines is below GIC minimum %d",
118 s
->num_irq
, GIC_INTERNAL
);
122 /* ITLinesNumber is represented as (N / 32) - 1, so this is an
123 * implementation imposed restriction, not an architectural one,
124 * so we don't have to deal with bitfields where only some of the
125 * bits in a 32-bit word should be valid.
127 if (s
->num_irq
% 32) {
129 "%d interrupt lines unsupported: not divisible by 32",
134 s
->cpu
= g_new0(GICv3CPUState
, s
->num_cpu
);
136 for (i
= 0; i
< s
->num_cpu
; i
++) {
137 CPUState
*cpu
= qemu_get_cpu(i
);
144 /* Pre-construct the GICR_TYPER:
145 * For our implementation:
146 * Top 32 bits are the affinity value of the associated CPU
147 * CommonLPIAff == 01 (redistributors with same Aff3 share LPI table)
148 * Processor_Number == CPU index starting from 0
149 * DPGS == 0 (GICR_CTLR.DPG* not supported)
150 * Last == 1 if this is the last redistributor in a series of
151 * contiguous redistributor pages
152 * DirectLPI == 0 (direct injection of LPIs not supported)
153 * VLPIS == 0 (virtual LPIs not supported)
154 * PLPIS == 0 (physical LPIs not supported)
156 cpu_affid
= object_property_get_int(OBJECT(cpu
), "mp-affinity", NULL
);
157 last
= (i
== s
->num_cpu
- 1);
159 /* The CPU mp-affinity property is in MPIDR register format; squash
160 * the affinity bytes into 32 bits as the GICR_TYPER has them.
162 cpu_affid
= (cpu_affid
& 0xFF00000000ULL
>> 8) | (cpu_affid
& 0xFFFFFF);
163 s
->cpu
[i
].gicr_typer
= (cpu_affid
<< 32) |
170 static void arm_gicv3_common_reset(DeviceState
*dev
)
172 GICv3State
*s
= ARM_GICV3_COMMON(dev
);
175 for (i
= 0; i
< s
->num_cpu
; i
++) {
176 GICv3CPUState
*cs
= &s
->cpu
[i
];
180 cs
->gicr_statusr
[GICV3_S
] = 0;
181 cs
->gicr_statusr
[GICV3_NS
] = 0;
182 cs
->gicr_waker
= GICR_WAKER_ProcessorSleep
| GICR_WAKER_ChildrenAsleep
;
183 cs
->gicr_propbaser
= 0;
184 cs
->gicr_pendbaser
= 0;
185 /* If we're resetting a TZ-aware GIC as if secure firmware
186 * had set it up ready to start a kernel in non-secure, we
187 * need to set interrupts to group 1 so the kernel can use them.
188 * Otherwise they reset to group 0 like the hardware.
190 if (s
->irq_reset_nonsecure
) {
191 cs
->gicr_igroupr0
= 0xffffffff;
193 cs
->gicr_igroupr0
= 0;
196 cs
->gicr_ienabler0
= 0;
197 cs
->gicr_ipendr0
= 0;
198 cs
->gicr_iactiver0
= 0;
199 cs
->edge_trigger
= 0xffff;
200 cs
->gicr_igrpmodr0
= 0;
202 memset(cs
->gicr_ipriorityr
, 0, sizeof(cs
->gicr_ipriorityr
));
204 /* State in the CPU interface must *not* be reset here, because it
205 * is part of the CPU's reset domain, not the GIC device's.
209 /* For our implementation affinity routing is always enabled */
210 if (s
->security_extn
) {
211 s
->gicd_ctlr
= GICD_CTLR_ARE_S
| GICD_CTLR_ARE_NS
;
213 s
->gicd_ctlr
= GICD_CTLR_DS
| GICD_CTLR_ARE
;
216 s
->gicd_statusr
[GICV3_S
] = 0;
217 s
->gicd_statusr
[GICV3_NS
] = 0;
219 memset(s
->group
, 0, sizeof(s
->group
));
220 memset(s
->grpmod
, 0, sizeof(s
->grpmod
));
221 memset(s
->enabled
, 0, sizeof(s
->enabled
));
222 memset(s
->pending
, 0, sizeof(s
->pending
));
223 memset(s
->active
, 0, sizeof(s
->active
));
224 memset(s
->level
, 0, sizeof(s
->level
));
225 memset(s
->edge_trigger
, 0, sizeof(s
->edge_trigger
));
226 memset(s
->gicd_ipriority
, 0, sizeof(s
->gicd_ipriority
));
227 memset(s
->gicd_irouter
, 0, sizeof(s
->gicd_irouter
));
228 memset(s
->gicd_nsacr
, 0, sizeof(s
->gicd_nsacr
));
230 if (s
->irq_reset_nonsecure
) {
231 /* If we're resetting a TZ-aware GIC as if secure firmware
232 * had set it up ready to start a kernel in non-secure, we
233 * need to set interrupts to group 1 so the kernel can use them.
234 * Otherwise they reset to group 0 like the hardware.
236 for (i
= GIC_INTERNAL
; i
< s
->num_irq
; i
++) {
237 gicv3_gicd_group_set(s
, i
);
242 static void arm_gic_common_linux_init(ARMLinuxBootIf
*obj
,
245 GICv3State
*s
= ARM_GICV3_COMMON(obj
);
247 if (s
->security_extn
&& !secure_boot
) {
248 /* We're directly booting a kernel into NonSecure. If this GIC
249 * implements the security extensions then we must configure it
250 * to have all the interrupts be NonSecure (this is a job that
251 * is done by the Secure boot firmware in real hardware, and in
252 * this mode QEMU is acting as a minimalist firmware-and-bootloader
255 s
->irq_reset_nonsecure
= true;
259 static Property arm_gicv3_common_properties
[] = {
260 DEFINE_PROP_UINT32("num-cpu", GICv3State
, num_cpu
, 1),
261 DEFINE_PROP_UINT32("num-irq", GICv3State
, num_irq
, 32),
262 DEFINE_PROP_UINT32("revision", GICv3State
, revision
, 3),
263 DEFINE_PROP_BOOL("has-security-extensions", GICv3State
, security_extn
, 0),
264 DEFINE_PROP_END_OF_LIST(),
267 static void arm_gicv3_common_class_init(ObjectClass
*klass
, void *data
)
269 DeviceClass
*dc
= DEVICE_CLASS(klass
);
270 ARMLinuxBootIfClass
*albifc
= ARM_LINUX_BOOT_IF_CLASS(klass
);
272 dc
->reset
= arm_gicv3_common_reset
;
273 dc
->realize
= arm_gicv3_common_realize
;
274 dc
->props
= arm_gicv3_common_properties
;
275 dc
->vmsd
= &vmstate_gicv3
;
276 albifc
->arm_linux_init
= arm_gic_common_linux_init
;
279 static const TypeInfo arm_gicv3_common_type
= {
280 .name
= TYPE_ARM_GICV3_COMMON
,
281 .parent
= TYPE_SYS_BUS_DEVICE
,
282 .instance_size
= sizeof(GICv3State
),
283 .class_size
= sizeof(ARMGICv3CommonClass
),
284 .class_init
= arm_gicv3_common_class_init
,
286 .interfaces
= (InterfaceInfo
[]) {
287 { TYPE_ARM_LINUX_BOOT_IF
},
292 static void register_types(void)
294 type_register_static(&arm_gicv3_common_type
);
297 type_init(register_types
)