sun4u: expose fw_cfg and NVRAM on ebus PCI IO address space
[qemu/ar7.git] / include / exec / cpu-common.h
blob74341b19d26a5d140d26f0161d92b58a67508cc0
1 #ifndef CPU_COMMON_H
2 #define CPU_COMMON_H
4 /* CPU interfaces that are target independent. */
6 #ifndef CONFIG_USER_ONLY
7 #include "exec/hwaddr.h"
8 #endif
10 #include "qemu/bswap.h"
11 #include "qemu/queue.h"
12 #include "qemu/fprintf-fn.h"
14 /**
15 * CPUListState:
16 * @cpu_fprintf: Print function.
17 * @file: File to print to using @cpu_fprint.
19 * State commonly used for iterating over CPU models.
21 typedef struct CPUListState {
22 fprintf_function cpu_fprintf;
23 FILE *file;
24 } CPUListState;
26 /* The CPU list lock nests outside tb_lock/tb_unlock. */
27 void qemu_init_cpu_list(void);
28 void cpu_list_lock(void);
29 void cpu_list_unlock(void);
31 void tcg_flush_softmmu_tlb(CPUState *cs);
33 #if !defined(CONFIG_USER_ONLY)
35 enum device_endian {
36 DEVICE_NATIVE_ENDIAN,
37 DEVICE_BIG_ENDIAN,
38 DEVICE_LITTLE_ENDIAN,
41 #if defined(HOST_WORDS_BIGENDIAN)
42 #define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN
43 #else
44 #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN
45 #endif
47 /* address in the RAM (different from a physical address) */
48 #if defined(CONFIG_XEN_BACKEND)
49 typedef uint64_t ram_addr_t;
50 # define RAM_ADDR_MAX UINT64_MAX
51 # define RAM_ADDR_FMT "%" PRIx64
52 #else
53 typedef uintptr_t ram_addr_t;
54 # define RAM_ADDR_MAX UINTPTR_MAX
55 # define RAM_ADDR_FMT "%" PRIxPTR
56 #endif
58 extern ram_addr_t ram_size;
60 /* memory API */
62 typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value);
63 typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr);
65 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
66 /* This should not be used by devices. */
67 ram_addr_t qemu_ram_addr_from_host(void *ptr);
68 RAMBlock *qemu_ram_block_by_name(const char *name);
69 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
70 ram_addr_t *offset);
71 void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev);
72 void qemu_ram_unset_idstr(RAMBlock *block);
73 const char *qemu_ram_get_idstr(RAMBlock *rb);
74 bool qemu_ram_is_shared(RAMBlock *rb);
75 size_t qemu_ram_pagesize(RAMBlock *block);
76 size_t qemu_ram_pagesize_largest(void);
78 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
79 int len, int is_write);
80 static inline void cpu_physical_memory_read(hwaddr addr,
81 void *buf, int len)
83 cpu_physical_memory_rw(addr, buf, len, 0);
85 static inline void cpu_physical_memory_write(hwaddr addr,
86 const void *buf, int len)
88 cpu_physical_memory_rw(addr, (void *)buf, len, 1);
90 void *cpu_physical_memory_map(hwaddr addr,
91 hwaddr *plen,
92 int is_write);
93 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
94 int is_write, hwaddr access_len);
95 void cpu_register_map_client(QEMUBH *bh);
96 void cpu_unregister_map_client(QEMUBH *bh);
98 bool cpu_physical_memory_is_io(hwaddr phys_addr);
100 /* Coalesced MMIO regions are areas where write operations can be reordered.
101 * This usually implies that write operations are side-effect free. This allows
102 * batching which can make a major impact on performance when using
103 * virtualization.
105 void qemu_flush_coalesced_mmio_buffer(void);
107 void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
108 const uint8_t *buf, int len);
109 void cpu_flush_icache_range(hwaddr start, int len);
111 extern struct MemoryRegion io_mem_rom;
112 extern struct MemoryRegion io_mem_notdirty;
114 typedef int (RAMBlockIterFunc)(const char *block_name, void *host_addr,
115 ram_addr_t offset, ram_addr_t length, void *opaque);
117 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque);
118 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length);
120 #endif
122 #endif /* CPU_COMMON_H */