2 * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
4 * Copyright (c) 2003-2005, 2007, 2017 Jocelyn Mayer
5 * Copyright (c) 2013 Hervé Poussineau
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
27 #include "hw/timer/m48t59.h"
28 #include "qemu/timer.h"
29 #include "sysemu/sysemu.h"
30 #include "hw/sysbus.h"
31 #include "exec/address-spaces.h"
34 #include "m48t59-internal.h"
36 #define TYPE_M48TXX_SYS_BUS "sysbus-m48txx"
37 #define M48TXX_SYS_BUS_GET_CLASS(obj) \
38 OBJECT_GET_CLASS(M48txxSysBusDeviceClass, (obj), TYPE_M48TXX_SYS_BUS)
39 #define M48TXX_SYS_BUS_CLASS(klass) \
40 OBJECT_CLASS_CHECK(M48txxSysBusDeviceClass, (klass), TYPE_M48TXX_SYS_BUS)
41 #define M48TXX_SYS_BUS(obj) \
42 OBJECT_CHECK(M48txxSysBusState, (obj), TYPE_M48TXX_SYS_BUS)
46 * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
47 * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
48 * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
51 typedef struct M48txxSysBusState
{
52 SysBusDevice parent_obj
;
57 typedef struct M48txxSysBusDeviceClass
{
58 SysBusDeviceClass parent_class
;
60 } M48txxSysBusDeviceClass
;
62 static M48txxInfo m48txx_sysbus_info
[] = {
64 .bus_name
= "sysbus-m48t02",
68 .bus_name
= "sysbus-m48t08",
72 .bus_name
= "sysbus-m48t59",
79 /* Fake timer functions */
81 /* Alarm management */
82 static void alarm_cb (void *opaque
)
86 M48t59State
*NVRAM
= opaque
;
88 qemu_set_irq(NVRAM
->IRQ
, 1);
89 if ((NVRAM
->buffer
[0x1FF5] & 0x80) == 0 &&
90 (NVRAM
->buffer
[0x1FF4] & 0x80) == 0 &&
91 (NVRAM
->buffer
[0x1FF3] & 0x80) == 0 &&
92 (NVRAM
->buffer
[0x1FF2] & 0x80) == 0) {
93 /* Repeat once a month */
94 qemu_get_timedate(&tm
, NVRAM
->time_offset
);
96 if (tm
.tm_mon
== 13) {
100 next_time
= qemu_timedate_diff(&tm
) - NVRAM
->time_offset
;
101 } else if ((NVRAM
->buffer
[0x1FF5] & 0x80) != 0 &&
102 (NVRAM
->buffer
[0x1FF4] & 0x80) == 0 &&
103 (NVRAM
->buffer
[0x1FF3] & 0x80) == 0 &&
104 (NVRAM
->buffer
[0x1FF2] & 0x80) == 0) {
105 /* Repeat once a day */
106 next_time
= 24 * 60 * 60;
107 } else if ((NVRAM
->buffer
[0x1FF5] & 0x80) != 0 &&
108 (NVRAM
->buffer
[0x1FF4] & 0x80) != 0 &&
109 (NVRAM
->buffer
[0x1FF3] & 0x80) == 0 &&
110 (NVRAM
->buffer
[0x1FF2] & 0x80) == 0) {
111 /* Repeat once an hour */
113 } else if ((NVRAM
->buffer
[0x1FF5] & 0x80) != 0 &&
114 (NVRAM
->buffer
[0x1FF4] & 0x80) != 0 &&
115 (NVRAM
->buffer
[0x1FF3] & 0x80) != 0 &&
116 (NVRAM
->buffer
[0x1FF2] & 0x80) == 0) {
117 /* Repeat once a minute */
120 /* Repeat once a second */
123 timer_mod(NVRAM
->alrm_timer
, qemu_clock_get_ns(rtc_clock
) +
125 qemu_set_irq(NVRAM
->IRQ
, 0);
128 static void set_alarm(M48t59State
*NVRAM
)
131 if (NVRAM
->alrm_timer
!= NULL
) {
132 timer_del(NVRAM
->alrm_timer
);
133 diff
= qemu_timedate_diff(&NVRAM
->alarm
) - NVRAM
->time_offset
;
135 timer_mod(NVRAM
->alrm_timer
, diff
* 1000);
139 /* RTC management helpers */
140 static inline void get_time(M48t59State
*NVRAM
, struct tm
*tm
)
142 qemu_get_timedate(tm
, NVRAM
->time_offset
);
145 static void set_time(M48t59State
*NVRAM
, struct tm
*tm
)
147 NVRAM
->time_offset
= qemu_timedate_diff(tm
);
151 /* Watchdog management */
152 static void watchdog_cb (void *opaque
)
154 M48t59State
*NVRAM
= opaque
;
156 NVRAM
->buffer
[0x1FF0] |= 0x80;
157 if (NVRAM
->buffer
[0x1FF7] & 0x80) {
158 NVRAM
->buffer
[0x1FF7] = 0x00;
159 NVRAM
->buffer
[0x1FFC] &= ~0x40;
160 /* May it be a hw CPU Reset instead ? */
161 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
163 qemu_set_irq(NVRAM
->IRQ
, 1);
164 qemu_set_irq(NVRAM
->IRQ
, 0);
168 static void set_up_watchdog(M48t59State
*NVRAM
, uint8_t value
)
170 uint64_t interval
; /* in 1/16 seconds */
172 NVRAM
->buffer
[0x1FF0] &= ~0x80;
173 if (NVRAM
->wd_timer
!= NULL
) {
174 timer_del(NVRAM
->wd_timer
);
176 interval
= (1 << (2 * (value
& 0x03))) * ((value
>> 2) & 0x1F);
177 timer_mod(NVRAM
->wd_timer
, ((uint64_t)time(NULL
) * 1000) +
178 ((interval
* 1000) >> 4));
183 /* Direct access to NVRAM */
184 void m48t59_write(M48t59State
*NVRAM
, uint32_t addr
, uint32_t val
)
189 if (addr
> 0x1FF8 && addr
< 0x2000)
190 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__
, addr
, val
);
192 /* check for NVRAM access */
193 if ((NVRAM
->model
== 2 && addr
< 0x7f8) ||
194 (NVRAM
->model
== 8 && addr
< 0x1ff8) ||
195 (NVRAM
->model
== 59 && addr
< 0x1ff0)) {
202 /* flags register : read-only */
209 tmp
= from_bcd(val
& 0x7F);
210 if (tmp
>= 0 && tmp
<= 59) {
211 NVRAM
->alarm
.tm_sec
= tmp
;
212 NVRAM
->buffer
[0x1FF2] = val
;
218 tmp
= from_bcd(val
& 0x7F);
219 if (tmp
>= 0 && tmp
<= 59) {
220 NVRAM
->alarm
.tm_min
= tmp
;
221 NVRAM
->buffer
[0x1FF3] = val
;
227 tmp
= from_bcd(val
& 0x3F);
228 if (tmp
>= 0 && tmp
<= 23) {
229 NVRAM
->alarm
.tm_hour
= tmp
;
230 NVRAM
->buffer
[0x1FF4] = val
;
236 tmp
= from_bcd(val
& 0x3F);
238 NVRAM
->alarm
.tm_mday
= tmp
;
239 NVRAM
->buffer
[0x1FF5] = val
;
245 NVRAM
->buffer
[0x1FF6] = val
;
249 NVRAM
->buffer
[0x1FF7] = val
;
250 set_up_watchdog(NVRAM
, val
);
255 NVRAM
->buffer
[addr
] = (val
& ~0xA0) | 0x90;
260 tmp
= from_bcd(val
& 0x7F);
261 if (tmp
>= 0 && tmp
<= 59) {
262 get_time(NVRAM
, &tm
);
264 set_time(NVRAM
, &tm
);
266 if ((val
& 0x80) ^ (NVRAM
->buffer
[addr
] & 0x80)) {
268 NVRAM
->stop_time
= time(NULL
);
270 NVRAM
->time_offset
+= NVRAM
->stop_time
- time(NULL
);
271 NVRAM
->stop_time
= 0;
274 NVRAM
->buffer
[addr
] = val
& 0x80;
279 tmp
= from_bcd(val
& 0x7F);
280 if (tmp
>= 0 && tmp
<= 59) {
281 get_time(NVRAM
, &tm
);
283 set_time(NVRAM
, &tm
);
289 tmp
= from_bcd(val
& 0x3F);
290 if (tmp
>= 0 && tmp
<= 23) {
291 get_time(NVRAM
, &tm
);
293 set_time(NVRAM
, &tm
);
298 /* day of the week / century */
299 tmp
= from_bcd(val
& 0x07);
300 get_time(NVRAM
, &tm
);
302 set_time(NVRAM
, &tm
);
303 NVRAM
->buffer
[addr
] = val
& 0x40;
308 tmp
= from_bcd(val
& 0x3F);
310 get_time(NVRAM
, &tm
);
312 set_time(NVRAM
, &tm
);
318 tmp
= from_bcd(val
& 0x1F);
319 if (tmp
>= 1 && tmp
<= 12) {
320 get_time(NVRAM
, &tm
);
322 set_time(NVRAM
, &tm
);
329 if (tmp
>= 0 && tmp
<= 99) {
330 get_time(NVRAM
, &tm
);
331 tm
.tm_year
= from_bcd(val
) + NVRAM
->base_year
- 1900;
332 set_time(NVRAM
, &tm
);
336 /* Check lock registers state */
337 if (addr
>= 0x20 && addr
<= 0x2F && (NVRAM
->lock
& 1))
339 if (addr
>= 0x30 && addr
<= 0x3F && (NVRAM
->lock
& 2))
342 if (addr
< NVRAM
->size
) {
343 NVRAM
->buffer
[addr
] = val
& 0xFF;
349 uint32_t m48t59_read(M48t59State
*NVRAM
, uint32_t addr
)
352 uint32_t retval
= 0xFF;
354 /* check for NVRAM access */
355 if ((NVRAM
->model
== 2 && addr
< 0x078f) ||
356 (NVRAM
->model
== 8 && addr
< 0x1ff8) ||
357 (NVRAM
->model
== 59 && addr
< 0x1ff0)) {
386 /* A read resets the watchdog */
387 set_up_watchdog(NVRAM
, NVRAM
->buffer
[0x1FF7]);
396 get_time(NVRAM
, &tm
);
397 retval
= (NVRAM
->buffer
[addr
] & 0x80) | to_bcd(tm
.tm_sec
);
402 get_time(NVRAM
, &tm
);
403 retval
= to_bcd(tm
.tm_min
);
408 get_time(NVRAM
, &tm
);
409 retval
= to_bcd(tm
.tm_hour
);
413 /* day of the week / century */
414 get_time(NVRAM
, &tm
);
415 retval
= NVRAM
->buffer
[addr
] | tm
.tm_wday
;
420 get_time(NVRAM
, &tm
);
421 retval
= to_bcd(tm
.tm_mday
);
426 get_time(NVRAM
, &tm
);
427 retval
= to_bcd(tm
.tm_mon
+ 1);
432 get_time(NVRAM
, &tm
);
433 retval
= to_bcd((tm
.tm_year
+ 1900 - NVRAM
->base_year
) % 100);
436 /* Check lock registers state */
437 if (addr
>= 0x20 && addr
<= 0x2F && (NVRAM
->lock
& 1))
439 if (addr
>= 0x30 && addr
<= 0x3F && (NVRAM
->lock
& 2))
442 if (addr
< NVRAM
->size
) {
443 retval
= NVRAM
->buffer
[addr
];
447 if (addr
> 0x1FF9 && addr
< 0x2000)
448 NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__
, addr
, retval
);
453 /* IO access to NVRAM */
454 static void NVRAM_writeb(void *opaque
, hwaddr addr
, uint64_t val
,
457 M48t59State
*NVRAM
= opaque
;
459 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__
, addr
, val
);
462 NVRAM
->addr
&= ~0x00FF;
466 NVRAM
->addr
&= ~0xFF00;
467 NVRAM
->addr
|= val
<< 8;
470 m48t59_write(NVRAM
, NVRAM
->addr
, val
);
471 NVRAM
->addr
= 0x0000;
478 static uint64_t NVRAM_readb(void *opaque
, hwaddr addr
, unsigned size
)
480 M48t59State
*NVRAM
= opaque
;
485 retval
= m48t59_read(NVRAM
, NVRAM
->addr
);
491 NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__
, addr
, retval
);
496 static void nvram_writeb (void *opaque
, hwaddr addr
, uint32_t value
)
498 M48t59State
*NVRAM
= opaque
;
500 m48t59_write(NVRAM
, addr
, value
& 0xff);
503 static void nvram_writew (void *opaque
, hwaddr addr
, uint32_t value
)
505 M48t59State
*NVRAM
= opaque
;
507 m48t59_write(NVRAM
, addr
, (value
>> 8) & 0xff);
508 m48t59_write(NVRAM
, addr
+ 1, value
& 0xff);
511 static void nvram_writel (void *opaque
, hwaddr addr
, uint32_t value
)
513 M48t59State
*NVRAM
= opaque
;
515 m48t59_write(NVRAM
, addr
, (value
>> 24) & 0xff);
516 m48t59_write(NVRAM
, addr
+ 1, (value
>> 16) & 0xff);
517 m48t59_write(NVRAM
, addr
+ 2, (value
>> 8) & 0xff);
518 m48t59_write(NVRAM
, addr
+ 3, value
& 0xff);
521 static uint32_t nvram_readb (void *opaque
, hwaddr addr
)
523 M48t59State
*NVRAM
= opaque
;
525 return m48t59_read(NVRAM
, addr
);
528 static uint32_t nvram_readw (void *opaque
, hwaddr addr
)
530 M48t59State
*NVRAM
= opaque
;
533 retval
= m48t59_read(NVRAM
, addr
) << 8;
534 retval
|= m48t59_read(NVRAM
, addr
+ 1);
538 static uint32_t nvram_readl (void *opaque
, hwaddr addr
)
540 M48t59State
*NVRAM
= opaque
;
543 retval
= m48t59_read(NVRAM
, addr
) << 24;
544 retval
|= m48t59_read(NVRAM
, addr
+ 1) << 16;
545 retval
|= m48t59_read(NVRAM
, addr
+ 2) << 8;
546 retval
|= m48t59_read(NVRAM
, addr
+ 3);
550 static const MemoryRegionOps nvram_ops
= {
552 .read
= { nvram_readb
, nvram_readw
, nvram_readl
, },
553 .write
= { nvram_writeb
, nvram_writew
, nvram_writel
, },
555 .endianness
= DEVICE_NATIVE_ENDIAN
,
558 static const VMStateDescription vmstate_m48t59
= {
561 .minimum_version_id
= 1,
562 .fields
= (VMStateField
[]) {
563 VMSTATE_UINT8(lock
, M48t59State
),
564 VMSTATE_UINT16(addr
, M48t59State
),
565 VMSTATE_VBUFFER_UINT32(buffer
, M48t59State
, 0, NULL
, size
),
566 VMSTATE_END_OF_LIST()
570 void m48t59_reset_common(M48t59State
*NVRAM
)
574 if (NVRAM
->alrm_timer
!= NULL
)
575 timer_del(NVRAM
->alrm_timer
);
577 if (NVRAM
->wd_timer
!= NULL
)
578 timer_del(NVRAM
->wd_timer
);
581 static void m48t59_reset_sysbus(DeviceState
*d
)
583 M48txxSysBusState
*sys
= M48TXX_SYS_BUS(d
);
584 M48t59State
*NVRAM
= &sys
->state
;
586 m48t59_reset_common(NVRAM
);
589 const MemoryRegionOps m48t59_io_ops
= {
591 .write
= NVRAM_writeb
,
593 .min_access_size
= 1,
594 .max_access_size
= 1,
596 .endianness
= DEVICE_LITTLE_ENDIAN
,
599 /* Initialisation routine */
600 Nvram
*m48t59_init(qemu_irq IRQ
, hwaddr mem_base
,
601 uint32_t io_base
, uint16_t size
, int base_year
,
608 for (i
= 0; i
< ARRAY_SIZE(m48txx_sysbus_info
); i
++) {
609 if (m48txx_sysbus_info
[i
].size
!= size
||
610 m48txx_sysbus_info
[i
].model
!= model
) {
614 dev
= qdev_create(NULL
, m48txx_sysbus_info
[i
].bus_name
);
615 qdev_prop_set_int32(dev
, "base-year", base_year
);
616 qdev_init_nofail(dev
);
617 s
= SYS_BUS_DEVICE(dev
);
618 sysbus_connect_irq(s
, 0, IRQ
);
620 memory_region_add_subregion(get_system_io(), io_base
,
621 sysbus_mmio_get_region(s
, 1));
624 sysbus_mmio_map(s
, 0, mem_base
);
634 void m48t59_realize_common(M48t59State
*s
, Error
**errp
)
636 s
->buffer
= g_malloc0(s
->size
);
637 if (s
->model
== 59) {
638 s
->alrm_timer
= timer_new_ns(rtc_clock
, &alarm_cb
, s
);
639 s
->wd_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, &watchdog_cb
, s
);
641 qemu_get_timedate(&s
->alarm
, 0);
644 static void m48t59_init1(Object
*obj
)
646 M48txxSysBusDeviceClass
*u
= M48TXX_SYS_BUS_GET_CLASS(obj
);
647 M48txxSysBusState
*d
= M48TXX_SYS_BUS(obj
);
648 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
649 M48t59State
*s
= &d
->state
;
651 s
->model
= u
->info
.model
;
652 s
->size
= u
->info
.size
;
653 sysbus_init_irq(dev
, &s
->IRQ
);
655 memory_region_init_io(&s
->iomem
, obj
, &nvram_ops
, s
, "m48t59.nvram",
657 memory_region_init_io(&d
->io
, obj
, &m48t59_io_ops
, s
, "m48t59", 4);
660 static void m48t59_realize(DeviceState
*dev
, Error
**errp
)
662 M48txxSysBusState
*d
= M48TXX_SYS_BUS(dev
);
663 M48t59State
*s
= &d
->state
;
664 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
666 sysbus_init_mmio(sbd
, &s
->iomem
);
667 sysbus_init_mmio(sbd
, &d
->io
);
668 m48t59_realize_common(s
, errp
);
671 static uint32_t m48txx_sysbus_read(Nvram
*obj
, uint32_t addr
)
673 M48txxSysBusState
*d
= M48TXX_SYS_BUS(obj
);
674 return m48t59_read(&d
->state
, addr
);
677 static void m48txx_sysbus_write(Nvram
*obj
, uint32_t addr
, uint32_t val
)
679 M48txxSysBusState
*d
= M48TXX_SYS_BUS(obj
);
680 m48t59_write(&d
->state
, addr
, val
);
683 static void m48txx_sysbus_toggle_lock(Nvram
*obj
, int lock
)
685 M48txxSysBusState
*d
= M48TXX_SYS_BUS(obj
);
686 m48t59_toggle_lock(&d
->state
, lock
);
689 static Property m48t59_sysbus_properties
[] = {
690 DEFINE_PROP_INT32("base-year", M48txxSysBusState
, state
.base_year
, 0),
691 DEFINE_PROP_END_OF_LIST(),
694 static void m48txx_sysbus_class_init(ObjectClass
*klass
, void *data
)
696 DeviceClass
*dc
= DEVICE_CLASS(klass
);
697 NvramClass
*nc
= NVRAM_CLASS(klass
);
699 dc
->realize
= m48t59_realize
;
700 dc
->reset
= m48t59_reset_sysbus
;
701 dc
->props
= m48t59_sysbus_properties
;
702 dc
->vmsd
= &vmstate_m48t59
;
703 nc
->read
= m48txx_sysbus_read
;
704 nc
->write
= m48txx_sysbus_write
;
705 nc
->toggle_lock
= m48txx_sysbus_toggle_lock
;
708 static void m48txx_sysbus_concrete_class_init(ObjectClass
*klass
, void *data
)
710 M48txxSysBusDeviceClass
*u
= M48TXX_SYS_BUS_CLASS(klass
);
711 M48txxInfo
*info
= data
;
716 static const TypeInfo nvram_info
= {
718 .parent
= TYPE_INTERFACE
,
719 .class_size
= sizeof(NvramClass
),
722 static const TypeInfo m48txx_sysbus_type_info
= {
723 .name
= TYPE_M48TXX_SYS_BUS
,
724 .parent
= TYPE_SYS_BUS_DEVICE
,
725 .instance_size
= sizeof(M48txxSysBusState
),
726 .instance_init
= m48t59_init1
,
728 .class_init
= m48txx_sysbus_class_init
,
729 .interfaces
= (InterfaceInfo
[]) {
735 static void m48t59_register_types(void)
737 TypeInfo sysbus_type_info
= {
738 .parent
= TYPE_M48TXX_SYS_BUS
,
739 .class_size
= sizeof(M48txxSysBusDeviceClass
),
740 .class_init
= m48txx_sysbus_concrete_class_init
,
744 type_register_static(&nvram_info
);
745 type_register_static(&m48txx_sysbus_type_info
);
747 for (i
= 0; i
< ARRAY_SIZE(m48txx_sysbus_info
); i
++) {
748 sysbus_type_info
.name
= m48txx_sysbus_info
[i
].bus_name
;
749 sysbus_type_info
.class_data
= &m48txx_sysbus_info
[i
];
750 type_register(&sysbus_type_info
);
754 type_init(m48t59_register_types
)