2 * QEMU model of the Xilinx Zynq SPI controller
4 * Copyright (c) 2012 Peter A. G. Crosthwaite
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "hw/sysbus.h"
27 #include "sysemu/sysemu.h"
28 #include "hw/ptimer.h"
30 #include "qemu/bitops.h"
31 #include "hw/ssi/xilinx_spips.h"
32 #include "qapi/error.h"
33 #include "hw/register.h"
34 #include "sysemu/dma.h"
35 #include "migration/blocker.h"
37 #ifndef XILINX_SPIPS_ERR_DEBUG
38 #define XILINX_SPIPS_ERR_DEBUG 0
41 #define DB_PRINT_L(level, ...) do { \
42 if (XILINX_SPIPS_ERR_DEBUG > (level)) { \
43 fprintf(stderr, ": %s: ", __func__); \
44 fprintf(stderr, ## __VA_ARGS__); \
49 #define R_CONFIG (0x00 / 4)
50 #define IFMODE (1U << 31)
51 #define R_CONFIG_ENDIAN (1 << 26)
52 #define MODEFAIL_GEN_EN (1 << 17)
53 #define MAN_START_COM (1 << 16)
54 #define MAN_START_EN (1 << 15)
55 #define MANUAL_CS (1 << 14)
56 #define CS (0xF << 10)
58 #define PERI_SEL (1 << 9)
59 #define REF_CLK (1 << 8)
60 #define FIFO_WIDTH (3 << 6)
61 #define BAUD_RATE_DIV (7 << 3)
62 #define CLK_PH (1 << 2)
63 #define CLK_POL (1 << 1)
64 #define MODE_SEL (1 << 0)
65 #define R_CONFIG_RSVD (0x7bf40000)
67 /* interrupt mechanism */
68 #define R_INTR_STATUS (0x04 / 4)
69 #define R_INTR_STATUS_RESET (0x104)
70 #define R_INTR_EN (0x08 / 4)
71 #define R_INTR_DIS (0x0C / 4)
72 #define R_INTR_MASK (0x10 / 4)
73 #define IXR_TX_FIFO_UNDERFLOW (1 << 6)
74 /* Poll timeout not implemented */
75 #define IXR_RX_FIFO_EMPTY (1 << 11)
76 #define IXR_GENERIC_FIFO_FULL (1 << 10)
77 #define IXR_GENERIC_FIFO_NOT_FULL (1 << 9)
78 #define IXR_TX_FIFO_EMPTY (1 << 8)
79 #define IXR_GENERIC_FIFO_EMPTY (1 << 7)
80 #define IXR_RX_FIFO_FULL (1 << 5)
81 #define IXR_RX_FIFO_NOT_EMPTY (1 << 4)
82 #define IXR_TX_FIFO_FULL (1 << 3)
83 #define IXR_TX_FIFO_NOT_FULL (1 << 2)
84 #define IXR_TX_FIFO_MODE_FAIL (1 << 1)
85 #define IXR_RX_FIFO_OVERFLOW (1 << 0)
86 #define IXR_ALL ((1 << 13) - 1)
87 #define GQSPI_IXR_MASK 0xFBE
88 #define IXR_SELF_CLEAR \
89 (IXR_GENERIC_FIFO_EMPTY \
90 | IXR_GENERIC_FIFO_FULL \
91 | IXR_GENERIC_FIFO_NOT_FULL \
94 | IXR_TX_FIFO_NOT_FULL \
97 | IXR_RX_FIFO_NOT_EMPTY)
99 #define R_EN (0x14 / 4)
100 #define R_DELAY (0x18 / 4)
101 #define R_TX_DATA (0x1C / 4)
102 #define R_RX_DATA (0x20 / 4)
103 #define R_SLAVE_IDLE_COUNT (0x24 / 4)
104 #define R_TX_THRES (0x28 / 4)
105 #define R_RX_THRES (0x2C / 4)
106 #define R_GPIO (0x30 / 4)
107 #define R_LPBK_DLY_ADJ (0x38 / 4)
108 #define R_LPBK_DLY_ADJ_RESET (0x33)
109 #define R_TXD1 (0x80 / 4)
110 #define R_TXD2 (0x84 / 4)
111 #define R_TXD3 (0x88 / 4)
113 #define R_LQSPI_CFG (0xa0 / 4)
114 #define R_LQSPI_CFG_RESET 0x03A002EB
115 #define LQSPI_CFG_LQ_MODE (1U << 31)
116 #define LQSPI_CFG_TWO_MEM (1 << 30)
117 #define LQSPI_CFG_SEP_BUS (1 << 29)
118 #define LQSPI_CFG_U_PAGE (1 << 28)
119 #define LQSPI_CFG_ADDR4 (1 << 27)
120 #define LQSPI_CFG_MODE_EN (1 << 25)
121 #define LQSPI_CFG_MODE_WIDTH 8
122 #define LQSPI_CFG_MODE_SHIFT 16
123 #define LQSPI_CFG_DUMMY_WIDTH 3
124 #define LQSPI_CFG_DUMMY_SHIFT 8
125 #define LQSPI_CFG_INST_CODE 0xFF
127 #define R_CMND (0xc0 / 4)
128 #define R_CMND_RXFIFO_DRAIN (1 << 19)
129 FIELD(CMND
, PARTIAL_BYTE_LEN
, 16, 3)
130 #define R_CMND_EXT_ADD (1 << 15)
131 FIELD(CMND
, RX_DISCARD
, 8, 7)
132 FIELD(CMND
, DUMMY_CYCLES
, 2, 6)
133 #define R_CMND_DMA_EN (1 << 1)
134 #define R_CMND_PUSH_WAIT (1 << 0)
135 #define R_TRANSFER_SIZE (0xc4 / 4)
136 #define R_LQSPI_STS (0xA4 / 4)
137 #define LQSPI_STS_WR_RECVD (1 << 1)
139 #define R_MOD_ID (0xFC / 4)
141 #define R_GQSPI_SELECT (0x144 / 4)
142 FIELD(GQSPI_SELECT
, GENERIC_QSPI_EN
, 0, 1)
143 #define R_GQSPI_ISR (0x104 / 4)
144 #define R_GQSPI_IER (0x108 / 4)
145 #define R_GQSPI_IDR (0x10c / 4)
146 #define R_GQSPI_IMR (0x110 / 4)
147 #define R_GQSPI_IMR_RESET (0xfbe)
148 #define R_GQSPI_TX_THRESH (0x128 / 4)
149 #define R_GQSPI_RX_THRESH (0x12c / 4)
150 #define R_GQSPI_GPIO (0x130 / 4)
151 #define R_GQSPI_LPBK_DLY_ADJ (0x138 / 4)
152 #define R_GQSPI_LPBK_DLY_ADJ_RESET (0x33)
153 #define R_GQSPI_CNFG (0x100 / 4)
154 FIELD(GQSPI_CNFG
, MODE_EN
, 30, 2)
155 FIELD(GQSPI_CNFG
, GEN_FIFO_START_MODE
, 29, 1)
156 FIELD(GQSPI_CNFG
, GEN_FIFO_START
, 28, 1)
157 FIELD(GQSPI_CNFG
, ENDIAN
, 26, 1)
158 /* Poll timeout not implemented */
159 FIELD(GQSPI_CNFG
, EN_POLL_TIMEOUT
, 20, 1)
160 /* QEMU doesnt care about any of these last three */
161 FIELD(GQSPI_CNFG
, BR
, 3, 3)
162 FIELD(GQSPI_CNFG
, CPH
, 2, 1)
163 FIELD(GQSPI_CNFG
, CPL
, 1, 1)
164 #define R_GQSPI_GEN_FIFO (0x140 / 4)
165 #define R_GQSPI_TXD (0x11c / 4)
166 #define R_GQSPI_RXD (0x120 / 4)
167 #define R_GQSPI_FIFO_CTRL (0x14c / 4)
168 FIELD(GQSPI_FIFO_CTRL
, RX_FIFO_RESET
, 2, 1)
169 FIELD(GQSPI_FIFO_CTRL
, TX_FIFO_RESET
, 1, 1)
170 FIELD(GQSPI_FIFO_CTRL
, GENERIC_FIFO_RESET
, 0, 1)
171 #define R_GQSPI_GFIFO_THRESH (0x150 / 4)
172 #define R_GQSPI_DATA_STS (0x15c / 4)
173 /* We use the snapshot register to hold the core state for the currently
174 * or most recently executed command. So the generic fifo format is defined
175 * for the snapshot register
177 #define R_GQSPI_GF_SNAPSHOT (0x160 / 4)
178 FIELD(GQSPI_GF_SNAPSHOT
, POLL
, 19, 1)
179 FIELD(GQSPI_GF_SNAPSHOT
, STRIPE
, 18, 1)
180 FIELD(GQSPI_GF_SNAPSHOT
, RECIEVE
, 17, 1)
181 FIELD(GQSPI_GF_SNAPSHOT
, TRANSMIT
, 16, 1)
182 FIELD(GQSPI_GF_SNAPSHOT
, DATA_BUS_SELECT
, 14, 2)
183 FIELD(GQSPI_GF_SNAPSHOT
, CHIP_SELECT
, 12, 2)
184 FIELD(GQSPI_GF_SNAPSHOT
, SPI_MODE
, 10, 2)
185 FIELD(GQSPI_GF_SNAPSHOT
, EXPONENT
, 9, 1)
186 FIELD(GQSPI_GF_SNAPSHOT
, DATA_XFER
, 8, 1)
187 FIELD(GQSPI_GF_SNAPSHOT
, IMMEDIATE_DATA
, 0, 8)
188 #define R_GQSPI_MOD_ID (0x1fc / 4)
189 #define R_GQSPI_MOD_ID_RESET (0x10a0000)
191 #define R_QSPIDMA_DST_CTRL (0x80c / 4)
192 #define R_QSPIDMA_DST_CTRL_RESET (0x803ffa00)
193 #define R_QSPIDMA_DST_I_MASK (0x820 / 4)
194 #define R_QSPIDMA_DST_I_MASK_RESET (0xfe)
195 #define R_QSPIDMA_DST_CTRL2 (0x824 / 4)
196 #define R_QSPIDMA_DST_CTRL2_RESET (0x081bfff8)
198 /* size of TXRX FIFOs */
202 #define RXFF_A_Q (64 * 4)
203 #define TXFF_A_Q (64 * 4)
205 /* 16MB per linear region */
206 #define LQSPI_ADDRESS_BITS 24
208 #define SNOOP_CHECKING 0xFF
209 #define SNOOP_ADDR 0xF0
210 #define SNOOP_NONE 0xEE
211 #define SNOOP_STRIPING 0
213 #define MIN_NUM_BUSSES 1
214 #define MAX_NUM_BUSSES 2
216 static inline int num_effective_busses(XilinxSPIPS
*s
)
218 return (s
->regs
[R_LQSPI_CFG
] & LQSPI_CFG_SEP_BUS
&&
219 s
->regs
[R_LQSPI_CFG
] & LQSPI_CFG_TWO_MEM
) ? s
->num_busses
: 1;
222 static void xilinx_spips_update_cs(XilinxSPIPS
*s
, int field
)
226 for (i
= 0; i
< s
->num_cs
* s
->num_busses
; i
++) {
227 bool old_state
= s
->cs_lines_state
[i
];
228 bool new_state
= field
& (1 << i
);
230 if (old_state
!= new_state
) {
231 s
->cs_lines_state
[i
] = new_state
;
232 s
->rx_discard
= ARRAY_FIELD_EX32(s
->regs
, CMND
, RX_DISCARD
);
233 DB_PRINT_L(1, "%sselecting slave %d\n", new_state
? "" : "de", i
);
235 qemu_set_irq(s
->cs_lines
[i
], !new_state
);
237 if (!(field
& ((1 << (s
->num_cs
* s
->num_busses
)) - 1))) {
238 s
->snoop_state
= SNOOP_CHECKING
;
241 s
->link_state_next
= 1;
242 s
->link_state_next_when
= 0;
243 DB_PRINT_L(1, "moving to snoop check state\n");
247 static void xlnx_zynqmp_qspips_update_cs_lines(XlnxZynqMPQSPIPS
*s
)
249 if (s
->regs
[R_GQSPI_GF_SNAPSHOT
]) {
250 int field
= ARRAY_FIELD_EX32(s
->regs
, GQSPI_GF_SNAPSHOT
, CHIP_SELECT
);
251 bool upper_cs_sel
= field
& (1 << 1);
252 bool lower_cs_sel
= field
& 1;
258 buses
= ARRAY_FIELD_EX32(s
->regs
, GQSPI_GF_SNAPSHOT
, DATA_BUS_SELECT
);
259 bus0_enabled
= buses
& 1;
260 bus1_enabled
= buses
& (1 << 1);
262 if (bus0_enabled
&& bus1_enabled
) {
269 } else if (bus0_enabled
) {
276 } else if (bus1_enabled
) {
284 xilinx_spips_update_cs(XILINX_SPIPS(s
), cs
);
288 static void xilinx_spips_update_cs_lines(XilinxSPIPS
*s
)
290 int field
= ~((s
->regs
[R_CONFIG
] & CS
) >> CS_SHIFT
);
292 /* In dual parallel, mirror low CS to both */
293 if (num_effective_busses(s
) == 2) {
294 /* Single bit chip-select for qspi */
297 /* Dual stack U-Page */
298 } else if (s
->regs
[R_LQSPI_CFG
] & LQSPI_CFG_TWO_MEM
&&
299 s
->regs
[R_LQSPI_STS
] & LQSPI_CFG_U_PAGE
) {
300 /* Single bit chip-select for qspi */
302 /* change from CS0 to CS1 */
306 if (!(s
->regs
[R_CONFIG
] & MANUAL_CS
) &&
307 fifo8_is_empty(&s
->tx_fifo
)) {
310 xilinx_spips_update_cs(s
, field
);
313 static void xilinx_spips_update_ixr(XilinxSPIPS
*s
)
315 if (!(s
->regs
[R_LQSPI_CFG
] & LQSPI_CFG_LQ_MODE
)) {
316 s
->regs
[R_INTR_STATUS
] &= ~IXR_SELF_CLEAR
;
317 s
->regs
[R_INTR_STATUS
] |=
318 (fifo8_is_full(&s
->rx_fifo
) ? IXR_RX_FIFO_FULL
: 0) |
319 (s
->rx_fifo
.num
>= s
->regs
[R_RX_THRES
] ?
320 IXR_RX_FIFO_NOT_EMPTY
: 0) |
321 (fifo8_is_full(&s
->tx_fifo
) ? IXR_TX_FIFO_FULL
: 0) |
322 (fifo8_is_empty(&s
->tx_fifo
) ? IXR_TX_FIFO_EMPTY
: 0) |
323 (s
->tx_fifo
.num
< s
->regs
[R_TX_THRES
] ? IXR_TX_FIFO_NOT_FULL
: 0);
325 int new_irqline
= !!(s
->regs
[R_INTR_MASK
] & s
->regs
[R_INTR_STATUS
] &
327 if (new_irqline
!= s
->irqline
) {
328 s
->irqline
= new_irqline
;
329 qemu_set_irq(s
->irq
, s
->irqline
);
333 static void xlnx_zynqmp_qspips_update_ixr(XlnxZynqMPQSPIPS
*s
)
338 s
->regs
[R_GQSPI_ISR
] &= ~IXR_SELF_CLEAR
;
339 s
->regs
[R_GQSPI_ISR
] |=
340 (fifo32_is_empty(&s
->fifo_g
) ? IXR_GENERIC_FIFO_EMPTY
: 0) |
341 (fifo32_is_full(&s
->fifo_g
) ? IXR_GENERIC_FIFO_FULL
: 0) |
342 (s
->fifo_g
.fifo
.num
< s
->regs
[R_GQSPI_GFIFO_THRESH
] ?
343 IXR_GENERIC_FIFO_NOT_FULL
: 0) |
344 (fifo8_is_empty(&s
->rx_fifo_g
) ? IXR_RX_FIFO_EMPTY
: 0) |
345 (fifo8_is_full(&s
->rx_fifo_g
) ? IXR_RX_FIFO_FULL
: 0) |
346 (s
->rx_fifo_g
.num
>= s
->regs
[R_GQSPI_RX_THRESH
] ?
347 IXR_RX_FIFO_NOT_EMPTY
: 0) |
348 (fifo8_is_empty(&s
->tx_fifo_g
) ? IXR_TX_FIFO_EMPTY
: 0) |
349 (fifo8_is_full(&s
->tx_fifo_g
) ? IXR_TX_FIFO_FULL
: 0) |
350 (s
->tx_fifo_g
.num
< s
->regs
[R_GQSPI_TX_THRESH
] ?
351 IXR_TX_FIFO_NOT_FULL
: 0);
353 /* GQSPI Interrupt Trigger Status */
354 gqspi_int
= (~s
->regs
[R_GQSPI_IMR
]) & s
->regs
[R_GQSPI_ISR
] & GQSPI_IXR_MASK
;
355 new_irqline
= !!(gqspi_int
& IXR_ALL
);
357 /* drive external interrupt pin */
358 if (new_irqline
!= s
->gqspi_irqline
) {
359 s
->gqspi_irqline
= new_irqline
;
360 qemu_set_irq(XILINX_SPIPS(s
)->irq
, s
->gqspi_irqline
);
364 static void xilinx_spips_reset(DeviceState
*d
)
366 XilinxSPIPS
*s
= XILINX_SPIPS(d
);
368 memset(s
->regs
, 0, sizeof(s
->regs
));
370 fifo8_reset(&s
->rx_fifo
);
371 fifo8_reset(&s
->rx_fifo
);
372 /* non zero resets */
373 s
->regs
[R_CONFIG
] |= MODEFAIL_GEN_EN
;
374 s
->regs
[R_SLAVE_IDLE_COUNT
] = 0xFF;
375 s
->regs
[R_TX_THRES
] = 1;
376 s
->regs
[R_RX_THRES
] = 1;
377 /* FIXME: move magic number definition somewhere sensible */
378 s
->regs
[R_MOD_ID
] = 0x01090106;
379 s
->regs
[R_LQSPI_CFG
] = R_LQSPI_CFG_RESET
;
381 s
->link_state_next
= 1;
382 s
->link_state_next_when
= 0;
383 s
->snoop_state
= SNOOP_CHECKING
;
385 s
->man_start_com
= false;
386 xilinx_spips_update_ixr(s
);
387 xilinx_spips_update_cs_lines(s
);
390 static void xlnx_zynqmp_qspips_reset(DeviceState
*d
)
392 XlnxZynqMPQSPIPS
*s
= XLNX_ZYNQMP_QSPIPS(d
);
394 xilinx_spips_reset(d
);
396 memset(s
->regs
, 0, sizeof(s
->regs
));
398 fifo8_reset(&s
->rx_fifo_g
);
399 fifo8_reset(&s
->rx_fifo_g
);
400 fifo32_reset(&s
->fifo_g
);
401 s
->regs
[R_INTR_STATUS
] = R_INTR_STATUS_RESET
;
403 s
->regs
[R_LPBK_DLY_ADJ
] = R_LPBK_DLY_ADJ_RESET
;
404 s
->regs
[R_GQSPI_GFIFO_THRESH
] = 0x10;
405 s
->regs
[R_MOD_ID
] = 0x01090101;
406 s
->regs
[R_GQSPI_IMR
] = R_GQSPI_IMR_RESET
;
407 s
->regs
[R_GQSPI_TX_THRESH
] = 1;
408 s
->regs
[R_GQSPI_RX_THRESH
] = 1;
409 s
->regs
[R_GQSPI_GPIO
] = 1;
410 s
->regs
[R_GQSPI_LPBK_DLY_ADJ
] = R_GQSPI_LPBK_DLY_ADJ_RESET
;
411 s
->regs
[R_GQSPI_MOD_ID
] = R_GQSPI_MOD_ID_RESET
;
412 s
->regs
[R_QSPIDMA_DST_CTRL
] = R_QSPIDMA_DST_CTRL_RESET
;
413 s
->regs
[R_QSPIDMA_DST_I_MASK
] = R_QSPIDMA_DST_I_MASK_RESET
;
414 s
->regs
[R_QSPIDMA_DST_CTRL2
] = R_QSPIDMA_DST_CTRL2_RESET
;
415 s
->man_start_com_g
= false;
416 s
->gqspi_irqline
= 0;
417 xlnx_zynqmp_qspips_update_ixr(s
);
420 /* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB)
421 * column wise (from element 0 to N-1). num is the length of x, and dir
422 * reverses the direction of the transform. Best illustrated by example:
423 * Each digit in the below array is a single bit (num == 3):
425 * {{ 76543210, } ----- stripe (dir == false) -----> {{ 741gdaFC, }
426 * { hgfedcba, } { 630fcHEB, }
427 * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { 52hebGDA, }}
430 static inline void stripe8(uint8_t *x
, int num
, bool dir
)
433 memset(r
, 0, sizeof(uint8_t) * num
);
438 for (idx
[0] = 0; idx
[0] < num
; ++idx
[0]) {
439 for (bit
[0] = 7; bit
[0] >= 0; bit
[0]--) {
440 r
[idx
[!d
]] |= x
[idx
[d
]] & 1 << bit
[d
] ? 1 << bit
[!d
] : 0;
441 idx
[1] = (idx
[1] + 1) % num
;
447 memcpy(x
, r
, sizeof(uint8_t) * num
);
450 static void xlnx_zynqmp_qspips_flush_fifo_g(XlnxZynqMPQSPIPS
*s
)
452 while (s
->regs
[R_GQSPI_DATA_STS
] || !fifo32_is_empty(&s
->fifo_g
)) {
453 uint8_t tx_rx
[2] = { 0 };
458 if (!s
->regs
[R_GQSPI_DATA_STS
]) {
461 s
->regs
[R_GQSPI_GF_SNAPSHOT
] = fifo32_pop(&s
->fifo_g
);
462 DB_PRINT_L(0, "GQSPI command: %x\n", s
->regs
[R_GQSPI_GF_SNAPSHOT
]);
463 if (!s
->regs
[R_GQSPI_GF_SNAPSHOT
]) {
464 DB_PRINT_L(0, "Dummy GQSPI Delay Command Entry, Do nothing");
467 xlnx_zynqmp_qspips_update_cs_lines(s
);
469 imm
= ARRAY_FIELD_EX32(s
->regs
, GQSPI_GF_SNAPSHOT
, IMMEDIATE_DATA
);
470 if (!ARRAY_FIELD_EX32(s
->regs
, GQSPI_GF_SNAPSHOT
, DATA_XFER
)) {
471 /* immedate transfer */
472 if (ARRAY_FIELD_EX32(s
->regs
, GQSPI_GF_SNAPSHOT
, TRANSMIT
) ||
473 ARRAY_FIELD_EX32(s
->regs
, GQSPI_GF_SNAPSHOT
, RECIEVE
)) {
474 s
->regs
[R_GQSPI_DATA_STS
] = 1;
475 /* CS setup/hold - do nothing */
477 s
->regs
[R_GQSPI_DATA_STS
] = 0;
479 } else if (ARRAY_FIELD_EX32(s
->regs
, GQSPI_GF_SNAPSHOT
, EXPONENT
)) {
481 qemu_log_mask(LOG_UNIMP
, "QSPI exponential transfer too"
482 " long - 2 ^ %" PRId8
" requested\n", imm
);
484 s
->regs
[R_GQSPI_DATA_STS
] = 1ul << imm
;
486 s
->regs
[R_GQSPI_DATA_STS
] = imm
;
489 /* Zero length transfer check */
490 if (!s
->regs
[R_GQSPI_DATA_STS
]) {
493 if (ARRAY_FIELD_EX32(s
->regs
, GQSPI_GF_SNAPSHOT
, RECIEVE
) &&
494 fifo8_is_full(&s
->rx_fifo_g
)) {
495 /* No space in RX fifo for transfer - try again later */
498 if (ARRAY_FIELD_EX32(s
->regs
, GQSPI_GF_SNAPSHOT
, STRIPE
) &&
499 (ARRAY_FIELD_EX32(s
->regs
, GQSPI_GF_SNAPSHOT
, TRANSMIT
) ||
500 ARRAY_FIELD_EX32(s
->regs
, GQSPI_GF_SNAPSHOT
, RECIEVE
))) {
503 if (!ARRAY_FIELD_EX32(s
->regs
, GQSPI_GF_SNAPSHOT
, DATA_XFER
)) {
504 tx_rx
[0] = ARRAY_FIELD_EX32(s
->regs
,
505 GQSPI_GF_SNAPSHOT
, IMMEDIATE_DATA
);
506 } else if (ARRAY_FIELD_EX32(s
->regs
, GQSPI_GF_SNAPSHOT
, TRANSMIT
)) {
507 for (i
= 0; i
< num_stripes
; ++i
) {
508 if (!fifo8_is_empty(&s
->tx_fifo_g
)) {
509 tx_rx
[i
] = fifo8_pop(&s
->tx_fifo_g
);
510 s
->tx_fifo_g_align
++;
516 if (num_stripes
== 1) {
520 busses
= ARRAY_FIELD_EX32(s
->regs
, GQSPI_GF_SNAPSHOT
, DATA_BUS_SELECT
);
521 for (i
= 0; i
< 2; ++i
) {
522 DB_PRINT_L(1, "bus %d tx = %02x\n", i
, tx_rx
[i
]);
523 tx_rx
[i
] = ssi_transfer(XILINX_SPIPS(s
)->spi
[i
], tx_rx
[i
]);
524 DB_PRINT_L(1, "bus %d rx = %02x\n", i
, tx_rx
[i
]);
526 if (s
->regs
[R_GQSPI_DATA_STS
] > 1 &&
527 busses
== 0x3 && num_stripes
== 2) {
528 s
->regs
[R_GQSPI_DATA_STS
] -= 2;
529 } else if (s
->regs
[R_GQSPI_DATA_STS
] > 0) {
530 s
->regs
[R_GQSPI_DATA_STS
]--;
532 if (ARRAY_FIELD_EX32(s
->regs
, GQSPI_GF_SNAPSHOT
, RECIEVE
)) {
533 for (i
= 0; i
< 2; ++i
) {
534 if (busses
& (1 << i
)) {
535 DB_PRINT_L(1, "bus %d push_byte = %02x\n", i
, tx_rx
[i
]);
536 fifo8_push(&s
->rx_fifo_g
, tx_rx
[i
]);
537 s
->rx_fifo_g_align
++;
541 if (!s
->regs
[R_GQSPI_DATA_STS
]) {
542 for (; s
->tx_fifo_g_align
% 4; s
->tx_fifo_g_align
++) {
543 fifo8_pop(&s
->tx_fifo_g
);
545 for (; s
->rx_fifo_g_align
% 4; s
->rx_fifo_g_align
++) {
546 fifo8_push(&s
->rx_fifo_g
, 0);
552 static int xilinx_spips_num_dummies(XilinxQSPIPS
*qs
, uint8_t command
)
555 /* The SPI device is not a QSPI device */
559 switch (command
) { /* check for dummies */
560 case READ
: /* no dummy bytes/cycles */
586 static inline uint8_t get_addr_length(XilinxSPIPS
*s
, uint8_t cmd
)
599 return (s
->regs
[R_CMND
] & R_CMND_EXT_ADD
) ? 4 : 3;
603 static void xilinx_spips_flush_txfifo(XilinxSPIPS
*s
)
606 XilinxQSPIPS
*q
= (XilinxQSPIPS
*) object_dynamic_cast(OBJECT(s
),
612 uint8_t tx_rx
[MAX_NUM_BUSSES
] = { 0 };
613 uint8_t dummy_cycles
= 0;
616 if (fifo8_is_empty(&s
->tx_fifo
)) {
617 xilinx_spips_update_ixr(s
);
619 } else if (s
->snoop_state
== SNOOP_STRIPING
) {
620 for (i
= 0; i
< num_effective_busses(s
); ++i
) {
621 tx_rx
[i
] = fifo8_pop(&s
->tx_fifo
);
623 stripe8(tx_rx
, num_effective_busses(s
), false);
624 } else if (s
->snoop_state
>= SNOOP_ADDR
) {
625 tx
= fifo8_pop(&s
->tx_fifo
);
626 for (i
= 0; i
< num_effective_busses(s
); ++i
) {
630 /* Extract a dummy byte and generate dummy cycles according to the
632 tx
= fifo8_pop(&s
->tx_fifo
);
633 dummy_cycles
= 8 / s
->link_state
;
636 for (i
= 0; i
< num_effective_busses(s
); ++i
) {
637 int bus
= num_effective_busses(s
) - 1 - i
;
640 for (d
= 0; d
< dummy_cycles
; ++d
) {
641 tx_rx
[0] = ssi_transfer(s
->spi
[bus
], (uint32_t)tx_rx
[0]);
644 DB_PRINT_L(debug_level
, "tx = %02x\n", tx_rx
[i
]);
645 tx_rx
[i
] = ssi_transfer(s
->spi
[bus
], (uint32_t)tx_rx
[i
]);
646 DB_PRINT_L(debug_level
, "rx = %02x\n", tx_rx
[i
]);
650 if (s
->regs
[R_CMND
] & R_CMND_RXFIFO_DRAIN
) {
651 DB_PRINT_L(debug_level
, "dircarding drained rx byte\n");
653 } else if (s
->rx_discard
) {
654 DB_PRINT_L(debug_level
, "dircarding discarded rx byte\n");
655 s
->rx_discard
-= 8 / s
->link_state
;
656 } else if (fifo8_is_full(&s
->rx_fifo
)) {
657 s
->regs
[R_INTR_STATUS
] |= IXR_RX_FIFO_OVERFLOW
;
658 DB_PRINT_L(0, "rx FIFO overflow");
659 } else if (s
->snoop_state
== SNOOP_STRIPING
) {
660 stripe8(tx_rx
, num_effective_busses(s
), true);
661 for (i
= 0; i
< num_effective_busses(s
); ++i
) {
662 fifo8_push(&s
->rx_fifo
, (uint8_t)tx_rx
[i
]);
663 DB_PRINT_L(debug_level
, "pushing striped rx byte\n");
666 DB_PRINT_L(debug_level
, "pushing unstriped rx byte\n");
667 fifo8_push(&s
->rx_fifo
, (uint8_t)tx_rx
[0]);
670 if (s
->link_state_next_when
) {
671 s
->link_state_next_when
--;
672 if (!s
->link_state_next_when
) {
673 s
->link_state
= s
->link_state_next
;
677 DB_PRINT_L(debug_level
, "initial snoop state: %x\n",
678 (unsigned)s
->snoop_state
);
679 switch (s
->snoop_state
) {
680 case (SNOOP_CHECKING
):
681 /* Store the count of dummy bytes in the txfifo */
682 s
->cmd_dummies
= xilinx_spips_num_dummies(q
, tx
);
683 addr_length
= get_addr_length(s
, tx
);
684 if (s
->cmd_dummies
< 0) {
685 s
->snoop_state
= SNOOP_NONE
;
687 s
->snoop_state
= SNOOP_ADDR
+ addr_length
- 1;
693 s
->link_state_next
= 2;
694 s
->link_state_next_when
= addr_length
+ s
->cmd_dummies
;
700 s
->link_state_next
= 4;
701 s
->link_state_next_when
= addr_length
+ s
->cmd_dummies
;
714 /* Address has been transmitted, transmit dummy cycles now if
716 if (s
->cmd_dummies
< 0) {
717 s
->snoop_state
= SNOOP_NONE
;
719 s
->snoop_state
= s
->cmd_dummies
;
722 case (SNOOP_STRIPING
):
724 /* Once we hit the boring stuff - squelch debug noise */
726 DB_PRINT_L(0, "squelching debug info ....\n");
733 DB_PRINT_L(debug_level
, "final snoop state: %x\n",
734 (unsigned)s
->snoop_state
);
738 static inline void tx_data_bytes(Fifo8
*fifo
, uint32_t value
, int num
, bool be
)
741 for (i
= 0; i
< num
&& !fifo8_is_full(fifo
); ++i
) {
743 fifo8_push(fifo
, (uint8_t)(value
>> 24));
746 fifo8_push(fifo
, (uint8_t)value
);
752 static void xilinx_spips_check_zero_pump(XilinxSPIPS
*s
)
754 if (!s
->regs
[R_TRANSFER_SIZE
]) {
757 if (!fifo8_is_empty(&s
->tx_fifo
) && s
->regs
[R_CMND
] & R_CMND_PUSH_WAIT
) {
761 * The zero pump must never fill tx fifo such that rx overflow is
764 while (s
->regs
[R_TRANSFER_SIZE
] &&
765 s
->rx_fifo
.num
+ s
->tx_fifo
.num
< RXFF_A_Q
- 3) {
766 /* endianess just doesn't matter when zero pumping */
767 tx_data_bytes(&s
->tx_fifo
, 0, 4, false);
768 s
->regs
[R_TRANSFER_SIZE
] &= ~0x03ull
;
769 s
->regs
[R_TRANSFER_SIZE
] -= 4;
773 static void xilinx_spips_check_flush(XilinxSPIPS
*s
)
775 if (s
->man_start_com
||
776 (!fifo8_is_empty(&s
->tx_fifo
) &&
777 !(s
->regs
[R_CONFIG
] & MAN_START_EN
))) {
778 xilinx_spips_check_zero_pump(s
);
779 xilinx_spips_flush_txfifo(s
);
781 if (fifo8_is_empty(&s
->tx_fifo
) && !s
->regs
[R_TRANSFER_SIZE
]) {
782 s
->man_start_com
= false;
784 xilinx_spips_update_ixr(s
);
787 static void xlnx_zynqmp_qspips_check_flush(XlnxZynqMPQSPIPS
*s
)
789 bool gqspi_has_work
= s
->regs
[R_GQSPI_DATA_STS
] ||
790 !fifo32_is_empty(&s
->fifo_g
);
792 if (ARRAY_FIELD_EX32(s
->regs
, GQSPI_SELECT
, GENERIC_QSPI_EN
)) {
793 if (s
->man_start_com_g
|| (gqspi_has_work
&&
794 !ARRAY_FIELD_EX32(s
->regs
, GQSPI_CNFG
, GEN_FIFO_START_MODE
))) {
795 xlnx_zynqmp_qspips_flush_fifo_g(s
);
798 xilinx_spips_check_flush(XILINX_SPIPS(s
));
800 if (!gqspi_has_work
) {
801 s
->man_start_com_g
= false;
803 xlnx_zynqmp_qspips_update_ixr(s
);
806 static inline int rx_data_bytes(Fifo8
*fifo
, uint8_t *value
, int max
)
810 for (i
= 0; i
< max
&& !fifo8_is_empty(fifo
); ++i
) {
811 value
[i
] = fifo8_pop(fifo
);
816 static const void *pop_buf(Fifo8
*fifo
, uint32_t max
, uint32_t *num
)
820 if (max
== 0 || max
> fifo
->num
) {
823 *num
= MIN(fifo
->capacity
- fifo
->head
, max
);
824 ret
= &fifo
->data
[fifo
->head
];
826 fifo
->head
%= fifo
->capacity
;
831 static void xlnx_zynqmp_qspips_notify(void *opaque
)
833 XlnxZynqMPQSPIPS
*rq
= XLNX_ZYNQMP_QSPIPS(opaque
);
834 XilinxSPIPS
*s
= XILINX_SPIPS(rq
);
837 if (ARRAY_FIELD_EX32(rq
->regs
, GQSPI_SELECT
, GENERIC_QSPI_EN
)) {
838 if (!(ARRAY_FIELD_EX32(rq
->regs
, GQSPI_CNFG
, MODE_EN
) == 2)) {
841 recv_fifo
= &rq
->rx_fifo_g
;
843 if (!(s
->regs
[R_CMND
] & R_CMND_DMA_EN
)) {
846 recv_fifo
= &s
->rx_fifo
;
848 while (recv_fifo
->num
>= 4
849 && stream_can_push(rq
->dma
, xlnx_zynqmp_qspips_notify
, rq
))
853 const void *rxd
= pop_buf(recv_fifo
, 4, &num
);
855 memcpy(rq
->dma_buf
, rxd
, num
);
857 ret
= stream_push(rq
->dma
, rq
->dma_buf
, 4);
859 xlnx_zynqmp_qspips_check_flush(rq
);
863 static uint64_t xilinx_spips_read(void *opaque
, hwaddr addr
,
866 XilinxSPIPS
*s
= opaque
;
875 mask
= ~(R_CONFIG_RSVD
| MAN_START_COM
);
878 ret
= s
->regs
[addr
] & IXR_ALL
;
880 DB_PRINT_L(0, "addr=" TARGET_FMT_plx
" = %x\n", addr
* 4, ret
);
881 xilinx_spips_update_ixr(s
);
889 case R_SLAVE_IDLE_COUNT
:
901 memset(rx_buf
, 0, sizeof(rx_buf
));
902 shortfall
= rx_data_bytes(&s
->rx_fifo
, rx_buf
, s
->num_txrx_bytes
);
903 ret
= s
->regs
[R_CONFIG
] & R_CONFIG_ENDIAN
?
904 cpu_to_be32(*(uint32_t *)rx_buf
) :
905 cpu_to_le32(*(uint32_t *)rx_buf
);
906 if (!(s
->regs
[R_CONFIG
] & R_CONFIG_ENDIAN
)) {
907 ret
<<= 8 * shortfall
;
909 DB_PRINT_L(0, "addr=" TARGET_FMT_plx
" = %x\n", addr
* 4, ret
);
910 xilinx_spips_check_flush(s
);
911 xilinx_spips_update_ixr(s
);
914 DB_PRINT_L(0, "addr=" TARGET_FMT_plx
" = %x\n", addr
* 4,
915 s
->regs
[addr
] & mask
);
916 return s
->regs
[addr
] & mask
;
920 static uint64_t xlnx_zynqmp_qspips_read(void *opaque
,
921 hwaddr addr
, unsigned size
)
923 XlnxZynqMPQSPIPS
*s
= XLNX_ZYNQMP_QSPIPS(opaque
);
924 uint32_t reg
= addr
/ 4;
929 if (reg
<= R_MOD_ID
) {
930 return xilinx_spips_read(opaque
, addr
, size
);
934 if (fifo8_is_empty(&s
->rx_fifo_g
)) {
935 qemu_log_mask(LOG_GUEST_ERROR
,
936 "Read from empty GQSPI RX FIFO\n");
939 memset(rx_buf
, 0, sizeof(rx_buf
));
940 shortfall
= rx_data_bytes(&s
->rx_fifo_g
, rx_buf
,
941 XILINX_SPIPS(s
)->num_txrx_bytes
);
942 ret
= ARRAY_FIELD_EX32(s
->regs
, GQSPI_CNFG
, ENDIAN
) ?
943 cpu_to_be32(*(uint32_t *)rx_buf
) :
944 cpu_to_le32(*(uint32_t *)rx_buf
);
945 if (!ARRAY_FIELD_EX32(s
->regs
, GQSPI_CNFG
, ENDIAN
)) {
946 ret
<<= 8 * shortfall
;
948 xlnx_zynqmp_qspips_check_flush(s
);
949 xlnx_zynqmp_qspips_update_ixr(s
);
957 static void xilinx_spips_write(void *opaque
, hwaddr addr
,
958 uint64_t value
, unsigned size
)
961 XilinxSPIPS
*s
= opaque
;
963 DB_PRINT_L(0, "addr=" TARGET_FMT_plx
" = %x\n", addr
, (unsigned)value
);
967 mask
= ~(R_CONFIG_RSVD
| MAN_START_COM
);
968 if ((value
& MAN_START_COM
) && (s
->regs
[R_CONFIG
] & MAN_START_EN
)) {
969 s
->man_start_com
= true;
974 s
->regs
[R_INTR_STATUS
] &= ~(mask
& value
);
978 s
->regs
[R_INTR_MASK
] &= ~(mask
& value
);
982 s
->regs
[R_INTR_MASK
] |= mask
& value
;
987 case R_SLAVE_IDLE_COUNT
:
996 tx_data_bytes(&s
->tx_fifo
, (uint32_t)value
, s
->num_txrx_bytes
,
997 s
->regs
[R_CONFIG
] & R_CONFIG_ENDIAN
);
1000 tx_data_bytes(&s
->tx_fifo
, (uint32_t)value
, 1,
1001 s
->regs
[R_CONFIG
] & R_CONFIG_ENDIAN
);
1004 tx_data_bytes(&s
->tx_fifo
, (uint32_t)value
, 2,
1005 s
->regs
[R_CONFIG
] & R_CONFIG_ENDIAN
);
1008 tx_data_bytes(&s
->tx_fifo
, (uint32_t)value
, 3,
1009 s
->regs
[R_CONFIG
] & R_CONFIG_ENDIAN
);
1012 s
->regs
[addr
] = (s
->regs
[addr
] & ~mask
) | (value
& mask
);
1014 xilinx_spips_update_cs_lines(s
);
1015 xilinx_spips_check_flush(s
);
1016 xilinx_spips_update_cs_lines(s
);
1017 xilinx_spips_update_ixr(s
);
1020 static const MemoryRegionOps spips_ops
= {
1021 .read
= xilinx_spips_read
,
1022 .write
= xilinx_spips_write
,
1023 .endianness
= DEVICE_LITTLE_ENDIAN
,
1026 static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS
*q
)
1028 XilinxSPIPS
*s
= &q
->parent_obj
;
1030 if ((q
->mmio_execution_enabled
) && (q
->lqspi_cached_addr
!= ~0ULL)) {
1031 /* Invalidate the current mapped mmio */
1032 memory_region_invalidate_mmio_ptr(&s
->mmlqspi
, q
->lqspi_cached_addr
,
1036 q
->lqspi_cached_addr
= ~0ULL;
1039 static void xilinx_qspips_write(void *opaque
, hwaddr addr
,
1040 uint64_t value
, unsigned size
)
1042 XilinxQSPIPS
*q
= XILINX_QSPIPS(opaque
);
1043 XilinxSPIPS
*s
= XILINX_SPIPS(opaque
);
1045 xilinx_spips_write(opaque
, addr
, value
, size
);
1048 if (addr
== R_LQSPI_CFG
) {
1049 xilinx_qspips_invalidate_mmio_ptr(q
);
1051 if (s
->regs
[R_CMND
] & R_CMND_RXFIFO_DRAIN
) {
1052 fifo8_reset(&s
->rx_fifo
);
1056 static void xlnx_zynqmp_qspips_write(void *opaque
, hwaddr addr
,
1057 uint64_t value
, unsigned size
)
1059 XlnxZynqMPQSPIPS
*s
= XLNX_ZYNQMP_QSPIPS(opaque
);
1060 uint32_t reg
= addr
/ 4;
1062 if (reg
<= R_MOD_ID
) {
1063 xilinx_qspips_write(opaque
, addr
, value
, size
);
1067 if (FIELD_EX32(value
, GQSPI_CNFG
, GEN_FIFO_START
) &&
1068 ARRAY_FIELD_EX32(s
->regs
, GQSPI_CNFG
, GEN_FIFO_START_MODE
)) {
1069 s
->man_start_com_g
= true;
1071 s
->regs
[reg
] = value
& ~(R_GQSPI_CNFG_GEN_FIFO_START_MASK
);
1073 case R_GQSPI_GEN_FIFO
:
1074 if (!fifo32_is_full(&s
->fifo_g
)) {
1075 fifo32_push(&s
->fifo_g
, value
);
1079 tx_data_bytes(&s
->tx_fifo_g
, (uint32_t)value
, 4,
1080 ARRAY_FIELD_EX32(s
->regs
, GQSPI_CNFG
, ENDIAN
));
1082 case R_GQSPI_FIFO_CTRL
:
1083 if (FIELD_EX32(value
, GQSPI_FIFO_CTRL
, GENERIC_FIFO_RESET
)) {
1084 fifo32_reset(&s
->fifo_g
);
1086 if (FIELD_EX32(value
, GQSPI_FIFO_CTRL
, TX_FIFO_RESET
)) {
1087 fifo8_reset(&s
->tx_fifo_g
);
1089 if (FIELD_EX32(value
, GQSPI_FIFO_CTRL
, RX_FIFO_RESET
)) {
1090 fifo8_reset(&s
->rx_fifo_g
);
1094 s
->regs
[R_GQSPI_IMR
] |= value
;
1097 s
->regs
[R_GQSPI_IMR
] &= ~value
;
1100 s
->regs
[R_GQSPI_ISR
] &= ~value
;
1104 case R_GQSPI_GF_SNAPSHOT
:
1105 case R_GQSPI_MOD_ID
:
1108 s
->regs
[reg
] = value
;
1111 xlnx_zynqmp_qspips_update_cs_lines(s
);
1112 xlnx_zynqmp_qspips_check_flush(s
);
1113 xlnx_zynqmp_qspips_update_cs_lines(s
);
1114 xlnx_zynqmp_qspips_update_ixr(s
);
1116 xlnx_zynqmp_qspips_notify(s
);
1119 static const MemoryRegionOps qspips_ops
= {
1120 .read
= xilinx_spips_read
,
1121 .write
= xilinx_qspips_write
,
1122 .endianness
= DEVICE_LITTLE_ENDIAN
,
1125 static const MemoryRegionOps xlnx_zynqmp_qspips_ops
= {
1126 .read
= xlnx_zynqmp_qspips_read
,
1127 .write
= xlnx_zynqmp_qspips_write
,
1128 .endianness
= DEVICE_LITTLE_ENDIAN
,
1131 #define LQSPI_CACHE_SIZE 1024
1133 static void lqspi_load_cache(void *opaque
, hwaddr addr
)
1135 XilinxQSPIPS
*q
= opaque
;
1136 XilinxSPIPS
*s
= opaque
;
1138 int flash_addr
= ((addr
& ~(LQSPI_CACHE_SIZE
- 1))
1139 / num_effective_busses(s
));
1140 int slave
= flash_addr
>> LQSPI_ADDRESS_BITS
;
1141 int cache_entry
= 0;
1142 uint32_t u_page_save
= s
->regs
[R_LQSPI_STS
] & ~LQSPI_CFG_U_PAGE
;
1144 if (addr
< q
->lqspi_cached_addr
||
1145 addr
> q
->lqspi_cached_addr
+ LQSPI_CACHE_SIZE
- 4) {
1146 xilinx_qspips_invalidate_mmio_ptr(q
);
1147 s
->regs
[R_LQSPI_STS
] &= ~LQSPI_CFG_U_PAGE
;
1148 s
->regs
[R_LQSPI_STS
] |= slave
? LQSPI_CFG_U_PAGE
: 0;
1150 DB_PRINT_L(0, "config reg status: %08x\n", s
->regs
[R_LQSPI_CFG
]);
1152 fifo8_reset(&s
->tx_fifo
);
1153 fifo8_reset(&s
->rx_fifo
);
1156 DB_PRINT_L(0, "pushing read instruction: %02x\n",
1157 (unsigned)(uint8_t)(s
->regs
[R_LQSPI_CFG
] &
1158 LQSPI_CFG_INST_CODE
));
1159 fifo8_push(&s
->tx_fifo
, s
->regs
[R_LQSPI_CFG
] & LQSPI_CFG_INST_CODE
);
1161 DB_PRINT_L(0, "pushing read address %06x\n", flash_addr
);
1162 if (s
->regs
[R_LQSPI_CFG
] & LQSPI_CFG_ADDR4
) {
1163 fifo8_push(&s
->tx_fifo
, (uint8_t)(flash_addr
>> 24));
1165 fifo8_push(&s
->tx_fifo
, (uint8_t)(flash_addr
>> 16));
1166 fifo8_push(&s
->tx_fifo
, (uint8_t)(flash_addr
>> 8));
1167 fifo8_push(&s
->tx_fifo
, (uint8_t)flash_addr
);
1169 if (s
->regs
[R_LQSPI_CFG
] & LQSPI_CFG_MODE_EN
) {
1170 fifo8_push(&s
->tx_fifo
, extract32(s
->regs
[R_LQSPI_CFG
],
1171 LQSPI_CFG_MODE_SHIFT
,
1172 LQSPI_CFG_MODE_WIDTH
));
1175 for (i
= 0; i
< (extract32(s
->regs
[R_LQSPI_CFG
], LQSPI_CFG_DUMMY_SHIFT
,
1176 LQSPI_CFG_DUMMY_WIDTH
)); ++i
) {
1177 DB_PRINT_L(0, "pushing dummy byte\n");
1178 fifo8_push(&s
->tx_fifo
, 0);
1180 xilinx_spips_update_cs_lines(s
);
1181 xilinx_spips_flush_txfifo(s
);
1182 fifo8_reset(&s
->rx_fifo
);
1184 DB_PRINT_L(0, "starting QSPI data read\n");
1186 while (cache_entry
< LQSPI_CACHE_SIZE
) {
1187 for (i
= 0; i
< 64; ++i
) {
1188 tx_data_bytes(&s
->tx_fifo
, 0, 1, false);
1190 xilinx_spips_flush_txfifo(s
);
1191 for (i
= 0; i
< 64; ++i
) {
1192 rx_data_bytes(&s
->rx_fifo
, &q
->lqspi_buf
[cache_entry
++], 1);
1196 s
->regs
[R_LQSPI_STS
] &= ~LQSPI_CFG_U_PAGE
;
1197 s
->regs
[R_LQSPI_STS
] |= u_page_save
;
1198 xilinx_spips_update_cs_lines(s
);
1200 q
->lqspi_cached_addr
= flash_addr
* num_effective_busses(s
);
1204 static void *lqspi_request_mmio_ptr(void *opaque
, hwaddr addr
, unsigned *size
,
1207 XilinxQSPIPS
*q
= opaque
;
1208 hwaddr offset_within_the_region
;
1210 if (!q
->mmio_execution_enabled
) {
1214 offset_within_the_region
= addr
& ~(LQSPI_CACHE_SIZE
- 1);
1215 lqspi_load_cache(opaque
, offset_within_the_region
);
1216 *size
= LQSPI_CACHE_SIZE
;
1217 *offset
= offset_within_the_region
;
1218 return q
->lqspi_buf
;
1222 lqspi_read(void *opaque
, hwaddr addr
, unsigned int size
)
1224 XilinxQSPIPS
*q
= opaque
;
1227 if (addr
>= q
->lqspi_cached_addr
&&
1228 addr
<= q
->lqspi_cached_addr
+ LQSPI_CACHE_SIZE
- 4) {
1229 uint8_t *retp
= &q
->lqspi_buf
[addr
- q
->lqspi_cached_addr
];
1230 ret
= cpu_to_le32(*(uint32_t *)retp
);
1231 DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr
,
1235 lqspi_load_cache(opaque
, addr
);
1236 return lqspi_read(opaque
, addr
, size
);
1240 static const MemoryRegionOps lqspi_ops
= {
1242 .request_ptr
= lqspi_request_mmio_ptr
,
1243 .endianness
= DEVICE_NATIVE_ENDIAN
,
1245 .min_access_size
= 1,
1246 .max_access_size
= 4
1250 static void xilinx_spips_realize(DeviceState
*dev
, Error
**errp
)
1252 XilinxSPIPS
*s
= XILINX_SPIPS(dev
);
1253 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1254 XilinxSPIPSClass
*xsc
= XILINX_SPIPS_GET_CLASS(s
);
1258 DB_PRINT_L(0, "realized spips\n");
1260 if (s
->num_busses
> MAX_NUM_BUSSES
) {
1262 "requested number of SPI busses %u exceeds maximum %d",
1263 s
->num_busses
, MAX_NUM_BUSSES
);
1266 if (s
->num_busses
< MIN_NUM_BUSSES
) {
1268 "requested number of SPI busses %u is below minimum %d",
1269 s
->num_busses
, MIN_NUM_BUSSES
);
1273 s
->spi
= g_new(SSIBus
*, s
->num_busses
);
1274 for (i
= 0; i
< s
->num_busses
; ++i
) {
1276 snprintf(bus_name
, 16, "spi%d", i
);
1277 s
->spi
[i
] = ssi_create_bus(dev
, bus_name
);
1280 s
->cs_lines
= g_new0(qemu_irq
, s
->num_cs
* s
->num_busses
);
1281 s
->cs_lines_state
= g_new0(bool, s
->num_cs
* s
->num_busses
);
1282 for (i
= 0, cs
= s
->cs_lines
; i
< s
->num_busses
; ++i
, cs
+= s
->num_cs
) {
1283 ssi_auto_connect_slaves(DEVICE(s
), cs
, s
->spi
[i
]);
1286 sysbus_init_irq(sbd
, &s
->irq
);
1287 for (i
= 0; i
< s
->num_cs
* s
->num_busses
; ++i
) {
1288 sysbus_init_irq(sbd
, &s
->cs_lines
[i
]);
1291 memory_region_init_io(&s
->iomem
, OBJECT(s
), xsc
->reg_ops
, s
,
1292 "spi", XLNX_ZYNQMP_SPIPS_R_MAX
* 4);
1293 sysbus_init_mmio(sbd
, &s
->iomem
);
1297 fifo8_create(&s
->rx_fifo
, xsc
->rx_fifo_size
);
1298 fifo8_create(&s
->tx_fifo
, xsc
->tx_fifo_size
);
1301 static void xilinx_qspips_realize(DeviceState
*dev
, Error
**errp
)
1303 XilinxSPIPS
*s
= XILINX_SPIPS(dev
);
1304 XilinxQSPIPS
*q
= XILINX_QSPIPS(dev
);
1305 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1307 DB_PRINT_L(0, "realized qspips\n");
1311 s
->num_txrx_bytes
= 4;
1313 xilinx_spips_realize(dev
, errp
);
1314 memory_region_init_io(&s
->mmlqspi
, OBJECT(s
), &lqspi_ops
, s
, "lqspi",
1315 (1 << LQSPI_ADDRESS_BITS
) * 2);
1316 sysbus_init_mmio(sbd
, &s
->mmlqspi
);
1318 q
->lqspi_cached_addr
= ~0ULL;
1320 /* mmio_execution breaks migration better aborting than having strange
1323 if (q
->mmio_execution_enabled
) {
1324 error_setg(&q
->migration_blocker
,
1325 "enabling mmio_execution breaks migration");
1326 migrate_add_blocker(q
->migration_blocker
, &error_fatal
);
1330 static void xlnx_zynqmp_qspips_realize(DeviceState
*dev
, Error
**errp
)
1332 XlnxZynqMPQSPIPS
*s
= XLNX_ZYNQMP_QSPIPS(dev
);
1333 XilinxSPIPSClass
*xsc
= XILINX_SPIPS_GET_CLASS(s
);
1335 xilinx_qspips_realize(dev
, errp
);
1336 fifo8_create(&s
->rx_fifo_g
, xsc
->rx_fifo_size
);
1337 fifo8_create(&s
->tx_fifo_g
, xsc
->tx_fifo_size
);
1338 fifo32_create(&s
->fifo_g
, 32);
1341 static void xlnx_zynqmp_qspips_init(Object
*obj
)
1343 XlnxZynqMPQSPIPS
*rq
= XLNX_ZYNQMP_QSPIPS(obj
);
1345 object_property_add_link(obj
, "stream-connected-dma", TYPE_STREAM_SLAVE
,
1346 (Object
**)&rq
->dma
,
1347 object_property_allow_set_link
,
1348 OBJ_PROP_LINK_UNREF_ON_RELEASE
,
1352 static int xilinx_spips_post_load(void *opaque
, int version_id
)
1354 xilinx_spips_update_ixr((XilinxSPIPS
*)opaque
);
1355 xilinx_spips_update_cs_lines((XilinxSPIPS
*)opaque
);
1359 static const VMStateDescription vmstate_xilinx_spips
= {
1360 .name
= "xilinx_spips",
1362 .minimum_version_id
= 2,
1363 .post_load
= xilinx_spips_post_load
,
1364 .fields
= (VMStateField
[]) {
1365 VMSTATE_FIFO8(tx_fifo
, XilinxSPIPS
),
1366 VMSTATE_FIFO8(rx_fifo
, XilinxSPIPS
),
1367 VMSTATE_UINT32_ARRAY(regs
, XilinxSPIPS
, XLNX_SPIPS_R_MAX
),
1368 VMSTATE_UINT8(snoop_state
, XilinxSPIPS
),
1369 VMSTATE_END_OF_LIST()
1373 static int xlnx_zynqmp_qspips_post_load(void *opaque
, int version_id
)
1375 XlnxZynqMPQSPIPS
*s
= (XlnxZynqMPQSPIPS
*)opaque
;
1376 XilinxSPIPS
*qs
= XILINX_SPIPS(s
);
1378 if (ARRAY_FIELD_EX32(s
->regs
, GQSPI_SELECT
, GENERIC_QSPI_EN
) &&
1379 fifo8_is_empty(&qs
->rx_fifo
) && fifo8_is_empty(&qs
->tx_fifo
)) {
1380 xlnx_zynqmp_qspips_update_ixr(s
);
1381 xlnx_zynqmp_qspips_update_cs_lines(s
);
1386 static const VMStateDescription vmstate_xilinx_qspips
= {
1387 .name
= "xilinx_qspips",
1389 .minimum_version_id
= 1,
1390 .fields
= (VMStateField
[]) {
1391 VMSTATE_STRUCT(parent_obj
, XilinxQSPIPS
, 0,
1392 vmstate_xilinx_spips
, XilinxSPIPS
),
1393 VMSTATE_END_OF_LIST()
1397 static const VMStateDescription vmstate_xlnx_zynqmp_qspips
= {
1398 .name
= "xlnx_zynqmp_qspips",
1400 .minimum_version_id
= 1,
1401 .post_load
= xlnx_zynqmp_qspips_post_load
,
1402 .fields
= (VMStateField
[]) {
1403 VMSTATE_STRUCT(parent_obj
, XlnxZynqMPQSPIPS
, 0,
1404 vmstate_xilinx_qspips
, XilinxQSPIPS
),
1405 VMSTATE_FIFO8(tx_fifo_g
, XlnxZynqMPQSPIPS
),
1406 VMSTATE_FIFO8(rx_fifo_g
, XlnxZynqMPQSPIPS
),
1407 VMSTATE_FIFO32(fifo_g
, XlnxZynqMPQSPIPS
),
1408 VMSTATE_UINT32_ARRAY(regs
, XlnxZynqMPQSPIPS
, XLNX_ZYNQMP_SPIPS_R_MAX
),
1409 VMSTATE_END_OF_LIST()
1413 static Property xilinx_qspips_properties
[] = {
1414 /* We had to turn this off for 2.10 as it is not compatible with migration.
1415 * It can be enabled but will prevent the device to be migrated.
1416 * This will go aways when a fix will be released.
1418 DEFINE_PROP_BOOL("x-mmio-exec", XilinxQSPIPS
, mmio_execution_enabled
,
1420 DEFINE_PROP_END_OF_LIST(),
1423 static Property xilinx_spips_properties
[] = {
1424 DEFINE_PROP_UINT8("num-busses", XilinxSPIPS
, num_busses
, 1),
1425 DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS
, num_cs
, 4),
1426 DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS
, num_txrx_bytes
, 1),
1427 DEFINE_PROP_END_OF_LIST(),
1430 static void xilinx_qspips_class_init(ObjectClass
*klass
, void * data
)
1432 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1433 XilinxSPIPSClass
*xsc
= XILINX_SPIPS_CLASS(klass
);
1435 dc
->realize
= xilinx_qspips_realize
;
1436 dc
->props
= xilinx_qspips_properties
;
1437 xsc
->reg_ops
= &qspips_ops
;
1438 xsc
->rx_fifo_size
= RXFF_A_Q
;
1439 xsc
->tx_fifo_size
= TXFF_A_Q
;
1442 static void xilinx_spips_class_init(ObjectClass
*klass
, void *data
)
1444 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1445 XilinxSPIPSClass
*xsc
= XILINX_SPIPS_CLASS(klass
);
1447 dc
->realize
= xilinx_spips_realize
;
1448 dc
->reset
= xilinx_spips_reset
;
1449 dc
->props
= xilinx_spips_properties
;
1450 dc
->vmsd
= &vmstate_xilinx_spips
;
1452 xsc
->reg_ops
= &spips_ops
;
1453 xsc
->rx_fifo_size
= RXFF_A
;
1454 xsc
->tx_fifo_size
= TXFF_A
;
1457 static void xlnx_zynqmp_qspips_class_init(ObjectClass
*klass
, void * data
)
1459 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1460 XilinxSPIPSClass
*xsc
= XILINX_SPIPS_CLASS(klass
);
1462 dc
->realize
= xlnx_zynqmp_qspips_realize
;
1463 dc
->reset
= xlnx_zynqmp_qspips_reset
;
1464 dc
->vmsd
= &vmstate_xlnx_zynqmp_qspips
;
1465 xsc
->reg_ops
= &xlnx_zynqmp_qspips_ops
;
1466 xsc
->rx_fifo_size
= RXFF_A_Q
;
1467 xsc
->tx_fifo_size
= TXFF_A_Q
;
1470 static const TypeInfo xilinx_spips_info
= {
1471 .name
= TYPE_XILINX_SPIPS
,
1472 .parent
= TYPE_SYS_BUS_DEVICE
,
1473 .instance_size
= sizeof(XilinxSPIPS
),
1474 .class_init
= xilinx_spips_class_init
,
1475 .class_size
= sizeof(XilinxSPIPSClass
),
1478 static const TypeInfo xilinx_qspips_info
= {
1479 .name
= TYPE_XILINX_QSPIPS
,
1480 .parent
= TYPE_XILINX_SPIPS
,
1481 .instance_size
= sizeof(XilinxQSPIPS
),
1482 .class_init
= xilinx_qspips_class_init
,
1485 static const TypeInfo xlnx_zynqmp_qspips_info
= {
1486 .name
= TYPE_XLNX_ZYNQMP_QSPIPS
,
1487 .parent
= TYPE_XILINX_QSPIPS
,
1488 .instance_size
= sizeof(XlnxZynqMPQSPIPS
),
1489 .instance_init
= xlnx_zynqmp_qspips_init
,
1490 .class_init
= xlnx_zynqmp_qspips_class_init
,
1493 static void xilinx_spips_register_types(void)
1495 type_register_static(&xilinx_spips_info
);
1496 type_register_static(&xilinx_qspips_info
);
1497 type_register_static(&xlnx_zynqmp_qspips_info
);
1500 type_init(xilinx_spips_register_types
)