hw/ppc/sam460ex.c

   1 /*
   2  * QEMU aCube Sam460ex board emulation
   3  *
   4  * Copyright (c) 2012 François Revol
   5  * Copyright (c) 2016-2018 BALATON Zoltan
   6  *
   7  * This file is derived from hw/ppc440_bamboo.c,
   8  * the copyright for that material belongs to the original owners.
   9  *
  10  * This work is licensed under the GNU GPL license version 2 or later.
  11  *
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "qemu-common.h"
  16 #include "qemu/cutils.h"
  17 #include "qemu/error-report.h"
  18 #include "qapi/error.h"
  19 #include "hw/hw.h"
  20 #include "sysemu/blockdev.h"
  21 #include "hw/boards.h"
  22 #include "sysemu/kvm.h"
  23 #include "kvm_ppc.h"
  24 #include "sysemu/device_tree.h"
  25 #include "sysemu/block-backend.h"
  26 #include "hw/loader.h"
  27 #include "elf.h"
  28 #include "exec/address-spaces.h"
  29 #include "exec/memory.h"
  30 #include "hw/ppc/ppc440.h"
  31 #include "hw/ppc/ppc405.h"
  32 #include "hw/block/flash.h"
  33 #include "sysemu/sysemu.h"
  34 #include "sysemu/qtest.h"
  35 #include "hw/sysbus.h"
  36 #include "hw/char/serial.h"
  37 #include "hw/i2c/ppc4xx_i2c.h"
  38 #include "hw/i2c/smbus.h"
  39 #include "hw/usb/hcd-ehci.h"
  40
  41 #define BINARY_DEVICE_TREE_FILE "canyonlands.dtb"
  42 #define UBOOT_FILENAME "u-boot-sam460-20100605.bin"
  43 /* to extract the official U-Boot bin from the updater: */
  44 /* dd bs=1 skip=$(($(stat -c '%s' updater/updater-460) - 0x80000)) \
  45      if=updater/updater-460 of=u-boot-sam460-20100605.bin */
  46
  47 /* from Sam460 U-Boot include/configs/Sam460ex.h */
  48 #define FLASH_BASE             0xfff00000
  49 #define FLASH_BASE_H           0x4
  50 #define FLASH_SIZE             (1 << 20)
  51 #define UBOOT_LOAD_BASE        0xfff80000
  52 #define UBOOT_SIZE             0x00080000
  53 #define UBOOT_ENTRY            0xfffffffc
  54
  55 /* from U-Boot */
  56 #define EPAPR_MAGIC           (0x45504150)
  57 #define KERNEL_ADDR           0x1000000
  58 #define FDT_ADDR              0x1800000
  59 #define RAMDISK_ADDR          0x1900000
  60
  61 /* Sam460ex IRQ MAP:
  62    IRQ0  = ETH_INT
  63    IRQ1  = FPGA_INT
  64    IRQ2  = PCI_INT (PCIA, PCIB, PCIC, PCIB)
  65    IRQ3  = FPGA_INT2
  66    IRQ11 = RTC_INT
  67    IRQ12 = SM502_INT
  68 */
  69
  70 #define SDRAM_NR_BANKS 4
  71
  72 /* FIXME: See u-boot.git 8ac41e, also fix in ppc440_uc.c */
  73 static const unsigned int ppc460ex_sdram_bank_sizes[] = {
  74     1024 << 20, 512 << 20, 256 << 20, 128 << 20, 64 << 20, 32 << 20, 0
  75 };
  76
  77 struct boot_info {
  78     uint32_t dt_base;
  79     uint32_t dt_size;
  80     uint32_t entry;
  81 };
  82
  83 /*****************************************************************************/
  84 /* SPD eeprom content from mips_malta.c */
  85
  86 struct _eeprom24c0x_t {
  87   uint8_t tick;
  88   uint8_t address;
  89   uint8_t command;
  90   uint8_t ack;
  91   uint8_t scl;
  92   uint8_t sda;
  93   uint8_t data;
  94   uint8_t contents[256];
  95 };
  96
  97 typedef struct _eeprom24c0x_t eeprom24c0x_t;
  98
  99 static eeprom24c0x_t spd_eeprom = {
 100     .contents = {
 101         /* 00000000: */ 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
 102         /* 00000008: */ 0x04, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
 103         /* 00000010: */ 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
 104         /* 00000018: */ 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
 105         /* 00000020: */ 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
 106         /* 00000028: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 107         /* 00000030: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 108         /* 00000038: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
 109         /* 00000040: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 110         /* 00000048: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 111         /* 00000050: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 112         /* 00000058: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 113         /* 00000060: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 114         /* 00000068: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 115         /* 00000070: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 116         /* 00000078: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
 117     },
 118 };
 119
 120 static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size)
 121 {
 122     enum { SDR = 0x4, DDR1 = 0x7, DDR2 = 0x8 } type;
 123     uint8_t *spd = spd_eeprom.contents;
 124     uint8_t nbanks = 0;
 125     uint16_t density = 0;
 126     int i;
 127
 128     /* work in terms of MB */
 129     ram_size >>= 20;
 130
 131     while ((ram_size >= 4) && (nbanks <= 2)) {
 132         int sz_log2 = MIN(31 - clz32(ram_size), 14);
 133         nbanks++;
 134         density |= 1 << (sz_log2 - 2);
 135         ram_size -= 1 << sz_log2;
 136     }
 137
 138     /* split to 2 banks if possible */
 139     if ((nbanks == 1) && (density > 1)) {
 140         nbanks++;
 141         density >>= 1;
 142     }
 143
 144     if (density & 0xff00) {
 145         density = (density & 0xe0) | ((density >> 8) & 0x1f);
 146         type = DDR2;
 147     } else if (!(density & 0x1f)) {
 148         type = DDR2;
 149     } else {
 150         type = SDR;
 151     }
 152
 153     if (ram_size) {
 154         warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB"
 155                     " of SDRAM", ram_size);
 156     }
 157
 158     /* fill in SPD memory information */
 159     spd[2] = type;
 160     spd[5] = nbanks;
 161     spd[31] = density;
 162
 163     /* XXX: this is totally random */
 164     spd[9] = 0x10; /* CAS tcyc */
 165     spd[18] = 0x20; /* CAS bit */
 166     spd[23] = 0x10; /* CAS tcyc */
 167     spd[25] = 0x10; /* CAS tcyc */
 168
 169     /* checksum */
 170     spd[63] = 0;
 171     for (i = 0; i < 63; i++) {
 172         spd[63] += spd[i];
 173     }
 174
 175     /* copy for SMBUS */
 176     memcpy(eeprom, spd, sizeof(spd_eeprom.contents));
 177 }
 178
 179 static void generate_eeprom_serial(uint8_t *eeprom)
 180 {
 181     int i, pos = 0;
 182     uint8_t mac[6] = { 0x00 };
 183     uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 };
 184
 185     /* version */
 186     eeprom[pos++] = 0x01;
 187
 188     /* count */
 189     eeprom[pos++] = 0x02;
 190
 191     /* MAC address */
 192     eeprom[pos++] = 0x01; /* MAC */
 193     eeprom[pos++] = 0x06; /* length */
 194     memcpy(&eeprom[pos], mac, sizeof(mac));
 195     pos += sizeof(mac);
 196
 197     /* serial number */
 198     eeprom[pos++] = 0x02; /* serial */
 199     eeprom[pos++] = 0x05; /* length */
 200     memcpy(&eeprom[pos], sn, sizeof(sn));
 201     pos += sizeof(sn);
 202
 203     /* checksum */
 204     eeprom[pos] = 0;
 205     for (i = 0; i < pos; i++) {
 206         eeprom[pos] += eeprom[i];
 207     }
 208 }
 209
 210 /*****************************************************************************/
 211
 212 static int sam460ex_load_uboot(void)
 213 {
 214     DriveInfo *dinfo;
 215     BlockBackend *blk = NULL;
 216     hwaddr base = FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32);
 217     long bios_size = FLASH_SIZE;
 218     int fl_sectors;
 219
 220     dinfo = drive_get(IF_PFLASH, 0, 0);
 221     if (dinfo) {
 222         blk = blk_by_legacy_dinfo(dinfo);
 223         bios_size = blk_getlength(blk);
 224     }
 225     fl_sectors = (bios_size + 65535) >> 16;
 226
 227     if (!pflash_cfi01_register(base, NULL, "sam460ex.flash", bios_size,
 228                                blk, (64 * 1024), fl_sectors,
 229                                1, 0x89, 0x18, 0x0000, 0x0, 1)) {
 230         error_report("qemu: Error registering flash memory.");
 231         /* XXX: return an error instead? */
 232         exit(1);
 233     }
 234
 235     if (!blk) {
 236         /*error_report("No flash image given with the 'pflash' parameter,"
 237                 " using default u-boot image");*/
 238         base = UBOOT_LOAD_BASE | ((hwaddr)FLASH_BASE_H << 32);
 239         rom_add_file_fixed(UBOOT_FILENAME, base, -1);
 240     }
 241
 242     return 0;
 243 }
 244
 245 static int sam460ex_load_device_tree(hwaddr addr,
 246                                      uint32_t ramsize,
 247                                      hwaddr initrd_base,
 248                                      hwaddr initrd_size,
 249                                      const char *kernel_cmdline)
 250 {
 251     int ret = -1;
 252     uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) };
 253     char *filename;
 254     int fdt_size;
 255     void *fdt;
 256     uint32_t tb_freq = 50000000;
 257     uint32_t clock_freq = 50000000;
 258
 259     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
 260     if (!filename) {
 261         goto out;
 262     }
 263     fdt = load_device_tree(filename, &fdt_size);
 264     g_free(filename);
 265     if (fdt == NULL) {
 266         goto out;
 267     }
 268
 269     /* Manipulate device tree in memory. */
 270
 271     ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
 272                                sizeof(mem_reg_property));
 273     if (ret < 0) {
 274         error_report("couldn't set /memory/reg");
 275     }
 276
 277     /* default FDT doesn't have a /chosen node... */
 278     qemu_fdt_add_subnode(fdt, "/chosen");
 279
 280     ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
 281                                     initrd_base);
 282     if (ret < 0) {
 283         error_report("couldn't set /chosen/linux,initrd-start");
 284     }
 285
 286     ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
 287                                     (initrd_base + initrd_size));
 288     if (ret < 0) {
 289         error_report("couldn't set /chosen/linux,initrd-end");
 290     }
 291
 292     ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
 293                                       kernel_cmdline);
 294     if (ret < 0) {
 295         error_report("couldn't set /chosen/bootargs");
 296     }
 297
 298     /* Copy data from the host device tree into the guest. Since the guest can
 299      * directly access the timebase without host involvement, we must expose
 300      * the correct frequencies. */
 301     if (kvm_enabled()) {
 302         tb_freq = kvmppc_get_tbfreq();
 303         clock_freq = kvmppc_get_clockfreq();
 304     }
 305
 306     qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency",
 307                               clock_freq);
 308     qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency",
 309                               tb_freq);
 310
 311     rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
 312     g_free(fdt);
 313     ret = fdt_size;
 314
 315 out:
 316
 317     return ret;
 318 }
 319
 320 /* Create reset TLB entries for BookE, mapping only the flash memory.  */
 321 static void mmubooke_create_initial_mapping_uboot(CPUPPCState *env)
 322 {
 323     ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
 324
 325     /* on reset the flash is mapped by a shadow TLB,
 326      * but since we don't implement them we need to use
 327      * the same values U-Boot will use to avoid a fault.
 328      */
 329     tlb->attr = 0;
 330     tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
 331     tlb->size = 0x10000000; /* up to 0xffffffff  */
 332     tlb->EPN = 0xf0000000 & TARGET_PAGE_MASK;
 333     tlb->RPN = (0xf0000000 & TARGET_PAGE_MASK) | 0x4;
 334     tlb->PID = 0;
 335 }
 336
 337 /* Create reset TLB entries for BookE, spanning the 32bit addr space.  */
 338 static void mmubooke_create_initial_mapping(CPUPPCState *env,
 339                                      target_ulong va,
 340                                      hwaddr pa)
 341 {
 342     ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
 343
 344     tlb->attr = 0;
 345     tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
 346     tlb->size = 1 << 31; /* up to 0x80000000  */
 347     tlb->EPN = va & TARGET_PAGE_MASK;
 348     tlb->RPN = pa & TARGET_PAGE_MASK;
 349     tlb->PID = 0;
 350 }
 351
 352 static void main_cpu_reset(void *opaque)
 353 {
 354     PowerPCCPU *cpu = opaque;
 355     CPUPPCState *env = &cpu->env;
 356     struct boot_info *bi = env->load_info;
 357
 358     cpu_reset(CPU(cpu));
 359
 360     /* either we have a kernel to boot or we jump to U-Boot */
 361     if (bi->entry != UBOOT_ENTRY) {
 362         env->gpr[1] = (16 << 20) - 8;
 363         env->gpr[3] = FDT_ADDR;
 364         env->nip = bi->entry;
 365
 366         /* Create a mapping for the kernel.  */
 367         mmubooke_create_initial_mapping(env, 0, 0);
 368         env->gpr[6] = tswap32(EPAPR_MAGIC);
 369         env->gpr[7] = (16 << 20) - 8; /*bi->ima_size;*/
 370
 371     } else {
 372         env->nip = UBOOT_ENTRY;
 373         mmubooke_create_initial_mapping_uboot(env);
 374     }
 375 }
 376
 377 static void sam460ex_init(MachineState *machine)
 378 {
 379     MemoryRegion *address_space_mem = get_system_memory();
 380     MemoryRegion *isa = g_new(MemoryRegion, 1);
 381     MemoryRegion *ram_memories = g_new(MemoryRegion, SDRAM_NR_BANKS);
 382     hwaddr ram_bases[SDRAM_NR_BANKS];
 383     hwaddr ram_sizes[SDRAM_NR_BANKS];
 384     MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
 385     qemu_irq *irqs, *uic[4];
 386     PCIBus *pci_bus;
 387     PowerPCCPU *cpu;
 388     CPUPPCState *env;
 389     PPC4xxI2CState *i2c[2];
 390     hwaddr entry = UBOOT_ENTRY;
 391     hwaddr loadaddr = 0;
 392     target_long initrd_size = 0;
 393     DeviceState *dev;
 394     SysBusDevice *sbdev;
 395     int success;
 396     int i;
 397     struct boot_info *boot_info;
 398     const size_t smbus_eeprom_size = 8 * 256;
 399     uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size);
 400
 401     cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
 402     env = &cpu->env;
 403     if (env->mmu_model != POWERPC_MMU_BOOKE) {
 404         error_report("Only MMU model BookE is supported by this machine.");
 405         exit(1);
 406     }
 407
 408 #ifdef TARGET_PPCEMB
 409     if (!qtest_enabled()) {
 410         warn_report("qemu-system-ppcemb is deprecated, "
 411                     "please use qemu-system-ppc instead.");
 412     }
 413 #endif
 414
 415     qemu_register_reset(main_cpu_reset, cpu);
 416     boot_info = g_malloc0(sizeof(*boot_info));
 417     env->load_info = boot_info;
 418
 419     ppc_booke_timers_init(cpu, 50000000, 0);
 420     ppc_dcr_init(env, NULL, NULL);
 421
 422     /* PLB arbitrer */
 423     ppc4xx_plb_init(env);
 424
 425     /* interrupt controllers */
 426     irqs = g_malloc0(sizeof(*irqs) * PPCUIC_OUTPUT_NB);
 427     irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
 428     irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
 429     uic[0] = ppcuic_init(env, irqs, 0xc0, 0, 1);
 430     uic[1] = ppcuic_init(env, &uic[0][30], 0xd0, 0, 1);
 431     uic[2] = ppcuic_init(env, &uic[0][10], 0xe0, 0, 1);
 432     uic[3] = ppcuic_init(env, &uic[0][16], 0xf0, 0, 1);
 433
 434     /* SDRAM controller */
 435     memset(ram_bases, 0, sizeof(ram_bases));
 436     memset(ram_sizes, 0, sizeof(ram_sizes));
 437     /* put all RAM on first bank because board has one slot
 438      * and firmware only checks that */
 439     machine->ram_size = ppc4xx_sdram_adjust(machine->ram_size, 1,
 440                                    ram_memories, ram_bases, ram_sizes,
 441                                    ppc460ex_sdram_bank_sizes);
 442
 443     /* FIXME: does 460EX have ECC interrupts? */
 444     ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories,
 445                       ram_bases, ram_sizes, 1);
 446
 447     /* generate SPD EEPROM data */
 448     for (i = 0; i < SDRAM_NR_BANKS; i++) {
 449         generate_eeprom_spd(&smbus_eeprom_buf[i * 256], ram_sizes[i]);
 450     }
 451     generate_eeprom_serial(&smbus_eeprom_buf[4 * 256]);
 452     generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
 453
 454     /* IIC controllers */
 455     dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, uic[0][2]);
 456     i2c[0] = PPC4xx_I2C(dev);
 457     object_property_set_bool(OBJECT(dev), true, "realized", NULL);
 458     smbus_eeprom_init(i2c[0]->bus, 8, smbus_eeprom_buf, smbus_eeprom_size);
 459     g_free(smbus_eeprom_buf);
 460
 461     dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, uic[0][3]);
 462     i2c[1] = PPC4xx_I2C(dev);
 463
 464     /* External bus controller */
 465     ppc405_ebc_init(env);
 466
 467     /* CPR */
 468     ppc4xx_cpr_init(env);
 469
 470     /* PLB to AHB bridge */
 471     ppc4xx_ahb_init(env);
 472
 473     /* System DCRs */
 474     ppc4xx_sdr_init(env);
 475
 476     /* MAL */
 477     ppc4xx_mal_init(env, 4, 16, &uic[2][3]);
 478
 479     /* 256K of L2 cache as memory */
 480     ppc4xx_l2sram_init(env);
 481     /* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */
 482     memory_region_init_ram(l2cache_ram, NULL, "ppc440.l2cache_ram", 256 << 10,
 483                            &error_abort);
 484     memory_region_add_subregion(address_space_mem, 0x400000000LL, l2cache_ram);
 485
 486     /* USB */
 487     sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, uic[2][29]);
 488     dev = qdev_create(NULL, "sysbus-ohci");
 489     qdev_prop_set_string(dev, "masterbus", "usb-bus.0");
 490     qdev_prop_set_uint32(dev, "num-ports", 6);
 491     qdev_init_nofail(dev);
 492     sbdev = SYS_BUS_DEVICE(dev);
 493     sysbus_mmio_map(sbdev, 0, 0x4bffd0000);
 494     sysbus_connect_irq(sbdev, 0, uic[2][30]);
 495     usb_create_simple(usb_bus_find(-1), "usb-kbd");
 496     usb_create_simple(usb_bus_find(-1), "usb-mouse");
 497
 498     /* PCI bus */
 499     ppc460ex_pcie_init(env);
 500     /* FIXME: is this correct? */
 501     dev = sysbus_create_varargs("ppc440-pcix-host", 0xc0ec00000,
 502                                 uic[1][0], uic[1][20], uic[1][21], uic[1][22],
 503                                 NULL);
 504     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 505     if (!pci_bus) {
 506         error_report("couldn't create PCI controller!");
 507         exit(1);
 508     }
 509     memory_region_init_alias(isa, NULL, "isa_mmio", get_system_io(),
 510                              0, 0x10000);
 511     memory_region_add_subregion(get_system_memory(), 0xc08000000, isa);
 512
 513     /* PCI devices */
 514     pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501");
 515     /* SoC has a single SATA port but we don't emulate that yet
 516      * However, firmware and usual clients have driver for SiI311x
 517      * so add one for convenience by default */
 518     if (defaults_enabled()) {
 519         pci_create_simple(pci_bus, -1, "sii3112");
 520     }
 521
 522     /* SoC has 4 UARTs
 523      * but board has only one wired and two are present in fdt */
 524     if (serial_hds[0] != NULL) {
 525         serial_mm_init(address_space_mem, 0x4ef600300, 0, uic[1][1],
 526                        PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
 527                        DEVICE_BIG_ENDIAN);
 528     }
 529     if (serial_hds[1] != NULL) {
 530         serial_mm_init(address_space_mem, 0x4ef600400, 0, uic[0][1],
 531                        PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
 532                        DEVICE_BIG_ENDIAN);
 533     }
 534
 535     /* Load U-Boot image. */
 536     if (!machine->kernel_filename) {
 537         success = sam460ex_load_uboot();
 538         if (success < 0) {
 539             error_report("qemu: could not load firmware");
 540             exit(1);
 541         }
 542     }
 543
 544     /* Load kernel. */
 545     if (machine->kernel_filename) {
 546         success = load_uimage(machine->kernel_filename, &entry, &loadaddr,
 547                               NULL, NULL, NULL);
 548         if (success < 0) {
 549             uint64_t elf_entry, elf_lowaddr;
 550
 551             success = load_elf(machine->kernel_filename, NULL, NULL, &elf_entry,
 552                                &elf_lowaddr, NULL, 1, PPC_ELF_MACHINE, 0, 0);
 553             entry = elf_entry;
 554             loadaddr = elf_lowaddr;
 555         }
 556         /* XXX try again as binary */
 557         if (success < 0) {
 558             error_report("qemu: could not load kernel '%s'",
 559                     machine->kernel_filename);
 560             exit(1);
 561         }
 562     }
 563
 564     /* Load initrd. */
 565     if (machine->initrd_filename) {
 566         initrd_size = load_image_targphys(machine->initrd_filename,
 567                                           RAMDISK_ADDR,
 568                                           machine->ram_size - RAMDISK_ADDR);
 569         if (initrd_size < 0) {
 570             error_report("qemu: could not load ram disk '%s' at %x",
 571                     machine->initrd_filename, RAMDISK_ADDR);
 572             exit(1);
 573         }
 574     }
 575
 576     /* If we're loading a kernel directly, we must load the device tree too. */
 577     if (machine->kernel_filename) {
 578         int dt_size;
 579
 580         dt_size = sam460ex_load_device_tree(FDT_ADDR, machine->ram_size,
 581                                     RAMDISK_ADDR, initrd_size,
 582                                     machine->kernel_cmdline);
 583         if (dt_size < 0) {
 584             error_report("couldn't load device tree");
 585             exit(1);
 586         }
 587
 588         boot_info->dt_base = FDT_ADDR;
 589         boot_info->dt_size = dt_size;
 590     }
 591
 592     boot_info->entry = entry;
 593 }
 594
 595 static void sam460ex_machine_init(MachineClass *mc)
 596 {
 597     mc->desc = "aCube Sam460ex";
 598     mc->init = sam460ex_init;
 599     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb");
 600     mc->default_ram_size = 512 * M_BYTE;
 601 }
 602
 603 DEFINE_MACHINE("sam460ex", sam460ex_machine_init)