include/qom/cpu.h

   1 /*
   2  * QEMU CPU model
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20 #ifndef QEMU_CPU_H
  21 #define QEMU_CPU_H
  22
  23 #include <signal.h>
  24 #include <setjmp.h>
  25 #include "hw/qdev-core.h"
  26 #include "disas/bfd.h"
  27 #include "exec/hwaddr.h"
  28 #include "exec/memattrs.h"
  29 #include "qemu/queue.h"
  30 #include "qemu/thread.h"
  31 #include "qemu/typedefs.h"
  32
  33 typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
  34                                      void *opaque);
  35
  36 /**
  37  * vaddr:
  38  * Type wide enough to contain any #target_ulong virtual address.
  39  */
  40 typedef uint64_t vaddr;
  41 #define VADDR_PRId PRId64
  42 #define VADDR_PRIu PRIu64
  43 #define VADDR_PRIo PRIo64
  44 #define VADDR_PRIx PRIx64
  45 #define VADDR_PRIX PRIX64
  46 #define VADDR_MAX UINT64_MAX
  47
  48 /**
  49  * SECTION:cpu
  50  * @section_id: QEMU-cpu
  51  * @title: CPU Class
  52  * @short_description: Base class for all CPUs
  53  */
  54
  55 #define TYPE_CPU "cpu"
  56
  57 /* Since this macro is used a lot in hot code paths and in conjunction with
  58  * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using
  59  * an unchecked cast.
  60  */
  61 #define CPU(obj) ((CPUState *)(obj))
  62
  63 #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
  64 #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
  65
  66 typedef struct CPUState CPUState;
  67
  68 typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
  69                                     bool is_write, bool is_exec, int opaque,
  70                                     unsigned size);
  71
  72 struct TranslationBlock;
  73
  74 /**
  75  * CPUClass:
  76  * @class_by_name: Callback to map -cpu command line model name to an
  77  * instantiatable CPU type.
  78  * @parse_features: Callback to parse command line arguments.
  79  * @reset: Callback to reset the #CPUState to its initial state.
  80  * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
  81  * @has_work: Callback for checking if there is work to do.
  82  * @do_interrupt: Callback for interrupt handling.
  83  * @do_unassigned_access: Callback for unassigned access handling.
  84  * @do_unaligned_access: Callback for unaligned access handling, if
  85  * the target defines #ALIGNED_ONLY.
  86  * @virtio_is_big_endian: Callback to return %true if a CPU which supports
  87  * runtime configurable endianness is currently big-endian. Non-configurable
  88  * CPUs can use the default implementation of this method. This method should
  89  * not be used by any callers other than the pre-1.0 virtio devices.
  90  * @memory_rw_debug: Callback for GDB memory access.
  91  * @dump_state: Callback for dumping state.
  92  * @dump_statistics: Callback for dumping statistics.
  93  * @get_arch_id: Callback for getting architecture-dependent CPU ID.
  94  * @get_paging_enabled: Callback for inquiring whether paging is enabled.
  95  * @get_memory_mapping: Callback for obtaining the memory mappings.
  96  * @set_pc: Callback for setting the Program Counter register.
  97  * @synchronize_from_tb: Callback for synchronizing state from a TCG
  98  * #TranslationBlock.
  99  * @handle_mmu_fault: Callback for handling an MMU fault.
 100  * @get_phys_page_debug: Callback for obtaining a physical address.
 101  * @gdb_read_register: Callback for letting GDB read a register.
 102  * @gdb_write_register: Callback for letting GDB write a register.
 103  * @debug_excp_handler: Callback for handling debug exceptions.
 104  * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
 105  * 64-bit VM coredump.
 106  * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
 107  * note to a 32-bit VM coredump.
 108  * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
 109  * 32-bit VM coredump.
 110  * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
 111  * note to a 32-bit VM coredump.
 112  * @vmsd: State description for migration.
 113  * @gdb_num_core_regs: Number of core registers accessible to GDB.
 114  * @gdb_core_xml_file: File name for core registers GDB XML description.
 115  * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
 116  *           before the insn which triggers a watchpoint rather than after it.
 117  * @cpu_exec_enter: Callback for cpu_exec preparation.
 118  * @cpu_exec_exit: Callback for cpu_exec cleanup.
 119  * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
 120  * @disas_set_info: Setup architecture specific components of disassembly info
 121  *
 122  * Represents a CPU family or model.
 123  */
 124 typedef struct CPUClass {
 125     /*< private >*/
 126     DeviceClass parent_class;
 127     /*< public >*/
 128
 129     ObjectClass *(*class_by_name)(const char *cpu_model);
 130     void (*parse_features)(CPUState *cpu, char *str, Error **errp);
 131
 132     void (*reset)(CPUState *cpu);
 133     int reset_dump_flags;
 134     bool (*has_work)(CPUState *cpu);
 135     void (*do_interrupt)(CPUState *cpu);
 136     CPUUnassignedAccess do_unassigned_access;
 137     void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
 138                                 int is_write, int is_user, uintptr_t retaddr);
 139     bool (*virtio_is_big_endian)(CPUState *cpu);
 140     int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
 141                            uint8_t *buf, int len, bool is_write);
 142     void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 143                        int flags);
 144     void (*dump_statistics)(CPUState *cpu, FILE *f,
 145                             fprintf_function cpu_fprintf, int flags);
 146     int64_t (*get_arch_id)(CPUState *cpu);
 147     bool (*get_paging_enabled)(const CPUState *cpu);
 148     void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
 149                                Error **errp);
 150     void (*set_pc)(CPUState *cpu, vaddr value);
 151     void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
 152     int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw,
 153                             int mmu_index);
 154     hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
 155     int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
 156     int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
 157     void (*debug_excp_handler)(CPUState *cpu);
 158
 159     int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
 160                             int cpuid, void *opaque);
 161     int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
 162                                 void *opaque);
 163     int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
 164                             int cpuid, void *opaque);
 165     int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
 166                                 void *opaque);
 167
 168     const struct VMStateDescription *vmsd;
 169     int gdb_num_core_regs;
 170     const char *gdb_core_xml_file;
 171     bool gdb_stop_before_watchpoint;
 172
 173     void (*cpu_exec_enter)(CPUState *cpu);
 174     void (*cpu_exec_exit)(CPUState *cpu);
 175     bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
 176
 177     void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
 178 } CPUClass;
 179
 180 #ifdef HOST_WORDS_BIGENDIAN
 181 typedef struct icount_decr_u16 {
 182     uint16_t high;
 183     uint16_t low;
 184 } icount_decr_u16;
 185 #else
 186 typedef struct icount_decr_u16 {
 187     uint16_t low;
 188     uint16_t high;
 189 } icount_decr_u16;
 190 #endif
 191
 192 typedef struct CPUBreakpoint {
 193     vaddr pc;
 194     int flags; /* BP_* */
 195     QTAILQ_ENTRY(CPUBreakpoint) entry;
 196 } CPUBreakpoint;
 197
 198 typedef struct CPUWatchpoint {
 199     vaddr vaddr;
 200     vaddr len;
 201     vaddr hitaddr;
 202     MemTxAttrs hitattrs;
 203     int flags; /* BP_* */
 204     QTAILQ_ENTRY(CPUWatchpoint) entry;
 205 } CPUWatchpoint;
 206
 207 struct KVMState;
 208 struct kvm_run;
 209
 210 #define TB_JMP_CACHE_BITS 12
 211 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
 212
 213 /**
 214  * CPUState:
 215  * @cpu_index: CPU index (informative).
 216  * @nr_cores: Number of cores within this CPU package.
 217  * @nr_threads: Number of threads within this CPU.
 218  * @numa_node: NUMA node this CPU is belonging to.
 219  * @host_tid: Host thread ID.
 220  * @running: #true if CPU is currently running (usermode).
 221  * @created: Indicates whether the CPU thread has been successfully created.
 222  * @interrupt_request: Indicates a pending interrupt request.
 223  * @halted: Nonzero if the CPU is in suspended state.
 224  * @stop: Indicates a pending stop request.
 225  * @stopped: Indicates the CPU has been artificially stopped.
 226  * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU
 227  * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
 228  *           CPU and return to its top level loop.
 229  * @singlestep_enabled: Flags for single-stepping.
 230  * @icount_extra: Instructions until next timer event.
 231  * @icount_decr: Number of cycles left, with interrupt flag in high bit.
 232  * This allows a single read-compare-cbranch-write sequence to test
 233  * for both decrementer underflow and exceptions.
 234  * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution
 235  * requires that IO only be performed on the last instruction of a TB
 236  * so that interrupts take effect immediately.
 237  * @env_ptr: Pointer to subclass-specific CPUArchState field.
 238  * @current_tb: Currently executing TB.
 239  * @gdb_regs: Additional GDB registers.
 240  * @gdb_num_regs: Number of total registers accessible to GDB.
 241  * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
 242  * @next_cpu: Next CPU sharing TB cache.
 243  * @opaque: User data.
 244  * @mem_io_pc: Host Program Counter at which the memory was accessed.
 245  * @mem_io_vaddr: Target virtual address at which the memory was accessed.
 246  * @kvm_fd: vCPU file descriptor for KVM.
 247  * @work_mutex: Lock to prevent multiple access to queued_work_*.
 248  * @queued_work_first: First asynchronous work pending.
 249  *
 250  * State of one CPU core or thread.
 251  */
 252 struct CPUState {
 253     /*< private >*/
 254     DeviceState parent_obj;
 255     /*< public >*/
 256
 257     int nr_cores;
 258     int nr_threads;
 259     int numa_node;
 260
 261     struct QemuThread *thread;
 262 #ifdef _WIN32
 263     HANDLE hThread;
 264 #endif
 265     int thread_id;
 266     uint32_t host_tid;
 267     bool running;
 268     struct QemuCond *halt_cond;
 269     bool thread_kicked;
 270     bool created;
 271     bool stop;
 272     bool stopped;
 273     /* Endianness, false = little endian, true = big endian. */
 274     bool bigendian;
 275     bool crash_occurred;
 276     bool exit_request;
 277     uint32_t interrupt_request;
 278     int singlestep_enabled;
 279     int64_t icount_extra;
 280     sigjmp_buf jmp_env;
 281
 282     QemuMutex work_mutex;
 283     struct qemu_work_item *queued_work_first, *queued_work_last;
 284
 285     AddressSpace *as;
 286     struct AddressSpaceDispatch *memory_dispatch;
 287     MemoryListener *tcg_as_listener;
 288
 289     void *env_ptr; /* CPUArchState */
 290     struct TranslationBlock *current_tb;
 291     struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
 292     struct GDBRegisterState *gdb_regs;
 293     int gdb_num_regs;
 294     int gdb_num_g_regs;
 295     QTAILQ_ENTRY(CPUState) node;
 296
 297     /* ice debug support */
 298     QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints;
 299
 300     QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;
 301     CPUWatchpoint *watchpoint_hit;
 302
 303     void *opaque;
 304
 305     /* In order to avoid passing too many arguments to the MMIO helpers,
 306      * we store some rarely used information in the CPU context.
 307      */
 308     uintptr_t mem_io_pc;
 309     vaddr mem_io_vaddr;
 310
 311     int kvm_fd;
 312     bool kvm_vcpu_dirty;
 313     struct KVMState *kvm_state;
 314     struct kvm_run *kvm_run;
 315
 316     /* TODO Move common fields from CPUArchState here. */
 317     int cpu_index; /* used by alpha TCG */
 318     uint32_t halted; /* used by alpha, cris, ppc TCG */
 319     union {
 320         uint32_t u32;
 321         icount_decr_u16 u16;
 322     } icount_decr;
 323     uint32_t can_do_io;
 324     int32_t exception_index; /* used by m68k TCG */
 325
 326     /* Note that this is accessed at the start of every TB via a negative
 327        offset from AREG0.  Leave this field at the end so as to make the
 328        (absolute value) offset as small as possible.  This reduces code
 329        size, especially for hosts without large memory offsets.  */
 330     uint32_t tcg_exit_req;
 331 };
 332
 333 QTAILQ_HEAD(CPUTailQ, CPUState);
 334 extern struct CPUTailQ cpus;
 335 #define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node)
 336 #define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node)
 337 #define CPU_FOREACH_SAFE(cpu, next_cpu) \
 338     QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu)
 339 #define CPU_FOREACH_REVERSE(cpu) \
 340     QTAILQ_FOREACH_REVERSE(cpu, &cpus, CPUTailQ, node)
 341 #define first_cpu QTAILQ_FIRST(&cpus)
 342
 343 extern __thread CPUState *current_cpu;
 344
 345 /**
 346  * cpu_paging_enabled:
 347  * @cpu: The CPU whose state is to be inspected.
 348  *
 349  * Returns: %true if paging is enabled, %false otherwise.
 350  */
 351 bool cpu_paging_enabled(const CPUState *cpu);
 352
 353 /**
 354  * cpu_get_memory_mapping:
 355  * @cpu: The CPU whose memory mappings are to be obtained.
 356  * @list: Where to write the memory mappings to.
 357  * @errp: Pointer for reporting an #Error.
 358  */
 359 void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
 360                             Error **errp);
 361
 362 /**
 363  * cpu_write_elf64_note:
 364  * @f: pointer to a function that writes memory to a file
 365  * @cpu: The CPU whose memory is to be dumped
 366  * @cpuid: ID number of the CPU
 367  * @opaque: pointer to the CPUState struct
 368  */
 369 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
 370                          int cpuid, void *opaque);
 371
 372 /**
 373  * cpu_write_elf64_qemunote:
 374  * @f: pointer to a function that writes memory to a file
 375  * @cpu: The CPU whose memory is to be dumped
 376  * @cpuid: ID number of the CPU
 377  * @opaque: pointer to the CPUState struct
 378  */
 379 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
 380                              void *opaque);
 381
 382 /**
 383  * cpu_write_elf32_note:
 384  * @f: pointer to a function that writes memory to a file
 385  * @cpu: The CPU whose memory is to be dumped
 386  * @cpuid: ID number of the CPU
 387  * @opaque: pointer to the CPUState struct
 388  */
 389 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
 390                          int cpuid, void *opaque);
 391
 392 /**
 393  * cpu_write_elf32_qemunote:
 394  * @f: pointer to a function that writes memory to a file
 395  * @cpu: The CPU whose memory is to be dumped
 396  * @cpuid: ID number of the CPU
 397  * @opaque: pointer to the CPUState struct
 398  */
 399 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
 400                              void *opaque);
 401
 402 /**
 403  * CPUDumpFlags:
 404  * @CPU_DUMP_CODE:
 405  * @CPU_DUMP_FPU: dump FPU register state, not just integer
 406  * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
 407  */
 408 enum CPUDumpFlags {
 409     CPU_DUMP_CODE = 0x00010000,
 410     CPU_DUMP_FPU  = 0x00020000,
 411     CPU_DUMP_CCOP = 0x00040000,
 412 };
 413
 414 /**
 415  * cpu_dump_state:
 416  * @cpu: The CPU whose state is to be dumped.
 417  * @f: File to dump to.
 418  * @cpu_fprintf: Function to dump with.
 419  * @flags: Flags what to dump.
 420  *
 421  * Dumps CPU state.
 422  */
 423 void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 424                     int flags);
 425
 426 /**
 427  * cpu_dump_statistics:
 428  * @cpu: The CPU whose state is to be dumped.
 429  * @f: File to dump to.
 430  * @cpu_fprintf: Function to dump with.
 431  * @flags: Flags what to dump.
 432  *
 433  * Dumps CPU statistics.
 434  */
 435 void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 436                          int flags);
 437
 438 #ifndef CONFIG_USER_ONLY
 439 /**
 440  * cpu_get_phys_page_debug:
 441  * @cpu: The CPU to obtain the physical page address for.
 442  * @addr: The virtual address.
 443  *
 444  * Obtains the physical page corresponding to a virtual one.
 445  * Use it only for debugging because no protection checks are done.
 446  *
 447  * Returns: Corresponding physical page address or -1 if no page found.
 448  */
 449 static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
 450 {
 451     CPUClass *cc = CPU_GET_CLASS(cpu);
 452
 453     return cc->get_phys_page_debug(cpu, addr);
 454 }
 455 #endif
 456
 457 /**
 458  * cpu_reset:
 459  * @cpu: The CPU whose state is to be reset.
 460  */
 461 void cpu_reset(CPUState *cpu);
 462
 463 /**
 464  * cpu_class_by_name:
 465  * @typename: The CPU base type.
 466  * @cpu_model: The model string without any parameters.
 467  *
 468  * Looks up a CPU #ObjectClass matching name @cpu_model.
 469  *
 470  * Returns: A #CPUClass or %NULL if not matching class is found.
 471  */
 472 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
 473
 474 /**
 475  * cpu_generic_init:
 476  * @typename: The CPU base type.
 477  * @cpu_model: The model string including optional parameters.
 478  *
 479  * Instantiates a CPU, processes optional parameters and realizes the CPU.
 480  *
 481  * Returns: A #CPUState or %NULL if an error occurred.
 482  */
 483 CPUState *cpu_generic_init(const char *typename, const char *cpu_model);
 484
 485 /**
 486  * cpu_has_work:
 487  * @cpu: The vCPU to check.
 488  *
 489  * Checks whether the CPU has work to do.
 490  *
 491  * Returns: %true if the CPU has work, %false otherwise.
 492  */
 493 static inline bool cpu_has_work(CPUState *cpu)
 494 {
 495     CPUClass *cc = CPU_GET_CLASS(cpu);
 496
 497     g_assert(cc->has_work);
 498     return cc->has_work(cpu);
 499 }
 500
 501 /**
 502  * qemu_cpu_is_self:
 503  * @cpu: The vCPU to check against.
 504  *
 505  * Checks whether the caller is executing on the vCPU thread.
 506  *
 507  * Returns: %true if called from @cpu's thread, %false otherwise.
 508  */
 509 bool qemu_cpu_is_self(CPUState *cpu);
 510
 511 /**
 512  * qemu_cpu_kick:
 513  * @cpu: The vCPU to kick.
 514  *
 515  * Kicks @cpu's thread.
 516  */
 517 void qemu_cpu_kick(CPUState *cpu);
 518
 519 /**
 520  * cpu_is_stopped:
 521  * @cpu: The CPU to check.
 522  *
 523  * Checks whether the CPU is stopped.
 524  *
 525  * Returns: %true if run state is not running or if artificially stopped;
 526  * %false otherwise.
 527  */
 528 bool cpu_is_stopped(CPUState *cpu);
 529
 530 /**
 531  * run_on_cpu:
 532  * @cpu: The vCPU to run on.
 533  * @func: The function to be executed.
 534  * @data: Data to pass to the function.
 535  *
 536  * Schedules the function @func for execution on the vCPU @cpu.
 537  */
 538 void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
 539
 540 /**
 541  * async_run_on_cpu:
 542  * @cpu: The vCPU to run on.
 543  * @func: The function to be executed.
 544  * @data: Data to pass to the function.
 545  *
 546  * Schedules the function @func for execution on the vCPU @cpu asynchronously.
 547  */
 548 void async_run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
 549
 550 /**
 551  * qemu_get_cpu:
 552  * @index: The CPUState@cpu_index value of the CPU to obtain.
 553  *
 554  * Gets a CPU matching @index.
 555  *
 556  * Returns: The CPU or %NULL if there is no matching CPU.
 557  */
 558 CPUState *qemu_get_cpu(int index);
 559
 560 /**
 561  * cpu_exists:
 562  * @id: Guest-exposed CPU ID to lookup.
 563  *
 564  * Search for CPU with specified ID.
 565  *
 566  * Returns: %true - CPU is found, %false - CPU isn't found.
 567  */
 568 bool cpu_exists(int64_t id);
 569
 570 #ifndef CONFIG_USER_ONLY
 571
 572 typedef void (*CPUInterruptHandler)(CPUState *, int);
 573
 574 extern CPUInterruptHandler cpu_interrupt_handler;
 575
 576 /**
 577  * cpu_interrupt:
 578  * @cpu: The CPU to set an interrupt on.
 579  * @mask: The interupts to set.
 580  *
 581  * Invokes the interrupt handler.
 582  */
 583 static inline void cpu_interrupt(CPUState *cpu, int mask)
 584 {
 585     cpu_interrupt_handler(cpu, mask);
 586 }
 587
 588 #else /* USER_ONLY */
 589
 590 void cpu_interrupt(CPUState *cpu, int mask);
 591
 592 #endif /* USER_ONLY */
 593
 594 #ifdef CONFIG_SOFTMMU
 595 static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 596                                          bool is_write, bool is_exec,
 597                                          int opaque, unsigned size)
 598 {
 599     CPUClass *cc = CPU_GET_CLASS(cpu);
 600
 601     if (cc->do_unassigned_access) {
 602         cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size);
 603     }
 604 }
 605
 606 static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
 607                                         int is_write, int is_user,
 608                                         uintptr_t retaddr)
 609 {
 610     CPUClass *cc = CPU_GET_CLASS(cpu);
 611
 612     cc->do_unaligned_access(cpu, addr, is_write, is_user, retaddr);
 613 }
 614 #endif
 615
 616 /**
 617  * cpu_set_pc:
 618  * @cpu: The CPU to set the program counter for.
 619  * @addr: Program counter value.
 620  *
 621  * Sets the program counter for a CPU.
 622  */
 623 static inline void cpu_set_pc(CPUState *cpu, vaddr addr)
 624 {
 625     CPUClass *cc = CPU_GET_CLASS(cpu);
 626
 627     cc->set_pc(cpu, addr);
 628 }
 629
 630 /**
 631  * cpu_reset_interrupt:
 632  * @cpu: The CPU to clear the interrupt on.
 633  * @mask: The interrupt mask to clear.
 634  *
 635  * Resets interrupts on the vCPU @cpu.
 636  */
 637 void cpu_reset_interrupt(CPUState *cpu, int mask);
 638
 639 /**
 640  * cpu_exit:
 641  * @cpu: The CPU to exit.
 642  *
 643  * Requests the CPU @cpu to exit execution.
 644  */
 645 void cpu_exit(CPUState *cpu);
 646
 647 /**
 648  * cpu_resume:
 649  * @cpu: The CPU to resume.
 650  *
 651  * Resumes CPU, i.e. puts CPU into runnable state.
 652  */
 653 void cpu_resume(CPUState *cpu);
 654
 655 /**
 656  * qemu_init_vcpu:
 657  * @cpu: The vCPU to initialize.
 658  *
 659  * Initializes a vCPU.
 660  */
 661 void qemu_init_vcpu(CPUState *cpu);
 662
 663 #define SSTEP_ENABLE  0x1  /* Enable simulated HW single stepping */
 664 #define SSTEP_NOIRQ   0x2  /* Do not use IRQ while single stepping */
 665 #define SSTEP_NOTIMER 0x4  /* Do not Timers while single stepping */
 666
 667 /**
 668  * cpu_single_step:
 669  * @cpu: CPU to the flags for.
 670  * @enabled: Flags to enable.
 671  *
 672  * Enables or disables single-stepping for @cpu.
 673  */
 674 void cpu_single_step(CPUState *cpu, int enabled);
 675
 676 /* Breakpoint/watchpoint flags */
 677 #define BP_MEM_READ           0x01
 678 #define BP_MEM_WRITE          0x02
 679 #define BP_MEM_ACCESS         (BP_MEM_READ | BP_MEM_WRITE)
 680 #define BP_STOP_BEFORE_ACCESS 0x04
 681 /* 0x08 currently unused */
 682 #define BP_GDB                0x10
 683 #define BP_CPU                0x20
 684 #define BP_WATCHPOINT_HIT_READ 0x40
 685 #define BP_WATCHPOINT_HIT_WRITE 0x80
 686 #define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE)
 687
 688 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
 689                           CPUBreakpoint **breakpoint);
 690 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags);
 691 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint);
 692 void cpu_breakpoint_remove_all(CPUState *cpu, int mask);
 693
 694 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
 695                           int flags, CPUWatchpoint **watchpoint);
 696 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
 697                           vaddr len, int flags);
 698 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
 699 void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
 700
 701 void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
 702     GCC_FMT_ATTR(2, 3);
 703 void cpu_exec_exit(CPUState *cpu);
 704
 705 #ifdef CONFIG_SOFTMMU
 706 extern const struct VMStateDescription vmstate_cpu_common;
 707 #else
 708 #define vmstate_cpu_common vmstate_dummy
 709 #endif
 710
 711 #define VMSTATE_CPU() {                                                     \
 712     .name = "parent_obj",                                                   \
 713     .size = sizeof(CPUState),                                               \
 714     .vmsd = &vmstate_cpu_common,                                            \
 715     .flags = VMS_STRUCT,                                                    \
 716     .offset = 0,                                                            \
 717 }
 718
 719 #endif