disas/alpha.c

   1 /* alpha-dis.c -- Disassemble Alpha AXP instructions
   2    Copyright 1996, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
   3    Contributed by Richard Henderson <rth@tamu.edu>,
   4    patterned after the PPC opcode handling written by Ian Lance Taylor.
   5
   6 This file is part of GDB, GAS, and the GNU binutils.
   7
   8 GDB, GAS, and the GNU binutils are free software; you can redistribute
   9 them and/or modify them under the terms of the GNU General Public
  10 License as published by the Free Software Foundation; either version
  11 2, or (at your option) any later version.
  12
  13 GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16 the GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this file; see the file COPYING.  If not, see
  20 <http://www.gnu.org/licenses/>. */
  21
  22 #include "disas/bfd.h"
  23
  24 /* MAX is redefined below, so remove any previous definition. */
  25 #undef MAX
  26
  27 /* The opcode table is an array of struct alpha_opcode.  */
  28
  29 struct alpha_opcode
  30 {
  31   /* The opcode name.  */
  32   const char *name;
  33
  34   /* The opcode itself.  Those bits which will be filled in with
  35      operands are zeroes.  */
  36   unsigned opcode;
  37
  38   /* The opcode mask.  This is used by the disassembler.  This is a
  39      mask containing ones indicating those bits which must match the
  40      opcode field, and zeroes indicating those bits which need not
  41      match (and are presumably filled in by operands).  */
  42   unsigned mask;
  43
  44   /* One bit flags for the opcode.  These are primarily used to
  45      indicate specific processors and environments support the
  46      instructions.  The defined values are listed below. */
  47   unsigned flags;
  48
  49   /* An array of operand codes.  Each code is an index into the
  50      operand table.  They appear in the order which the operands must
  51      appear in assembly code, and are terminated by a zero.  */
  52   unsigned char operands[4];
  53 };
  54
  55 /* The table itself is sorted by major opcode number, and is otherwise
  56    in the order in which the disassembler should consider
  57    instructions.  */
  58 extern const struct alpha_opcode alpha_opcodes[];
  59 extern const unsigned alpha_num_opcodes;
  60
  61 /* Values defined for the flags field of a struct alpha_opcode.  */
  62
  63 /* CPU Availability */
  64 #define AXP_OPCODE_BASE  0x0001  /* Base architecture -- all cpus.  */
  65 #define AXP_OPCODE_EV4   0x0002  /* EV4 specific PALcode insns.  */
  66 #define AXP_OPCODE_EV5   0x0004  /* EV5 specific PALcode insns.  */
  67 #define AXP_OPCODE_EV6   0x0008  /* EV6 specific PALcode insns.  */
  68 #define AXP_OPCODE_BWX   0x0100  /* Byte/word extension (amask bit 0).  */
  69 #define AXP_OPCODE_CIX   0x0200  /* "Count" extension (amask bit 1).  */
  70 #define AXP_OPCODE_MAX   0x0400  /* Multimedia extension (amask bit 8).  */
  71
  72 #define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6))
  73
  74 /* A macro to extract the major opcode from an instruction.  */
  75 #define AXP_OP(i)       (((i) >> 26) & 0x3F)
  76
  77 /* The total number of major opcodes. */
  78 #define AXP_NOPS        0x40
  79
  80 \f
  81 /* The operands table is an array of struct alpha_operand.  */
  82
  83 struct alpha_operand
  84 {
  85   /* The number of bits in the operand.  */
  86   unsigned int bits : 5;
  87
  88   /* How far the operand is left shifted in the instruction.  */
  89   unsigned int shift : 5;
  90
  91   /* The default relocation type for this operand.  */
  92   signed int default_reloc : 16;
  93
  94   /* One bit syntax flags.  */
  95   unsigned int flags : 16;
  96
  97   /* Insertion function.  This is used by the assembler.  To insert an
  98      operand value into an instruction, check this field.
  99
 100      If it is NULL, execute
 101          i |= (op & ((1 << o->bits) - 1)) << o->shift;
 102      (i is the instruction which we are filling in, o is a pointer to
 103      this structure, and op is the opcode value; this assumes twos
 104      complement arithmetic).
 105
 106      If this field is not NULL, then simply call it with the
 107      instruction and the operand value.  It will return the new value
 108      of the instruction.  If the ERRMSG argument is not NULL, then if
 109      the operand value is illegal, *ERRMSG will be set to a warning
 110      string (the operand will be inserted in any case).  If the
 111      operand value is legal, *ERRMSG will be unchanged (most operands
 112      can accept any value).  */
 113   unsigned (*insert) (unsigned instruction, int op,
 114                       const char **errmsg);
 115
 116   /* Extraction function.  This is used by the disassembler.  To
 117      extract this operand type from an instruction, check this field.
 118
 119      If it is NULL, compute
 120          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 121          if ((o->flags & AXP_OPERAND_SIGNED) != 0
 122              && (op & (1 << (o->bits - 1))) != 0)
 123            op -= 1 << o->bits;
 124      (i is the instruction, o is a pointer to this structure, and op
 125      is the result; this assumes twos complement arithmetic).
 126
 127      If this field is not NULL, then simply call it with the
 128      instruction value.  It will return the value of the operand.  If
 129      the INVALID argument is not NULL, *INVALID will be set to
 130      non-zero if this operand type can not actually be extracted from
 131      this operand (i.e., the instruction does not match).  If the
 132      operand is valid, *INVALID will not be changed.  */
 133   int (*extract) (unsigned instruction, int *invalid);
 134 };
 135
 136 /* Elements in the table are retrieved by indexing with values from
 137    the operands field of the alpha_opcodes table.  */
 138
 139 extern const struct alpha_operand alpha_operands[];
 140 extern const unsigned alpha_num_operands;
 141
 142 /* Values defined for the flags field of a struct alpha_operand.  */
 143
 144 /* Mask for selecting the type for typecheck purposes */
 145 #define AXP_OPERAND_TYPECHECK_MASK                                      \
 146   (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR |            \
 147    AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED |        \
 148    AXP_OPERAND_UNSIGNED)
 149
 150 /* This operand does not actually exist in the assembler input.  This
 151    is used to support extended mnemonics, for which two operands fields
 152    are identical.  The assembler should call the insert function with
 153    any op value.  The disassembler should call the extract function,
 154    ignore the return value, and check the value placed in the invalid
 155    argument.  */
 156 #define AXP_OPERAND_FAKE        01
 157
 158 /* The operand should be wrapped in parentheses rather than separated
 159    from the previous by a comma.  This is used for the load and store
 160    instructions which want their operands to look like "Ra,disp(Rb)".  */
 161 #define AXP_OPERAND_PARENS      02
 162
 163 /* Used in combination with PARENS, this suppresses the suppression of
 164    the comma.  This is used for "jmp Ra,(Rb),hint".  */
 165 #define AXP_OPERAND_COMMA       04
 166
 167 /* This operand names an integer register.  */
 168 #define AXP_OPERAND_IR          010
 169
 170 /* This operand names a floating point register.  */
 171 #define AXP_OPERAND_FPR         020
 172
 173 /* This operand is a relative branch displacement.  The disassembler
 174    prints these symbolically if possible.  */
 175 #define AXP_OPERAND_RELATIVE    040
 176
 177 /* This operand takes signed values.  */
 178 #define AXP_OPERAND_SIGNED      0100
 179
 180 /* This operand takes unsigned values.  This exists primarily so that
 181    a flags value of 0 can be treated as end-of-arguments.  */
 182 #define AXP_OPERAND_UNSIGNED    0200
 183
 184 /* Suppress overflow detection on this field.  This is used for hints. */
 185 #define AXP_OPERAND_NOOVERFLOW  0400
 186
 187 /* Mask for optional argument default value.  */
 188 #define AXP_OPERAND_OPTIONAL_MASK 07000
 189
 190 /* This operand defaults to zero.  This is used for jump hints.  */
 191 #define AXP_OPERAND_DEFAULT_ZERO 01000
 192
 193 /* This operand should default to the first (real) operand and is used
 194    in conjunction with AXP_OPERAND_OPTIONAL.  This allows
 195    "and $0,3,$0" to be written as "and $0,3", etc.  I don't like
 196    it, but it's what DEC does.  */
 197 #define AXP_OPERAND_DEFAULT_FIRST 02000
 198
 199 /* Similarly, this operand should default to the second (real) operand.
 200    This allows "negl $0" instead of "negl $0,$0".  */
 201 #define AXP_OPERAND_DEFAULT_SECOND 04000
 202
 203 \f
 204 /* Register common names */
 205
 206 #define AXP_REG_V0      0
 207 #define AXP_REG_T0      1
 208 #define AXP_REG_T1      2
 209 #define AXP_REG_T2      3
 210 #define AXP_REG_T3      4
 211 #define AXP_REG_T4      5
 212 #define AXP_REG_T5      6
 213 #define AXP_REG_T6      7
 214 #define AXP_REG_T7      8
 215 #define AXP_REG_S0      9
 216 #define AXP_REG_S1      10
 217 #define AXP_REG_S2      11
 218 #define AXP_REG_S3      12
 219 #define AXP_REG_S4      13
 220 #define AXP_REG_S5      14
 221 #define AXP_REG_FP      15
 222 #define AXP_REG_A0      16
 223 #define AXP_REG_A1      17
 224 #define AXP_REG_A2      18
 225 #define AXP_REG_A3      19
 226 #define AXP_REG_A4      20
 227 #define AXP_REG_A5      21
 228 #define AXP_REG_T8      22
 229 #define AXP_REG_T9      23
 230 #define AXP_REG_T10     24
 231 #define AXP_REG_T11     25
 232 #define AXP_REG_RA      26
 233 #define AXP_REG_PV      27
 234 #define AXP_REG_T12     27
 235 #define AXP_REG_AT      28
 236 #define AXP_REG_GP      29
 237 #define AXP_REG_SP      30
 238 #define AXP_REG_ZERO    31
 239
 240 enum bfd_reloc_code_real {
 241     BFD_RELOC_23_PCREL_S2,
 242     BFD_RELOC_ALPHA_HINT
 243 };
 244
 245 /* This file holds the Alpha AXP opcode table.  The opcode table includes
 246    almost all of the extended instruction mnemonics.  This permits the
 247    disassembler to use them, and simplifies the assembler logic, at the
 248    cost of increasing the table size.  The table is strictly constant
 249    data, so the compiler should be able to put it in the text segment.
 250
 251    This file also holds the operand table.  All knowledge about inserting
 252    and extracting operands from instructions is kept in this file.
 253
 254    The information for the base instruction set was compiled from the
 255    _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE,
 256    version 2.
 257
 258    The information for the post-ev5 architecture extensions BWX, CIX and
 259    MAX came from version 3 of this same document, which is also available
 260    on-line at http://ftp.digital.com/pub/Digital/info/semiconductor
 261    /literature/alphahb2.pdf
 262
 263    The information for the EV4 PALcode instructions was compiled from
 264    _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware
 265    Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary
 266    revision dated June 1994.
 267
 268    The information for the EV5 PALcode instructions was compiled from
 269    _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital
 270    Order Number EC-QAEQB-TE, preliminary revision dated April 1995.  */
 271 \f
 272 /* Local insertion and extraction functions */
 273
 274 static unsigned insert_rba (unsigned, int, const char **);
 275 static unsigned insert_rca (unsigned, int, const char **);
 276 static unsigned insert_za (unsigned, int, const char **);
 277 static unsigned insert_zb (unsigned, int, const char **);
 278 static unsigned insert_zc (unsigned, int, const char **);
 279 static unsigned insert_bdisp (unsigned, int, const char **);
 280 static unsigned insert_jhint (unsigned, int, const char **);
 281 static unsigned insert_ev6hwjhint (unsigned, int, const char **);
 282
 283 static int extract_rba (unsigned, int *);
 284 static int extract_rca (unsigned, int *);
 285 static int extract_za (unsigned, int *);
 286 static int extract_zb (unsigned, int *);
 287 static int extract_zc (unsigned, int *);
 288 static int extract_bdisp (unsigned, int *);
 289 static int extract_jhint (unsigned, int *);
 290 static int extract_ev6hwjhint (unsigned, int *);
 291
 292 \f
 293 /* The operands table  */
 294
 295 const struct alpha_operand alpha_operands[] =
 296 {
 297   /* The fields are bits, shift, insert, extract, flags */
 298   /* The zero index is used to indicate end-of-list */
 299 #define UNUSED          0
 300   { 0, 0, 0, 0, 0, 0 },
 301
 302   /* The plain integer register fields */
 303 #define RA              (UNUSED + 1)
 304   { 5, 21, 0, AXP_OPERAND_IR, 0, 0 },
 305 #define RB              (RA + 1)
 306   { 5, 16, 0, AXP_OPERAND_IR, 0, 0 },
 307 #define RC              (RB + 1)
 308   { 5, 0, 0, AXP_OPERAND_IR, 0, 0 },
 309
 310   /* The plain fp register fields */
 311 #define FA              (RC + 1)
 312   { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 },
 313 #define FB              (FA + 1)
 314   { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 },
 315 #define FC              (FB + 1)
 316   { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 },
 317
 318   /* The integer registers when they are ZERO */
 319 #define ZA              (FC + 1)
 320   { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za },
 321 #define ZB              (ZA + 1)
 322   { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb },
 323 #define ZC              (ZB + 1)
 324   { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc },
 325
 326   /* The RB field when it needs parentheses */
 327 #define PRB             (ZC + 1)
 328   { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 },
 329
 330   /* The RB field when it needs parentheses _and_ a preceding comma */
 331 #define CPRB            (PRB + 1)
 332   { 5, 16, 0,
 333     AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 },
 334
 335   /* The RB field when it must be the same as the RA field */
 336 #define RBA             (CPRB + 1)
 337   { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba },
 338
 339   /* The RC field when it must be the same as the RB field */
 340 #define RCA             (RBA + 1)
 341   { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca },
 342
 343   /* The RC field when it can *default* to RA */
 344 #define DRC1            (RCA + 1)
 345   { 5, 0, 0,
 346     AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
 347
 348   /* The RC field when it can *default* to RB */
 349 #define DRC2            (DRC1 + 1)
 350   { 5, 0, 0,
 351     AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
 352
 353   /* The FC field when it can *default* to RA */
 354 #define DFC1            (DRC2 + 1)
 355   { 5, 0, 0,
 356     AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
 357
 358   /* The FC field when it can *default* to RB */
 359 #define DFC2            (DFC1 + 1)
 360   { 5, 0, 0,
 361     AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
 362
 363   /* The unsigned 8-bit literal of Operate format insns */
 364 #define LIT             (DFC2 + 1)
 365   { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 },
 366
 367   /* The signed 16-bit displacement of Memory format insns.  From here
 368      we can't tell what relocation should be used, so don't use a default. */
 369 #define MDISP           (LIT + 1)
 370   { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 },
 371
 372   /* The signed "23-bit" aligned displacement of Branch format insns */
 373 #define BDISP           (MDISP + 1)
 374   { 21, 0, BFD_RELOC_23_PCREL_S2,
 375     AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp },
 376
 377   /* The 26-bit PALcode function */
 378 #define PALFN           (BDISP + 1)
 379   { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 },
 380
 381   /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */
 382 #define JMPHINT         (PALFN + 1)
 383   { 14, 0, BFD_RELOC_ALPHA_HINT,
 384     AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
 385     insert_jhint, extract_jhint },
 386
 387   /* The optional hint to RET/JSR_COROUTINE */
 388 #define RETHINT         (JMPHINT + 1)
 389   { 14, 0, -RETHINT,
 390     AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 },
 391
 392   /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns */
 393 #define EV4HWDISP       (RETHINT + 1)
 394 #define EV6HWDISP       (EV4HWDISP)
 395   { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
 396
 397   /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */
 398 #define EV4HWINDEX      (EV4HWDISP + 1)
 399   { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
 400
 401   /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns
 402      that occur in DEC PALcode.  */
 403 #define EV4EXTHWINDEX   (EV4HWINDEX + 1)
 404   { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
 405
 406   /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */
 407 #define EV5HWDISP       (EV4EXTHWINDEX + 1)
 408   { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
 409
 410   /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */
 411 #define EV5HWINDEX      (EV5HWDISP + 1)
 412   { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
 413
 414   /* The 16-bit combined index/scoreboard mask for the ev6
 415      hw_m[ft]pr (pal19/pal1d) insns */
 416 #define EV6HWINDEX      (EV5HWINDEX + 1)
 417   { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
 418
 419   /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn */
 420 #define EV6HWJMPHINT    (EV6HWINDEX+ 1)
 421   { 8, 0, -EV6HWJMPHINT,
 422     AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
 423     insert_ev6hwjhint, extract_ev6hwjhint }
 424 };
 425
 426 const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands);
 427
 428 /* The RB field when it is the same as the RA field in the same insn.
 429    This operand is marked fake.  The insertion function just copies
 430    the RA field into the RB field, and the extraction function just
 431    checks that the fields are the same. */
 432
 433 /*ARGSUSED*/
 434 static unsigned
 435 insert_rba(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED)
 436 {
 437   return insn | (((insn >> 21) & 0x1f) << 16);
 438 }
 439
 440 static int
 441 extract_rba(unsigned insn, int *invalid)
 442 {
 443   if (invalid != (int *) NULL
 444       && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 445     *invalid = 1;
 446   return 0;
 447 }
 448
 449
 450 /* The same for the RC field */
 451
 452 /*ARGSUSED*/
 453 static unsigned
 454 insert_rca(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED)
 455 {
 456   return insn | ((insn >> 21) & 0x1f);
 457 }
 458
 459 static int
 460 extract_rca(unsigned insn, int *invalid)
 461 {
 462   if (invalid != (int *) NULL
 463       && ((insn >> 21) & 0x1f) != (insn & 0x1f))
 464     *invalid = 1;
 465   return 0;
 466 }
 467
 468
 469 /* Fake arguments in which the registers must be set to ZERO */
 470
 471 /*ARGSUSED*/
 472 static unsigned
 473 insert_za(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED)
 474 {
 475   return insn | (31 << 21);
 476 }
 477
 478 static int
 479 extract_za(unsigned insn, int *invalid)
 480 {
 481   if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31)
 482     *invalid = 1;
 483   return 0;
 484 }
 485
 486 /*ARGSUSED*/
 487 static unsigned
 488 insert_zb(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED)
 489 {
 490   return insn | (31 << 16);
 491 }
 492
 493 static int
 494 extract_zb(unsigned insn, int *invalid)
 495 {
 496   if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31)
 497     *invalid = 1;
 498   return 0;
 499 }
 500
 501 /*ARGSUSED*/
 502 static unsigned
 503 insert_zc(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED)
 504 {
 505   return insn | 31;
 506 }
 507
 508 static int
 509 extract_zc(unsigned insn, int *invalid)
 510 {
 511   if (invalid != (int *) NULL && (insn & 0x1f) != 31)
 512     *invalid = 1;
 513   return 0;
 514 }
 515
 516
 517 /* The displacement field of a Branch format insn.  */
 518
 519 static unsigned
 520 insert_bdisp(unsigned insn, int value, const char **errmsg)
 521 {
 522   if (errmsg != (const char **)NULL && (value & 3))
 523     *errmsg = _("branch operand unaligned");
 524   return insn | ((value / 4) & 0x1FFFFF);
 525 }
 526
 527 /*ARGSUSED*/
 528 static int
 529 extract_bdisp(unsigned insn, int *invalid ATTRIBUTE_UNUSED)
 530 {
 531   return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000);
 532 }
 533
 534
 535 /* The hint field of a JMP/JSR insn.  */
 536
 537 static unsigned
 538 insert_jhint(unsigned insn, int value, const char **errmsg)
 539 {
 540   if (errmsg != (const char **)NULL && (value & 3))
 541     *errmsg = _("jump hint unaligned");
 542   return insn | ((value / 4) & 0x3FFF);
 543 }
 544
 545 /*ARGSUSED*/
 546 static int
 547 extract_jhint(unsigned insn, int *invalid ATTRIBUTE_UNUSED)
 548 {
 549   return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000);
 550 }
 551
 552 /* The hint field of an EV6 HW_JMP/JSR insn.  */
 553
 554 static unsigned
 555 insert_ev6hwjhint(unsigned insn, int value, const char **errmsg)
 556 {
 557   if (errmsg != (const char **)NULL && (value & 3))
 558     *errmsg = _("jump hint unaligned");
 559   return insn | ((value / 4) & 0x1FFF);
 560 }
 561
 562 /*ARGSUSED*/
 563 static int
 564 extract_ev6hwjhint(unsigned insn, int *invalid ATTRIBUTE_UNUSED)
 565 {
 566   return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000);
 567 }
 568
 569 \f
 570 /* Macros used to form opcodes */
 571
 572 /* The main opcode */
 573 #define OP(x)           (((x) & 0x3F) << 26)
 574 #define OP_MASK         0xFC000000
 575
 576 /* Branch format instructions */
 577 #define BRA_(oo)        OP(oo)
 578 #define BRA_MASK        OP_MASK
 579 #define BRA(oo)         BRA_(oo), BRA_MASK
 580
 581 /* Floating point format instructions */
 582 #define FP_(oo,fff)     (OP(oo) | (((fff) & 0x7FF) << 5))
 583 #define FP_MASK         (OP_MASK | 0xFFE0)
 584 #define FP(oo,fff)      FP_(oo,fff), FP_MASK
 585
 586 /* Memory format instructions */
 587 #define MEM_(oo)        OP(oo)
 588 #define MEM_MASK        OP_MASK
 589 #define MEM(oo)         MEM_(oo), MEM_MASK
 590
 591 /* Memory/Func Code format instructions */
 592 #define MFC_(oo,ffff)   (OP(oo) | ((ffff) & 0xFFFF))
 593 #define MFC_MASK        (OP_MASK | 0xFFFF)
 594 #define MFC(oo,ffff)    MFC_(oo,ffff), MFC_MASK
 595
 596 /* Memory/Branch format instructions */
 597 #define MBR_(oo,h)      (OP(oo) | (((h) & 3) << 14))
 598 #define MBR_MASK        (OP_MASK | 0xC000)
 599 #define MBR(oo,h)       MBR_(oo,h), MBR_MASK
 600
 601 /* Operate format instructions.  The OPRL variant specifies a
 602    literal second argument. */
 603 #define OPR_(oo,ff)     (OP(oo) | (((ff) & 0x7F) << 5))
 604 #define OPRL_(oo,ff)    (OPR_((oo),(ff)) | 0x1000)
 605 #define OPR_MASK        (OP_MASK | 0x1FE0)
 606 #define OPR(oo,ff)      OPR_(oo,ff), OPR_MASK
 607 #define OPRL(oo,ff)     OPRL_(oo,ff), OPR_MASK
 608
 609 /* Generic PALcode format instructions */
 610 #define PCD_(oo)        OP(oo)
 611 #define PCD_MASK        OP_MASK
 612 #define PCD(oo)         PCD_(oo), PCD_MASK
 613
 614 /* Specific PALcode instructions */
 615 #define SPCD_(oo,ffff)  (OP(oo) | ((ffff) & 0x3FFFFFF))
 616 #define SPCD_MASK       0xFFFFFFFF
 617 #define SPCD(oo,ffff)   SPCD_(oo,ffff), SPCD_MASK
 618
 619 /* Hardware memory (hw_{ld,st}) instructions */
 620 #define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12))
 621 #define EV4HWMEM_MASK   (OP_MASK | 0xF000)
 622 #define EV4HWMEM(oo,f)  EV4HWMEM_(oo,f), EV4HWMEM_MASK
 623
 624 #define EV5HWMEM_(oo,f) (OP(oo) | (((f) & 0x3F) << 10))
 625 #define EV5HWMEM_MASK   (OP_MASK | 0xF800)
 626 #define EV5HWMEM(oo,f)  EV5HWMEM_(oo,f), EV5HWMEM_MASK
 627
 628 #define EV6HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12))
 629 #define EV6HWMEM_MASK   (OP_MASK | 0xF000)
 630 #define EV6HWMEM(oo,f)  EV6HWMEM_(oo,f), EV6HWMEM_MASK
 631
 632 #define EV6HWMBR_(oo,h) (OP(oo) | (((h) & 7) << 13))
 633 #define EV6HWMBR_MASK   (OP_MASK | 0xE000)
 634 #define EV6HWMBR(oo,h)  EV6HWMBR_(oo,h), EV6HWMBR_MASK
 635
 636 /* Abbreviations for instruction subsets.  */
 637 #define BASE                    AXP_OPCODE_BASE
 638 #define EV4                     AXP_OPCODE_EV4
 639 #define EV5                     AXP_OPCODE_EV5
 640 #define EV6                     AXP_OPCODE_EV6
 641 #define BWX                     AXP_OPCODE_BWX
 642 #define CIX                     AXP_OPCODE_CIX
 643 #define MAX                     AXP_OPCODE_MAX
 644
 645 /* Common combinations of arguments */
 646 #define ARG_NONE                { 0 }
 647 #define ARG_BRA                 { RA, BDISP }
 648 #define ARG_FBRA                { FA, BDISP }
 649 #define ARG_FP                  { FA, FB, DFC1 }
 650 #define ARG_FPZ1                { ZA, FB, DFC1 }
 651 #define ARG_MEM                 { RA, MDISP, PRB }
 652 #define ARG_FMEM                { FA, MDISP, PRB }
 653 #define ARG_OPR                 { RA, RB, DRC1 }
 654 #define ARG_OPRL                { RA, LIT, DRC1 }
 655 #define ARG_OPRZ1               { ZA, RB, DRC1 }
 656 #define ARG_OPRLZ1              { ZA, LIT, RC }
 657 #define ARG_PCD                 { PALFN }
 658 #define ARG_EV4HWMEM            { RA, EV4HWDISP, PRB }
 659 #define ARG_EV4HWMPR            { RA, RBA, EV4HWINDEX }
 660 #define ARG_EV5HWMEM            { RA, EV5HWDISP, PRB }
 661 #define ARG_EV6HWMEM            { RA, EV6HWDISP, PRB }
 662 \f
 663 /* The opcode table.
 664
 665    The format of the opcode table is:
 666
 667    NAME OPCODE MASK { OPERANDS }
 668
 669    NAME         is the name of the instruction.
 670
 671    OPCODE       is the instruction opcode.
 672
 673    MASK         is the opcode mask; this is used to tell the disassembler
 674                 which bits in the actual opcode must match OPCODE.
 675
 676    OPERANDS     is the list of operands.
 677
 678    The preceding macros merge the text of the OPCODE and MASK fields.
 679
 680    The disassembler reads the table in order and prints the first
 681    instruction which matches, so this table is sorted to put more
 682    specific instructions before more general instructions.
 683
 684    Otherwise, it is sorted by major opcode and minor function code.
 685
 686    There are three classes of not-really-instructions in this table:
 687
 688    ALIAS        is another name for another instruction.  Some of
 689                 these come from the Architecture Handbook, some
 690                 come from the original gas opcode tables.  In all
 691                 cases, the functionality of the opcode is unchanged.
 692
 693    PSEUDO       a stylized code form endorsed by Chapter A.4 of the
 694                 Architecture Handbook.
 695
 696    EXTRA        a stylized code form found in the original gas tables.
 697
 698    And two annotations:
 699
 700    EV56 BUT     opcodes that are officially introduced as of the ev56,
 701                 but with defined results on previous implementations.
 702
 703    EV56 UNA     opcodes that were introduced as of the ev56 with
 704                 presumably undefined results on previous implementations
 705                 that were not assigned to a particular extension.
 706 */
 707
 708 const struct alpha_opcode alpha_opcodes[] = {
 709   { "halt",             SPCD(0x00,0x0000), BASE, ARG_NONE },
 710   { "draina",           SPCD(0x00,0x0002), BASE, ARG_NONE },
 711   { "bpt",              SPCD(0x00,0x0080), BASE, ARG_NONE },
 712   { "bugchk",           SPCD(0x00,0x0081), BASE, ARG_NONE },
 713   { "callsys",          SPCD(0x00,0x0083), BASE, ARG_NONE },
 714   { "chmk",             SPCD(0x00,0x0083), BASE, ARG_NONE },
 715   { "imb",              SPCD(0x00,0x0086), BASE, ARG_NONE },
 716   { "rduniq",           SPCD(0x00,0x009e), BASE, ARG_NONE },
 717   { "wruniq",           SPCD(0x00,0x009f), BASE, ARG_NONE },
 718   { "gentrap",          SPCD(0x00,0x00aa), BASE, ARG_NONE },
 719   { "call_pal",         PCD(0x00), BASE, ARG_PCD },
 720   { "pal",              PCD(0x00), BASE, ARG_PCD },             /* alias */
 721
 722   { "lda",              MEM(0x08), BASE, { RA, MDISP, ZB } },   /* pseudo */
 723   { "lda",              MEM(0x08), BASE, ARG_MEM },
 724   { "ldah",             MEM(0x09), BASE, { RA, MDISP, ZB } },   /* pseudo */
 725   { "ldah",             MEM(0x09), BASE, ARG_MEM },
 726   { "ldbu",             MEM(0x0A), BWX, ARG_MEM },
 727   { "unop",             MEM_(0x0B) | (30 << 16),
 728                         MEM_MASK, BASE, { ZA } },               /* pseudo */
 729   { "ldq_u",            MEM(0x0B), BASE, ARG_MEM },
 730   { "ldwu",             MEM(0x0C), BWX, ARG_MEM },
 731   { "stw",              MEM(0x0D), BWX, ARG_MEM },
 732   { "stb",              MEM(0x0E), BWX, ARG_MEM },
 733   { "stq_u",            MEM(0x0F), BASE, ARG_MEM },
 734
 735   { "sextl",            OPR(0x10,0x00), BASE, ARG_OPRZ1 },      /* pseudo */
 736   { "sextl",            OPRL(0x10,0x00), BASE, ARG_OPRLZ1 },    /* pseudo */
 737   { "addl",             OPR(0x10,0x00), BASE, ARG_OPR },
 738   { "addl",             OPRL(0x10,0x00), BASE, ARG_OPRL },
 739   { "s4addl",           OPR(0x10,0x02), BASE, ARG_OPR },
 740   { "s4addl",           OPRL(0x10,0x02), BASE, ARG_OPRL },
 741   { "negl",             OPR(0x10,0x09), BASE, ARG_OPRZ1 },      /* pseudo */
 742   { "negl",             OPRL(0x10,0x09), BASE, ARG_OPRLZ1 },    /* pseudo */
 743   { "subl",             OPR(0x10,0x09), BASE, ARG_OPR },
 744   { "subl",             OPRL(0x10,0x09), BASE, ARG_OPRL },
 745   { "s4subl",           OPR(0x10,0x0B), BASE, ARG_OPR },
 746   { "s4subl",           OPRL(0x10,0x0B), BASE, ARG_OPRL },
 747   { "cmpbge",           OPR(0x10,0x0F), BASE, ARG_OPR },
 748   { "cmpbge",           OPRL(0x10,0x0F), BASE, ARG_OPRL },
 749   { "s8addl",           OPR(0x10,0x12), BASE, ARG_OPR },
 750   { "s8addl",           OPRL(0x10,0x12), BASE, ARG_OPRL },
 751   { "s8subl",           OPR(0x10,0x1B), BASE, ARG_OPR },
 752   { "s8subl",           OPRL(0x10,0x1B), BASE, ARG_OPRL },
 753   { "cmpult",           OPR(0x10,0x1D), BASE, ARG_OPR },
 754   { "cmpult",           OPRL(0x10,0x1D), BASE, ARG_OPRL },
 755   { "addq",             OPR(0x10,0x20), BASE, ARG_OPR },
 756   { "addq",             OPRL(0x10,0x20), BASE, ARG_OPRL },
 757   { "s4addq",           OPR(0x10,0x22), BASE, ARG_OPR },
 758   { "s4addq",           OPRL(0x10,0x22), BASE, ARG_OPRL },
 759   { "negq",             OPR(0x10,0x29), BASE, ARG_OPRZ1 },      /* pseudo */
 760   { "negq",             OPRL(0x10,0x29), BASE, ARG_OPRLZ1 },    /* pseudo */
 761   { "subq",             OPR(0x10,0x29), BASE, ARG_OPR },
 762   { "subq",             OPRL(0x10,0x29), BASE, ARG_OPRL },
 763   { "s4subq",           OPR(0x10,0x2B), BASE, ARG_OPR },
 764   { "s4subq",           OPRL(0x10,0x2B), BASE, ARG_OPRL },
 765   { "cmpeq",            OPR(0x10,0x2D), BASE, ARG_OPR },
 766   { "cmpeq",            OPRL(0x10,0x2D), BASE, ARG_OPRL },
 767   { "s8addq",           OPR(0x10,0x32), BASE, ARG_OPR },
 768   { "s8addq",           OPRL(0x10,0x32), BASE, ARG_OPRL },
 769   { "s8subq",           OPR(0x10,0x3B), BASE, ARG_OPR },
 770   { "s8subq",           OPRL(0x10,0x3B), BASE, ARG_OPRL },
 771   { "cmpule",           OPR(0x10,0x3D), BASE, ARG_OPR },
 772   { "cmpule",           OPRL(0x10,0x3D), BASE, ARG_OPRL },
 773   { "addl/v",           OPR(0x10,0x40), BASE, ARG_OPR },
 774   { "addl/v",           OPRL(0x10,0x40), BASE, ARG_OPRL },
 775   { "negl/v",           OPR(0x10,0x49), BASE, ARG_OPRZ1 },      /* pseudo */
 776   { "negl/v",           OPRL(0x10,0x49), BASE, ARG_OPRLZ1 },    /* pseudo */
 777   { "subl/v",           OPR(0x10,0x49), BASE, ARG_OPR },
 778   { "subl/v",           OPRL(0x10,0x49), BASE, ARG_OPRL },
 779   { "cmplt",            OPR(0x10,0x4D), BASE, ARG_OPR },
 780   { "cmplt",            OPRL(0x10,0x4D), BASE, ARG_OPRL },
 781   { "addq/v",           OPR(0x10,0x60), BASE, ARG_OPR },
 782   { "addq/v",           OPRL(0x10,0x60), BASE, ARG_OPRL },
 783   { "negq/v",           OPR(0x10,0x69), BASE, ARG_OPRZ1 },      /* pseudo */
 784   { "negq/v",           OPRL(0x10,0x69), BASE, ARG_OPRLZ1 },    /* pseudo */
 785   { "subq/v",           OPR(0x10,0x69), BASE, ARG_OPR },
 786   { "subq/v",           OPRL(0x10,0x69), BASE, ARG_OPRL },
 787   { "cmple",            OPR(0x10,0x6D), BASE, ARG_OPR },
 788   { "cmple",            OPRL(0x10,0x6D), BASE, ARG_OPRL },
 789
 790   { "and",              OPR(0x11,0x00), BASE, ARG_OPR },
 791   { "and",              OPRL(0x11,0x00), BASE, ARG_OPRL },
 792   { "andnot",           OPR(0x11,0x08), BASE, ARG_OPR },        /* alias */
 793   { "andnot",           OPRL(0x11,0x08), BASE, ARG_OPRL },      /* alias */
 794   { "bic",              OPR(0x11,0x08), BASE, ARG_OPR },
 795   { "bic",              OPRL(0x11,0x08), BASE, ARG_OPRL },
 796   { "cmovlbs",          OPR(0x11,0x14), BASE, ARG_OPR },
 797   { "cmovlbs",          OPRL(0x11,0x14), BASE, ARG_OPRL },
 798   { "cmovlbc",          OPR(0x11,0x16), BASE, ARG_OPR },
 799   { "cmovlbc",          OPRL(0x11,0x16), BASE, ARG_OPRL },
 800   { "nop",              OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */
 801   { "clr",              OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */
 802   { "mov",              OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */
 803   { "mov",              OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */
 804   { "mov",              OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */
 805   { "or",               OPR(0x11,0x20), BASE, ARG_OPR },        /* alias */
 806   { "or",               OPRL(0x11,0x20), BASE, ARG_OPRL },      /* alias */
 807   { "bis",              OPR(0x11,0x20), BASE, ARG_OPR },
 808   { "bis",              OPRL(0x11,0x20), BASE, ARG_OPRL },
 809   { "cmoveq",           OPR(0x11,0x24), BASE, ARG_OPR },
 810   { "cmoveq",           OPRL(0x11,0x24), BASE, ARG_OPRL },
 811   { "cmovne",           OPR(0x11,0x26), BASE, ARG_OPR },
 812   { "cmovne",           OPRL(0x11,0x26), BASE, ARG_OPRL },
 813   { "not",              OPR(0x11,0x28), BASE, ARG_OPRZ1 },      /* pseudo */
 814   { "not",              OPRL(0x11,0x28), BASE, ARG_OPRLZ1 },    /* pseudo */
 815   { "ornot",            OPR(0x11,0x28), BASE, ARG_OPR },
 816   { "ornot",            OPRL(0x11,0x28), BASE, ARG_OPRL },
 817   { "xor",              OPR(0x11,0x40), BASE, ARG_OPR },
 818   { "xor",              OPRL(0x11,0x40), BASE, ARG_OPRL },
 819   { "cmovlt",           OPR(0x11,0x44), BASE, ARG_OPR },
 820   { "cmovlt",           OPRL(0x11,0x44), BASE, ARG_OPRL },
 821   { "cmovge",           OPR(0x11,0x46), BASE, ARG_OPR },
 822   { "cmovge",           OPRL(0x11,0x46), BASE, ARG_OPRL },
 823   { "eqv",              OPR(0x11,0x48), BASE, ARG_OPR },
 824   { "eqv",              OPRL(0x11,0x48), BASE, ARG_OPRL },
 825   { "xornot",           OPR(0x11,0x48), BASE, ARG_OPR },        /* alias */
 826   { "xornot",           OPRL(0x11,0x48), BASE, ARG_OPRL },      /* alias */
 827   { "amask",            OPR(0x11,0x61), BASE, ARG_OPRZ1 },      /* ev56 but */
 828   { "amask",            OPRL(0x11,0x61), BASE, ARG_OPRLZ1 },    /* ev56 but */
 829   { "cmovle",           OPR(0x11,0x64), BASE, ARG_OPR },
 830   { "cmovle",           OPRL(0x11,0x64), BASE, ARG_OPRL },
 831   { "cmovgt",           OPR(0x11,0x66), BASE, ARG_OPR },
 832   { "cmovgt",           OPRL(0x11,0x66), BASE, ARG_OPRL },
 833   { "implver",          OPRL_(0x11,0x6C)|(31<<21)|(1<<13),
 834                         0xFFFFFFE0, BASE, { RC } },             /* ev56 but */
 835
 836   { "mskbl",            OPR(0x12,0x02), BASE, ARG_OPR },
 837   { "mskbl",            OPRL(0x12,0x02), BASE, ARG_OPRL },
 838   { "extbl",            OPR(0x12,0x06), BASE, ARG_OPR },
 839   { "extbl",            OPRL(0x12,0x06), BASE, ARG_OPRL },
 840   { "insbl",            OPR(0x12,0x0B), BASE, ARG_OPR },
 841   { "insbl",            OPRL(0x12,0x0B), BASE, ARG_OPRL },
 842   { "mskwl",            OPR(0x12,0x12), BASE, ARG_OPR },
 843   { "mskwl",            OPRL(0x12,0x12), BASE, ARG_OPRL },
 844   { "extwl",            OPR(0x12,0x16), BASE, ARG_OPR },
 845   { "extwl",            OPRL(0x12,0x16), BASE, ARG_OPRL },
 846   { "inswl",            OPR(0x12,0x1B), BASE, ARG_OPR },
 847   { "inswl",            OPRL(0x12,0x1B), BASE, ARG_OPRL },
 848   { "mskll",            OPR(0x12,0x22), BASE, ARG_OPR },
 849   { "mskll",            OPRL(0x12,0x22), BASE, ARG_OPRL },
 850   { "extll",            OPR(0x12,0x26), BASE, ARG_OPR },
 851   { "extll",            OPRL(0x12,0x26), BASE, ARG_OPRL },
 852   { "insll",            OPR(0x12,0x2B), BASE, ARG_OPR },
 853   { "insll",            OPRL(0x12,0x2B), BASE, ARG_OPRL },
 854   { "zap",              OPR(0x12,0x30), BASE, ARG_OPR },
 855   { "zap",              OPRL(0x12,0x30), BASE, ARG_OPRL },
 856   { "zapnot",           OPR(0x12,0x31), BASE, ARG_OPR },
 857   { "zapnot",           OPRL(0x12,0x31), BASE, ARG_OPRL },
 858   { "mskql",            OPR(0x12,0x32), BASE, ARG_OPR },
 859   { "mskql",            OPRL(0x12,0x32), BASE, ARG_OPRL },
 860   { "srl",              OPR(0x12,0x34), BASE, ARG_OPR },
 861   { "srl",              OPRL(0x12,0x34), BASE, ARG_OPRL },
 862   { "extql",            OPR(0x12,0x36), BASE, ARG_OPR },
 863   { "extql",            OPRL(0x12,0x36), BASE, ARG_OPRL },
 864   { "sll",              OPR(0x12,0x39), BASE, ARG_OPR },
 865   { "sll",              OPRL(0x12,0x39), BASE, ARG_OPRL },
 866   { "insql",            OPR(0x12,0x3B), BASE, ARG_OPR },
 867   { "insql",            OPRL(0x12,0x3B), BASE, ARG_OPRL },
 868   { "sra",              OPR(0x12,0x3C), BASE, ARG_OPR },
 869   { "sra",              OPRL(0x12,0x3C), BASE, ARG_OPRL },
 870   { "mskwh",            OPR(0x12,0x52), BASE, ARG_OPR },
 871   { "mskwh",            OPRL(0x12,0x52), BASE, ARG_OPRL },
 872   { "inswh",            OPR(0x12,0x57), BASE, ARG_OPR },
 873   { "inswh",            OPRL(0x12,0x57), BASE, ARG_OPRL },
 874   { "extwh",            OPR(0x12,0x5A), BASE, ARG_OPR },
 875   { "extwh",            OPRL(0x12,0x5A), BASE, ARG_OPRL },
 876   { "msklh",            OPR(0x12,0x62), BASE, ARG_OPR },
 877   { "msklh",            OPRL(0x12,0x62), BASE, ARG_OPRL },
 878   { "inslh",            OPR(0x12,0x67), BASE, ARG_OPR },
 879   { "inslh",            OPRL(0x12,0x67), BASE, ARG_OPRL },
 880   { "extlh",            OPR(0x12,0x6A), BASE, ARG_OPR },
 881   { "extlh",            OPRL(0x12,0x6A), BASE, ARG_OPRL },
 882   { "mskqh",            OPR(0x12,0x72), BASE, ARG_OPR },
 883   { "mskqh",            OPRL(0x12,0x72), BASE, ARG_OPRL },
 884   { "insqh",            OPR(0x12,0x77), BASE, ARG_OPR },
 885   { "insqh",            OPRL(0x12,0x77), BASE, ARG_OPRL },
 886   { "extqh",            OPR(0x12,0x7A), BASE, ARG_OPR },
 887   { "extqh",            OPRL(0x12,0x7A), BASE, ARG_OPRL },
 888
 889   { "mull",             OPR(0x13,0x00), BASE, ARG_OPR },
 890   { "mull",             OPRL(0x13,0x00), BASE, ARG_OPRL },
 891   { "mulq",             OPR(0x13,0x20), BASE, ARG_OPR },
 892   { "mulq",             OPRL(0x13,0x20), BASE, ARG_OPRL },
 893   { "umulh",            OPR(0x13,0x30), BASE, ARG_OPR },
 894   { "umulh",            OPRL(0x13,0x30), BASE, ARG_OPRL },
 895   { "mull/v",           OPR(0x13,0x40), BASE, ARG_OPR },
 896   { "mull/v",           OPRL(0x13,0x40), BASE, ARG_OPRL },
 897   { "mulq/v",           OPR(0x13,0x60), BASE, ARG_OPR },
 898   { "mulq/v",           OPRL(0x13,0x60), BASE, ARG_OPRL },
 899
 900   { "itofs",            FP(0x14,0x004), CIX, { RA, ZB, FC } },
 901   { "sqrtf/c",          FP(0x14,0x00A), CIX, ARG_FPZ1 },
 902   { "sqrts/c",          FP(0x14,0x00B), CIX, ARG_FPZ1 },
 903   { "itoff",            FP(0x14,0x014), CIX, { RA, ZB, FC } },
 904   { "itoft",            FP(0x14,0x024), CIX, { RA, ZB, FC } },
 905   { "sqrtg/c",          FP(0x14,0x02A), CIX, ARG_FPZ1 },
 906   { "sqrtt/c",          FP(0x14,0x02B), CIX, ARG_FPZ1 },
 907   { "sqrts/m",          FP(0x14,0x04B), CIX, ARG_FPZ1 },
 908   { "sqrtt/m",          FP(0x14,0x06B), CIX, ARG_FPZ1 },
 909   { "sqrtf",            FP(0x14,0x08A), CIX, ARG_FPZ1 },
 910   { "sqrts",            FP(0x14,0x08B), CIX, ARG_FPZ1 },
 911   { "sqrtg",            FP(0x14,0x0AA), CIX, ARG_FPZ1 },
 912   { "sqrtt",            FP(0x14,0x0AB), CIX, ARG_FPZ1 },
 913   { "sqrts/d",          FP(0x14,0x0CB), CIX, ARG_FPZ1 },
 914   { "sqrtt/d",          FP(0x14,0x0EB), CIX, ARG_FPZ1 },
 915   { "sqrtf/uc",         FP(0x14,0x10A), CIX, ARG_FPZ1 },
 916   { "sqrts/uc",         FP(0x14,0x10B), CIX, ARG_FPZ1 },
 917   { "sqrtg/uc",         FP(0x14,0x12A), CIX, ARG_FPZ1 },
 918   { "sqrtt/uc",         FP(0x14,0x12B), CIX, ARG_FPZ1 },
 919   { "sqrts/um",         FP(0x14,0x14B), CIX, ARG_FPZ1 },
 920   { "sqrtt/um",         FP(0x14,0x16B), CIX, ARG_FPZ1 },
 921   { "sqrtf/u",          FP(0x14,0x18A), CIX, ARG_FPZ1 },
 922   { "sqrts/u",          FP(0x14,0x18B), CIX, ARG_FPZ1 },
 923   { "sqrtg/u",          FP(0x14,0x1AA), CIX, ARG_FPZ1 },
 924   { "sqrtt/u",          FP(0x14,0x1AB), CIX, ARG_FPZ1 },
 925   { "sqrts/ud",         FP(0x14,0x1CB), CIX, ARG_FPZ1 },
 926   { "sqrtt/ud",         FP(0x14,0x1EB), CIX, ARG_FPZ1 },
 927   { "sqrtf/sc",         FP(0x14,0x40A), CIX, ARG_FPZ1 },
 928   { "sqrtg/sc",         FP(0x14,0x42A), CIX, ARG_FPZ1 },
 929   { "sqrtf/s",          FP(0x14,0x48A), CIX, ARG_FPZ1 },
 930   { "sqrtg/s",          FP(0x14,0x4AA), CIX, ARG_FPZ1 },
 931   { "sqrtf/suc",        FP(0x14,0x50A), CIX, ARG_FPZ1 },
 932   { "sqrts/suc",        FP(0x14,0x50B), CIX, ARG_FPZ1 },
 933   { "sqrtg/suc",        FP(0x14,0x52A), CIX, ARG_FPZ1 },
 934   { "sqrtt/suc",        FP(0x14,0x52B), CIX, ARG_FPZ1 },
 935   { "sqrts/sum",        FP(0x14,0x54B), CIX, ARG_FPZ1 },
 936   { "sqrtt/sum",        FP(0x14,0x56B), CIX, ARG_FPZ1 },
 937   { "sqrtf/su",         FP(0x14,0x58A), CIX, ARG_FPZ1 },
 938   { "sqrts/su",         FP(0x14,0x58B), CIX, ARG_FPZ1 },
 939   { "sqrtg/su",         FP(0x14,0x5AA), CIX, ARG_FPZ1 },
 940   { "sqrtt/su",         FP(0x14,0x5AB), CIX, ARG_FPZ1 },
 941   { "sqrts/sud",        FP(0x14,0x5CB), CIX, ARG_FPZ1 },
 942   { "sqrtt/sud",        FP(0x14,0x5EB), CIX, ARG_FPZ1 },
 943   { "sqrts/suic",       FP(0x14,0x70B), CIX, ARG_FPZ1 },
 944   { "sqrtt/suic",       FP(0x14,0x72B), CIX, ARG_FPZ1 },
 945   { "sqrts/suim",       FP(0x14,0x74B), CIX, ARG_FPZ1 },
 946   { "sqrtt/suim",       FP(0x14,0x76B), CIX, ARG_FPZ1 },
 947   { "sqrts/sui",        FP(0x14,0x78B), CIX, ARG_FPZ1 },
 948   { "sqrtt/sui",        FP(0x14,0x7AB), CIX, ARG_FPZ1 },
 949   { "sqrts/suid",       FP(0x14,0x7CB), CIX, ARG_FPZ1 },
 950   { "sqrtt/suid",       FP(0x14,0x7EB), CIX, ARG_FPZ1 },
 951
 952   { "addf/c",           FP(0x15,0x000), BASE, ARG_FP },
 953   { "subf/c",           FP(0x15,0x001), BASE, ARG_FP },
 954   { "mulf/c",           FP(0x15,0x002), BASE, ARG_FP },
 955   { "divf/c",           FP(0x15,0x003), BASE, ARG_FP },
 956   { "cvtdg/c",          FP(0x15,0x01E), BASE, ARG_FPZ1 },
 957   { "addg/c",           FP(0x15,0x020), BASE, ARG_FP },
 958   { "subg/c",           FP(0x15,0x021), BASE, ARG_FP },
 959   { "mulg/c",           FP(0x15,0x022), BASE, ARG_FP },
 960   { "divg/c",           FP(0x15,0x023), BASE, ARG_FP },
 961   { "cvtgf/c",          FP(0x15,0x02C), BASE, ARG_FPZ1 },
 962   { "cvtgd/c",          FP(0x15,0x02D), BASE, ARG_FPZ1 },
 963   { "cvtgq/c",          FP(0x15,0x02F), BASE, ARG_FPZ1 },
 964   { "cvtqf/c",          FP(0x15,0x03C), BASE, ARG_FPZ1 },
 965   { "cvtqg/c",          FP(0x15,0x03E), BASE, ARG_FPZ1 },
 966   { "addf",             FP(0x15,0x080), BASE, ARG_FP },
 967   { "negf",             FP(0x15,0x081), BASE, ARG_FPZ1 },       /* pseudo */
 968   { "subf",             FP(0x15,0x081), BASE, ARG_FP },
 969   { "mulf",             FP(0x15,0x082), BASE, ARG_FP },
 970   { "divf",             FP(0x15,0x083), BASE, ARG_FP },
 971   { "cvtdg",            FP(0x15,0x09E), BASE, ARG_FPZ1 },
 972   { "addg",             FP(0x15,0x0A0), BASE, ARG_FP },
 973   { "negg",             FP(0x15,0x0A1), BASE, ARG_FPZ1 },       /* pseudo */
 974   { "subg",             FP(0x15,0x0A1), BASE, ARG_FP },
 975   { "mulg",             FP(0x15,0x0A2), BASE, ARG_FP },
 976   { "divg",             FP(0x15,0x0A3), BASE, ARG_FP },
 977   { "cmpgeq",           FP(0x15,0x0A5), BASE, ARG_FP },
 978   { "cmpglt",           FP(0x15,0x0A6), BASE, ARG_FP },
 979   { "cmpgle",           FP(0x15,0x0A7), BASE, ARG_FP },
 980   { "cvtgf",            FP(0x15,0x0AC), BASE, ARG_FPZ1 },
 981   { "cvtgd",            FP(0x15,0x0AD), BASE, ARG_FPZ1 },
 982   { "cvtgq",            FP(0x15,0x0AF), BASE, ARG_FPZ1 },
 983   { "cvtqf",            FP(0x15,0x0BC), BASE, ARG_FPZ1 },
 984   { "cvtqg",            FP(0x15,0x0BE), BASE, ARG_FPZ1 },
 985   { "addf/uc",          FP(0x15,0x100), BASE, ARG_FP },
 986   { "subf/uc",          FP(0x15,0x101), BASE, ARG_FP },
 987   { "mulf/uc",          FP(0x15,0x102), BASE, ARG_FP },
 988   { "divf/uc",          FP(0x15,0x103), BASE, ARG_FP },
 989   { "cvtdg/uc",         FP(0x15,0x11E), BASE, ARG_FPZ1 },
 990   { "addg/uc",          FP(0x15,0x120), BASE, ARG_FP },
 991   { "subg/uc",          FP(0x15,0x121), BASE, ARG_FP },
 992   { "mulg/uc",          FP(0x15,0x122), BASE, ARG_FP },
 993   { "divg/uc",          FP(0x15,0x123), BASE, ARG_FP },
 994   { "cvtgf/uc",         FP(0x15,0x12C), BASE, ARG_FPZ1 },
 995   { "cvtgd/uc",         FP(0x15,0x12D), BASE, ARG_FPZ1 },
 996   { "cvtgq/vc",         FP(0x15,0x12F), BASE, ARG_FPZ1 },
 997   { "addf/u",           FP(0x15,0x180), BASE, ARG_FP },
 998   { "subf/u",           FP(0x15,0x181), BASE, ARG_FP },
 999   { "mulf/u",           FP(0x15,0x182), BASE, ARG_FP },
1000   { "divf/u",           FP(0x15,0x183), BASE, ARG_FP },
1001   { "cvtdg/u",          FP(0x15,0x19E), BASE, ARG_FPZ1 },
1002   { "addg/u",           FP(0x15,0x1A0), BASE, ARG_FP },
1003   { "subg/u",           FP(0x15,0x1A1), BASE, ARG_FP },
1004   { "mulg/u",           FP(0x15,0x1A2), BASE, ARG_FP },
1005   { "divg/u",           FP(0x15,0x1A3), BASE, ARG_FP },
1006   { "cvtgf/u",          FP(0x15,0x1AC), BASE, ARG_FPZ1 },
1007   { "cvtgd/u",          FP(0x15,0x1AD), BASE, ARG_FPZ1 },
1008   { "cvtgq/v",          FP(0x15,0x1AF), BASE, ARG_FPZ1 },
1009   { "addf/sc",          FP(0x15,0x400), BASE, ARG_FP },
1010   { "subf/sc",          FP(0x15,0x401), BASE, ARG_FP },
1011   { "mulf/sc",          FP(0x15,0x402), BASE, ARG_FP },
1012   { "divf/sc",          FP(0x15,0x403), BASE, ARG_FP },
1013   { "cvtdg/sc",         FP(0x15,0x41E), BASE, ARG_FPZ1 },
1014   { "addg/sc",          FP(0x15,0x420), BASE, ARG_FP },
1015   { "subg/sc",          FP(0x15,0x421), BASE, ARG_FP },
1016   { "mulg/sc",          FP(0x15,0x422), BASE, ARG_FP },
1017   { "divg/sc",          FP(0x15,0x423), BASE, ARG_FP },
1018   { "cvtgf/sc",         FP(0x15,0x42C), BASE, ARG_FPZ1 },
1019   { "cvtgd/sc",         FP(0x15,0x42D), BASE, ARG_FPZ1 },
1020   { "cvtgq/sc",         FP(0x15,0x42F), BASE, ARG_FPZ1 },
1021   { "addf/s",           FP(0x15,0x480), BASE, ARG_FP },
1022   { "negf/s",           FP(0x15,0x481), BASE, ARG_FPZ1 },       /* pseudo */
1023   { "subf/s",           FP(0x15,0x481), BASE, ARG_FP },
1024   { "mulf/s",           FP(0x15,0x482), BASE, ARG_FP },
1025   { "divf/s",           FP(0x15,0x483), BASE, ARG_FP },
1026   { "cvtdg/s",          FP(0x15,0x49E), BASE, ARG_FPZ1 },
1027   { "addg/s",           FP(0x15,0x4A0), BASE, ARG_FP },
1028   { "negg/s",           FP(0x15,0x4A1), BASE, ARG_FPZ1 },       /* pseudo */
1029   { "subg/s",           FP(0x15,0x4A1), BASE, ARG_FP },
1030   { "mulg/s",           FP(0x15,0x4A2), BASE, ARG_FP },
1031   { "divg/s",           FP(0x15,0x4A3), BASE, ARG_FP },
1032   { "cmpgeq/s",         FP(0x15,0x4A5), BASE, ARG_FP },
1033   { "cmpglt/s",         FP(0x15,0x4A6), BASE, ARG_FP },
1034   { "cmpgle/s",         FP(0x15,0x4A7), BASE, ARG_FP },
1035   { "cvtgf/s",          FP(0x15,0x4AC), BASE, ARG_FPZ1 },
1036   { "cvtgd/s",          FP(0x15,0x4AD), BASE, ARG_FPZ1 },
1037   { "cvtgq/s",          FP(0x15,0x4AF), BASE, ARG_FPZ1 },
1038   { "addf/suc",         FP(0x15,0x500), BASE, ARG_FP },
1039   { "subf/suc",         FP(0x15,0x501), BASE, ARG_FP },
1040   { "mulf/suc",         FP(0x15,0x502), BASE, ARG_FP },
1041   { "divf/suc",         FP(0x15,0x503), BASE, ARG_FP },
1042   { "cvtdg/suc",        FP(0x15,0x51E), BASE, ARG_FPZ1 },
1043   { "addg/suc",         FP(0x15,0x520), BASE, ARG_FP },
1044   { "subg/suc",         FP(0x15,0x521), BASE, ARG_FP },
1045   { "mulg/suc",         FP(0x15,0x522), BASE, ARG_FP },
1046   { "divg/suc",         FP(0x15,0x523), BASE, ARG_FP },
1047   { "cvtgf/suc",        FP(0x15,0x52C), BASE, ARG_FPZ1 },
1048   { "cvtgd/suc",        FP(0x15,0x52D), BASE, ARG_FPZ1 },
1049   { "cvtgq/svc",        FP(0x15,0x52F), BASE, ARG_FPZ1 },
1050   { "addf/su",          FP(0x15,0x580), BASE, ARG_FP },
1051   { "subf/su",          FP(0x15,0x581), BASE, ARG_FP },
1052   { "mulf/su",          FP(0x15,0x582), BASE, ARG_FP },
1053   { "divf/su",          FP(0x15,0x583), BASE, ARG_FP },
1054   { "cvtdg/su",         FP(0x15,0x59E), BASE, ARG_FPZ1 },
1055   { "addg/su",          FP(0x15,0x5A0), BASE, ARG_FP },
1056   { "subg/su",          FP(0x15,0x5A1), BASE, ARG_FP },
1057   { "mulg/su",          FP(0x15,0x5A2), BASE, ARG_FP },
1058   { "divg/su",          FP(0x15,0x5A3), BASE, ARG_FP },
1059   { "cvtgf/su",         FP(0x15,0x5AC), BASE, ARG_FPZ1 },
1060   { "cvtgd/su",         FP(0x15,0x5AD), BASE, ARG_FPZ1 },
1061   { "cvtgq/sv",         FP(0x15,0x5AF), BASE, ARG_FPZ1 },
1062
1063   { "adds/c",           FP(0x16,0x000), BASE, ARG_FP },
1064   { "subs/c",           FP(0x16,0x001), BASE, ARG_FP },
1065   { "muls/c",           FP(0x16,0x002), BASE, ARG_FP },
1066   { "divs/c",           FP(0x16,0x003), BASE, ARG_FP },
1067   { "addt/c",           FP(0x16,0x020), BASE, ARG_FP },
1068   { "subt/c",           FP(0x16,0x021), BASE, ARG_FP },
1069   { "mult/c",           FP(0x16,0x022), BASE, ARG_FP },
1070   { "divt/c",           FP(0x16,0x023), BASE, ARG_FP },
1071   { "cvtts/c",          FP(0x16,0x02C), BASE, ARG_FPZ1 },
1072   { "cvttq/c",          FP(0x16,0x02F), BASE, ARG_FPZ1 },
1073   { "cvtqs/c",          FP(0x16,0x03C), BASE, ARG_FPZ1 },
1074   { "cvtqt/c",          FP(0x16,0x03E), BASE, ARG_FPZ1 },
1075   { "adds/m",           FP(0x16,0x040), BASE, ARG_FP },
1076   { "subs/m",           FP(0x16,0x041), BASE, ARG_FP },
1077   { "muls/m",           FP(0x16,0x042), BASE, ARG_FP },
1078   { "divs/m",           FP(0x16,0x043), BASE, ARG_FP },
1079   { "addt/m",           FP(0x16,0x060), BASE, ARG_FP },
1080   { "subt/m",           FP(0x16,0x061), BASE, ARG_FP },
1081   { "mult/m",           FP(0x16,0x062), BASE, ARG_FP },
1082   { "divt/m",           FP(0x16,0x063), BASE, ARG_FP },
1083   { "cvtts/m",          FP(0x16,0x06C), BASE, ARG_FPZ1 },
1084   { "cvttq/m",          FP(0x16,0x06F), BASE, ARG_FPZ1 },
1085   { "cvtqs/m",          FP(0x16,0x07C), BASE, ARG_FPZ1 },
1086   { "cvtqt/m",          FP(0x16,0x07E), BASE, ARG_FPZ1 },
1087   { "adds",             FP(0x16,0x080), BASE, ARG_FP },
1088   { "negs",             FP(0x16,0x081), BASE, ARG_FPZ1 },       /* pseudo */
1089   { "subs",             FP(0x16,0x081), BASE, ARG_FP },
1090   { "muls",             FP(0x16,0x082), BASE, ARG_FP },
1091   { "divs",             FP(0x16,0x083), BASE, ARG_FP },
1092   { "addt",             FP(0x16,0x0A0), BASE, ARG_FP },
1093   { "negt",             FP(0x16,0x0A1), BASE, ARG_FPZ1 },       /* pseudo */
1094   { "subt",             FP(0x16,0x0A1), BASE, ARG_FP },
1095   { "mult",             FP(0x16,0x0A2), BASE, ARG_FP },
1096   { "divt",             FP(0x16,0x0A3), BASE, ARG_FP },
1097   { "cmptun",           FP(0x16,0x0A4), BASE, ARG_FP },
1098   { "cmpteq",           FP(0x16,0x0A5), BASE, ARG_FP },
1099   { "cmptlt",           FP(0x16,0x0A6), BASE, ARG_FP },
1100   { "cmptle",           FP(0x16,0x0A7), BASE, ARG_FP },
1101   { "cvtts",            FP(0x16,0x0AC), BASE, ARG_FPZ1 },
1102   { "cvttq",            FP(0x16,0x0AF), BASE, ARG_FPZ1 },
1103   { "cvtqs",            FP(0x16,0x0BC), BASE, ARG_FPZ1 },
1104   { "cvtqt",            FP(0x16,0x0BE), BASE, ARG_FPZ1 },
1105   { "adds/d",           FP(0x16,0x0C0), BASE, ARG_FP },
1106   { "subs/d",           FP(0x16,0x0C1), BASE, ARG_FP },
1107   { "muls/d",           FP(0x16,0x0C2), BASE, ARG_FP },
1108   { "divs/d",           FP(0x16,0x0C3), BASE, ARG_FP },
1109   { "addt/d",           FP(0x16,0x0E0), BASE, ARG_FP },
1110   { "subt/d",           FP(0x16,0x0E1), BASE, ARG_FP },
1111   { "mult/d",           FP(0x16,0x0E2), BASE, ARG_FP },
1112   { "divt/d",           FP(0x16,0x0E3), BASE, ARG_FP },
1113   { "cvtts/d",          FP(0x16,0x0EC), BASE, ARG_FPZ1 },
1114   { "cvttq/d",          FP(0x16,0x0EF), BASE, ARG_FPZ1 },
1115   { "cvtqs/d",          FP(0x16,0x0FC), BASE, ARG_FPZ1 },
1116   { "cvtqt/d",          FP(0x16,0x0FE), BASE, ARG_FPZ1 },
1117   { "adds/uc",          FP(0x16,0x100), BASE, ARG_FP },
1118   { "subs/uc",          FP(0x16,0x101), BASE, ARG_FP },
1119   { "muls/uc",          FP(0x16,0x102), BASE, ARG_FP },
1120   { "divs/uc",          FP(0x16,0x103), BASE, ARG_FP },
1121   { "addt/uc",          FP(0x16,0x120), BASE, ARG_FP },
1122   { "subt/uc",          FP(0x16,0x121), BASE, ARG_FP },
1123   { "mult/uc",          FP(0x16,0x122), BASE, ARG_FP },
1124   { "divt/uc",          FP(0x16,0x123), BASE, ARG_FP },
1125   { "cvtts/uc",         FP(0x16,0x12C), BASE, ARG_FPZ1 },
1126   { "cvttq/vc",         FP(0x16,0x12F), BASE, ARG_FPZ1 },
1127   { "adds/um",          FP(0x16,0x140), BASE, ARG_FP },
1128   { "subs/um",          FP(0x16,0x141), BASE, ARG_FP },
1129   { "muls/um",          FP(0x16,0x142), BASE, ARG_FP },
1130   { "divs/um",          FP(0x16,0x143), BASE, ARG_FP },
1131   { "addt/um",          FP(0x16,0x160), BASE, ARG_FP },
1132   { "subt/um",          FP(0x16,0x161), BASE, ARG_FP },
1133   { "mult/um",          FP(0x16,0x162), BASE, ARG_FP },
1134   { "divt/um",          FP(0x16,0x163), BASE, ARG_FP },
1135   { "cvtts/um",         FP(0x16,0x16C), BASE, ARG_FPZ1 },
1136   { "cvttq/vm",         FP(0x16,0x16F), BASE, ARG_FPZ1 },
1137   { "adds/u",           FP(0x16,0x180), BASE, ARG_FP },
1138   { "subs/u",           FP(0x16,0x181), BASE, ARG_FP },
1139   { "muls/u",           FP(0x16,0x182), BASE, ARG_FP },
1140   { "divs/u",           FP(0x16,0x183), BASE, ARG_FP },
1141   { "addt/u",           FP(0x16,0x1A0), BASE, ARG_FP },
1142   { "subt/u",           FP(0x16,0x1A1), BASE, ARG_FP },
1143   { "mult/u",           FP(0x16,0x1A2), BASE, ARG_FP },
1144   { "divt/u",           FP(0x16,0x1A3), BASE, ARG_FP },
1145   { "cvtts/u",          FP(0x16,0x1AC), BASE, ARG_FPZ1 },
1146   { "cvttq/v",          FP(0x16,0x1AF), BASE, ARG_FPZ1 },
1147   { "adds/ud",          FP(0x16,0x1C0), BASE, ARG_FP },
1148   { "subs/ud",          FP(0x16,0x1C1), BASE, ARG_FP },
1149   { "muls/ud",          FP(0x16,0x1C2), BASE, ARG_FP },
1150   { "divs/ud",          FP(0x16,0x1C3), BASE, ARG_FP },
1151   { "addt/ud",          FP(0x16,0x1E0), BASE, ARG_FP },
1152   { "subt/ud",          FP(0x16,0x1E1), BASE, ARG_FP },
1153   { "mult/ud",          FP(0x16,0x1E2), BASE, ARG_FP },
1154   { "divt/ud",          FP(0x16,0x1E3), BASE, ARG_FP },
1155   { "cvtts/ud",         FP(0x16,0x1EC), BASE, ARG_FPZ1 },
1156   { "cvttq/vd",         FP(0x16,0x1EF), BASE, ARG_FPZ1 },
1157   { "cvtst",            FP(0x16,0x2AC), BASE, ARG_FPZ1 },
1158   { "adds/suc",         FP(0x16,0x500), BASE, ARG_FP },
1159   { "subs/suc",         FP(0x16,0x501), BASE, ARG_FP },
1160   { "muls/suc",         FP(0x16,0x502), BASE, ARG_FP },
1161   { "divs/suc",         FP(0x16,0x503), BASE, ARG_FP },
1162   { "addt/suc",         FP(0x16,0x520), BASE, ARG_FP },
1163   { "subt/suc",         FP(0x16,0x521), BASE, ARG_FP },
1164   { "mult/suc",         FP(0x16,0x522), BASE, ARG_FP },
1165   { "divt/suc",         FP(0x16,0x523), BASE, ARG_FP },
1166   { "cvtts/suc",        FP(0x16,0x52C), BASE, ARG_FPZ1 },
1167   { "cvttq/svc",        FP(0x16,0x52F), BASE, ARG_FPZ1 },
1168   { "adds/sum",         FP(0x16,0x540), BASE, ARG_FP },
1169   { "subs/sum",         FP(0x16,0x541), BASE, ARG_FP },
1170   { "muls/sum",         FP(0x16,0x542), BASE, ARG_FP },
1171   { "divs/sum",         FP(0x16,0x543), BASE, ARG_FP },
1172   { "addt/sum",         FP(0x16,0x560), BASE, ARG_FP },
1173   { "subt/sum",         FP(0x16,0x561), BASE, ARG_FP },
1174   { "mult/sum",         FP(0x16,0x562), BASE, ARG_FP },
1175   { "divt/sum",         FP(0x16,0x563), BASE, ARG_FP },
1176   { "cvtts/sum",        FP(0x16,0x56C), BASE, ARG_FPZ1 },
1177   { "cvttq/svm",        FP(0x16,0x56F), BASE, ARG_FPZ1 },
1178   { "adds/su",          FP(0x16,0x580), BASE, ARG_FP },
1179   { "negs/su",          FP(0x16,0x581), BASE, ARG_FPZ1 },       /* pseudo */
1180   { "subs/su",          FP(0x16,0x581), BASE, ARG_FP },
1181   { "muls/su",          FP(0x16,0x582), BASE, ARG_FP },
1182   { "divs/su",          FP(0x16,0x583), BASE, ARG_FP },
1183   { "addt/su",          FP(0x16,0x5A0), BASE, ARG_FP },
1184   { "negt/su",          FP(0x16,0x5A1), BASE, ARG_FPZ1 },       /* pseudo */
1185   { "subt/su",          FP(0x16,0x5A1), BASE, ARG_FP },
1186   { "mult/su",          FP(0x16,0x5A2), BASE, ARG_FP },
1187   { "divt/su",          FP(0x16,0x5A3), BASE, ARG_FP },
1188   { "cmptun/su",        FP(0x16,0x5A4), BASE, ARG_FP },
1189   { "cmpteq/su",        FP(0x16,0x5A5), BASE, ARG_FP },
1190   { "cmptlt/su",        FP(0x16,0x5A6), BASE, ARG_FP },
1191   { "cmptle/su",        FP(0x16,0x5A7), BASE, ARG_FP },
1192   { "cvtts/su",         FP(0x16,0x5AC), BASE, ARG_FPZ1 },
1193   { "cvttq/sv",         FP(0x16,0x5AF), BASE, ARG_FPZ1 },
1194   { "adds/sud",         FP(0x16,0x5C0), BASE, ARG_FP },
1195   { "subs/sud",         FP(0x16,0x5C1), BASE, ARG_FP },
1196   { "muls/sud",         FP(0x16,0x5C2), BASE, ARG_FP },
1197   { "divs/sud",         FP(0x16,0x5C3), BASE, ARG_FP },
1198   { "addt/sud",         FP(0x16,0x5E0), BASE, ARG_FP },
1199   { "subt/sud",         FP(0x16,0x5E1), BASE, ARG_FP },
1200   { "mult/sud",         FP(0x16,0x5E2), BASE, ARG_FP },
1201   { "divt/sud",         FP(0x16,0x5E3), BASE, ARG_FP },
1202   { "cvtts/sud",        FP(0x16,0x5EC), BASE, ARG_FPZ1 },
1203   { "cvttq/svd",        FP(0x16,0x5EF), BASE, ARG_FPZ1 },
1204   { "cvtst/s",          FP(0x16,0x6AC), BASE, ARG_FPZ1 },
1205   { "adds/suic",        FP(0x16,0x700), BASE, ARG_FP },
1206   { "subs/suic",        FP(0x16,0x701), BASE, ARG_FP },
1207   { "muls/suic",        FP(0x16,0x702), BASE, ARG_FP },
1208   { "divs/suic",        FP(0x16,0x703), BASE, ARG_FP },
1209   { "addt/suic",        FP(0x16,0x720), BASE, ARG_FP },
1210   { "subt/suic",        FP(0x16,0x721), BASE, ARG_FP },
1211   { "mult/suic",        FP(0x16,0x722), BASE, ARG_FP },
1212   { "divt/suic",        FP(0x16,0x723), BASE, ARG_FP },
1213   { "cvtts/suic",       FP(0x16,0x72C), BASE, ARG_FPZ1 },
1214   { "cvttq/svic",       FP(0x16,0x72F), BASE, ARG_FPZ1 },
1215   { "cvtqs/suic",       FP(0x16,0x73C), BASE, ARG_FPZ1 },
1216   { "cvtqt/suic",       FP(0x16,0x73E), BASE, ARG_FPZ1 },
1217   { "adds/suim",        FP(0x16,0x740), BASE, ARG_FP },
1218   { "subs/suim",        FP(0x16,0x741), BASE, ARG_FP },
1219   { "muls/suim",        FP(0x16,0x742), BASE, ARG_FP },
1220   { "divs/suim",        FP(0x16,0x743), BASE, ARG_FP },
1221   { "addt/suim",        FP(0x16,0x760), BASE, ARG_FP },
1222   { "subt/suim",        FP(0x16,0x761), BASE, ARG_FP },
1223   { "mult/suim",        FP(0x16,0x762), BASE, ARG_FP },
1224   { "divt/suim",        FP(0x16,0x763), BASE, ARG_FP },
1225   { "cvtts/suim",       FP(0x16,0x76C), BASE, ARG_FPZ1 },
1226   { "cvttq/svim",       FP(0x16,0x76F), BASE, ARG_FPZ1 },
1227   { "cvtqs/suim",       FP(0x16,0x77C), BASE, ARG_FPZ1 },
1228   { "cvtqt/suim",       FP(0x16,0x77E), BASE, ARG_FPZ1 },
1229   { "adds/sui",         FP(0x16,0x780), BASE, ARG_FP },
1230   { "negs/sui",         FP(0x16,0x781), BASE, ARG_FPZ1 },       /* pseudo */
1231   { "subs/sui",         FP(0x16,0x781), BASE, ARG_FP },
1232   { "muls/sui",         FP(0x16,0x782), BASE, ARG_FP },
1233   { "divs/sui",         FP(0x16,0x783), BASE, ARG_FP },
1234   { "addt/sui",         FP(0x16,0x7A0), BASE, ARG_FP },
1235   { "negt/sui",         FP(0x16,0x7A1), BASE, ARG_FPZ1 },       /* pseudo */
1236   { "subt/sui",         FP(0x16,0x7A1), BASE, ARG_FP },
1237   { "mult/sui",         FP(0x16,0x7A2), BASE, ARG_FP },
1238   { "divt/sui",         FP(0x16,0x7A3), BASE, ARG_FP },
1239   { "cvtts/sui",        FP(0x16,0x7AC), BASE, ARG_FPZ1 },
1240   { "cvttq/svi",        FP(0x16,0x7AF), BASE, ARG_FPZ1 },
1241   { "cvtqs/sui",        FP(0x16,0x7BC), BASE, ARG_FPZ1 },
1242   { "cvtqt/sui",        FP(0x16,0x7BE), BASE, ARG_FPZ1 },
1243   { "adds/suid",        FP(0x16,0x7C0), BASE, ARG_FP },
1244   { "subs/suid",        FP(0x16,0x7C1), BASE, ARG_FP },
1245   { "muls/suid",        FP(0x16,0x7C2), BASE, ARG_FP },
1246   { "divs/suid",        FP(0x16,0x7C3), BASE, ARG_FP },
1247   { "addt/suid",        FP(0x16,0x7E0), BASE, ARG_FP },
1248   { "subt/suid",        FP(0x16,0x7E1), BASE, ARG_FP },
1249   { "mult/suid",        FP(0x16,0x7E2), BASE, ARG_FP },
1250   { "divt/suid",        FP(0x16,0x7E3), BASE, ARG_FP },
1251   { "cvtts/suid",       FP(0x16,0x7EC), BASE, ARG_FPZ1 },
1252   { "cvttq/svid",       FP(0x16,0x7EF), BASE, ARG_FPZ1 },
1253   { "cvtqs/suid",       FP(0x16,0x7FC), BASE, ARG_FPZ1 },
1254   { "cvtqt/suid",       FP(0x16,0x7FE), BASE, ARG_FPZ1 },
1255
1256   { "cvtlq",            FP(0x17,0x010), BASE, ARG_FPZ1 },
1257   { "fnop",             FP(0x17,0x020), BASE, { ZA, ZB, ZC } }, /* pseudo */
1258   { "fclr",             FP(0x17,0x020), BASE, { ZA, ZB, FC } }, /* pseudo */
1259   { "fabs",             FP(0x17,0x020), BASE, ARG_FPZ1 },       /* pseudo */
1260   { "fmov",             FP(0x17,0x020), BASE, { FA, RBA, FC } }, /* pseudo */
1261   { "cpys",             FP(0x17,0x020), BASE, ARG_FP },
1262   { "fneg",             FP(0x17,0x021), BASE, { FA, RBA, FC } }, /* pseudo */
1263   { "cpysn",            FP(0x17,0x021), BASE, ARG_FP },
1264   { "cpyse",            FP(0x17,0x022), BASE, ARG_FP },
1265   { "mt_fpcr",          FP(0x17,0x024), BASE, { FA, RBA, RCA } },
1266   { "mf_fpcr",          FP(0x17,0x025), BASE, { FA, RBA, RCA } },
1267   { "fcmoveq",          FP(0x17,0x02A), BASE, ARG_FP },
1268   { "fcmovne",          FP(0x17,0x02B), BASE, ARG_FP },
1269   { "fcmovlt",          FP(0x17,0x02C), BASE, ARG_FP },
1270   { "fcmovge",          FP(0x17,0x02D), BASE, ARG_FP },
1271   { "fcmovle",          FP(0x17,0x02E), BASE, ARG_FP },
1272   { "fcmovgt",          FP(0x17,0x02F), BASE, ARG_FP },
1273   { "cvtql",            FP(0x17,0x030), BASE, ARG_FPZ1 },
1274   { "cvtql/v",          FP(0x17,0x130), BASE, ARG_FPZ1 },
1275   { "cvtql/sv",         FP(0x17,0x530), BASE, ARG_FPZ1 },
1276
1277   { "trapb",            MFC(0x18,0x0000), BASE, ARG_NONE },
1278   { "draint",           MFC(0x18,0x0000), BASE, ARG_NONE },     /* alias */
1279   { "excb",             MFC(0x18,0x0400), BASE, ARG_NONE },
1280   { "mb",               MFC(0x18,0x4000), BASE, ARG_NONE },
1281   { "wmb",              MFC(0x18,0x4400), BASE, ARG_NONE },
1282   { "fetch",            MFC(0x18,0x8000), BASE, { ZA, PRB } },
1283   { "fetch_m",          MFC(0x18,0xA000), BASE, { ZA, PRB } },
1284   { "rpcc",             MFC(0x18,0xC000), BASE, { RA } },
1285   { "rc",               MFC(0x18,0xE000), BASE, { RA } },
1286   { "ecb",              MFC(0x18,0xE800), BASE, { ZA, PRB } },  /* ev56 una */
1287   { "rs",               MFC(0x18,0xF000), BASE, { RA } },
1288   { "wh64",             MFC(0x18,0xF800), BASE, { ZA, PRB } },  /* ev56 una */
1289   { "wh64en",           MFC(0x18,0xFC00), BASE, { ZA, PRB } },  /* ev7 una */
1290
1291   { "hw_mfpr",          OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
1292   { "hw_mfpr",          OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
1293   { "hw_mfpr",          OP(0x19), OP_MASK, EV6, { RA, ZB, EV6HWINDEX } },
1294   { "hw_mfpr/i",        OPR(0x19,0x01), EV4, ARG_EV4HWMPR },
1295   { "hw_mfpr/a",        OPR(0x19,0x02), EV4, ARG_EV4HWMPR },
1296   { "hw_mfpr/ai",       OPR(0x19,0x03), EV4, ARG_EV4HWMPR },
1297   { "hw_mfpr/p",        OPR(0x19,0x04), EV4, ARG_EV4HWMPR },
1298   { "hw_mfpr/pi",       OPR(0x19,0x05), EV4, ARG_EV4HWMPR },
1299   { "hw_mfpr/pa",       OPR(0x19,0x06), EV4, ARG_EV4HWMPR },
1300   { "hw_mfpr/pai",      OPR(0x19,0x07), EV4, ARG_EV4HWMPR },
1301   { "pal19",            PCD(0x19), BASE, ARG_PCD },
1302
1303   { "jmp",              MBR_(0x1A,0), MBR_MASK | 0x3FFF,        /* pseudo */
1304                         BASE, { ZA, CPRB } },
1305   { "jmp",              MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } },
1306   { "jsr",              MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } },
1307   { "ret",              MBR_(0x1A,2) | (31 << 21) | (26 << 16) | 1,/* pseudo */
1308                         0xFFFFFFFF, BASE, { 0 } },
1309   { "ret",              MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } },
1310   { "jcr",              MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */
1311   { "jsr_coroutine",    MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } },
1312
1313   { "hw_ldl",           EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
1314   { "hw_ldl",           EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
1315   { "hw_ldl",           EV6HWMEM(0x1B,0x8), EV6, ARG_EV6HWMEM },
1316   { "hw_ldl/a",         EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
1317   { "hw_ldl/a",         EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
1318   { "hw_ldl/a",         EV6HWMEM(0x1B,0xC), EV6, ARG_EV6HWMEM },
1319   { "hw_ldl/al",        EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1320   { "hw_ldl/ar",        EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
1321   { "hw_ldl/av",        EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM },
1322   { "hw_ldl/avl",       EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1323   { "hw_ldl/aw",        EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM },
1324   { "hw_ldl/awl",       EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1325   { "hw_ldl/awv",       EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM },
1326   { "hw_ldl/awvl",      EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1327   { "hw_ldl/l",         EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1328   { "hw_ldl/p",         EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
1329   { "hw_ldl/p",         EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM },
1330   { "hw_ldl/p",         EV6HWMEM(0x1B,0x0), EV6, ARG_EV6HWMEM },
1331   { "hw_ldl/pa",        EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
1332   { "hw_ldl/pa",        EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM },
1333   { "hw_ldl/pal",       EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1334   { "hw_ldl/par",       EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
1335   { "hw_ldl/pav",       EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM },
1336   { "hw_ldl/pavl",      EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1337   { "hw_ldl/paw",       EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM },
1338   { "hw_ldl/pawl",      EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1339   { "hw_ldl/pawv",      EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM },
1340   { "hw_ldl/pawvl",     EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1341   { "hw_ldl/pl",        EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1342   { "hw_ldl/pr",        EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
1343   { "hw_ldl/pv",        EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM },
1344   { "hw_ldl/pvl",       EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1345   { "hw_ldl/pw",        EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM },
1346   { "hw_ldl/pwl",       EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1347   { "hw_ldl/pwv",       EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM },
1348   { "hw_ldl/pwvl",      EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1349   { "hw_ldl/r",         EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
1350   { "hw_ldl/v",         EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM },
1351   { "hw_ldl/v",         EV6HWMEM(0x1B,0x4), EV6, ARG_EV6HWMEM },
1352   { "hw_ldl/vl",        EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1353   { "hw_ldl/w",         EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM },
1354   { "hw_ldl/w",         EV6HWMEM(0x1B,0xA), EV6, ARG_EV6HWMEM },
1355   { "hw_ldl/wa",        EV6HWMEM(0x1B,0xE), EV6, ARG_EV6HWMEM },
1356   { "hw_ldl/wl",        EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1357   { "hw_ldl/wv",        EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM },
1358   { "hw_ldl/wvl",       EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1359   { "hw_ldl_l",         EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1360   { "hw_ldl_l/a",       EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1361   { "hw_ldl_l/av",      EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1362   { "hw_ldl_l/aw",      EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1363   { "hw_ldl_l/awv",     EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1364   { "hw_ldl_l/p",       EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1365   { "hw_ldl_l/p",       EV6HWMEM(0x1B,0x2), EV6, ARG_EV6HWMEM },
1366   { "hw_ldl_l/pa",      EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1367   { "hw_ldl_l/pav",     EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1368   { "hw_ldl_l/paw",     EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1369   { "hw_ldl_l/pawv",    EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1370   { "hw_ldl_l/pv",      EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1371   { "hw_ldl_l/pw",      EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1372   { "hw_ldl_l/pwv",     EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1373   { "hw_ldl_l/v",       EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1374   { "hw_ldl_l/w",       EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1375   { "hw_ldl_l/wv",      EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1376   { "hw_ldq",           EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
1377   { "hw_ldq",           EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM },
1378   { "hw_ldq",           EV6HWMEM(0x1B,0x9), EV6, ARG_EV6HWMEM },
1379   { "hw_ldq/a",         EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
1380   { "hw_ldq/a",         EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM },
1381   { "hw_ldq/a",         EV6HWMEM(0x1B,0xD), EV6, ARG_EV6HWMEM },
1382   { "hw_ldq/al",        EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1383   { "hw_ldq/ar",        EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
1384   { "hw_ldq/av",        EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM },
1385   { "hw_ldq/avl",       EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1386   { "hw_ldq/aw",        EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM },
1387   { "hw_ldq/awl",       EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1388   { "hw_ldq/awv",       EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM },
1389   { "hw_ldq/awvl",      EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1390   { "hw_ldq/l",         EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1391   { "hw_ldq/p",         EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
1392   { "hw_ldq/p",         EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM },
1393   { "hw_ldq/p",         EV6HWMEM(0x1B,0x1), EV6, ARG_EV6HWMEM },
1394   { "hw_ldq/pa",        EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
1395   { "hw_ldq/pa",        EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM },
1396   { "hw_ldq/pal",       EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1397   { "hw_ldq/par",       EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
1398   { "hw_ldq/pav",       EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM },
1399   { "hw_ldq/pavl",      EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1400   { "hw_ldq/paw",       EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM },
1401   { "hw_ldq/pawl",      EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1402   { "hw_ldq/pawv",      EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM },
1403   { "hw_ldq/pawvl",     EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1404   { "hw_ldq/pl",        EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1405   { "hw_ldq/pr",        EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
1406   { "hw_ldq/pv",        EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM },
1407   { "hw_ldq/pvl",       EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1408   { "hw_ldq/pw",        EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM },
1409   { "hw_ldq/pwl",       EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1410   { "hw_ldq/pwv",       EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM },
1411   { "hw_ldq/pwvl",      EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1412   { "hw_ldq/r",         EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
1413   { "hw_ldq/v",         EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM },
1414   { "hw_ldq/v",         EV6HWMEM(0x1B,0x5), EV6, ARG_EV6HWMEM },
1415   { "hw_ldq/vl",        EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1416   { "hw_ldq/w",         EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM },
1417   { "hw_ldq/w",         EV6HWMEM(0x1B,0xB), EV6, ARG_EV6HWMEM },
1418   { "hw_ldq/wa",        EV6HWMEM(0x1B,0xF), EV6, ARG_EV6HWMEM },
1419   { "hw_ldq/wl",        EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1420   { "hw_ldq/wv",        EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM },
1421   { "hw_ldq/wvl",       EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1422   { "hw_ldq_l",         EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1423   { "hw_ldq_l/a",       EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1424   { "hw_ldq_l/av",      EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1425   { "hw_ldq_l/aw",      EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1426   { "hw_ldq_l/awv",     EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1427   { "hw_ldq_l/p",       EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1428   { "hw_ldq_l/p",       EV6HWMEM(0x1B,0x3), EV6, ARG_EV6HWMEM },
1429   { "hw_ldq_l/pa",      EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1430   { "hw_ldq_l/pav",     EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1431   { "hw_ldq_l/paw",     EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1432   { "hw_ldq_l/pawv",    EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1433   { "hw_ldq_l/pv",      EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1434   { "hw_ldq_l/pw",      EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1435   { "hw_ldq_l/pwv",     EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1436   { "hw_ldq_l/v",       EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1437   { "hw_ldq_l/w",       EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1438   { "hw_ldq_l/wv",      EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1439   { "hw_ld",            EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
1440   { "hw_ld",            EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
1441   { "hw_ld/a",          EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
1442   { "hw_ld/a",          EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
1443   { "hw_ld/al",         EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1444   { "hw_ld/aq",         EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
1445   { "hw_ld/aq",         EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM },
1446   { "hw_ld/aql",        EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1447   { "hw_ld/aqv",        EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM },
1448   { "hw_ld/aqvl",       EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1449   { "hw_ld/ar",         EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
1450   { "hw_ld/arq",        EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
1451   { "hw_ld/av",         EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM },
1452   { "hw_ld/avl",        EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1453   { "hw_ld/aw",         EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM },
1454   { "hw_ld/awl",        EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1455   { "hw_ld/awq",        EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM },
1456   { "hw_ld/awql",       EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1457   { "hw_ld/awqv",       EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM },
1458   { "hw_ld/awqvl",      EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1459   { "hw_ld/awv",        EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM },
1460   { "hw_ld/awvl",       EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1461   { "hw_ld/l",          EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1462   { "hw_ld/p",          EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
1463   { "hw_ld/p",          EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM },
1464   { "hw_ld/pa",         EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
1465   { "hw_ld/pa",         EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM },
1466   { "hw_ld/pal",        EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1467   { "hw_ld/paq",        EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
1468   { "hw_ld/paq",        EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM },
1469   { "hw_ld/paql",       EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1470   { "hw_ld/paqv",       EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM },
1471   { "hw_ld/paqvl",      EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1472   { "hw_ld/par",        EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
1473   { "hw_ld/parq",       EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
1474   { "hw_ld/pav",        EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM },
1475   { "hw_ld/pavl",       EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1476   { "hw_ld/paw",        EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM },
1477   { "hw_ld/pawl",       EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1478   { "hw_ld/pawq",       EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM },
1479   { "hw_ld/pawql",      EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1480   { "hw_ld/pawqv",      EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM },
1481   { "hw_ld/pawqvl",     EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1482   { "hw_ld/pawv",       EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM },
1483   { "hw_ld/pawvl",      EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1484   { "hw_ld/pl",         EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1485   { "hw_ld/pq",         EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
1486   { "hw_ld/pq",         EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM },
1487   { "hw_ld/pql",        EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1488   { "hw_ld/pqv",        EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM },
1489   { "hw_ld/pqvl",       EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1490   { "hw_ld/pr",         EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
1491   { "hw_ld/prq",        EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
1492   { "hw_ld/pv",         EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM },
1493   { "hw_ld/pvl",        EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1494   { "hw_ld/pw",         EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM },
1495   { "hw_ld/pwl",        EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1496   { "hw_ld/pwq",        EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM },
1497   { "hw_ld/pwql",       EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1498   { "hw_ld/pwqv",       EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM },
1499   { "hw_ld/pwqvl",      EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1500   { "hw_ld/pwv",        EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM },
1501   { "hw_ld/pwvl",       EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1502   { "hw_ld/q",          EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
1503   { "hw_ld/q",          EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM },
1504   { "hw_ld/ql",         EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1505   { "hw_ld/qv",         EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM },
1506   { "hw_ld/qvl",        EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1507   { "hw_ld/r",          EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
1508   { "hw_ld/rq",         EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
1509   { "hw_ld/v",          EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM },
1510   { "hw_ld/vl",         EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1511   { "hw_ld/w",          EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM },
1512   { "hw_ld/wl",         EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1513   { "hw_ld/wq",         EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM },
1514   { "hw_ld/wql",        EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1515   { "hw_ld/wqv",        EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM },
1516   { "hw_ld/wqvl",       EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1517   { "hw_ld/wv",         EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM },
1518   { "hw_ld/wvl",        EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1519   { "pal1b",            PCD(0x1B), BASE, ARG_PCD },
1520
1521   { "sextb",            OPR(0x1C, 0x00), BWX, ARG_OPRZ1 },
1522   { "sextw",            OPR(0x1C, 0x01), BWX, ARG_OPRZ1 },
1523   { "ctpop",            OPR(0x1C, 0x30), CIX, ARG_OPRZ1 },
1524   { "perr",             OPR(0x1C, 0x31), MAX, ARG_OPR },
1525   { "ctlz",             OPR(0x1C, 0x32), CIX, ARG_OPRZ1 },
1526   { "cttz",             OPR(0x1C, 0x33), CIX, ARG_OPRZ1 },
1527   { "unpkbw",           OPR(0x1C, 0x34), MAX, ARG_OPRZ1 },
1528   { "unpkbl",           OPR(0x1C, 0x35), MAX, ARG_OPRZ1 },
1529   { "pkwb",             OPR(0x1C, 0x36), MAX, ARG_OPRZ1 },
1530   { "pklb",             OPR(0x1C, 0x37), MAX, ARG_OPRZ1 },
1531   { "minsb8",           OPR(0x1C, 0x38), MAX, ARG_OPR },
1532   { "minsb8",           OPRL(0x1C, 0x38), MAX, ARG_OPRL },
1533   { "minsw4",           OPR(0x1C, 0x39), MAX, ARG_OPR },
1534   { "minsw4",           OPRL(0x1C, 0x39), MAX, ARG_OPRL },
1535   { "minub8",           OPR(0x1C, 0x3A), MAX, ARG_OPR },
1536   { "minub8",           OPRL(0x1C, 0x3A), MAX, ARG_OPRL },
1537   { "minuw4",           OPR(0x1C, 0x3B), MAX, ARG_OPR },
1538   { "minuw4",           OPRL(0x1C, 0x3B), MAX, ARG_OPRL },
1539   { "maxub8",           OPR(0x1C, 0x3C), MAX, ARG_OPR },
1540   { "maxub8",           OPRL(0x1C, 0x3C), MAX, ARG_OPRL },
1541   { "maxuw4",           OPR(0x1C, 0x3D), MAX, ARG_OPR },
1542   { "maxuw4",           OPRL(0x1C, 0x3D), MAX, ARG_OPRL },
1543   { "maxsb8",           OPR(0x1C, 0x3E), MAX, ARG_OPR },
1544   { "maxsb8",           OPRL(0x1C, 0x3E), MAX, ARG_OPRL },
1545   { "maxsw4",           OPR(0x1C, 0x3F), MAX, ARG_OPR },
1546   { "maxsw4",           OPRL(0x1C, 0x3F), MAX, ARG_OPRL },
1547   { "ftoit",            FP(0x1C, 0x70), CIX, { FA, ZB, RC } },
1548   { "ftois",            FP(0x1C, 0x78), CIX, { FA, ZB, RC } },
1549
1550   { "hw_mtpr",          OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
1551   { "hw_mtpr",          OP(0x1D), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
1552   { "hw_mtpr",          OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } },
1553   { "hw_mtpr/i",        OPR(0x1D,0x01), EV4, ARG_EV4HWMPR },
1554   { "hw_mtpr/a",        OPR(0x1D,0x02), EV4, ARG_EV4HWMPR },
1555   { "hw_mtpr/ai",       OPR(0x1D,0x03), EV4, ARG_EV4HWMPR },
1556   { "hw_mtpr/p",        OPR(0x1D,0x04), EV4, ARG_EV4HWMPR },
1557   { "hw_mtpr/pi",       OPR(0x1D,0x05), EV4, ARG_EV4HWMPR },
1558   { "hw_mtpr/pa",       OPR(0x1D,0x06), EV4, ARG_EV4HWMPR },
1559   { "hw_mtpr/pai",      OPR(0x1D,0x07), EV4, ARG_EV4HWMPR },
1560   { "pal1d",            PCD(0x1D), BASE, ARG_PCD },
1561
1562   { "hw_rei",           SPCD(0x1E,0x3FF8000), EV4|EV5, ARG_NONE },
1563   { "hw_rei_stall",     SPCD(0x1E,0x3FFC000), EV5, ARG_NONE },
1564   { "hw_jmp",           EV6HWMBR(0x1E,0x0), EV6, { ZA, PRB, EV6HWJMPHINT } },
1565   { "hw_jsr",           EV6HWMBR(0x1E,0x2), EV6, { ZA, PRB, EV6HWJMPHINT } },
1566   { "hw_ret",           EV6HWMBR(0x1E,0x4), EV6, { ZA, PRB } },
1567   { "hw_jcr",           EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } },
1568   { "hw_coroutine",     EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, /* alias */
1569   { "hw_jmp/stall",     EV6HWMBR(0x1E,0x1), EV6, { ZA, PRB, EV6HWJMPHINT } },
1570   { "hw_jsr/stall",     EV6HWMBR(0x1E,0x3), EV6, { ZA, PRB, EV6HWJMPHINT } },
1571   { "hw_ret/stall",     EV6HWMBR(0x1E,0x5), EV6, { ZA, PRB } },
1572   { "hw_jcr/stall",     EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } },
1573   { "hw_coroutine/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, /* alias */
1574   { "pal1e",            PCD(0x1E), BASE, ARG_PCD },
1575
1576   { "hw_stl",           EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
1577   { "hw_stl",           EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM },
1578   { "hw_stl",           EV6HWMEM(0x1F,0x4), EV6, ARG_EV6HWMEM }, /* ??? 8 */
1579   { "hw_stl/a",         EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
1580   { "hw_stl/a",         EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM },
1581   { "hw_stl/a",         EV6HWMEM(0x1F,0xC), EV6, ARG_EV6HWMEM },
1582   { "hw_stl/ac",        EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1583   { "hw_stl/ar",        EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
1584   { "hw_stl/av",        EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM },
1585   { "hw_stl/avc",       EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1586   { "hw_stl/c",         EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1587   { "hw_stl/p",         EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
1588   { "hw_stl/p",         EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM },
1589   { "hw_stl/p",         EV6HWMEM(0x1F,0x0), EV6, ARG_EV6HWMEM },
1590   { "hw_stl/pa",        EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
1591   { "hw_stl/pa",        EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM },
1592   { "hw_stl/pac",       EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1593   { "hw_stl/pav",       EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM },
1594   { "hw_stl/pavc",      EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1595   { "hw_stl/pc",        EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1596   { "hw_stl/pr",        EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
1597   { "hw_stl/pv",        EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM },
1598   { "hw_stl/pvc",       EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1599   { "hw_stl/r",         EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
1600   { "hw_stl/v",         EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM },
1601   { "hw_stl/vc",        EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1602   { "hw_stl_c",         EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1603   { "hw_stl_c/a",       EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1604   { "hw_stl_c/av",      EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1605   { "hw_stl_c/p",       EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1606   { "hw_stl_c/p",       EV6HWMEM(0x1F,0x2), EV6, ARG_EV6HWMEM },
1607   { "hw_stl_c/pa",      EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1608   { "hw_stl_c/pav",     EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1609   { "hw_stl_c/pv",      EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1610   { "hw_stl_c/v",       EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1611   { "hw_stq",           EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
1612   { "hw_stq",           EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM },
1613   { "hw_stq",           EV6HWMEM(0x1F,0x5), EV6, ARG_EV6HWMEM }, /* ??? 9 */
1614   { "hw_stq/a",         EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
1615   { "hw_stq/a",         EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM },
1616   { "hw_stq/a",         EV6HWMEM(0x1F,0xD), EV6, ARG_EV6HWMEM },
1617   { "hw_stq/ac",        EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1618   { "hw_stq/ar",        EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
1619   { "hw_stq/av",        EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM },
1620   { "hw_stq/avc",       EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1621   { "hw_stq/c",         EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1622   { "hw_stq/p",         EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
1623   { "hw_stq/p",         EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM },
1624   { "hw_stq/p",         EV6HWMEM(0x1F,0x1), EV6, ARG_EV6HWMEM },
1625   { "hw_stq/pa",        EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
1626   { "hw_stq/pa",        EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM },
1627   { "hw_stq/pac",       EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1628   { "hw_stq/par",       EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
1629   { "hw_stq/par",       EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
1630   { "hw_stq/pav",       EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM },
1631   { "hw_stq/pavc",      EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1632   { "hw_stq/pc",        EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1633   { "hw_stq/pr",        EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
1634   { "hw_stq/pv",        EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM },
1635   { "hw_stq/pvc",       EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1636   { "hw_stq/r",         EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM },
1637   { "hw_stq/v",         EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM },
1638   { "hw_stq/vc",        EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1639   { "hw_stq_c",         EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1640   { "hw_stq_c/a",       EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1641   { "hw_stq_c/av",      EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1642   { "hw_stq_c/p",       EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1643   { "hw_stq_c/p",       EV6HWMEM(0x1F,0x3), EV6, ARG_EV6HWMEM },
1644   { "hw_stq_c/pa",      EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1645   { "hw_stq_c/pav",     EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1646   { "hw_stq_c/pv",      EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1647   { "hw_stq_c/v",       EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1648   { "hw_st",            EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
1649   { "hw_st",            EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM },
1650   { "hw_st/a",          EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
1651   { "hw_st/a",          EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM },
1652   { "hw_st/ac",         EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1653   { "hw_st/aq",         EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
1654   { "hw_st/aq",         EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM },
1655   { "hw_st/aqc",        EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1656   { "hw_st/aqv",        EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM },
1657   { "hw_st/aqvc",       EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1658   { "hw_st/ar",         EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
1659   { "hw_st/arq",        EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
1660   { "hw_st/av",         EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM },
1661   { "hw_st/avc",        EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1662   { "hw_st/c",          EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1663   { "hw_st/p",          EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
1664   { "hw_st/p",          EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM },
1665   { "hw_st/pa",         EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
1666   { "hw_st/pa",         EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM },
1667   { "hw_st/pac",        EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1668   { "hw_st/paq",        EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
1669   { "hw_st/paq",        EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM },
1670   { "hw_st/paqc",       EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1671   { "hw_st/paqv",       EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM },
1672   { "hw_st/paqvc",      EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1673   { "hw_st/par",        EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
1674   { "hw_st/parq",       EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
1675   { "hw_st/pav",        EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM },
1676   { "hw_st/pavc",       EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1677   { "hw_st/pc",         EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1678   { "hw_st/pq",         EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
1679   { "hw_st/pq",         EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM },
1680   { "hw_st/pqc",        EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1681   { "hw_st/pqv",        EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM },
1682   { "hw_st/pqvc",       EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1683   { "hw_st/pr",         EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
1684   { "hw_st/prq",        EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
1685   { "hw_st/pv",         EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM },
1686   { "hw_st/pvc",        EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1687   { "hw_st/q",          EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
1688   { "hw_st/q",          EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM },
1689   { "hw_st/qc",         EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1690   { "hw_st/qv",         EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM },
1691   { "hw_st/qvc",        EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1692   { "hw_st/r",          EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
1693   { "hw_st/v",          EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM },
1694   { "hw_st/vc",         EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1695   { "pal1f",            PCD(0x1F), BASE, ARG_PCD },
1696
1697   { "ldf",              MEM(0x20), BASE, ARG_FMEM },
1698   { "ldg",              MEM(0x21), BASE, ARG_FMEM },
1699   { "lds",              MEM(0x22), BASE, ARG_FMEM },
1700   { "ldt",              MEM(0x23), BASE, ARG_FMEM },
1701   { "stf",              MEM(0x24), BASE, ARG_FMEM },
1702   { "stg",              MEM(0x25), BASE, ARG_FMEM },
1703   { "sts",              MEM(0x26), BASE, ARG_FMEM },
1704   { "stt",              MEM(0x27), BASE, ARG_FMEM },
1705
1706   { "ldl",              MEM(0x28), BASE, ARG_MEM },
1707   { "ldq",              MEM(0x29), BASE, ARG_MEM },
1708   { "ldl_l",            MEM(0x2A), BASE, ARG_MEM },
1709   { "ldq_l",            MEM(0x2B), BASE, ARG_MEM },
1710   { "stl",              MEM(0x2C), BASE, ARG_MEM },
1711   { "stq",              MEM(0x2D), BASE, ARG_MEM },
1712   { "stl_c",            MEM(0x2E), BASE, ARG_MEM },
1713   { "stq_c",            MEM(0x2F), BASE, ARG_MEM },
1714
1715   { "br",               BRA(0x30), BASE, { ZA, BDISP } },       /* pseudo */
1716   { "br",               BRA(0x30), BASE, ARG_BRA },
1717   { "fbeq",             BRA(0x31), BASE, ARG_FBRA },
1718   { "fblt",             BRA(0x32), BASE, ARG_FBRA },
1719   { "fble",             BRA(0x33), BASE, ARG_FBRA },
1720   { "bsr",              BRA(0x34), BASE, ARG_BRA },
1721   { "fbne",             BRA(0x35), BASE, ARG_FBRA },
1722   { "fbge",             BRA(0x36), BASE, ARG_FBRA },
1723   { "fbgt",             BRA(0x37), BASE, ARG_FBRA },
1724   { "blbc",             BRA(0x38), BASE, ARG_BRA },
1725   { "beq",              BRA(0x39), BASE, ARG_BRA },
1726   { "blt",              BRA(0x3A), BASE, ARG_BRA },
1727   { "ble",              BRA(0x3B), BASE, ARG_BRA },
1728   { "blbs",             BRA(0x3C), BASE, ARG_BRA },
1729   { "bne",              BRA(0x3D), BASE, ARG_BRA },
1730   { "bge",              BRA(0x3E), BASE, ARG_BRA },
1731   { "bgt",              BRA(0x3F), BASE, ARG_BRA },
1732 };
1733
1734 const unsigned alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes);
1735
1736 /* OSF register names.  */
1737
1738 static const char * const osf_regnames[64] = {
1739   "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
1740   "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",
1741   "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
1742   "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero",
1743   "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
1744   "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
1745   "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
1746   "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
1747 };
1748
1749 /* VMS register names.  */
1750
1751 static const char * const vms_regnames[64] = {
1752   "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
1753   "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
1754   "R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23",
1755   "R24", "AI", "RA", "PV", "AT", "FP", "SP", "RZ",
1756   "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7",
1757   "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15",
1758   "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23",
1759   "F24", "F25", "F26", "F27", "F28", "F29", "F30", "FZ"
1760 };
1761
1762 /* Disassemble Alpha instructions.  */
1763
1764 int
1765 print_insn_alpha (bfd_vma memaddr, struct disassemble_info *info)
1766 {
1767   static const struct alpha_opcode *opcode_index[AXP_NOPS+1];
1768   const char * const * regnames;
1769   const struct alpha_opcode *opcode, *opcode_end;
1770   const unsigned char *opindex;
1771   unsigned insn, op, isa_mask;
1772   int need_comma;
1773
1774   /* Initialize the majorop table the first time through */
1775   if (!opcode_index[0])
1776     {
1777       opcode = alpha_opcodes;
1778       opcode_end = opcode + alpha_num_opcodes;
1779
1780       for (op = 0; op < AXP_NOPS; ++op)
1781         {
1782           opcode_index[op] = opcode;
1783           while (opcode < opcode_end && op == AXP_OP (opcode->opcode))
1784             ++opcode;
1785         }
1786       opcode_index[op] = opcode;
1787     }
1788
1789   if (info->flavour == bfd_target_evax_flavour)
1790     regnames = vms_regnames;
1791   else
1792     regnames = osf_regnames;
1793
1794   isa_mask = AXP_OPCODE_NOPAL;
1795   switch (info->mach)
1796     {
1797     case bfd_mach_alpha_ev4:
1798       isa_mask |= AXP_OPCODE_EV4;
1799       break;
1800     case bfd_mach_alpha_ev5:
1801       isa_mask |= AXP_OPCODE_EV5;
1802       break;
1803     case bfd_mach_alpha_ev6:
1804       isa_mask |= AXP_OPCODE_EV6;
1805       break;
1806     }
1807
1808   /* Read the insn into a host word */
1809   {
1810     bfd_byte buffer[4];
1811     int status = (*info->read_memory_func) (memaddr, buffer, 4, info);
1812     if (status != 0)
1813       {
1814         (*info->memory_error_func) (status, memaddr, info);
1815         return -1;
1816       }
1817     insn = bfd_getl32 (buffer);
1818   }
1819
1820   /* Get the major opcode of the instruction.  */
1821   op = AXP_OP (insn);
1822
1823   /* Find the first match in the opcode table.  */
1824   opcode_end = opcode_index[op + 1];
1825   for (opcode = opcode_index[op]; opcode < opcode_end; ++opcode)
1826     {
1827       if ((insn ^ opcode->opcode) & opcode->mask)
1828         continue;
1829
1830       if (!(opcode->flags & isa_mask))
1831         continue;
1832
1833       /* Make two passes over the operands.  First see if any of them
1834          have extraction functions, and, if they do, make sure the
1835          instruction is valid.  */
1836       {
1837         int invalid = 0;
1838         for (opindex = opcode->operands; *opindex != 0; opindex++)
1839           {
1840             const struct alpha_operand *operand = alpha_operands + *opindex;
1841             if (operand->extract)
1842               (*operand->extract) (insn, &invalid);
1843           }
1844         if (invalid)
1845           continue;
1846       }
1847
1848       /* The instruction is valid.  */
1849       goto found;
1850     }
1851
1852   /* No instruction found */
1853   (*info->fprintf_func) (info->stream, ".long %#08x", insn);
1854
1855   return 4;
1856
1857 found:
1858   (*info->fprintf_func) (info->stream, "%s", opcode->name);
1859   if (opcode->operands[0] != 0)
1860     (*info->fprintf_func) (info->stream, "\t");
1861
1862   /* Now extract and print the operands.  */
1863   need_comma = 0;
1864   for (opindex = opcode->operands; *opindex != 0; opindex++)
1865     {
1866       const struct alpha_operand *operand = alpha_operands + *opindex;
1867       int value;
1868
1869       /* Operands that are marked FAKE are simply ignored.  We
1870          already made sure that the extract function considered
1871          the instruction to be valid.  */
1872       if ((operand->flags & AXP_OPERAND_FAKE) != 0)
1873         continue;
1874
1875       /* Extract the value from the instruction.  */
1876       if (operand->extract)
1877         value = (*operand->extract) (insn, (int *) NULL);
1878       else
1879         {
1880           value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
1881           if (operand->flags & AXP_OPERAND_SIGNED)
1882             {
1883               int signbit = 1 << (operand->bits - 1);
1884               value = (value ^ signbit) - signbit;
1885             }
1886         }
1887
1888       if (need_comma &&
1889           ((operand->flags & (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA))
1890            != AXP_OPERAND_PARENS))
1891         {
1892           (*info->fprintf_func) (info->stream, ",");
1893         }
1894       if (operand->flags & AXP_OPERAND_PARENS)
1895         (*info->fprintf_func) (info->stream, "(");
1896
1897       /* Print the operand as directed by the flags.  */
1898       if (operand->flags & AXP_OPERAND_IR)
1899         (*info->fprintf_func) (info->stream, "%s", regnames[value]);
1900       else if (operand->flags & AXP_OPERAND_FPR)
1901         (*info->fprintf_func) (info->stream, "%s", regnames[value + 32]);
1902       else if (operand->flags & AXP_OPERAND_RELATIVE)
1903         (*info->print_address_func) (memaddr + 4 + value, info);
1904       else if (operand->flags & AXP_OPERAND_SIGNED)
1905         (*info->fprintf_func) (info->stream, "%d", value);
1906       else
1907         (*info->fprintf_func) (info->stream, "%#x", value);
1908
1909       if (operand->flags & AXP_OPERAND_PARENS)
1910         (*info->fprintf_func) (info->stream, ")");
1911       need_comma = 1;
1912     }
1913
1914   return 4;
1915 }