xlnx-zynqmp-rtc: Initial commit
[qemu/ar7.git] / include / hw / timer / xlnx-zynqmp-rtc.h
blob87649836cc05c72138183f7f66c4520deb7c4c69
1 /*
2 * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC).
4 * Copyright (c) 2017 Xilinx Inc.
6 * Written-by: Alistair Francis <alistair.francis@xilinx.com>
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
27 #include "hw/register.h"
29 #define TYPE_XLNX_ZYNQMP_RTC "xlnx-zynmp.rtc"
31 #define XLNX_ZYNQMP_RTC(obj) \
32 OBJECT_CHECK(XlnxZynqMPRTC, (obj), TYPE_XLNX_ZYNQMP_RTC)
34 REG32(SET_TIME_WRITE, 0x0)
35 REG32(SET_TIME_READ, 0x4)
36 REG32(CALIB_WRITE, 0x8)
37 FIELD(CALIB_WRITE, FRACTION_EN, 20, 1)
38 FIELD(CALIB_WRITE, FRACTION_DATA, 16, 4)
39 FIELD(CALIB_WRITE, MAX_TICK, 0, 16)
40 REG32(CALIB_READ, 0xc)
41 FIELD(CALIB_READ, FRACTION_EN, 20, 1)
42 FIELD(CALIB_READ, FRACTION_DATA, 16, 4)
43 FIELD(CALIB_READ, MAX_TICK, 0, 16)
44 REG32(CURRENT_TIME, 0x10)
45 REG32(CURRENT_TICK, 0x14)
46 FIELD(CURRENT_TICK, VALUE, 0, 16)
47 REG32(ALARM, 0x18)
48 REG32(RTC_INT_STATUS, 0x20)
49 FIELD(RTC_INT_STATUS, ALARM, 1, 1)
50 FIELD(RTC_INT_STATUS, SECONDS, 0, 1)
51 REG32(RTC_INT_MASK, 0x24)
52 FIELD(RTC_INT_MASK, ALARM, 1, 1)
53 FIELD(RTC_INT_MASK, SECONDS, 0, 1)
54 REG32(RTC_INT_EN, 0x28)
55 FIELD(RTC_INT_EN, ALARM, 1, 1)
56 FIELD(RTC_INT_EN, SECONDS, 0, 1)
57 REG32(RTC_INT_DIS, 0x2c)
58 FIELD(RTC_INT_DIS, ALARM, 1, 1)
59 FIELD(RTC_INT_DIS, SECONDS, 0, 1)
60 REG32(ADDR_ERROR, 0x30)
61 FIELD(ADDR_ERROR, STATUS, 0, 1)
62 REG32(ADDR_ERROR_INT_MASK, 0x34)
63 FIELD(ADDR_ERROR_INT_MASK, MASK, 0, 1)
64 REG32(ADDR_ERROR_INT_EN, 0x38)
65 FIELD(ADDR_ERROR_INT_EN, MASK, 0, 1)
66 REG32(ADDR_ERROR_INT_DIS, 0x3c)
67 FIELD(ADDR_ERROR_INT_DIS, MASK, 0, 1)
68 REG32(CONTROL, 0x40)
69 FIELD(CONTROL, BATTERY_DISABLE, 31, 1)
70 FIELD(CONTROL, OSC_CNTRL, 24, 4)
71 FIELD(CONTROL, SLVERR_ENABLE, 0, 1)
72 REG32(SAFETY_CHK, 0x50)
74 #define XLNX_ZYNQMP_RTC_R_MAX (R_SAFETY_CHK + 1)
76 typedef struct XlnxZynqMPRTC {
77 SysBusDevice parent_obj;
78 MemoryRegion iomem;
79 qemu_irq irq_rtc_int;
80 qemu_irq irq_addr_error_int;
82 uint32_t regs[XLNX_ZYNQMP_RTC_R_MAX];
83 RegisterInfo regs_info[XLNX_ZYNQMP_RTC_R_MAX];
84 } XlnxZynqMPRTC;