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Merge tag 'v5.2.0-rc1'
[qemu/ar7.git] / target / mips / op_helper.c
blobfad3342be3364796207748e936c5e7256d06d07d
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 *
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/main-loop.h"
23 #include "cpu.h"
24 #include "internal.h"
25 #include "qemu/host-utils.h"
26 #include "exec/helper-proto.h"
27 #include "exec/exec-all.h"
28 #include "exec/cpu_ldst.h"
29 #include "exec/memop.h"
30 #include "sysemu/kvm.h"
31
32
33 /*****************************************************************************/
34 /* Exceptions processing helpers */
35
36 QEMU_NORETURN
37 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
38 int error_code)
39 {
40 do_raise_exception_err(env, exception, error_code, 0);
41 }
42
43 QEMU_NORETURN
44 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
45 {
46 do_raise_exception(env, exception, GETPC());
47 }
48
49 QEMU_NORETURN void helper_raise_exception_debug(CPUMIPSState *env)
50 {
51 do_raise_exception(env, EXCP_DEBUG, 0);
52 }
53
54 static QEMU_NORETURN
55 void raise_exception(CPUMIPSState *env, uint32_t exception)
56 {
57 do_raise_exception(env, exception, 0);
58 }
59
60 /* 64 bits arithmetic for 32 bits hosts */
61 static inline uint64_t get_HILO(CPUMIPSState *env)
62 {
63 return ((uint64_t)(env->active_tc.HI[0]) << 32) |
64 (uint32_t)env->active_tc.LO[0];
65 }
66
67 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
68 {
69 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
70 return env->active_tc.HI[0] = (int32_t)(HILO >> 32);
71 }
72
73 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
74 {
75 target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
76 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
77 return tmp;
78 }
79
80 /* Multiplication variants of the vr54xx. */
81 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
82 target_ulong arg2)
83 {
84 return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
85 (int64_t)(int32_t)arg2));
86 }
87
88 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
89 target_ulong arg2)
90 {
91 return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
92 (uint64_t)(uint32_t)arg2);
93 }
94
95 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
96 target_ulong arg2)
97 {
98 return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
99 (int64_t)(int32_t)arg2);
100 }
101
102 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
103 target_ulong arg2)
104 {
105 return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
106 (int64_t)(int32_t)arg2);
107 }
108
109 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
110 target_ulong arg2)
111 {
112 return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
113 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
114 }
115
116 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
117 target_ulong arg2)
118 {
119 return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
120 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
121 }
122
123 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
124 target_ulong arg2)
125 {
126 return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
127 (int64_t)(int32_t)arg2);
128 }
129
130 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
131 target_ulong arg2)
132 {
133 return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
134 (int64_t)(int32_t)arg2);
135 }
136
137 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
138 target_ulong arg2)
139 {
140 return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
141 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
142 }
143
144 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
145 target_ulong arg2)
146 {
147 return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
148 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
149 }
150
151 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
152 target_ulong arg2)
153 {
154 return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
155 }
156
157 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
158 target_ulong arg2)
159 {
160 return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
161 (uint64_t)(uint32_t)arg2);
162 }
163
164 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
165 target_ulong arg2)
166 {
167 return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
168 (int64_t)(int32_t)arg2);
169 }
170
171 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
172 target_ulong arg2)
173 {
174 return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
175 (uint64_t)(uint32_t)arg2);
176 }
177
178 static inline target_ulong bitswap(target_ulong v)
179 {
180 v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
181 ((v & (target_ulong)0x5555555555555555ULL) << 1);
182 v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
183 ((v & (target_ulong)0x3333333333333333ULL) << 2);
184 v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
185 ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
186 return v;
187 }
188
189 #ifdef TARGET_MIPS64
190 target_ulong helper_dbitswap(target_ulong rt)
191 {
192 return bitswap(rt);
193 }
194 #endif
195
196 target_ulong helper_bitswap(target_ulong rt)
197 {
198 return (int32_t)bitswap(rt);
199 }
200
201 target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx,
202 uint32_t stripe)
203 {
204 int i;
205 uint64_t tmp0 = ((uint64_t)rs) << 32 | ((uint64_t)rs & 0xffffffff);
206 uint64_t tmp1 = tmp0;
207 for (i = 0; i <= 46; i++) {
208 int s;
209 if (i & 0x8) {
210 s = shift;
211 } else {
212 s = shiftx;
213 }
214
215 if (stripe != 0 && !(i & 0x4)) {
216 s = ~s;
217 }
218 if (s & 0x10) {
219 if (tmp0 & (1LL << (i + 16))) {
220 tmp1 |= 1LL << i;
221 } else {
222 tmp1 &= ~(1LL << i);
223 }
224 }
225 }
226
227 uint64_t tmp2 = tmp1;
228 for (i = 0; i <= 38; i++) {
229 int s;
230 if (i & 0x4) {
231 s = shift;
232 } else {
233 s = shiftx;
234 }
235
236 if (s & 0x8) {
237 if (tmp1 & (1LL << (i + 8))) {
238 tmp2 |= 1LL << i;
239 } else {
240 tmp2 &= ~(1LL << i);
241 }
242 }
243 }
244
245 uint64_t tmp3 = tmp2;
246 for (i = 0; i <= 34; i++) {
247 int s;
248 if (i & 0x2) {
249 s = shift;
250 } else {
251 s = shiftx;
252 }
253 if (s & 0x4) {
254 if (tmp2 & (1LL << (i + 4))) {
255 tmp3 |= 1LL << i;
256 } else {
257 tmp3 &= ~(1LL << i);
258 }
259 }
260 }
261
262 uint64_t tmp4 = tmp3;
263 for (i = 0; i <= 32; i++) {
264 int s;
265 if (i & 0x1) {
266 s = shift;
267 } else {
268 s = shiftx;
269 }
270 if (s & 0x2) {
271 if (tmp3 & (1LL << (i + 2))) {
272 tmp4 |= 1LL << i;
273 } else {
274 tmp4 &= ~(1LL << i);
275 }
276 }
277 }
278
279 uint64_t tmp5 = tmp4;
280 for (i = 0; i <= 31; i++) {
281 int s;
282 s = shift;
283 if (s & 0x1) {
284 if (tmp4 & (1LL << (i + 1))) {
285 tmp5 |= 1LL << i;
286 } else {
287 tmp5 &= ~(1LL << i);
288 }
289 }
290 }
291
292 return (int64_t)(int32_t)(uint32_t)tmp5;
293 }
294
295 #ifndef CONFIG_USER_ONLY
296
297 static inline hwaddr do_translate_address(CPUMIPSState *env,
298 target_ulong address,
299 int rw, uintptr_t retaddr)
300 {
301 hwaddr paddr;
302 CPUState *cs = env_cpu(env);
303
304 paddr = cpu_mips_translate_address(env, address, rw);
305
306 if (paddr == -1LL) {
307 cpu_loop_exit_restore(cs, retaddr);
308 } else {
309 return paddr;
310 }
311 }
312
313 #define HELPER_LD_ATOMIC(name, insn, almask, do_cast) \
314 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
315 { \
316 if (arg & almask) { \
317 if (!(env->hflags & MIPS_HFLAG_DM)) { \
318 env->CP0_BadVAddr = arg; \
319 } \
320 do_raise_exception(env, EXCP_AdEL, GETPC()); \
321 } \
322 env->CP0_LLAddr = do_translate_address(env, arg, 0, GETPC()); \
323 env->lladdr = arg; \
324 env->llval = do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC()); \
325 return env->llval; \
326 }
327 HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t))
328 #ifdef TARGET_MIPS64
329 HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong))
330 #endif
331 #undef HELPER_LD_ATOMIC
332 #endif
333
334 #ifdef TARGET_WORDS_BIGENDIAN
335 #define GET_LMASK(v) ((v) & 3)
336 #define GET_OFFSET(addr, offset) (addr + (offset))
337 #else
338 #define GET_LMASK(v) (((v) & 3) ^ 3)
339 #define GET_OFFSET(addr, offset) (addr - (offset))
340 #endif
341
342 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
343 int mem_idx)
344 {
345 cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
346
347 if (GET_LMASK(arg2) <= 2) {
348 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16),
349 mem_idx, GETPC());
350 }
351
352 if (GET_LMASK(arg2) <= 1) {
353 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8),
354 mem_idx, GETPC());
355 }
356
357 if (GET_LMASK(arg2) == 0) {
358 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1,
359 mem_idx, GETPC());
360 }
361 }
362
363 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
364 int mem_idx)
365 {
366 cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
367
368 if (GET_LMASK(arg2) >= 1) {
369 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8),
370 mem_idx, GETPC());
371 }
372
373 if (GET_LMASK(arg2) >= 2) {
374 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16),
375 mem_idx, GETPC());
376 }
377
378 if (GET_LMASK(arg2) == 3) {
379 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24),
380 mem_idx, GETPC());
381 }
382 }
383
384 #if defined(TARGET_MIPS64)
385 /*
386 * "half" load and stores. We must do the memory access inline,
387 * or fault handling won't work.
388 */
389 #ifdef TARGET_WORDS_BIGENDIAN
390 #define GET_LMASK64(v) ((v) & 7)
391 #else
392 #define GET_LMASK64(v) (((v) & 7) ^ 7)
393 #endif
394
395 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
396 int mem_idx)
397 {
398 cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
399
400 if (GET_LMASK64(arg2) <= 6) {
401 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48),
402 mem_idx, GETPC());
403 }
404
405 if (GET_LMASK64(arg2) <= 5) {
406 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40),
407 mem_idx, GETPC());
408 }
409
410 if (GET_LMASK64(arg2) <= 4) {
411 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32),
412 mem_idx, GETPC());
413 }
414
415 if (GET_LMASK64(arg2) <= 3) {
416 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24),
417 mem_idx, GETPC());
418 }
419
420 if (GET_LMASK64(arg2) <= 2) {
421 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16),
422 mem_idx, GETPC());
423 }
424
425 if (GET_LMASK64(arg2) <= 1) {
426 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8),
427 mem_idx, GETPC());
428 }
429
430 if (GET_LMASK64(arg2) <= 0) {
431 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 7), (uint8_t)arg1,
432 mem_idx, GETPC());
433 }
434 }
435
436 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
437 int mem_idx)
438 {
439 cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
440
441 if (GET_LMASK64(arg2) >= 1) {
442 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8),
443 mem_idx, GETPC());
444 }
445
446 if (GET_LMASK64(arg2) >= 2) {
447 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16),
448 mem_idx, GETPC());
449 }
450
451 if (GET_LMASK64(arg2) >= 3) {
452 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24),
453 mem_idx, GETPC());
454 }
455
456 if (GET_LMASK64(arg2) >= 4) {
457 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32),
458 mem_idx, GETPC());
459 }
460
461 if (GET_LMASK64(arg2) >= 5) {
462 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40),
463 mem_idx, GETPC());
464 }
465
466 if (GET_LMASK64(arg2) >= 6) {
467 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48),
468 mem_idx, GETPC());
469 }
470
471 if (GET_LMASK64(arg2) == 7) {
472 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56),
473 mem_idx, GETPC());
474 }
475 }
476 #endif /* TARGET_MIPS64 */
477
478 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
479
480 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
481 uint32_t mem_idx)
482 {
483 target_ulong base_reglist = reglist & 0xf;
484 target_ulong do_r31 = reglist & 0x10;
485
486 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
487 target_ulong i;
488
489 for (i = 0; i < base_reglist; i++) {
490 env->active_tc.gpr[multiple_regs[i]] =
491 (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());
492 addr += 4;
493 }
494 }
495
496 if (do_r31) {
497 env->active_tc.gpr[31] =
498 (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());
499 }
500 }
501
502 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
503 uint32_t mem_idx)
504 {
505 target_ulong base_reglist = reglist & 0xf;
506 target_ulong do_r31 = reglist & 0x10;
507
508 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
509 target_ulong i;
510
511 for (i = 0; i < base_reglist; i++) {
512 cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],
513 mem_idx, GETPC());
514 addr += 4;
515 }
516 }
517
518 if (do_r31) {
519 cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
520 }
521 }
522
523 #if defined(TARGET_MIPS64)
524 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
525 uint32_t mem_idx)
526 {
527 target_ulong base_reglist = reglist & 0xf;
528 target_ulong do_r31 = reglist & 0x10;
529
530 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
531 target_ulong i;
532
533 for (i = 0; i < base_reglist; i++) {
534 env->active_tc.gpr[multiple_regs[i]] =
535 cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC());
536 addr += 8;
537 }
538 }
539
540 if (do_r31) {
541 env->active_tc.gpr[31] =
542 cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC());
543 }
544 }
545
546 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
547 uint32_t mem_idx)
548 {
549 target_ulong base_reglist = reglist & 0xf;
550 target_ulong do_r31 = reglist & 0x10;
551
552 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
553 target_ulong i;
554
555 for (i = 0; i < base_reglist; i++) {
556 cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],
557 mem_idx, GETPC());
558 addr += 8;
559 }
560 }
561
562 if (do_r31) {
563 cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
564 }
565 }
566 #endif
567
568
569 void helper_fork(target_ulong arg1, target_ulong arg2)
570 {
571 /*
572 * arg1 = rt, arg2 = rs
573 * TODO: store to TC register
574 */
575 }
576
577 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
578 {
579 target_long arg1 = arg;
580
581 if (arg1 < 0) {
582 /* No scheduling policy implemented. */
583 if (arg1 != -2) {
584 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
585 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
586 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
587 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
588 do_raise_exception(env, EXCP_THREAD, GETPC());
589 }
590 }
591 } else if (arg1 == 0) {
592 if (0) {
593 /* TODO: TC underflow */
594 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
595 do_raise_exception(env, EXCP_THREAD, GETPC());
596 } else {
597 /* TODO: Deallocate TC */
598 }
599 } else if (arg1 > 0) {
600 /* Yield qualifier inputs not implemented. */
601 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
602 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
603 do_raise_exception(env, EXCP_THREAD, GETPC());
604 }
605 return env->CP0_YQMask;
606 }
607
608 #ifndef CONFIG_USER_ONLY
609 /* TLB management */
610 static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first)
611 {
612 /* Discard entries from env->tlb[first] onwards. */
613 while (env->tlb->tlb_in_use > first) {
614 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
615 }
616 }
617
618 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
619 {
620 #if defined(TARGET_MIPS64)
621 return extract64(entrylo, 6, 54);
622 #else
623 return extract64(entrylo, 6, 24) | /* PFN */
624 (extract64(entrylo, 32, 32) << 24); /* PFNX */
625 #endif
626 }
627
628 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
629 {
630 r4k_tlb_t *tlb;
631 uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1);
632
633 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
634 tlb = &env->tlb->mmu.r4k.tlb[idx];
635 if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
636 tlb->EHINV = 1;
637 return;
638 }
639 tlb->EHINV = 0;
640 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
641 #if defined(TARGET_MIPS64)
642 tlb->VPN &= env->SEGMask;
643 #endif
644 tlb->ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
645 tlb->MMID = env->CP0_MemoryMapID;
646 tlb->PageMask = env->CP0_PageMask;
647 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
648 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
649 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
650 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
651 tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
652 tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
653 tlb->PFN[0] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) << 12;
654 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
655 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
656 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
657 tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
658 tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
659 tlb->PFN[1] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) << 12;
660 }
661
662 void r4k_helper_tlbinv(CPUMIPSState *env)
663 {
664 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
665 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
666 uint32_t MMID = env->CP0_MemoryMapID;
667 uint32_t tlb_mmid;
668 r4k_tlb_t *tlb;
669 int idx;
670
671 MMID = mi ? MMID : (uint32_t) ASID;
672 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
673 tlb = &env->tlb->mmu.r4k.tlb[idx];
674 tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID;
675 if (!tlb->G && tlb_mmid == MMID) {
676 tlb->EHINV = 1;
677 }
678 }
679 cpu_mips_tlb_flush(env);
680 }
681
682 void r4k_helper_tlbinvf(CPUMIPSState *env)
683 {
684 int idx;
685
686 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
687 env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
688 }
689 cpu_mips_tlb_flush(env);
690 }
691
692 void r4k_helper_tlbwi(CPUMIPSState *env)
693 {
694 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
695 target_ulong VPN;
696 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
697 uint32_t MMID = env->CP0_MemoryMapID;
698 uint32_t tlb_mmid;
699 bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1;
700 r4k_tlb_t *tlb;
701 int idx;
702
703 MMID = mi ? MMID : (uint32_t) ASID;
704
705 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
706 tlb = &env->tlb->mmu.r4k.tlb[idx];
707 VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
708 #if defined(TARGET_MIPS64)
709 VPN &= env->SEGMask;
710 #endif
711 EHINV = (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) != 0;
712 G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
713 V0 = (env->CP0_EntryLo0 & 2) != 0;
714 D0 = (env->CP0_EntryLo0 & 4) != 0;
715 XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) &1;
716 RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) &1;
717 V1 = (env->CP0_EntryLo1 & 2) != 0;
718 D1 = (env->CP0_EntryLo1 & 4) != 0;
719 XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) &1;
720 RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) &1;
721
722 tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID;
723 /*
724 * Discard cached TLB entries, unless tlbwi is just upgrading access
725 * permissions on the current entry.
726 */
727 if (tlb->VPN != VPN || tlb_mmid != MMID || tlb->G != G ||
728 (!tlb->EHINV && EHINV) ||
729 (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
730 (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) ||
731 (tlb->V1 && !V1) || (tlb->D1 && !D1) ||
732 (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) {
733 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
734 }
735
736 r4k_invalidate_tlb(env, idx, 0);
737 r4k_fill_tlb(env, idx);
738 }
739
740 void r4k_helper_tlbwr(CPUMIPSState *env)
741 {
742 int r = cpu_mips_get_random(env);
743
744 r4k_invalidate_tlb(env, r, 1);
745 r4k_fill_tlb(env, r);
746 }
747
748 void r4k_helper_tlbp(CPUMIPSState *env)
749 {
750 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
751 r4k_tlb_t *tlb;
752 target_ulong mask;
753 target_ulong tag;
754 target_ulong VPN;
755 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
756 uint32_t MMID = env->CP0_MemoryMapID;
757 uint32_t tlb_mmid;
758 int i;
759
760 MMID = mi ? MMID : (uint32_t) ASID;
761 for (i = 0; i < env->tlb->nb_tlb; i++) {
762 tlb = &env->tlb->mmu.r4k.tlb[i];
763 /* 1k pages are not supported. */
764 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
765 tag = env->CP0_EntryHi & ~mask;
766 VPN = tlb->VPN & ~mask;
767 #if defined(TARGET_MIPS64)
768 tag &= env->SEGMask;
769 #endif
770 tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID;
771 /* Check ASID/MMID, virtual page number & size */
772 if ((tlb->G == 1 || tlb_mmid == MMID) && VPN == tag && !tlb->EHINV) {
773 /* TLB match */
774 env->CP0_Index = i;
775 break;
776 }
777 }
778 if (i == env->tlb->nb_tlb) {
779 /* No match. Discard any shadow entries, if any of them match. */
780 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
781 tlb = &env->tlb->mmu.r4k.tlb[i];
782 /* 1k pages are not supported. */
783 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
784 tag = env->CP0_EntryHi & ~mask;
785 VPN = tlb->VPN & ~mask;
786 #if defined(TARGET_MIPS64)
787 tag &= env->SEGMask;
788 #endif
789 tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID;
790 /* Check ASID/MMID, virtual page number & size */
791 if ((tlb->G == 1 || tlb_mmid == MMID) && VPN == tag) {
792 r4k_mips_tlb_flush_extra(env, i);
793 break;
794 }
795 }
796
797 env->CP0_Index |= 0x80000000;
798 }
799 }
800
801 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
802 {
803 #if defined(TARGET_MIPS64)
804 return tlb_pfn << 6;
805 #else
806 return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
807 (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
808 #endif
809 }
810
811 void r4k_helper_tlbr(CPUMIPSState *env)
812 {
813 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
814 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
815 uint32_t MMID = env->CP0_MemoryMapID;
816 uint32_t tlb_mmid;
817 r4k_tlb_t *tlb;
818 int idx;
819
820 MMID = mi ? MMID : (uint32_t) ASID;
821 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
822 tlb = &env->tlb->mmu.r4k.tlb[idx];
823
824 tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID;
825 /* If this will change the current ASID/MMID, flush qemu's TLB. */
826 if (MMID != tlb_mmid) {
827 cpu_mips_tlb_flush(env);
828 }
829
830 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
831
832 if (tlb->EHINV) {
833 env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
834 env->CP0_PageMask = 0;
835 env->CP0_EntryLo0 = 0;
836 env->CP0_EntryLo1 = 0;
837 } else {
838 env->CP0_EntryHi = mi ? tlb->VPN : tlb->VPN | tlb->ASID;
839 env->CP0_MemoryMapID = tlb->MMID;
840 env->CP0_PageMask = tlb->PageMask;
841 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
842 ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
843 ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
844 get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
845 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
846 ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
847 ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
848 get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
849 }
850 }
851
852 void helper_tlbwi(CPUMIPSState *env)
853 {
854 env->tlb->helper_tlbwi(env);
855 }
856
857 void helper_tlbwr(CPUMIPSState *env)
858 {
859 env->tlb->helper_tlbwr(env);
860 }
861
862 void helper_tlbp(CPUMIPSState *env)
863 {
864 env->tlb->helper_tlbp(env);
865 }
866
867 void helper_tlbr(CPUMIPSState *env)
868 {
869 env->tlb->helper_tlbr(env);
870 }
871
872 void helper_tlbinv(CPUMIPSState *env)
873 {
874 env->tlb->helper_tlbinv(env);
875 }
876
877 void helper_tlbinvf(CPUMIPSState *env)
878 {
879 env->tlb->helper_tlbinvf(env);
880 }
881
882 static void global_invalidate_tlb(CPUMIPSState *env,
883 uint32_t invMsgVPN2,
884 uint8_t invMsgR,
885 uint32_t invMsgMMid,
886 bool invAll,
887 bool invVAMMid,
888 bool invMMid,
889 bool invVA)
890 {
891
892 int idx;
893 r4k_tlb_t *tlb;
894 bool VAMatch;
895 bool MMidMatch;
896
897 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
898 tlb = &env->tlb->mmu.r4k.tlb[idx];
899 VAMatch =
900 (((tlb->VPN & ~tlb->PageMask) == (invMsgVPN2 & ~tlb->PageMask))
901 #ifdef TARGET_MIPS64
902 &&
903 (extract64(env->CP0_EntryHi, 62, 2) == invMsgR)
904 #endif
905 );
906 MMidMatch = tlb->MMID == invMsgMMid;
907 if ((invAll && (idx > env->CP0_Wired)) ||
908 (VAMatch && invVAMMid && (tlb->G || MMidMatch)) ||
909 (VAMatch && invVA) ||
910 (MMidMatch && !(tlb->G) && invMMid)) {
911 tlb->EHINV = 1;
912 }
913 }
914 cpu_mips_tlb_flush(env);
915 }
916
917 void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type)
918 {
919 bool invAll = type == 0;
920 bool invVA = type == 1;
921 bool invMMid = type == 2;
922 bool invVAMMid = type == 3;
923 uint32_t invMsgVPN2 = arg & (TARGET_PAGE_MASK << 1);
924 uint8_t invMsgR = 0;
925 uint32_t invMsgMMid = env->CP0_MemoryMapID;
926 CPUState *other_cs = first_cpu;
927
928 #ifdef TARGET_MIPS64
929 invMsgR = extract64(arg, 62, 2);
930 #endif
931
932 CPU_FOREACH(other_cs) {
933 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
934 global_invalidate_tlb(&other_cpu->env, invMsgVPN2, invMsgR, invMsgMMid,
935 invAll, invVAMMid, invMMid, invVA);
936 }
937 }
938
939 /* Specials */
940 target_ulong helper_di(CPUMIPSState *env)
941 {
942 target_ulong t0 = env->CP0_Status;
943
944 env->CP0_Status = t0 & ~(1 << CP0St_IE);
945 return t0;
946 }
947
948 target_ulong helper_ei(CPUMIPSState *env)
949 {
950 target_ulong t0 = env->CP0_Status;
951
952 env->CP0_Status = t0 | (1 << CP0St_IE);
953 return t0;
954 }
955
956 static void debug_pre_eret(CPUMIPSState *env)
957 {
958 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
959 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
960 env->active_tc.PC, env->CP0_EPC);
961 if (env->CP0_Status & (1 << CP0St_ERL)) {
962 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
963 }
964 if (env->hflags & MIPS_HFLAG_DM) {
965 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
966 }
967 qemu_log("\n");
968 }
969 }
970
971 static void debug_post_eret(CPUMIPSState *env)
972 {
973 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
974 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
975 env->active_tc.PC, env->CP0_EPC);
976 if (env->CP0_Status & (1 << CP0St_ERL)) {
977 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
978 }
979 if (env->hflags & MIPS_HFLAG_DM) {
980 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
981 }
982 switch (cpu_mmu_index(env, false)) {
983 case 3:
984 qemu_log(", ERL\n");
985 break;
986 case MIPS_HFLAG_UM:
987 qemu_log(", UM\n");
988 break;
989 case MIPS_HFLAG_SM:
990 qemu_log(", SM\n");
991 break;
992 case MIPS_HFLAG_KM:
993 qemu_log("\n");
994 break;
995 default:
996 cpu_abort(env_cpu(env), "Invalid MMU mode!\n");
997 break;
998 }
999 }
1000 }
1001
1002 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
1003 {
1004 env->active_tc.PC = error_pc & ~(target_ulong)1;
1005 if (error_pc & 1) {
1006 env->hflags |= MIPS_HFLAG_M16;
1007 } else {
1008 env->hflags &= ~(MIPS_HFLAG_M16);
1009 }
1010 }
1011
1012 static inline void exception_return(CPUMIPSState *env)
1013 {
1014 debug_pre_eret(env);
1015 if (env->CP0_Status & (1 << CP0St_ERL)) {
1016 set_pc(env, env->CP0_ErrorEPC);
1017 env->CP0_Status &= ~(1 << CP0St_ERL);
1018 } else {
1019 set_pc(env, env->CP0_EPC);
1020 env->CP0_Status &= ~(1 << CP0St_EXL);
1021 }
1022 compute_hflags(env);
1023 debug_post_eret(env);
1024 }
1025
1026 void helper_eret(CPUMIPSState *env)
1027 {
1028 exception_return(env);
1029 env->CP0_LLAddr = 1;
1030 env->lladdr = 1;
1031 }
1032
1033 void helper_eretnc(CPUMIPSState *env)
1034 {
1035 exception_return(env);
1036 }
1037
1038 void helper_deret(CPUMIPSState *env)
1039 {
1040 debug_pre_eret(env);
1041
1042 env->hflags &= ~MIPS_HFLAG_DM;
1043 compute_hflags(env);
1044
1045 set_pc(env, env->CP0_DEPC);
1046
1047 debug_post_eret(env);
1048 }
1049 #endif /* !CONFIG_USER_ONLY */
1050
1051 static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc)
1052 {
1053 if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) {
1054 return;
1055 }
1056 do_raise_exception(env, EXCP_RI, pc);
1057 }
1058
1059 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
1060 {
1061 check_hwrena(env, 0, GETPC());
1062 return env->CP0_EBase & 0x3ff;
1063 }
1064
1065 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
1066 {
1067 check_hwrena(env, 1, GETPC());
1068 return env->SYNCI_Step;
1069 }
1070
1071 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
1072 {
1073 check_hwrena(env, 2, GETPC());
1074 #ifdef CONFIG_USER_ONLY
1075 return env->CP0_Count;
1076 #else
1077 return (int32_t)cpu_mips_get_count(env);
1078 #endif
1079 }
1080
1081 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
1082 {
1083 check_hwrena(env, 3, GETPC());
1084 return env->CCRes;
1085 }
1086
1087 target_ulong helper_rdhwr_performance(CPUMIPSState *env)
1088 {
1089 check_hwrena(env, 4, GETPC());
1090 return env->CP0_Performance0;
1091 }
1092
1093 target_ulong helper_rdhwr_xnp(CPUMIPSState *env)
1094 {
1095 check_hwrena(env, 5, GETPC());
1096 return (env->CP0_Config5 >> CP0C5_XNP) & 1;
1097 }
1098
1099 void helper_pmon(CPUMIPSState *env, int function)
1100 {
1101 function /= 2;
1102 switch (function) {
1103 case 2: /* TODO: char inbyte(int waitflag); */
1104 if (env->active_tc.gpr[4] == 0) {
1105 env->active_tc.gpr[2] = -1;
1106 }
1107 /* Fall through */
1108 case 11: /* TODO: char inbyte (void); */
1109 env->active_tc.gpr[2] = -1;
1110 break;
1111 case 3:
1112 case 12:
1113 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
1114 break;
1115 case 17:
1116 break;
1117 case 158:
1118 {
1119 unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
1120 printf("%s", fmt);
1121 }
1122 break;
1123 }
1124 }
1125
1126 void helper_wait(CPUMIPSState *env)
1127 {
1128 CPUState *cs = env_cpu(env);
1129
1130 cs->halted = 1;
1131 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
1132 /*
1133 * Last instruction in the block, PC was updated before
1134 * - no need to recover PC and icount.
1135 */
1136 raise_exception(env, EXCP_HLT);
1137 }
1138
1139 #if !defined(CONFIG_USER_ONLY)
1140
1141 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
1142 MMUAccessType access_type,
1143 int mmu_idx, uintptr_t retaddr)
1144 {
1145 MIPSCPU *cpu = MIPS_CPU(cs);
1146 CPUMIPSState *env = &cpu->env;
1147 int error_code = 0;
1148 int excp;
1149
1150 if (!(env->hflags & MIPS_HFLAG_DM)) {
1151 env->CP0_BadVAddr = addr;
1152 }
1153
1154 if (access_type == MMU_DATA_STORE) {
1155 excp = EXCP_AdES;
1156 } else {
1157 excp = EXCP_AdEL;
1158 if (access_type == MMU_INST_FETCH) {
1159 error_code |= EXCP_INST_NOTAVAIL;
1160 }
1161 }
1162
1163 do_raise_exception_err(env, excp, error_code, retaddr);
1164 }
1165
1166 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
1167 vaddr addr, unsigned size,
1168 MMUAccessType access_type,
1169 int mmu_idx, MemTxAttrs attrs,
1170 MemTxResult response, uintptr_t retaddr)
1171 {
1172 MIPSCPU *cpu = MIPS_CPU(cs);
1173 CPUMIPSState *env = &cpu->env;
1174
1175 if (access_type == MMU_INST_FETCH) {
1176 do_raise_exception(env, EXCP_IBE, retaddr);
1177 } else {
1178 do_raise_exception(env, EXCP_DBE, retaddr);
1179 }
1180 }
1181 #endif /* !CONFIG_USER_ONLY */
1182
1183
1184 /* MSA */
1185 /* Data format min and max values */
1186 #define DF_BITS(df) (1 << ((df) + 3))
1187
1188 /* Element-by-element access macros */
1189 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
1190
1191 #if !defined(CONFIG_USER_ONLY)
1192 #define MEMOP_IDX(DF) \
1193 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
1194 cpu_mmu_index(env, false));
1195 #else
1196 #define MEMOP_IDX(DF)
1197 #endif
1198
1199 void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd,
1200 target_ulong addr)
1201 {
1202 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1203 MEMOP_IDX(DF_BYTE)
1204 #if !defined(CONFIG_USER_ONLY)
1205 #if !defined(HOST_WORDS_BIGENDIAN)
1206 pwd->b[0] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC());
1207 pwd->b[1] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC());
1208 pwd->b[2] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC());
1209 pwd->b[3] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC());
1210 pwd->b[4] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC());
1211 pwd->b[5] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC());
1212 pwd->b[6] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC());
1213 pwd->b[7] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC());
1214 pwd->b[8] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC());
1215 pwd->b[9] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC());
1216 pwd->b[10] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC());
1217 pwd->b[11] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC());
1218 pwd->b[12] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC());
1219 pwd->b[13] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC());
1220 pwd->b[14] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC());
1221 pwd->b[15] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC());
1222 #else
1223 pwd->b[0] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC());
1224 pwd->b[1] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC());
1225 pwd->b[2] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC());
1226 pwd->b[3] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC());
1227 pwd->b[4] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC());
1228 pwd->b[5] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC());
1229 pwd->b[6] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC());
1230 pwd->b[7] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC());
1231 pwd->b[8] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC());
1232 pwd->b[9] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC());
1233 pwd->b[10] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC());
1234 pwd->b[11] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC());
1235 pwd->b[12] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC());
1236 pwd->b[13] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC());
1237 pwd->b[14] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC());
1238 pwd->b[15] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC());
1239 #endif
1240 #else
1241 #if !defined(HOST_WORDS_BIGENDIAN)
1242 pwd->b[0] = cpu_ldub_data(env, addr + (0 << DF_BYTE));
1243 pwd->b[1] = cpu_ldub_data(env, addr + (1 << DF_BYTE));
1244 pwd->b[2] = cpu_ldub_data(env, addr + (2 << DF_BYTE));
1245 pwd->b[3] = cpu_ldub_data(env, addr + (3 << DF_BYTE));
1246 pwd->b[4] = cpu_ldub_data(env, addr + (4 << DF_BYTE));
1247 pwd->b[5] = cpu_ldub_data(env, addr + (5 << DF_BYTE));
1248 pwd->b[6] = cpu_ldub_data(env, addr + (6 << DF_BYTE));
1249 pwd->b[7] = cpu_ldub_data(env, addr + (7 << DF_BYTE));
1250 pwd->b[8] = cpu_ldub_data(env, addr + (8 << DF_BYTE));
1251 pwd->b[9] = cpu_ldub_data(env, addr + (9 << DF_BYTE));
1252 pwd->b[10] = cpu_ldub_data(env, addr + (10 << DF_BYTE));
1253 pwd->b[11] = cpu_ldub_data(env, addr + (11 << DF_BYTE));
1254 pwd->b[12] = cpu_ldub_data(env, addr + (12 << DF_BYTE));
1255 pwd->b[13] = cpu_ldub_data(env, addr + (13 << DF_BYTE));
1256 pwd->b[14] = cpu_ldub_data(env, addr + (14 << DF_BYTE));
1257 pwd->b[15] = cpu_ldub_data(env, addr + (15 << DF_BYTE));
1258 #else
1259 pwd->b[0] = cpu_ldub_data(env, addr + (7 << DF_BYTE));
1260 pwd->b[1] = cpu_ldub_data(env, addr + (6 << DF_BYTE));
1261 pwd->b[2] = cpu_ldub_data(env, addr + (5 << DF_BYTE));
1262 pwd->b[3] = cpu_ldub_data(env, addr + (4 << DF_BYTE));
1263 pwd->b[4] = cpu_ldub_data(env, addr + (3 << DF_BYTE));
1264 pwd->b[5] = cpu_ldub_data(env, addr + (2 << DF_BYTE));
1265 pwd->b[6] = cpu_ldub_data(env, addr + (1 << DF_BYTE));
1266 pwd->b[7] = cpu_ldub_data(env, addr + (0 << DF_BYTE));
1267 pwd->b[8] = cpu_ldub_data(env, addr + (15 << DF_BYTE));
1268 pwd->b[9] = cpu_ldub_data(env, addr + (14 << DF_BYTE));
1269 pwd->b[10] = cpu_ldub_data(env, addr + (13 << DF_BYTE));
1270 pwd->b[11] = cpu_ldub_data(env, addr + (12 << DF_BYTE));
1271 pwd->b[12] = cpu_ldub_data(env, addr + (11 << DF_BYTE));
1272 pwd->b[13] = cpu_ldub_data(env, addr + (10 << DF_BYTE));
1273 pwd->b[14] = cpu_ldub_data(env, addr + (9 << DF_BYTE));
1274 pwd->b[15] = cpu_ldub_data(env, addr + (8 << DF_BYTE));
1275 #endif
1276 #endif
1277 }
1278
1279 void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd,
1280 target_ulong addr)
1281 {
1282 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1283 MEMOP_IDX(DF_HALF)
1284 #if !defined(CONFIG_USER_ONLY)
1285 #if !defined(HOST_WORDS_BIGENDIAN)
1286 pwd->h[0] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC());
1287 pwd->h[1] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC());
1288 pwd->h[2] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC());
1289 pwd->h[3] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC());
1290 pwd->h[4] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC());
1291 pwd->h[5] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC());
1292 pwd->h[6] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC());
1293 pwd->h[7] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC());
1294 #else
1295 pwd->h[0] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC());
1296 pwd->h[1] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC());
1297 pwd->h[2] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC());
1298 pwd->h[3] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC());
1299 pwd->h[4] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC());
1300 pwd->h[5] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC());
1301 pwd->h[6] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC());
1302 pwd->h[7] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC());
1303 #endif
1304 #else
1305 #if !defined(HOST_WORDS_BIGENDIAN)
1306 pwd->h[0] = cpu_lduw_data(env, addr + (0 << DF_HALF));
1307 pwd->h[1] = cpu_lduw_data(env, addr + (1 << DF_HALF));
1308 pwd->h[2] = cpu_lduw_data(env, addr + (2 << DF_HALF));
1309 pwd->h[3] = cpu_lduw_data(env, addr + (3 << DF_HALF));
1310 pwd->h[4] = cpu_lduw_data(env, addr + (4 << DF_HALF));
1311 pwd->h[5] = cpu_lduw_data(env, addr + (5 << DF_HALF));
1312 pwd->h[6] = cpu_lduw_data(env, addr + (6 << DF_HALF));
1313 pwd->h[7] = cpu_lduw_data(env, addr + (7 << DF_HALF));
1314 #else
1315 pwd->h[0] = cpu_lduw_data(env, addr + (3 << DF_HALF));
1316 pwd->h[1] = cpu_lduw_data(env, addr + (2 << DF_HALF));
1317 pwd->h[2] = cpu_lduw_data(env, addr + (1 << DF_HALF));
1318 pwd->h[3] = cpu_lduw_data(env, addr + (0 << DF_HALF));
1319 pwd->h[4] = cpu_lduw_data(env, addr + (7 << DF_HALF));
1320 pwd->h[5] = cpu_lduw_data(env, addr + (6 << DF_HALF));
1321 pwd->h[6] = cpu_lduw_data(env, addr + (5 << DF_HALF));
1322 pwd->h[7] = cpu_lduw_data(env, addr + (4 << DF_HALF));
1323 #endif
1324 #endif
1325 }
1326
1327 void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd,
1328 target_ulong addr)
1329 {
1330 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1331 MEMOP_IDX(DF_WORD)
1332 #if !defined(CONFIG_USER_ONLY)
1333 #if !defined(HOST_WORDS_BIGENDIAN)
1334 pwd->w[0] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC());
1335 pwd->w[1] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC());
1336 pwd->w[2] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC());
1337 pwd->w[3] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC());
1338 #else
1339 pwd->w[0] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC());
1340 pwd->w[1] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC());
1341 pwd->w[2] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC());
1342 pwd->w[3] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC());
1343 #endif
1344 #else
1345 #if !defined(HOST_WORDS_BIGENDIAN)
1346 pwd->w[0] = cpu_ldl_data(env, addr + (0 << DF_WORD));
1347 pwd->w[1] = cpu_ldl_data(env, addr + (1 << DF_WORD));
1348 pwd->w[2] = cpu_ldl_data(env, addr + (2 << DF_WORD));
1349 pwd->w[3] = cpu_ldl_data(env, addr + (3 << DF_WORD));
1350 #else
1351 pwd->w[0] = cpu_ldl_data(env, addr + (1 << DF_WORD));
1352 pwd->w[1] = cpu_ldl_data(env, addr + (0 << DF_WORD));
1353 pwd->w[2] = cpu_ldl_data(env, addr + (3 << DF_WORD));
1354 pwd->w[3] = cpu_ldl_data(env, addr + (2 << DF_WORD));
1355 #endif
1356 #endif
1357 }
1358
1359 void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd,
1360 target_ulong addr)
1361 {
1362 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1363 MEMOP_IDX(DF_DOUBLE)
1364 #if !defined(CONFIG_USER_ONLY)
1365 pwd->d[0] = helper_ret_ldq_mmu(env, addr + (0 << DF_DOUBLE), oi, GETPC());
1366 pwd->d[1] = helper_ret_ldq_mmu(env, addr + (1 << DF_DOUBLE), oi, GETPC());
1367 #else
1368 pwd->d[0] = cpu_ldq_data(env, addr + (0 << DF_DOUBLE));
1369 pwd->d[1] = cpu_ldq_data(env, addr + (1 << DF_DOUBLE));
1370 #endif
1371 }
1372
1373 #define MSA_PAGESPAN(x) \
1374 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >= TARGET_PAGE_SIZE)
1375
1376 static inline void ensure_writable_pages(CPUMIPSState *env,
1377 target_ulong addr,
1378 int mmu_idx,
1379 uintptr_t retaddr)
1380 {
1381 /* FIXME: Probe the actual accesses (pass and use a size) */
1382 if (unlikely(MSA_PAGESPAN(addr))) {
1383 /* first page */
1384 probe_write(env, addr, 0, mmu_idx, retaddr);
1385 /* second page */
1386 addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1387 probe_write(env, addr, 0, mmu_idx, retaddr);
1388 }
1389 }
1390
1391 void helper_msa_st_b(CPUMIPSState *env, uint32_t wd,
1392 target_ulong addr)
1393 {
1394 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1395 int mmu_idx = cpu_mmu_index(env, false);
1396
1397 MEMOP_IDX(DF_BYTE)
1398 ensure_writable_pages(env, addr, mmu_idx, GETPC());
1399 #if !defined(CONFIG_USER_ONLY)
1400 #if !defined(HOST_WORDS_BIGENDIAN)
1401 helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[0], oi, GETPC());
1402 helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[1], oi, GETPC());
1403 helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[2], oi, GETPC());
1404 helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[3], oi, GETPC());
1405 helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[4], oi, GETPC());
1406 helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[5], oi, GETPC());
1407 helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[6], oi, GETPC());
1408 helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[7], oi, GETPC());
1409 helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[8], oi, GETPC());
1410 helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[9], oi, GETPC());
1411 helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[10], oi, GETPC());
1412 helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[11], oi, GETPC());
1413 helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[12], oi, GETPC());
1414 helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[13], oi, GETPC());
1415 helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[14], oi, GETPC());
1416 helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[15], oi, GETPC());
1417 #else
1418 helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[0], oi, GETPC());
1419 helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[1], oi, GETPC());
1420 helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[2], oi, GETPC());
1421 helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[3], oi, GETPC());
1422 helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[4], oi, GETPC());
1423 helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[5], oi, GETPC());
1424 helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[6], oi, GETPC());
1425 helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[7], oi, GETPC());
1426 helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[8], oi, GETPC());
1427 helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[9], oi, GETPC());
1428 helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[10], oi, GETPC());
1429 helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[11], oi, GETPC());
1430 helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[12], oi, GETPC());
1431 helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[13], oi, GETPC());
1432 helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[14], oi, GETPC());
1433 helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[15], oi, GETPC());
1434 #endif
1435 #else
1436 #if !defined(HOST_WORDS_BIGENDIAN)
1437 cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[0]);
1438 cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[1]);
1439 cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[2]);
1440 cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[3]);
1441 cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[4]);
1442 cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[5]);
1443 cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[6]);
1444 cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[7]);
1445 cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[8]);
1446 cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[9]);
1447 cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[10]);
1448 cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[11]);
1449 cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[12]);
1450 cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[13]);
1451 cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[14]);
1452 cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[15]);
1453 #else
1454 cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[0]);
1455 cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[1]);
1456 cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[2]);
1457 cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[3]);
1458 cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[4]);
1459 cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[5]);
1460 cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[6]);
1461 cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[7]);
1462 cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[8]);
1463 cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[9]);
1464 cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[10]);
1465 cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[11]);
1466 cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[12]);
1467 cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[13]);
1468 cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[14]);
1469 cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[15]);
1470 #endif
1471 #endif
1472 }
1473
1474 void helper_msa_st_h(CPUMIPSState *env, uint32_t wd,
1475 target_ulong addr)
1476 {
1477 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1478 int mmu_idx = cpu_mmu_index(env, false);
1479
1480 MEMOP_IDX(DF_HALF)
1481 ensure_writable_pages(env, addr, mmu_idx, GETPC());
1482 #if !defined(CONFIG_USER_ONLY)
1483 #if !defined(HOST_WORDS_BIGENDIAN)
1484 helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[0], oi, GETPC());
1485 helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[1], oi, GETPC());
1486 helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[2], oi, GETPC());
1487 helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[3], oi, GETPC());
1488 helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[4], oi, GETPC());
1489 helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[5], oi, GETPC());
1490 helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[6], oi, GETPC());
1491 helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[7], oi, GETPC());
1492 #else
1493 helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[0], oi, GETPC());
1494 helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[1], oi, GETPC());
1495 helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[2], oi, GETPC());
1496 helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[3], oi, GETPC());
1497 helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[4], oi, GETPC());
1498 helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[5], oi, GETPC());
1499 helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[6], oi, GETPC());
1500 helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[7], oi, GETPC());
1501 #endif
1502 #else
1503 #if !defined(HOST_WORDS_BIGENDIAN)
1504 cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[0]);
1505 cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[1]);
1506 cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[2]);
1507 cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[3]);
1508 cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[4]);
1509 cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[5]);
1510 cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[6]);
1511 cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[7]);
1512 #else
1513 cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[0]);
1514 cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[1]);
1515 cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[2]);
1516 cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[3]);
1517 cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[4]);
1518 cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[5]);
1519 cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[6]);
1520 cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[7]);
1521 #endif
1522 #endif
1523 }
1524
1525 void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,
1526 target_ulong addr)
1527 {
1528 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1529 int mmu_idx = cpu_mmu_index(env, false);
1530
1531 MEMOP_IDX(DF_WORD)
1532 ensure_writable_pages(env, addr, mmu_idx, GETPC());
1533 #if !defined(CONFIG_USER_ONLY)
1534 #if !defined(HOST_WORDS_BIGENDIAN)
1535 helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC());
1536 helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC());
1537 helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC());
1538 helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC());
1539 #else
1540 helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC());
1541 helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC());
1542 helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC());
1543 helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC());
1544 #endif
1545 #else
1546 #if !defined(HOST_WORDS_BIGENDIAN)
1547 cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[0]);
1548 cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[1]);
1549 cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[2]);
1550 cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[3]);
1551 #else
1552 cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[0]);
1553 cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[1]);
1554 cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[2]);
1555 cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[3]);
1556 #endif
1557 #endif
1558 }
1559
1560 void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
1561 target_ulong addr)
1562 {
1563 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1564 int mmu_idx = cpu_mmu_index(env, false);
1565
1566 MEMOP_IDX(DF_DOUBLE)
1567 ensure_writable_pages(env, addr, mmu_idx, GETPC());
1568 #if !defined(CONFIG_USER_ONLY)
1569 helper_ret_stq_mmu(env, addr + (0 << DF_DOUBLE), pwd->d[0], oi, GETPC());
1570 helper_ret_stq_mmu(env, addr + (1 << DF_DOUBLE), pwd->d[1], oi, GETPC());
1571 #else
1572 cpu_stq_data(env, addr + (0 << DF_DOUBLE), pwd->d[0]);
1573 cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]);
1574 #endif
1575 }
1576
1577 void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
1578 {
1579 #ifndef CONFIG_USER_ONLY
1580 static const char *const type_name[] = {
1581 "Primary Instruction",
1582 "Primary Data or Unified Primary",
1583 "Tertiary",
1584 "Secondary"
1585 };
1586 uint32_t cache_type = extract32(op, 0, 2);
1587 uint32_t cache_operation = extract32(op, 2, 3);
1588 target_ulong index = addr & 0x1fffffff;
1589
1590 switch (cache_operation) {
1591 case 0b010: /* Index Store Tag */
1592 memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
1593 MO_64, MEMTXATTRS_UNSPECIFIED);
1594 break;
1595 case 0b001: /* Index Load Tag */
1596 memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
1597 MO_64, MEMTXATTRS_UNSPECIFIED);
1598 break;
1599 case 0b000: /* Index Invalidate */
1600 case 0b100: /* Hit Invalidate */
1601 case 0b110: /* Hit Writeback */
1602 /* no-op */
1603 break;
1604 default:
1605 qemu_log_mask(LOG_UNIMP, "cache operation:%u (type: %s cache)\n",
1606 cache_operation, type_name[cache_type]);
1607 break;
1608 }
1609 #endif
1610 }
AR7 emulation for QEMU