target/openrisc/cpu.c

   1 /*
   2  * QEMU OpenRISC CPU
   3  *
   4  * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "cpu.h"
  23 #include "qemu-common.h"
  24 #include "exec/exec-all.h"
  25
  26 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
  27 {
  28     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
  29
  30     cpu->env.pc = value;
  31 }
  32
  33 static bool openrisc_cpu_has_work(CPUState *cs)
  34 {
  35     return cs->interrupt_request & (CPU_INTERRUPT_HARD |
  36                                     CPU_INTERRUPT_TIMER);
  37 }
  38
  39 /* CPUClass::reset() */
  40 static void openrisc_cpu_reset(CPUState *s)
  41 {
  42     OpenRISCCPU *cpu = OPENRISC_CPU(s);
  43     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
  44
  45     occ->parent_reset(s);
  46
  47     memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
  48
  49     cpu->env.pc = 0x100;
  50     cpu->env.sr = SR_FO | SR_SM;
  51     cpu->env.lock_addr = -1;
  52     s->exception_index = -1;
  53
  54     cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP |
  55                    UPR_PMP;
  56     cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
  57     cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
  58
  59 #ifndef CONFIG_USER_ONLY
  60     cpu->env.picmr = 0x00000000;
  61     cpu->env.picsr = 0x00000000;
  62
  63     cpu->env.ttmr = 0x00000000;
  64     cpu->env.ttcr = 0x00000000;
  65 #endif
  66 }
  67
  68 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
  69 {
  70     CPUState *cs = CPU(dev);
  71     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
  72     Error *local_err = NULL;
  73
  74     cpu_exec_realizefn(cs, &local_err);
  75     if (local_err != NULL) {
  76         error_propagate(errp, local_err);
  77         return;
  78     }
  79
  80     qemu_init_vcpu(cs);
  81     cpu_reset(cs);
  82
  83     occ->parent_realize(dev, errp);
  84 }
  85
  86 static void openrisc_cpu_initfn(Object *obj)
  87 {
  88     CPUState *cs = CPU(obj);
  89     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
  90     static int inited;
  91
  92     cs->env_ptr = &cpu->env;
  93
  94 #ifndef CONFIG_USER_ONLY
  95     cpu_openrisc_mmu_init(cpu);
  96 #endif
  97
  98     if (tcg_enabled() && !inited) {
  99         inited = 1;
 100         openrisc_translate_init();
 101     }
 102 }
 103
 104 /* CPU models */
 105
 106 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
 107 {
 108     ObjectClass *oc;
 109     char *typename;
 110
 111     typename = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, cpu_model);
 112     oc = object_class_by_name(typename);
 113     g_free(typename);
 114     if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
 115                        object_class_is_abstract(oc))) {
 116         return NULL;
 117     }
 118     return oc;
 119 }
 120
 121 static void or1200_initfn(Object *obj)
 122 {
 123     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 124
 125     cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
 126                        CPUCFGR_EVBARP;
 127 }
 128
 129 static void openrisc_any_initfn(Object *obj)
 130 {
 131     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 132
 133     cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP;
 134 }
 135
 136 typedef struct OpenRISCCPUInfo {
 137     const char *name;
 138     void (*initfn)(Object *obj);
 139 } OpenRISCCPUInfo;
 140
 141 static const OpenRISCCPUInfo openrisc_cpus[] = {
 142     { .name = "or1200",      .initfn = or1200_initfn },
 143     { .name = "any",         .initfn = openrisc_any_initfn },
 144 };
 145
 146 static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
 147 {
 148     OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
 149     CPUClass *cc = CPU_CLASS(occ);
 150     DeviceClass *dc = DEVICE_CLASS(oc);
 151
 152     occ->parent_realize = dc->realize;
 153     dc->realize = openrisc_cpu_realizefn;
 154
 155     occ->parent_reset = cc->reset;
 156     cc->reset = openrisc_cpu_reset;
 157
 158     cc->class_by_name = openrisc_cpu_class_by_name;
 159     cc->has_work = openrisc_cpu_has_work;
 160     cc->do_interrupt = openrisc_cpu_do_interrupt;
 161     cc->cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
 162     cc->dump_state = openrisc_cpu_dump_state;
 163     cc->set_pc = openrisc_cpu_set_pc;
 164     cc->gdb_read_register = openrisc_cpu_gdb_read_register;
 165     cc->gdb_write_register = openrisc_cpu_gdb_write_register;
 166 #ifdef CONFIG_USER_ONLY
 167     cc->handle_mmu_fault = openrisc_cpu_handle_mmu_fault;
 168 #else
 169     cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
 170     dc->vmsd = &vmstate_openrisc_cpu;
 171 #endif
 172     cc->gdb_num_core_regs = 32 + 3;
 173 }
 174
 175 static void cpu_register(const OpenRISCCPUInfo *info)
 176 {
 177     TypeInfo type_info = {
 178         .parent = TYPE_OPENRISC_CPU,
 179         .instance_size = sizeof(OpenRISCCPU),
 180         .instance_init = info->initfn,
 181         .class_size = sizeof(OpenRISCCPUClass),
 182     };
 183
 184     type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name);
 185     type_register(&type_info);
 186     g_free((void *)type_info.name);
 187 }
 188
 189 static const TypeInfo openrisc_cpu_type_info = {
 190     .name = TYPE_OPENRISC_CPU,
 191     .parent = TYPE_CPU,
 192     .instance_size = sizeof(OpenRISCCPU),
 193     .instance_init = openrisc_cpu_initfn,
 194     .abstract = true,
 195     .class_size = sizeof(OpenRISCCPUClass),
 196     .class_init = openrisc_cpu_class_init,
 197 };
 198
 199 static void openrisc_cpu_register_types(void)
 200 {
 201     int i;
 202
 203     type_register_static(&openrisc_cpu_type_info);
 204     for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) {
 205         cpu_register(&openrisc_cpus[i]);
 206     }
 207 }
 208
 209 /* Sort alphabetically by type name, except for "any". */
 210 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
 211 {
 212     ObjectClass *class_a = (ObjectClass *)a;
 213     ObjectClass *class_b = (ObjectClass *)b;
 214     const char *name_a, *name_b;
 215
 216     name_a = object_class_get_name(class_a);
 217     name_b = object_class_get_name(class_b);
 218     if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
 219         return 1;
 220     } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
 221         return -1;
 222     } else {
 223         return strcmp(name_a, name_b);
 224     }
 225 }
 226
 227 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
 228 {
 229     ObjectClass *oc = data;
 230     CPUListState *s = user_data;
 231     const char *typename;
 232     char *name;
 233
 234     typename = object_class_get_name(oc);
 235     name = g_strndup(typename,
 236                      strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
 237     (*s->cpu_fprintf)(s->file, "  %s\n",
 238                       name);
 239     g_free(name);
 240 }
 241
 242 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf)
 243 {
 244     CPUListState s = {
 245         .file = f,
 246         .cpu_fprintf = cpu_fprintf,
 247     };
 248     GSList *list;
 249
 250     list = object_class_get_list(TYPE_OPENRISC_CPU, false);
 251     list = g_slist_sort(list, openrisc_cpu_list_compare);
 252     (*cpu_fprintf)(f, "Available CPUs:\n");
 253     g_slist_foreach(list, openrisc_cpu_list_entry, &s);
 254     g_slist_free(list);
 255 }
 256
 257 type_init(openrisc_cpu_register_types)