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net: mcf: limit buffer descriptor count
[qemu/ar7.git] / target-i386 / kvm.c
bloba0e42b2c4ed7b266f2a0b66f99b5303dddfa8077
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/kvm_int.h"
27 #include "kvm_i386.h"
28 #include "hyperv.h"
29
30 #include "exec/gdbstub.h"
31 #include "qemu/host-utils.h"
32 #include "qemu/config-file.h"
33 #include "qemu/error-report.h"
34 #include "hw/i386/pc.h"
35 #include "hw/i386/apic.h"
36 #include "hw/i386/apic_internal.h"
37 #include "hw/i386/apic-msidef.h"
38 #include "hw/i386/intel_iommu.h"
39 #include "hw/i386/x86-iommu.h"
40
41 #include "exec/ioport.h"
42 #include "standard-headers/asm-x86/hyperv.h"
43 #include "hw/pci/pci.h"
44 #include "hw/pci/msi.h"
45 #include "migration/migration.h"
46 #include "exec/memattrs.h"
47 #include "trace.h"
48
49 //#define DEBUG_KVM
50
51 #ifdef DEBUG_KVM
52 #define DPRINTF(fmt, ...) \
53 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
54 #else
55 #define DPRINTF(fmt, ...) \
56 do { } while (0)
57 #endif
58
59 #define MSR_KVM_WALL_CLOCK 0x11
60 #define MSR_KVM_SYSTEM_TIME 0x12
61
62 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
63 * 255 kvm_msr_entry structs */
64 #define MSR_BUF_SIZE 4096
65
66 #ifndef BUS_MCEERR_AR
67 #define BUS_MCEERR_AR 4
68 #endif
69 #ifndef BUS_MCEERR_AO
70 #define BUS_MCEERR_AO 5
71 #endif
72
73 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
74 KVM_CAP_INFO(SET_TSS_ADDR),
75 KVM_CAP_INFO(EXT_CPUID),
76 KVM_CAP_INFO(MP_STATE),
77 KVM_CAP_LAST_INFO
78 };
79
80 static bool has_msr_star;
81 static bool has_msr_hsave_pa;
82 static bool has_msr_tsc_aux;
83 static bool has_msr_tsc_adjust;
84 static bool has_msr_tsc_deadline;
85 static bool has_msr_feature_control;
86 static bool has_msr_async_pf_en;
87 static bool has_msr_pv_eoi_en;
88 static bool has_msr_misc_enable;
89 static bool has_msr_smbase;
90 static bool has_msr_bndcfgs;
91 static bool has_msr_kvm_steal_time;
92 static int lm_capable_kernel;
93 static bool has_msr_hv_hypercall;
94 static bool has_msr_hv_vapic;
95 static bool has_msr_hv_tsc;
96 static bool has_msr_hv_crash;
97 static bool has_msr_hv_reset;
98 static bool has_msr_hv_vpindex;
99 static bool has_msr_hv_runtime;
100 static bool has_msr_hv_synic;
101 static bool has_msr_hv_stimer;
102 static bool has_msr_mtrr;
103 static bool has_msr_xss;
104
105 static bool has_msr_architectural_pmu;
106 static uint32_t num_architectural_pmu_counters;
107
108 static int has_xsave;
109 static int has_xcrs;
110 static int has_pit_state2;
111
112 static bool has_msr_mcg_ext_ctl;
113
114 static struct kvm_cpuid2 *cpuid_cache;
115
116 int kvm_has_pit_state2(void)
117 {
118 return has_pit_state2;
119 }
120
121 bool kvm_has_smm(void)
122 {
123 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
124 }
125
126 bool kvm_allows_irq0_override(void)
127 {
128 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
129 }
130
131 static int kvm_get_tsc(CPUState *cs)
132 {
133 X86CPU *cpu = X86_CPU(cs);
134 CPUX86State *env = &cpu->env;
135 struct {
136 struct kvm_msrs info;
137 struct kvm_msr_entry entries[1];
138 } msr_data;
139 int ret;
140
141 if (env->tsc_valid) {
142 return 0;
143 }
144
145 msr_data.info.nmsrs = 1;
146 msr_data.entries[0].index = MSR_IA32_TSC;
147 env->tsc_valid = !runstate_is_running();
148
149 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
150 if (ret < 0) {
151 return ret;
152 }
153
154 assert(ret == 1);
155 env->tsc = msr_data.entries[0].data;
156 return 0;
157 }
158
159 static inline void do_kvm_synchronize_tsc(void *arg)
160 {
161 CPUState *cpu = arg;
162
163 kvm_get_tsc(cpu);
164 }
165
166 void kvm_synchronize_all_tsc(void)
167 {
168 CPUState *cpu;
169
170 if (kvm_enabled()) {
171 CPU_FOREACH(cpu) {
172 run_on_cpu(cpu, do_kvm_synchronize_tsc, cpu);
173 }
174 }
175 }
176
177 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
178 {
179 struct kvm_cpuid2 *cpuid;
180 int r, size;
181
182 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
183 cpuid = g_malloc0(size);
184 cpuid->nent = max;
185 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
186 if (r == 0 && cpuid->nent >= max) {
187 r = -E2BIG;
188 }
189 if (r < 0) {
190 if (r == -E2BIG) {
191 g_free(cpuid);
192 return NULL;
193 } else {
194 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
195 strerror(-r));
196 exit(1);
197 }
198 }
199 return cpuid;
200 }
201
202 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
203 * for all entries.
204 */
205 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
206 {
207 struct kvm_cpuid2 *cpuid;
208 int max = 1;
209
210 if (cpuid_cache != NULL) {
211 return cpuid_cache;
212 }
213 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
214 max *= 2;
215 }
216 cpuid_cache = cpuid;
217 return cpuid;
218 }
219
220 static const struct kvm_para_features {
221 int cap;
222 int feature;
223 } para_features[] = {
224 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
225 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
226 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
227 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
228 };
229
230 static int get_para_features(KVMState *s)
231 {
232 int i, features = 0;
233
234 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
235 if (kvm_check_extension(s, para_features[i].cap)) {
236 features |= (1 << para_features[i].feature);
237 }
238 }
239
240 return features;
241 }
242
243
244 /* Returns the value for a specific register on the cpuid entry
245 */
246 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
247 {
248 uint32_t ret = 0;
249 switch (reg) {
250 case R_EAX:
251 ret = entry->eax;
252 break;
253 case R_EBX:
254 ret = entry->ebx;
255 break;
256 case R_ECX:
257 ret = entry->ecx;
258 break;
259 case R_EDX:
260 ret = entry->edx;
261 break;
262 }
263 return ret;
264 }
265
266 /* Find matching entry for function/index on kvm_cpuid2 struct
267 */
268 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
269 uint32_t function,
270 uint32_t index)
271 {
272 int i;
273 for (i = 0; i < cpuid->nent; ++i) {
274 if (cpuid->entries[i].function == function &&
275 cpuid->entries[i].index == index) {
276 return &cpuid->entries[i];
277 }
278 }
279 /* not found: */
280 return NULL;
281 }
282
283 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
284 uint32_t index, int reg)
285 {
286 struct kvm_cpuid2 *cpuid;
287 uint32_t ret = 0;
288 uint32_t cpuid_1_edx;
289 bool found = false;
290
291 cpuid = get_supported_cpuid(s);
292
293 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
294 if (entry) {
295 found = true;
296 ret = cpuid_entry_get_reg(entry, reg);
297 }
298
299 /* Fixups for the data returned by KVM, below */
300
301 if (function == 1 && reg == R_EDX) {
302 /* KVM before 2.6.30 misreports the following features */
303 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
304 } else if (function == 1 && reg == R_ECX) {
305 /* We can set the hypervisor flag, even if KVM does not return it on
306 * GET_SUPPORTED_CPUID
307 */
308 ret |= CPUID_EXT_HYPERVISOR;
309 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
310 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
311 * and the irqchip is in the kernel.
312 */
313 if (kvm_irqchip_in_kernel() &&
314 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
315 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
316 }
317
318 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
319 * without the in-kernel irqchip
320 */
321 if (!kvm_irqchip_in_kernel()) {
322 ret &= ~CPUID_EXT_X2APIC;
323 }
324 } else if (function == 6 && reg == R_EAX) {
325 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
326 } else if (function == 0x80000001 && reg == R_EDX) {
327 /* On Intel, kvm returns cpuid according to the Intel spec,
328 * so add missing bits according to the AMD spec:
329 */
330 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
331 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
332 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
333 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
334 * be enabled without the in-kernel irqchip
335 */
336 if (!kvm_irqchip_in_kernel()) {
337 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
338 }
339 }
340
341 /* fallback for older kernels */
342 if ((function == KVM_CPUID_FEATURES) && !found) {
343 ret = get_para_features(s);
344 }
345
346 return ret;
347 }
348
349 typedef struct HWPoisonPage {
350 ram_addr_t ram_addr;
351 QLIST_ENTRY(HWPoisonPage) list;
352 } HWPoisonPage;
353
354 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
355 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
356
357 static void kvm_unpoison_all(void *param)
358 {
359 HWPoisonPage *page, *next_page;
360
361 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
362 QLIST_REMOVE(page, list);
363 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
364 g_free(page);
365 }
366 }
367
368 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
369 {
370 HWPoisonPage *page;
371
372 QLIST_FOREACH(page, &hwpoison_page_list, list) {
373 if (page->ram_addr == ram_addr) {
374 return;
375 }
376 }
377 page = g_new(HWPoisonPage, 1);
378 page->ram_addr = ram_addr;
379 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
380 }
381
382 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
383 int *max_banks)
384 {
385 int r;
386
387 r = kvm_check_extension(s, KVM_CAP_MCE);
388 if (r > 0) {
389 *max_banks = r;
390 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
391 }
392 return -ENOSYS;
393 }
394
395 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
396 {
397 CPUState *cs = CPU(cpu);
398 CPUX86State *env = &cpu->env;
399 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
400 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
401 uint64_t mcg_status = MCG_STATUS_MCIP;
402 int flags = 0;
403
404 if (code == BUS_MCEERR_AR) {
405 status |= MCI_STATUS_AR | 0x134;
406 mcg_status |= MCG_STATUS_EIPV;
407 } else {
408 status |= 0xc0;
409 mcg_status |= MCG_STATUS_RIPV;
410 }
411
412 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
413 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
414 * guest kernel back into env->mcg_ext_ctl.
415 */
416 cpu_synchronize_state(cs);
417 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
418 mcg_status |= MCG_STATUS_LMCE;
419 flags = 0;
420 }
421
422 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
423 (MCM_ADDR_PHYS << 6) | 0xc, flags);
424 }
425
426 static void hardware_memory_error(void)
427 {
428 fprintf(stderr, "Hardware memory error!\n");
429 exit(1);
430 }
431
432 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
433 {
434 X86CPU *cpu = X86_CPU(c);
435 CPUX86State *env = &cpu->env;
436 ram_addr_t ram_addr;
437 hwaddr paddr;
438
439 if ((env->mcg_cap & MCG_SER_P) && addr
440 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
441 ram_addr = qemu_ram_addr_from_host(addr);
442 if (ram_addr == RAM_ADDR_INVALID ||
443 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
444 fprintf(stderr, "Hardware memory error for memory used by "
445 "QEMU itself instead of guest system!\n");
446 /* Hope we are lucky for AO MCE */
447 if (code == BUS_MCEERR_AO) {
448 return 0;
449 } else {
450 hardware_memory_error();
451 }
452 }
453 kvm_hwpoison_page_add(ram_addr);
454 kvm_mce_inject(cpu, paddr, code);
455 } else {
456 if (code == BUS_MCEERR_AO) {
457 return 0;
458 } else if (code == BUS_MCEERR_AR) {
459 hardware_memory_error();
460 } else {
461 return 1;
462 }
463 }
464 return 0;
465 }
466
467 int kvm_arch_on_sigbus(int code, void *addr)
468 {
469 X86CPU *cpu = X86_CPU(first_cpu);
470
471 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
472 ram_addr_t ram_addr;
473 hwaddr paddr;
474
475 /* Hope we are lucky for AO MCE */
476 ram_addr = qemu_ram_addr_from_host(addr);
477 if (ram_addr == RAM_ADDR_INVALID ||
478 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
479 addr, &paddr)) {
480 fprintf(stderr, "Hardware memory error for memory used by "
481 "QEMU itself instead of guest system!: %p\n", addr);
482 return 0;
483 }
484 kvm_hwpoison_page_add(ram_addr);
485 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
486 } else {
487 if (code == BUS_MCEERR_AO) {
488 return 0;
489 } else if (code == BUS_MCEERR_AR) {
490 hardware_memory_error();
491 } else {
492 return 1;
493 }
494 }
495 return 0;
496 }
497
498 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
499 {
500 CPUX86State *env = &cpu->env;
501
502 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
503 unsigned int bank, bank_num = env->mcg_cap & 0xff;
504 struct kvm_x86_mce mce;
505
506 env->exception_injected = -1;
507
508 /*
509 * There must be at least one bank in use if an MCE is pending.
510 * Find it and use its values for the event injection.
511 */
512 for (bank = 0; bank < bank_num; bank++) {
513 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
514 break;
515 }
516 }
517 assert(bank < bank_num);
518
519 mce.bank = bank;
520 mce.status = env->mce_banks[bank * 4 + 1];
521 mce.mcg_status = env->mcg_status;
522 mce.addr = env->mce_banks[bank * 4 + 2];
523 mce.misc = env->mce_banks[bank * 4 + 3];
524
525 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
526 }
527 return 0;
528 }
529
530 static void cpu_update_state(void *opaque, int running, RunState state)
531 {
532 CPUX86State *env = opaque;
533
534 if (running) {
535 env->tsc_valid = false;
536 }
537 }
538
539 unsigned long kvm_arch_vcpu_id(CPUState *cs)
540 {
541 X86CPU *cpu = X86_CPU(cs);
542 return cpu->apic_id;
543 }
544
545 #ifndef KVM_CPUID_SIGNATURE_NEXT
546 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
547 #endif
548
549 static bool hyperv_hypercall_available(X86CPU *cpu)
550 {
551 return cpu->hyperv_vapic ||
552 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
553 }
554
555 static bool hyperv_enabled(X86CPU *cpu)
556 {
557 CPUState *cs = CPU(cpu);
558 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
559 (hyperv_hypercall_available(cpu) ||
560 cpu->hyperv_time ||
561 cpu->hyperv_relaxed_timing ||
562 cpu->hyperv_crash ||
563 cpu->hyperv_reset ||
564 cpu->hyperv_vpindex ||
565 cpu->hyperv_runtime ||
566 cpu->hyperv_synic ||
567 cpu->hyperv_stimer);
568 }
569
570 static int kvm_arch_set_tsc_khz(CPUState *cs)
571 {
572 X86CPU *cpu = X86_CPU(cs);
573 CPUX86State *env = &cpu->env;
574 int r;
575
576 if (!env->tsc_khz) {
577 return 0;
578 }
579
580 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
581 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
582 -ENOTSUP;
583 if (r < 0) {
584 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
585 * TSC frequency doesn't match the one we want.
586 */
587 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
588 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
589 -ENOTSUP;
590 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
591 error_report("warning: TSC frequency mismatch between "
592 "VM (%" PRId64 " kHz) and host (%d kHz), "
593 "and TSC scaling unavailable",
594 env->tsc_khz, cur_freq);
595 return r;
596 }
597 }
598
599 return 0;
600 }
601
602 static int hyperv_handle_properties(CPUState *cs)
603 {
604 X86CPU *cpu = X86_CPU(cs);
605 CPUX86State *env = &cpu->env;
606
607 if (cpu->hyperv_relaxed_timing) {
608 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
609 }
610 if (cpu->hyperv_vapic) {
611 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
612 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
613 has_msr_hv_vapic = true;
614 }
615 if (cpu->hyperv_time &&
616 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
617 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
618 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
619 env->features[FEAT_HYPERV_EAX] |= 0x200;
620 has_msr_hv_tsc = true;
621 }
622 if (cpu->hyperv_crash && has_msr_hv_crash) {
623 env->features[FEAT_HYPERV_EDX] |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
624 }
625 env->features[FEAT_HYPERV_EDX] |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
626 if (cpu->hyperv_reset && has_msr_hv_reset) {
627 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_RESET_AVAILABLE;
628 }
629 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
630 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_INDEX_AVAILABLE;
631 }
632 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
633 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
634 }
635 if (cpu->hyperv_synic) {
636 int sint;
637
638 if (!has_msr_hv_synic ||
639 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
640 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
641 return -ENOSYS;
642 }
643
644 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNIC_AVAILABLE;
645 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
646 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
647 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
648 }
649 }
650 if (cpu->hyperv_stimer) {
651 if (!has_msr_hv_stimer) {
652 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
653 return -ENOSYS;
654 }
655 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNTIMER_AVAILABLE;
656 }
657 return 0;
658 }
659
660 static Error *invtsc_mig_blocker;
661
662 #define KVM_MAX_CPUID_ENTRIES 100
663
664 int kvm_arch_init_vcpu(CPUState *cs)
665 {
666 struct {
667 struct kvm_cpuid2 cpuid;
668 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
669 } QEMU_PACKED cpuid_data;
670 X86CPU *cpu = X86_CPU(cs);
671 CPUX86State *env = &cpu->env;
672 uint32_t limit, i, j, cpuid_i;
673 uint32_t unused;
674 struct kvm_cpuid_entry2 *c;
675 uint32_t signature[3];
676 int kvm_base = KVM_CPUID_SIGNATURE;
677 int r;
678
679 memset(&cpuid_data, 0, sizeof(cpuid_data));
680
681 cpuid_i = 0;
682
683 /* Paravirtualization CPUIDs */
684 if (hyperv_enabled(cpu)) {
685 c = &cpuid_data.entries[cpuid_i++];
686 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
687 if (!cpu->hyperv_vendor_id) {
688 memcpy(signature, "Microsoft Hv", 12);
689 } else {
690 size_t len = strlen(cpu->hyperv_vendor_id);
691
692 if (len > 12) {
693 error_report("hv-vendor-id truncated to 12 characters");
694 len = 12;
695 }
696 memset(signature, 0, 12);
697 memcpy(signature, cpu->hyperv_vendor_id, len);
698 }
699 c->eax = HYPERV_CPUID_MIN;
700 c->ebx = signature[0];
701 c->ecx = signature[1];
702 c->edx = signature[2];
703
704 c = &cpuid_data.entries[cpuid_i++];
705 c->function = HYPERV_CPUID_INTERFACE;
706 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
707 c->eax = signature[0];
708 c->ebx = 0;
709 c->ecx = 0;
710 c->edx = 0;
711
712 c = &cpuid_data.entries[cpuid_i++];
713 c->function = HYPERV_CPUID_VERSION;
714 c->eax = 0x00001bbc;
715 c->ebx = 0x00060001;
716
717 c = &cpuid_data.entries[cpuid_i++];
718 c->function = HYPERV_CPUID_FEATURES;
719 r = hyperv_handle_properties(cs);
720 if (r) {
721 return r;
722 }
723 c->eax = env->features[FEAT_HYPERV_EAX];
724 c->ebx = env->features[FEAT_HYPERV_EBX];
725 c->edx = env->features[FEAT_HYPERV_EDX];
726
727 c = &cpuid_data.entries[cpuid_i++];
728 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
729 if (cpu->hyperv_relaxed_timing) {
730 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
731 }
732 if (has_msr_hv_vapic) {
733 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
734 }
735 c->ebx = cpu->hyperv_spinlock_attempts;
736
737 c = &cpuid_data.entries[cpuid_i++];
738 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
739 c->eax = 0x40;
740 c->ebx = 0x40;
741
742 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
743 has_msr_hv_hypercall = true;
744 }
745
746 if (cpu->expose_kvm) {
747 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
748 c = &cpuid_data.entries[cpuid_i++];
749 c->function = KVM_CPUID_SIGNATURE | kvm_base;
750 c->eax = KVM_CPUID_FEATURES | kvm_base;
751 c->ebx = signature[0];
752 c->ecx = signature[1];
753 c->edx = signature[2];
754
755 c = &cpuid_data.entries[cpuid_i++];
756 c->function = KVM_CPUID_FEATURES | kvm_base;
757 c->eax = env->features[FEAT_KVM];
758
759 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
760
761 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
762
763 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
764 }
765
766 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
767
768 for (i = 0; i <= limit; i++) {
769 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
770 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
771 abort();
772 }
773 c = &cpuid_data.entries[cpuid_i++];
774
775 switch (i) {
776 case 2: {
777 /* Keep reading function 2 till all the input is received */
778 int times;
779
780 c->function = i;
781 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
782 KVM_CPUID_FLAG_STATE_READ_NEXT;
783 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
784 times = c->eax & 0xff;
785
786 for (j = 1; j < times; ++j) {
787 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
788 fprintf(stderr, "cpuid_data is full, no space for "
789 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
790 abort();
791 }
792 c = &cpuid_data.entries[cpuid_i++];
793 c->function = i;
794 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
795 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
796 }
797 break;
798 }
799 case 4:
800 case 0xb:
801 case 0xd:
802 for (j = 0; ; j++) {
803 if (i == 0xd && j == 64) {
804 break;
805 }
806 c->function = i;
807 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
808 c->index = j;
809 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
810
811 if (i == 4 && c->eax == 0) {
812 break;
813 }
814 if (i == 0xb && !(c->ecx & 0xff00)) {
815 break;
816 }
817 if (i == 0xd && c->eax == 0) {
818 continue;
819 }
820 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
821 fprintf(stderr, "cpuid_data is full, no space for "
822 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
823 abort();
824 }
825 c = &cpuid_data.entries[cpuid_i++];
826 }
827 break;
828 default:
829 c->function = i;
830 c->flags = 0;
831 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
832 break;
833 }
834 }
835
836 if (limit >= 0x0a) {
837 uint32_t ver;
838
839 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
840 if ((ver & 0xff) > 0) {
841 has_msr_architectural_pmu = true;
842 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
843
844 /* Shouldn't be more than 32, since that's the number of bits
845 * available in EBX to tell us _which_ counters are available.
846 * Play it safe.
847 */
848 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
849 num_architectural_pmu_counters = MAX_GP_COUNTERS;
850 }
851 }
852 }
853
854 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
855
856 for (i = 0x80000000; i <= limit; i++) {
857 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
858 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
859 abort();
860 }
861 c = &cpuid_data.entries[cpuid_i++];
862
863 c->function = i;
864 c->flags = 0;
865 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
866 }
867
868 /* Call Centaur's CPUID instructions they are supported. */
869 if (env->cpuid_xlevel2 > 0) {
870 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
871
872 for (i = 0xC0000000; i <= limit; i++) {
873 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
874 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
875 abort();
876 }
877 c = &cpuid_data.entries[cpuid_i++];
878
879 c->function = i;
880 c->flags = 0;
881 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
882 }
883 }
884
885 cpuid_data.cpuid.nent = cpuid_i;
886
887 if (((env->cpuid_version >> 8)&0xF) >= 6
888 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
889 (CPUID_MCE | CPUID_MCA)
890 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
891 uint64_t mcg_cap, unsupported_caps;
892 int banks;
893 int ret;
894
895 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
896 if (ret < 0) {
897 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
898 return ret;
899 }
900
901 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
902 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
903 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
904 return -ENOTSUP;
905 }
906
907 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
908 if (unsupported_caps) {
909 if (unsupported_caps & MCG_LMCE_P) {
910 error_report("kvm: LMCE not supported");
911 return -ENOTSUP;
912 }
913 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
914 unsupported_caps);
915 }
916
917 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
918 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
919 if (ret < 0) {
920 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
921 return ret;
922 }
923 }
924
925 qemu_add_vm_change_state_handler(cpu_update_state, env);
926
927 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
928 if (c) {
929 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
930 !!(c->ecx & CPUID_EXT_SMX);
931 }
932
933 if (env->mcg_cap & MCG_LMCE_P) {
934 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
935 }
936
937 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
938 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
939 /* for migration */
940 error_setg(&invtsc_mig_blocker,
941 "State blocked by non-migratable CPU device"
942 " (invtsc flag)");
943 migrate_add_blocker(invtsc_mig_blocker);
944 /* for savevm */
945 vmstate_x86_cpu.unmigratable = 1;
946 }
947
948 cpuid_data.cpuid.padding = 0;
949 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
950 if (r) {
951 return r;
952 }
953
954 r = kvm_arch_set_tsc_khz(cs);
955 if (r < 0) {
956 return r;
957 }
958
959 /* vcpu's TSC frequency is either specified by user, or following
960 * the value used by KVM if the former is not present. In the
961 * latter case, we query it from KVM and record in env->tsc_khz,
962 * so that vcpu's TSC frequency can be migrated later via this field.
963 */
964 if (!env->tsc_khz) {
965 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
966 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
967 -ENOTSUP;
968 if (r > 0) {
969 env->tsc_khz = r;
970 }
971 }
972
973 if (has_xsave) {
974 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
975 }
976 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
977
978 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
979 has_msr_mtrr = true;
980 }
981 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
982 has_msr_tsc_aux = false;
983 }
984
985 return 0;
986 }
987
988 void kvm_arch_reset_vcpu(X86CPU *cpu)
989 {
990 CPUX86State *env = &cpu->env;
991
992 env->exception_injected = -1;
993 env->interrupt_injected = -1;
994 env->xcr0 = 1;
995 if (kvm_irqchip_in_kernel()) {
996 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
997 KVM_MP_STATE_UNINITIALIZED;
998 } else {
999 env->mp_state = KVM_MP_STATE_RUNNABLE;
1000 }
1001 }
1002
1003 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1004 {
1005 CPUX86State *env = &cpu->env;
1006
1007 /* APs get directly into wait-for-SIPI state. */
1008 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1009 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1010 }
1011 }
1012
1013 static int kvm_get_supported_msrs(KVMState *s)
1014 {
1015 static int kvm_supported_msrs;
1016 int ret = 0;
1017
1018 /* first time */
1019 if (kvm_supported_msrs == 0) {
1020 struct kvm_msr_list msr_list, *kvm_msr_list;
1021
1022 kvm_supported_msrs = -1;
1023
1024 /* Obtain MSR list from KVM. These are the MSRs that we must
1025 * save/restore */
1026 msr_list.nmsrs = 0;
1027 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1028 if (ret < 0 && ret != -E2BIG) {
1029 return ret;
1030 }
1031 /* Old kernel modules had a bug and could write beyond the provided
1032 memory. Allocate at least a safe amount of 1K. */
1033 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1034 msr_list.nmsrs *
1035 sizeof(msr_list.indices[0])));
1036
1037 kvm_msr_list->nmsrs = msr_list.nmsrs;
1038 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1039 if (ret >= 0) {
1040 int i;
1041
1042 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1043 if (kvm_msr_list->indices[i] == MSR_STAR) {
1044 has_msr_star = true;
1045 continue;
1046 }
1047 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
1048 has_msr_hsave_pa = true;
1049 continue;
1050 }
1051 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
1052 has_msr_tsc_aux = true;
1053 continue;
1054 }
1055 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
1056 has_msr_tsc_adjust = true;
1057 continue;
1058 }
1059 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1060 has_msr_tsc_deadline = true;
1061 continue;
1062 }
1063 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1064 has_msr_smbase = true;
1065 continue;
1066 }
1067 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1068 has_msr_misc_enable = true;
1069 continue;
1070 }
1071 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1072 has_msr_bndcfgs = true;
1073 continue;
1074 }
1075 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1076 has_msr_xss = true;
1077 continue;
1078 }
1079 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1080 has_msr_hv_crash = true;
1081 continue;
1082 }
1083 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1084 has_msr_hv_reset = true;
1085 continue;
1086 }
1087 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1088 has_msr_hv_vpindex = true;
1089 continue;
1090 }
1091 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1092 has_msr_hv_runtime = true;
1093 continue;
1094 }
1095 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1096 has_msr_hv_synic = true;
1097 continue;
1098 }
1099 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1100 has_msr_hv_stimer = true;
1101 continue;
1102 }
1103 }
1104 }
1105
1106 g_free(kvm_msr_list);
1107 }
1108
1109 return ret;
1110 }
1111
1112 static Notifier smram_machine_done;
1113 static KVMMemoryListener smram_listener;
1114 static AddressSpace smram_address_space;
1115 static MemoryRegion smram_as_root;
1116 static MemoryRegion smram_as_mem;
1117
1118 static void register_smram_listener(Notifier *n, void *unused)
1119 {
1120 MemoryRegion *smram =
1121 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1122
1123 /* Outer container... */
1124 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1125 memory_region_set_enabled(&smram_as_root, true);
1126
1127 /* ... with two regions inside: normal system memory with low
1128 * priority, and...
1129 */
1130 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1131 get_system_memory(), 0, ~0ull);
1132 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1133 memory_region_set_enabled(&smram_as_mem, true);
1134
1135 if (smram) {
1136 /* ... SMRAM with higher priority */
1137 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1138 memory_region_set_enabled(smram, true);
1139 }
1140
1141 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1142 kvm_memory_listener_register(kvm_state, &smram_listener,
1143 &smram_address_space, 1);
1144 }
1145
1146 int kvm_arch_init(MachineState *ms, KVMState *s)
1147 {
1148 uint64_t identity_base = 0xfffbc000;
1149 uint64_t shadow_mem;
1150 int ret;
1151 struct utsname utsname;
1152
1153 #ifdef KVM_CAP_XSAVE
1154 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1155 #endif
1156
1157 #ifdef KVM_CAP_XCRS
1158 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1159 #endif
1160
1161 #ifdef KVM_CAP_PIT_STATE2
1162 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1163 #endif
1164
1165 ret = kvm_get_supported_msrs(s);
1166 if (ret < 0) {
1167 return ret;
1168 }
1169
1170 uname(&utsname);
1171 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1172
1173 /*
1174 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1175 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1176 * Since these must be part of guest physical memory, we need to allocate
1177 * them, both by setting their start addresses in the kernel and by
1178 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1179 *
1180 * Older KVM versions may not support setting the identity map base. In
1181 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1182 * size.
1183 */
1184 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1185 /* Allows up to 16M BIOSes. */
1186 identity_base = 0xfeffc000;
1187
1188 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1189 if (ret < 0) {
1190 return ret;
1191 }
1192 }
1193
1194 /* Set TSS base one page after EPT identity map. */
1195 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1196 if (ret < 0) {
1197 return ret;
1198 }
1199
1200 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1201 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1202 if (ret < 0) {
1203 fprintf(stderr, "e820_add_entry() table is full\n");
1204 return ret;
1205 }
1206 qemu_register_reset(kvm_unpoison_all, NULL);
1207
1208 shadow_mem = machine_kvm_shadow_mem(ms);
1209 if (shadow_mem != -1) {
1210 shadow_mem /= 4096;
1211 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1212 if (ret < 0) {
1213 return ret;
1214 }
1215 }
1216
1217 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1218 smram_machine_done.notify = register_smram_listener;
1219 qemu_add_machine_init_done_notifier(&smram_machine_done);
1220 }
1221 return 0;
1222 }
1223
1224 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1225 {
1226 lhs->selector = rhs->selector;
1227 lhs->base = rhs->base;
1228 lhs->limit = rhs->limit;
1229 lhs->type = 3;
1230 lhs->present = 1;
1231 lhs->dpl = 3;
1232 lhs->db = 0;
1233 lhs->s = 1;
1234 lhs->l = 0;
1235 lhs->g = 0;
1236 lhs->avl = 0;
1237 lhs->unusable = 0;
1238 }
1239
1240 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1241 {
1242 unsigned flags = rhs->flags;
1243 lhs->selector = rhs->selector;
1244 lhs->base = rhs->base;
1245 lhs->limit = rhs->limit;
1246 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1247 lhs->present = (flags & DESC_P_MASK) != 0;
1248 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1249 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1250 lhs->s = (flags & DESC_S_MASK) != 0;
1251 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1252 lhs->g = (flags & DESC_G_MASK) != 0;
1253 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1254 lhs->unusable = !lhs->present;
1255 lhs->padding = 0;
1256 }
1257
1258 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1259 {
1260 lhs->selector = rhs->selector;
1261 lhs->base = rhs->base;
1262 lhs->limit = rhs->limit;
1263 if (rhs->unusable) {
1264 lhs->flags = 0;
1265 } else {
1266 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1267 (rhs->present * DESC_P_MASK) |
1268 (rhs->dpl << DESC_DPL_SHIFT) |
1269 (rhs->db << DESC_B_SHIFT) |
1270 (rhs->s * DESC_S_MASK) |
1271 (rhs->l << DESC_L_SHIFT) |
1272 (rhs->g * DESC_G_MASK) |
1273 (rhs->avl * DESC_AVL_MASK);
1274 }
1275 }
1276
1277 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1278 {
1279 if (set) {
1280 *kvm_reg = *qemu_reg;
1281 } else {
1282 *qemu_reg = *kvm_reg;
1283 }
1284 }
1285
1286 static int kvm_getput_regs(X86CPU *cpu, int set)
1287 {
1288 CPUX86State *env = &cpu->env;
1289 struct kvm_regs regs;
1290 int ret = 0;
1291
1292 if (!set) {
1293 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1294 if (ret < 0) {
1295 return ret;
1296 }
1297 }
1298
1299 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1300 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1301 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1302 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1303 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1304 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1305 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1306 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1307 #ifdef TARGET_X86_64
1308 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1309 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1310 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1311 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1312 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1313 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1314 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1315 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1316 #endif
1317
1318 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1319 kvm_getput_reg(&regs.rip, &env->eip, set);
1320
1321 if (set) {
1322 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1323 }
1324
1325 return ret;
1326 }
1327
1328 static int kvm_put_fpu(X86CPU *cpu)
1329 {
1330 CPUX86State *env = &cpu->env;
1331 struct kvm_fpu fpu;
1332 int i;
1333
1334 memset(&fpu, 0, sizeof fpu);
1335 fpu.fsw = env->fpus & ~(7 << 11);
1336 fpu.fsw |= (env->fpstt & 7) << 11;
1337 fpu.fcw = env->fpuc;
1338 fpu.last_opcode = env->fpop;
1339 fpu.last_ip = env->fpip;
1340 fpu.last_dp = env->fpdp;
1341 for (i = 0; i < 8; ++i) {
1342 fpu.ftwx |= (!env->fptags[i]) << i;
1343 }
1344 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1345 for (i = 0; i < CPU_NB_REGS; i++) {
1346 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1347 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1348 }
1349 fpu.mxcsr = env->mxcsr;
1350
1351 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1352 }
1353
1354 #define XSAVE_FCW_FSW 0
1355 #define XSAVE_FTW_FOP 1
1356 #define XSAVE_CWD_RIP 2
1357 #define XSAVE_CWD_RDP 4
1358 #define XSAVE_MXCSR 6
1359 #define XSAVE_ST_SPACE 8
1360 #define XSAVE_XMM_SPACE 40
1361 #define XSAVE_XSTATE_BV 128
1362 #define XSAVE_YMMH_SPACE 144
1363 #define XSAVE_BNDREGS 240
1364 #define XSAVE_BNDCSR 256
1365 #define XSAVE_OPMASK 272
1366 #define XSAVE_ZMM_Hi256 288
1367 #define XSAVE_Hi16_ZMM 416
1368 #define XSAVE_PKRU 672
1369
1370 #define XSAVE_BYTE_OFFSET(word_offset) \
1371 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1372
1373 #define ASSERT_OFFSET(word_offset, field) \
1374 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1375 offsetof(X86XSaveArea, field))
1376
1377 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1378 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1379 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1380 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1381 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1382 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1383 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1384 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1385 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1386 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1387 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1388 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1389 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1390 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1391 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1392
1393 static int kvm_put_xsave(X86CPU *cpu)
1394 {
1395 CPUX86State *env = &cpu->env;
1396 X86XSaveArea *xsave = env->kvm_xsave_buf;
1397 uint16_t cwd, swd, twd;
1398 int i;
1399
1400 if (!has_xsave) {
1401 return kvm_put_fpu(cpu);
1402 }
1403
1404 memset(xsave, 0, sizeof(struct kvm_xsave));
1405 twd = 0;
1406 swd = env->fpus & ~(7 << 11);
1407 swd |= (env->fpstt & 7) << 11;
1408 cwd = env->fpuc;
1409 for (i = 0; i < 8; ++i) {
1410 twd |= (!env->fptags[i]) << i;
1411 }
1412 xsave->legacy.fcw = cwd;
1413 xsave->legacy.fsw = swd;
1414 xsave->legacy.ftw = twd;
1415 xsave->legacy.fpop = env->fpop;
1416 xsave->legacy.fpip = env->fpip;
1417 xsave->legacy.fpdp = env->fpdp;
1418 memcpy(&xsave->legacy.fpregs, env->fpregs,
1419 sizeof env->fpregs);
1420 xsave->legacy.mxcsr = env->mxcsr;
1421 xsave->header.xstate_bv = env->xstate_bv;
1422 memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs,
1423 sizeof env->bnd_regs);
1424 xsave->bndcsr_state.bndcsr = env->bndcs_regs;
1425 memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs,
1426 sizeof env->opmask_regs);
1427
1428 for (i = 0; i < CPU_NB_REGS; i++) {
1429 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1430 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1431 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1432 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1433 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1434 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1435 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1436 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1437 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1438 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1439 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
1440 }
1441
1442 #ifdef TARGET_X86_64
1443 memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16],
1444 16 * sizeof env->xmm_regs[16]);
1445 memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru);
1446 #endif
1447 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1448 }
1449
1450 static int kvm_put_xcrs(X86CPU *cpu)
1451 {
1452 CPUX86State *env = &cpu->env;
1453 struct kvm_xcrs xcrs = {};
1454
1455 if (!has_xcrs) {
1456 return 0;
1457 }
1458
1459 xcrs.nr_xcrs = 1;
1460 xcrs.flags = 0;
1461 xcrs.xcrs[0].xcr = 0;
1462 xcrs.xcrs[0].value = env->xcr0;
1463 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1464 }
1465
1466 static int kvm_put_sregs(X86CPU *cpu)
1467 {
1468 CPUX86State *env = &cpu->env;
1469 struct kvm_sregs sregs;
1470
1471 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1472 if (env->interrupt_injected >= 0) {
1473 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1474 (uint64_t)1 << (env->interrupt_injected % 64);
1475 }
1476
1477 if ((env->eflags & VM_MASK)) {
1478 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1479 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1480 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1481 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1482 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1483 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1484 } else {
1485 set_seg(&sregs.cs, &env->segs[R_CS]);
1486 set_seg(&sregs.ds, &env->segs[R_DS]);
1487 set_seg(&sregs.es, &env->segs[R_ES]);
1488 set_seg(&sregs.fs, &env->segs[R_FS]);
1489 set_seg(&sregs.gs, &env->segs[R_GS]);
1490 set_seg(&sregs.ss, &env->segs[R_SS]);
1491 }
1492
1493 set_seg(&sregs.tr, &env->tr);
1494 set_seg(&sregs.ldt, &env->ldt);
1495
1496 sregs.idt.limit = env->idt.limit;
1497 sregs.idt.base = env->idt.base;
1498 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1499 sregs.gdt.limit = env->gdt.limit;
1500 sregs.gdt.base = env->gdt.base;
1501 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1502
1503 sregs.cr0 = env->cr[0];
1504 sregs.cr2 = env->cr[2];
1505 sregs.cr3 = env->cr[3];
1506 sregs.cr4 = env->cr[4];
1507
1508 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1509 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1510
1511 sregs.efer = env->efer;
1512
1513 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1514 }
1515
1516 static void kvm_msr_buf_reset(X86CPU *cpu)
1517 {
1518 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1519 }
1520
1521 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1522 {
1523 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1524 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1525 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1526
1527 assert((void *)(entry + 1) <= limit);
1528
1529 entry->index = index;
1530 entry->reserved = 0;
1531 entry->data = value;
1532 msrs->nmsrs++;
1533 }
1534
1535 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1536 {
1537 kvm_msr_buf_reset(cpu);
1538 kvm_msr_entry_add(cpu, index, value);
1539
1540 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1541 }
1542
1543 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1544 {
1545 int ret;
1546
1547 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1548 assert(ret == 1);
1549 }
1550
1551 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1552 {
1553 CPUX86State *env = &cpu->env;
1554 int ret;
1555
1556 if (!has_msr_tsc_deadline) {
1557 return 0;
1558 }
1559
1560 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1561 if (ret < 0) {
1562 return ret;
1563 }
1564
1565 assert(ret == 1);
1566 return 0;
1567 }
1568
1569 /*
1570 * Provide a separate write service for the feature control MSR in order to
1571 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1572 * before writing any other state because forcibly leaving nested mode
1573 * invalidates the VCPU state.
1574 */
1575 static int kvm_put_msr_feature_control(X86CPU *cpu)
1576 {
1577 int ret;
1578
1579 if (!has_msr_feature_control) {
1580 return 0;
1581 }
1582
1583 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1584 cpu->env.msr_ia32_feature_control);
1585 if (ret < 0) {
1586 return ret;
1587 }
1588
1589 assert(ret == 1);
1590 return 0;
1591 }
1592
1593 static int kvm_put_msrs(X86CPU *cpu, int level)
1594 {
1595 CPUX86State *env = &cpu->env;
1596 int i;
1597 int ret;
1598
1599 kvm_msr_buf_reset(cpu);
1600
1601 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1602 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1603 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1604 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1605 if (has_msr_star) {
1606 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1607 }
1608 if (has_msr_hsave_pa) {
1609 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1610 }
1611 if (has_msr_tsc_aux) {
1612 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1613 }
1614 if (has_msr_tsc_adjust) {
1615 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1616 }
1617 if (has_msr_misc_enable) {
1618 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1619 env->msr_ia32_misc_enable);
1620 }
1621 if (has_msr_smbase) {
1622 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1623 }
1624 if (has_msr_bndcfgs) {
1625 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1626 }
1627 if (has_msr_xss) {
1628 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1629 }
1630 #ifdef TARGET_X86_64
1631 if (lm_capable_kernel) {
1632 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1633 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1634 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1635 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1636 }
1637 #endif
1638 /*
1639 * The following MSRs have side effects on the guest or are too heavy
1640 * for normal writeback. Limit them to reset or full state updates.
1641 */
1642 if (level >= KVM_PUT_RESET_STATE) {
1643 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1644 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1645 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1646 if (has_msr_async_pf_en) {
1647 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1648 }
1649 if (has_msr_pv_eoi_en) {
1650 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
1651 }
1652 if (has_msr_kvm_steal_time) {
1653 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
1654 }
1655 if (has_msr_architectural_pmu) {
1656 /* Stop the counter. */
1657 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1658 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1659
1660 /* Set the counter values. */
1661 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1662 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
1663 env->msr_fixed_counters[i]);
1664 }
1665 for (i = 0; i < num_architectural_pmu_counters; i++) {
1666 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
1667 env->msr_gp_counters[i]);
1668 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
1669 env->msr_gp_evtsel[i]);
1670 }
1671 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1672 env->msr_global_status);
1673 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1674 env->msr_global_ovf_ctrl);
1675
1676 /* Now start the PMU. */
1677 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1678 env->msr_fixed_ctr_ctrl);
1679 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1680 env->msr_global_ctrl);
1681 }
1682 if (has_msr_hv_hypercall) {
1683 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1684 env->msr_hv_guest_os_id);
1685 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1686 env->msr_hv_hypercall);
1687 }
1688 if (has_msr_hv_vapic) {
1689 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
1690 env->msr_hv_vapic);
1691 }
1692 if (has_msr_hv_tsc) {
1693 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
1694 }
1695 if (has_msr_hv_crash) {
1696 int j;
1697
1698 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1699 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
1700 env->msr_hv_crash_params[j]);
1701
1702 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL,
1703 HV_X64_MSR_CRASH_CTL_NOTIFY);
1704 }
1705 if (has_msr_hv_runtime) {
1706 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
1707 }
1708 if (cpu->hyperv_synic) {
1709 int j;
1710
1711 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
1712 env->msr_hv_synic_control);
1713 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
1714 env->msr_hv_synic_version);
1715 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
1716 env->msr_hv_synic_evt_page);
1717 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
1718 env->msr_hv_synic_msg_page);
1719
1720 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1721 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
1722 env->msr_hv_synic_sint[j]);
1723 }
1724 }
1725 if (has_msr_hv_stimer) {
1726 int j;
1727
1728 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1729 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
1730 env->msr_hv_stimer_config[j]);
1731 }
1732
1733 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1734 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
1735 env->msr_hv_stimer_count[j]);
1736 }
1737 }
1738 if (has_msr_mtrr) {
1739 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1740
1741 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1742 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1743 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1744 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1745 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1746 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1747 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1748 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1749 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1750 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1751 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1752 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1753 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1754 /* The CPU GPs if we write to a bit above the physical limit of
1755 * the host CPU (and KVM emulates that)
1756 */
1757 uint64_t mask = env->mtrr_var[i].mask;
1758 mask &= phys_mask;
1759
1760 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1761 env->mtrr_var[i].base);
1762 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
1763 }
1764 }
1765
1766 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1767 * kvm_put_msr_feature_control. */
1768 }
1769 if (env->mcg_cap) {
1770 int i;
1771
1772 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1773 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
1774 if (has_msr_mcg_ext_ctl) {
1775 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1776 }
1777 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1778 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
1779 }
1780 }
1781
1782 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1783 if (ret < 0) {
1784 return ret;
1785 }
1786
1787 assert(ret == cpu->kvm_msr_buf->nmsrs);
1788 return 0;
1789 }
1790
1791
1792 static int kvm_get_fpu(X86CPU *cpu)
1793 {
1794 CPUX86State *env = &cpu->env;
1795 struct kvm_fpu fpu;
1796 int i, ret;
1797
1798 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1799 if (ret < 0) {
1800 return ret;
1801 }
1802
1803 env->fpstt = (fpu.fsw >> 11) & 7;
1804 env->fpus = fpu.fsw;
1805 env->fpuc = fpu.fcw;
1806 env->fpop = fpu.last_opcode;
1807 env->fpip = fpu.last_ip;
1808 env->fpdp = fpu.last_dp;
1809 for (i = 0; i < 8; ++i) {
1810 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1811 }
1812 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1813 for (i = 0; i < CPU_NB_REGS; i++) {
1814 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1815 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1816 }
1817 env->mxcsr = fpu.mxcsr;
1818
1819 return 0;
1820 }
1821
1822 static int kvm_get_xsave(X86CPU *cpu)
1823 {
1824 CPUX86State *env = &cpu->env;
1825 X86XSaveArea *xsave = env->kvm_xsave_buf;
1826 int ret, i;
1827 uint16_t cwd, swd, twd;
1828
1829 if (!has_xsave) {
1830 return kvm_get_fpu(cpu);
1831 }
1832
1833 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1834 if (ret < 0) {
1835 return ret;
1836 }
1837
1838 cwd = xsave->legacy.fcw;
1839 swd = xsave->legacy.fsw;
1840 twd = xsave->legacy.ftw;
1841 env->fpop = xsave->legacy.fpop;
1842 env->fpstt = (swd >> 11) & 7;
1843 env->fpus = swd;
1844 env->fpuc = cwd;
1845 for (i = 0; i < 8; ++i) {
1846 env->fptags[i] = !((twd >> i) & 1);
1847 }
1848 env->fpip = xsave->legacy.fpip;
1849 env->fpdp = xsave->legacy.fpdp;
1850 env->mxcsr = xsave->legacy.mxcsr;
1851 memcpy(env->fpregs, &xsave->legacy.fpregs,
1852 sizeof env->fpregs);
1853 env->xstate_bv = xsave->header.xstate_bv;
1854 memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs,
1855 sizeof env->bnd_regs);
1856 env->bndcs_regs = xsave->bndcsr_state.bndcsr;
1857 memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs,
1858 sizeof env->opmask_regs);
1859
1860 for (i = 0; i < CPU_NB_REGS; i++) {
1861 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1862 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1863 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1864 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1865 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1866 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1867 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1868 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1869 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1870 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1871 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
1872 }
1873
1874 #ifdef TARGET_X86_64
1875 memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm,
1876 16 * sizeof env->xmm_regs[16]);
1877 memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru);
1878 #endif
1879 return 0;
1880 }
1881
1882 static int kvm_get_xcrs(X86CPU *cpu)
1883 {
1884 CPUX86State *env = &cpu->env;
1885 int i, ret;
1886 struct kvm_xcrs xcrs;
1887
1888 if (!has_xcrs) {
1889 return 0;
1890 }
1891
1892 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1893 if (ret < 0) {
1894 return ret;
1895 }
1896
1897 for (i = 0; i < xcrs.nr_xcrs; i++) {
1898 /* Only support xcr0 now */
1899 if (xcrs.xcrs[i].xcr == 0) {
1900 env->xcr0 = xcrs.xcrs[i].value;
1901 break;
1902 }
1903 }
1904 return 0;
1905 }
1906
1907 static int kvm_get_sregs(X86CPU *cpu)
1908 {
1909 CPUX86State *env = &cpu->env;
1910 struct kvm_sregs sregs;
1911 uint32_t hflags;
1912 int bit, i, ret;
1913
1914 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1915 if (ret < 0) {
1916 return ret;
1917 }
1918
1919 /* There can only be one pending IRQ set in the bitmap at a time, so try
1920 to find it and save its number instead (-1 for none). */
1921 env->interrupt_injected = -1;
1922 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1923 if (sregs.interrupt_bitmap[i]) {
1924 bit = ctz64(sregs.interrupt_bitmap[i]);
1925 env->interrupt_injected = i * 64 + bit;
1926 break;
1927 }
1928 }
1929
1930 get_seg(&env->segs[R_CS], &sregs.cs);
1931 get_seg(&env->segs[R_DS], &sregs.ds);
1932 get_seg(&env->segs[R_ES], &sregs.es);
1933 get_seg(&env->segs[R_FS], &sregs.fs);
1934 get_seg(&env->segs[R_GS], &sregs.gs);
1935 get_seg(&env->segs[R_SS], &sregs.ss);
1936
1937 get_seg(&env->tr, &sregs.tr);
1938 get_seg(&env->ldt, &sregs.ldt);
1939
1940 env->idt.limit = sregs.idt.limit;
1941 env->idt.base = sregs.idt.base;
1942 env->gdt.limit = sregs.gdt.limit;
1943 env->gdt.base = sregs.gdt.base;
1944
1945 env->cr[0] = sregs.cr0;
1946 env->cr[2] = sregs.cr2;
1947 env->cr[3] = sregs.cr3;
1948 env->cr[4] = sregs.cr4;
1949
1950 env->efer = sregs.efer;
1951
1952 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1953
1954 #define HFLAG_COPY_MASK \
1955 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1956 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1957 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1958 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1959
1960 hflags = env->hflags & HFLAG_COPY_MASK;
1961 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1962 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1963 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1964 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1965 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1966
1967 if (env->cr[4] & CR4_OSFXSR_MASK) {
1968 hflags |= HF_OSFXSR_MASK;
1969 }
1970
1971 if (env->efer & MSR_EFER_LMA) {
1972 hflags |= HF_LMA_MASK;
1973 }
1974
1975 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1976 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1977 } else {
1978 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1979 (DESC_B_SHIFT - HF_CS32_SHIFT);
1980 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1981 (DESC_B_SHIFT - HF_SS32_SHIFT);
1982 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1983 !(hflags & HF_CS32_MASK)) {
1984 hflags |= HF_ADDSEG_MASK;
1985 } else {
1986 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1987 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1988 }
1989 }
1990 env->hflags = hflags;
1991
1992 return 0;
1993 }
1994
1995 static int kvm_get_msrs(X86CPU *cpu)
1996 {
1997 CPUX86State *env = &cpu->env;
1998 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
1999 int ret, i;
2000 uint64_t mtrr_top_bits;
2001
2002 kvm_msr_buf_reset(cpu);
2003
2004 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2005 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2006 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2007 kvm_msr_entry_add(cpu, MSR_PAT, 0);
2008 if (has_msr_star) {
2009 kvm_msr_entry_add(cpu, MSR_STAR, 0);
2010 }
2011 if (has_msr_hsave_pa) {
2012 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
2013 }
2014 if (has_msr_tsc_aux) {
2015 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
2016 }
2017 if (has_msr_tsc_adjust) {
2018 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
2019 }
2020 if (has_msr_tsc_deadline) {
2021 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
2022 }
2023 if (has_msr_misc_enable) {
2024 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
2025 }
2026 if (has_msr_smbase) {
2027 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2028 }
2029 if (has_msr_feature_control) {
2030 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2031 }
2032 if (has_msr_bndcfgs) {
2033 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2034 }
2035 if (has_msr_xss) {
2036 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2037 }
2038
2039
2040 if (!env->tsc_valid) {
2041 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2042 env->tsc_valid = !runstate_is_running();
2043 }
2044
2045 #ifdef TARGET_X86_64
2046 if (lm_capable_kernel) {
2047 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2048 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2049 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2050 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2051 }
2052 #endif
2053 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2054 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2055 if (has_msr_async_pf_en) {
2056 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2057 }
2058 if (has_msr_pv_eoi_en) {
2059 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2060 }
2061 if (has_msr_kvm_steal_time) {
2062 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2063 }
2064 if (has_msr_architectural_pmu) {
2065 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2066 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2067 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2068 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2069 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
2070 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2071 }
2072 for (i = 0; i < num_architectural_pmu_counters; i++) {
2073 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2074 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2075 }
2076 }
2077
2078 if (env->mcg_cap) {
2079 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2080 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2081 if (has_msr_mcg_ext_ctl) {
2082 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2083 }
2084 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2085 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2086 }
2087 }
2088
2089 if (has_msr_hv_hypercall) {
2090 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2091 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2092 }
2093 if (has_msr_hv_vapic) {
2094 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2095 }
2096 if (has_msr_hv_tsc) {
2097 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2098 }
2099 if (has_msr_hv_crash) {
2100 int j;
2101
2102 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
2103 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2104 }
2105 }
2106 if (has_msr_hv_runtime) {
2107 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2108 }
2109 if (cpu->hyperv_synic) {
2110 uint32_t msr;
2111
2112 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2113 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2114 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2115 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2116 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2117 kvm_msr_entry_add(cpu, msr, 0);
2118 }
2119 }
2120 if (has_msr_hv_stimer) {
2121 uint32_t msr;
2122
2123 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2124 msr++) {
2125 kvm_msr_entry_add(cpu, msr, 0);
2126 }
2127 }
2128 if (has_msr_mtrr) {
2129 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2130 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2131 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2132 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2133 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2134 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2135 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2136 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2137 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2138 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2139 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2140 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2141 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2142 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2143 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2144 }
2145 }
2146
2147 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2148 if (ret < 0) {
2149 return ret;
2150 }
2151
2152 assert(ret == cpu->kvm_msr_buf->nmsrs);
2153 /*
2154 * MTRR masks: Each mask consists of 5 parts
2155 * a 10..0: must be zero
2156 * b 11 : valid bit
2157 * c n-1.12: actual mask bits
2158 * d 51..n: reserved must be zero
2159 * e 63.52: reserved must be zero
2160 *
2161 * 'n' is the number of physical bits supported by the CPU and is
2162 * apparently always <= 52. We know our 'n' but don't know what
2163 * the destinations 'n' is; it might be smaller, in which case
2164 * it masks (c) on loading. It might be larger, in which case
2165 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2166 * we're migrating to.
2167 */
2168
2169 if (cpu->fill_mtrr_mask) {
2170 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2171 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2172 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2173 } else {
2174 mtrr_top_bits = 0;
2175 }
2176
2177 for (i = 0; i < ret; i++) {
2178 uint32_t index = msrs[i].index;
2179 switch (index) {
2180 case MSR_IA32_SYSENTER_CS:
2181 env->sysenter_cs = msrs[i].data;
2182 break;
2183 case MSR_IA32_SYSENTER_ESP:
2184 env->sysenter_esp = msrs[i].data;
2185 break;
2186 case MSR_IA32_SYSENTER_EIP:
2187 env->sysenter_eip = msrs[i].data;
2188 break;
2189 case MSR_PAT:
2190 env->pat = msrs[i].data;
2191 break;
2192 case MSR_STAR:
2193 env->star = msrs[i].data;
2194 break;
2195 #ifdef TARGET_X86_64
2196 case MSR_CSTAR:
2197 env->cstar = msrs[i].data;
2198 break;
2199 case MSR_KERNELGSBASE:
2200 env->kernelgsbase = msrs[i].data;
2201 break;
2202 case MSR_FMASK:
2203 env->fmask = msrs[i].data;
2204 break;
2205 case MSR_LSTAR:
2206 env->lstar = msrs[i].data;
2207 break;
2208 #endif
2209 case MSR_IA32_TSC:
2210 env->tsc = msrs[i].data;
2211 break;
2212 case MSR_TSC_AUX:
2213 env->tsc_aux = msrs[i].data;
2214 break;
2215 case MSR_TSC_ADJUST:
2216 env->tsc_adjust = msrs[i].data;
2217 break;
2218 case MSR_IA32_TSCDEADLINE:
2219 env->tsc_deadline = msrs[i].data;
2220 break;
2221 case MSR_VM_HSAVE_PA:
2222 env->vm_hsave = msrs[i].data;
2223 break;
2224 case MSR_KVM_SYSTEM_TIME:
2225 env->system_time_msr = msrs[i].data;
2226 break;
2227 case MSR_KVM_WALL_CLOCK:
2228 env->wall_clock_msr = msrs[i].data;
2229 break;
2230 case MSR_MCG_STATUS:
2231 env->mcg_status = msrs[i].data;
2232 break;
2233 case MSR_MCG_CTL:
2234 env->mcg_ctl = msrs[i].data;
2235 break;
2236 case MSR_MCG_EXT_CTL:
2237 env->mcg_ext_ctl = msrs[i].data;
2238 break;
2239 case MSR_IA32_MISC_ENABLE:
2240 env->msr_ia32_misc_enable = msrs[i].data;
2241 break;
2242 case MSR_IA32_SMBASE:
2243 env->smbase = msrs[i].data;
2244 break;
2245 case MSR_IA32_FEATURE_CONTROL:
2246 env->msr_ia32_feature_control = msrs[i].data;
2247 break;
2248 case MSR_IA32_BNDCFGS:
2249 env->msr_bndcfgs = msrs[i].data;
2250 break;
2251 case MSR_IA32_XSS:
2252 env->xss = msrs[i].data;
2253 break;
2254 default:
2255 if (msrs[i].index >= MSR_MC0_CTL &&
2256 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2257 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2258 }
2259 break;
2260 case MSR_KVM_ASYNC_PF_EN:
2261 env->async_pf_en_msr = msrs[i].data;
2262 break;
2263 case MSR_KVM_PV_EOI_EN:
2264 env->pv_eoi_en_msr = msrs[i].data;
2265 break;
2266 case MSR_KVM_STEAL_TIME:
2267 env->steal_time_msr = msrs[i].data;
2268 break;
2269 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2270 env->msr_fixed_ctr_ctrl = msrs[i].data;
2271 break;
2272 case MSR_CORE_PERF_GLOBAL_CTRL:
2273 env->msr_global_ctrl = msrs[i].data;
2274 break;
2275 case MSR_CORE_PERF_GLOBAL_STATUS:
2276 env->msr_global_status = msrs[i].data;
2277 break;
2278 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2279 env->msr_global_ovf_ctrl = msrs[i].data;
2280 break;
2281 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2282 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2283 break;
2284 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2285 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2286 break;
2287 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2288 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2289 break;
2290 case HV_X64_MSR_HYPERCALL:
2291 env->msr_hv_hypercall = msrs[i].data;
2292 break;
2293 case HV_X64_MSR_GUEST_OS_ID:
2294 env->msr_hv_guest_os_id = msrs[i].data;
2295 break;
2296 case HV_X64_MSR_APIC_ASSIST_PAGE:
2297 env->msr_hv_vapic = msrs[i].data;
2298 break;
2299 case HV_X64_MSR_REFERENCE_TSC:
2300 env->msr_hv_tsc = msrs[i].data;
2301 break;
2302 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2303 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2304 break;
2305 case HV_X64_MSR_VP_RUNTIME:
2306 env->msr_hv_runtime = msrs[i].data;
2307 break;
2308 case HV_X64_MSR_SCONTROL:
2309 env->msr_hv_synic_control = msrs[i].data;
2310 break;
2311 case HV_X64_MSR_SVERSION:
2312 env->msr_hv_synic_version = msrs[i].data;
2313 break;
2314 case HV_X64_MSR_SIEFP:
2315 env->msr_hv_synic_evt_page = msrs[i].data;
2316 break;
2317 case HV_X64_MSR_SIMP:
2318 env->msr_hv_synic_msg_page = msrs[i].data;
2319 break;
2320 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2321 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2322 break;
2323 case HV_X64_MSR_STIMER0_CONFIG:
2324 case HV_X64_MSR_STIMER1_CONFIG:
2325 case HV_X64_MSR_STIMER2_CONFIG:
2326 case HV_X64_MSR_STIMER3_CONFIG:
2327 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2328 msrs[i].data;
2329 break;
2330 case HV_X64_MSR_STIMER0_COUNT:
2331 case HV_X64_MSR_STIMER1_COUNT:
2332 case HV_X64_MSR_STIMER2_COUNT:
2333 case HV_X64_MSR_STIMER3_COUNT:
2334 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2335 msrs[i].data;
2336 break;
2337 case MSR_MTRRdefType:
2338 env->mtrr_deftype = msrs[i].data;
2339 break;
2340 case MSR_MTRRfix64K_00000:
2341 env->mtrr_fixed[0] = msrs[i].data;
2342 break;
2343 case MSR_MTRRfix16K_80000:
2344 env->mtrr_fixed[1] = msrs[i].data;
2345 break;
2346 case MSR_MTRRfix16K_A0000:
2347 env->mtrr_fixed[2] = msrs[i].data;
2348 break;
2349 case MSR_MTRRfix4K_C0000:
2350 env->mtrr_fixed[3] = msrs[i].data;
2351 break;
2352 case MSR_MTRRfix4K_C8000:
2353 env->mtrr_fixed[4] = msrs[i].data;
2354 break;
2355 case MSR_MTRRfix4K_D0000:
2356 env->mtrr_fixed[5] = msrs[i].data;
2357 break;
2358 case MSR_MTRRfix4K_D8000:
2359 env->mtrr_fixed[6] = msrs[i].data;
2360 break;
2361 case MSR_MTRRfix4K_E0000:
2362 env->mtrr_fixed[7] = msrs[i].data;
2363 break;
2364 case MSR_MTRRfix4K_E8000:
2365 env->mtrr_fixed[8] = msrs[i].data;
2366 break;
2367 case MSR_MTRRfix4K_F0000:
2368 env->mtrr_fixed[9] = msrs[i].data;
2369 break;
2370 case MSR_MTRRfix4K_F8000:
2371 env->mtrr_fixed[10] = msrs[i].data;
2372 break;
2373 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2374 if (index & 1) {
2375 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2376 mtrr_top_bits;
2377 } else {
2378 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2379 }
2380 break;
2381 }
2382 }
2383
2384 return 0;
2385 }
2386
2387 static int kvm_put_mp_state(X86CPU *cpu)
2388 {
2389 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2390
2391 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2392 }
2393
2394 static int kvm_get_mp_state(X86CPU *cpu)
2395 {
2396 CPUState *cs = CPU(cpu);
2397 CPUX86State *env = &cpu->env;
2398 struct kvm_mp_state mp_state;
2399 int ret;
2400
2401 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2402 if (ret < 0) {
2403 return ret;
2404 }
2405 env->mp_state = mp_state.mp_state;
2406 if (kvm_irqchip_in_kernel()) {
2407 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2408 }
2409 return 0;
2410 }
2411
2412 static int kvm_get_apic(X86CPU *cpu)
2413 {
2414 DeviceState *apic = cpu->apic_state;
2415 struct kvm_lapic_state kapic;
2416 int ret;
2417
2418 if (apic && kvm_irqchip_in_kernel()) {
2419 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2420 if (ret < 0) {
2421 return ret;
2422 }
2423
2424 kvm_get_apic_state(apic, &kapic);
2425 }
2426 return 0;
2427 }
2428
2429 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2430 {
2431 CPUState *cs = CPU(cpu);
2432 CPUX86State *env = &cpu->env;
2433 struct kvm_vcpu_events events = {};
2434
2435 if (!kvm_has_vcpu_events()) {
2436 return 0;
2437 }
2438
2439 events.exception.injected = (env->exception_injected >= 0);
2440 events.exception.nr = env->exception_injected;
2441 events.exception.has_error_code = env->has_error_code;
2442 events.exception.error_code = env->error_code;
2443 events.exception.pad = 0;
2444
2445 events.interrupt.injected = (env->interrupt_injected >= 0);
2446 events.interrupt.nr = env->interrupt_injected;
2447 events.interrupt.soft = env->soft_interrupt;
2448
2449 events.nmi.injected = env->nmi_injected;
2450 events.nmi.pending = env->nmi_pending;
2451 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2452 events.nmi.pad = 0;
2453
2454 events.sipi_vector = env->sipi_vector;
2455 events.flags = 0;
2456
2457 if (has_msr_smbase) {
2458 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2459 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2460 if (kvm_irqchip_in_kernel()) {
2461 /* As soon as these are moved to the kernel, remove them
2462 * from cs->interrupt_request.
2463 */
2464 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2465 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2466 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2467 } else {
2468 /* Keep these in cs->interrupt_request. */
2469 events.smi.pending = 0;
2470 events.smi.latched_init = 0;
2471 }
2472 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2473 }
2474
2475 if (level >= KVM_PUT_RESET_STATE) {
2476 events.flags |=
2477 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2478 }
2479
2480 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2481 }
2482
2483 static int kvm_get_vcpu_events(X86CPU *cpu)
2484 {
2485 CPUX86State *env = &cpu->env;
2486 struct kvm_vcpu_events events;
2487 int ret;
2488
2489 if (!kvm_has_vcpu_events()) {
2490 return 0;
2491 }
2492
2493 memset(&events, 0, sizeof(events));
2494 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2495 if (ret < 0) {
2496 return ret;
2497 }
2498 env->exception_injected =
2499 events.exception.injected ? events.exception.nr : -1;
2500 env->has_error_code = events.exception.has_error_code;
2501 env->error_code = events.exception.error_code;
2502
2503 env->interrupt_injected =
2504 events.interrupt.injected ? events.interrupt.nr : -1;
2505 env->soft_interrupt = events.interrupt.soft;
2506
2507 env->nmi_injected = events.nmi.injected;
2508 env->nmi_pending = events.nmi.pending;
2509 if (events.nmi.masked) {
2510 env->hflags2 |= HF2_NMI_MASK;
2511 } else {
2512 env->hflags2 &= ~HF2_NMI_MASK;
2513 }
2514
2515 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2516 if (events.smi.smm) {
2517 env->hflags |= HF_SMM_MASK;
2518 } else {
2519 env->hflags &= ~HF_SMM_MASK;
2520 }
2521 if (events.smi.pending) {
2522 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2523 } else {
2524 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2525 }
2526 if (events.smi.smm_inside_nmi) {
2527 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2528 } else {
2529 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2530 }
2531 if (events.smi.latched_init) {
2532 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2533 } else {
2534 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2535 }
2536 }
2537
2538 env->sipi_vector = events.sipi_vector;
2539
2540 return 0;
2541 }
2542
2543 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2544 {
2545 CPUState *cs = CPU(cpu);
2546 CPUX86State *env = &cpu->env;
2547 int ret = 0;
2548 unsigned long reinject_trap = 0;
2549
2550 if (!kvm_has_vcpu_events()) {
2551 if (env->exception_injected == 1) {
2552 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2553 } else if (env->exception_injected == 3) {
2554 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2555 }
2556 env->exception_injected = -1;
2557 }
2558
2559 /*
2560 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2561 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2562 * by updating the debug state once again if single-stepping is on.
2563 * Another reason to call kvm_update_guest_debug here is a pending debug
2564 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2565 * reinject them via SET_GUEST_DEBUG.
2566 */
2567 if (reinject_trap ||
2568 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2569 ret = kvm_update_guest_debug(cs, reinject_trap);
2570 }
2571 return ret;
2572 }
2573
2574 static int kvm_put_debugregs(X86CPU *cpu)
2575 {
2576 CPUX86State *env = &cpu->env;
2577 struct kvm_debugregs dbgregs;
2578 int i;
2579
2580 if (!kvm_has_debugregs()) {
2581 return 0;
2582 }
2583
2584 for (i = 0; i < 4; i++) {
2585 dbgregs.db[i] = env->dr[i];
2586 }
2587 dbgregs.dr6 = env->dr[6];
2588 dbgregs.dr7 = env->dr[7];
2589 dbgregs.flags = 0;
2590
2591 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2592 }
2593
2594 static int kvm_get_debugregs(X86CPU *cpu)
2595 {
2596 CPUX86State *env = &cpu->env;
2597 struct kvm_debugregs dbgregs;
2598 int i, ret;
2599
2600 if (!kvm_has_debugregs()) {
2601 return 0;
2602 }
2603
2604 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2605 if (ret < 0) {
2606 return ret;
2607 }
2608 for (i = 0; i < 4; i++) {
2609 env->dr[i] = dbgregs.db[i];
2610 }
2611 env->dr[4] = env->dr[6] = dbgregs.dr6;
2612 env->dr[5] = env->dr[7] = dbgregs.dr7;
2613
2614 return 0;
2615 }
2616
2617 int kvm_arch_put_registers(CPUState *cpu, int level)
2618 {
2619 X86CPU *x86_cpu = X86_CPU(cpu);
2620 int ret;
2621
2622 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2623
2624 if (level >= KVM_PUT_RESET_STATE) {
2625 ret = kvm_put_msr_feature_control(x86_cpu);
2626 if (ret < 0) {
2627 return ret;
2628 }
2629 }
2630
2631 if (level == KVM_PUT_FULL_STATE) {
2632 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2633 * because TSC frequency mismatch shouldn't abort migration,
2634 * unless the user explicitly asked for a more strict TSC
2635 * setting (e.g. using an explicit "tsc-freq" option).
2636 */
2637 kvm_arch_set_tsc_khz(cpu);
2638 }
2639
2640 ret = kvm_getput_regs(x86_cpu, 1);
2641 if (ret < 0) {
2642 return ret;
2643 }
2644 ret = kvm_put_xsave(x86_cpu);
2645 if (ret < 0) {
2646 return ret;
2647 }
2648 ret = kvm_put_xcrs(x86_cpu);
2649 if (ret < 0) {
2650 return ret;
2651 }
2652 ret = kvm_put_sregs(x86_cpu);
2653 if (ret < 0) {
2654 return ret;
2655 }
2656 /* must be before kvm_put_msrs */
2657 ret = kvm_inject_mce_oldstyle(x86_cpu);
2658 if (ret < 0) {
2659 return ret;
2660 }
2661 ret = kvm_put_msrs(x86_cpu, level);
2662 if (ret < 0) {
2663 return ret;
2664 }
2665 if (level >= KVM_PUT_RESET_STATE) {
2666 ret = kvm_put_mp_state(x86_cpu);
2667 if (ret < 0) {
2668 return ret;
2669 }
2670 }
2671
2672 ret = kvm_put_tscdeadline_msr(x86_cpu);
2673 if (ret < 0) {
2674 return ret;
2675 }
2676
2677 ret = kvm_put_vcpu_events(x86_cpu, level);
2678 if (ret < 0) {
2679 return ret;
2680 }
2681 ret = kvm_put_debugregs(x86_cpu);
2682 if (ret < 0) {
2683 return ret;
2684 }
2685 /* must be last */
2686 ret = kvm_guest_debug_workarounds(x86_cpu);
2687 if (ret < 0) {
2688 return ret;
2689 }
2690 return 0;
2691 }
2692
2693 int kvm_arch_get_registers(CPUState *cs)
2694 {
2695 X86CPU *cpu = X86_CPU(cs);
2696 int ret;
2697
2698 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2699
2700 ret = kvm_getput_regs(cpu, 0);
2701 if (ret < 0) {
2702 goto out;
2703 }
2704 ret = kvm_get_xsave(cpu);
2705 if (ret < 0) {
2706 goto out;
2707 }
2708 ret = kvm_get_xcrs(cpu);
2709 if (ret < 0) {
2710 goto out;
2711 }
2712 ret = kvm_get_sregs(cpu);
2713 if (ret < 0) {
2714 goto out;
2715 }
2716 ret = kvm_get_msrs(cpu);
2717 if (ret < 0) {
2718 goto out;
2719 }
2720 ret = kvm_get_mp_state(cpu);
2721 if (ret < 0) {
2722 goto out;
2723 }
2724 ret = kvm_get_apic(cpu);
2725 if (ret < 0) {
2726 goto out;
2727 }
2728 ret = kvm_get_vcpu_events(cpu);
2729 if (ret < 0) {
2730 goto out;
2731 }
2732 ret = kvm_get_debugregs(cpu);
2733 if (ret < 0) {
2734 goto out;
2735 }
2736 ret = 0;
2737 out:
2738 cpu_sync_bndcs_hflags(&cpu->env);
2739 return ret;
2740 }
2741
2742 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2743 {
2744 X86CPU *x86_cpu = X86_CPU(cpu);
2745 CPUX86State *env = &x86_cpu->env;
2746 int ret;
2747
2748 /* Inject NMI */
2749 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2750 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2751 qemu_mutex_lock_iothread();
2752 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2753 qemu_mutex_unlock_iothread();
2754 DPRINTF("injected NMI\n");
2755 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2756 if (ret < 0) {
2757 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2758 strerror(-ret));
2759 }
2760 }
2761 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2762 qemu_mutex_lock_iothread();
2763 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2764 qemu_mutex_unlock_iothread();
2765 DPRINTF("injected SMI\n");
2766 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2767 if (ret < 0) {
2768 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2769 strerror(-ret));
2770 }
2771 }
2772 }
2773
2774 if (!kvm_pic_in_kernel()) {
2775 qemu_mutex_lock_iothread();
2776 }
2777
2778 /* Force the VCPU out of its inner loop to process any INIT requests
2779 * or (for userspace APIC, but it is cheap to combine the checks here)
2780 * pending TPR access reports.
2781 */
2782 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2783 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2784 !(env->hflags & HF_SMM_MASK)) {
2785 cpu->exit_request = 1;
2786 }
2787 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2788 cpu->exit_request = 1;
2789 }
2790 }
2791
2792 if (!kvm_pic_in_kernel()) {
2793 /* Try to inject an interrupt if the guest can accept it */
2794 if (run->ready_for_interrupt_injection &&
2795 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2796 (env->eflags & IF_MASK)) {
2797 int irq;
2798
2799 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2800 irq = cpu_get_pic_interrupt(env);
2801 if (irq >= 0) {
2802 struct kvm_interrupt intr;
2803
2804 intr.irq = irq;
2805 DPRINTF("injected interrupt %d\n", irq);
2806 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2807 if (ret < 0) {
2808 fprintf(stderr,
2809 "KVM: injection failed, interrupt lost (%s)\n",
2810 strerror(-ret));
2811 }
2812 }
2813 }
2814
2815 /* If we have an interrupt but the guest is not ready to receive an
2816 * interrupt, request an interrupt window exit. This will
2817 * cause a return to userspace as soon as the guest is ready to
2818 * receive interrupts. */
2819 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2820 run->request_interrupt_window = 1;
2821 } else {
2822 run->request_interrupt_window = 0;
2823 }
2824
2825 DPRINTF("setting tpr\n");
2826 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2827
2828 qemu_mutex_unlock_iothread();
2829 }
2830 }
2831
2832 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2833 {
2834 X86CPU *x86_cpu = X86_CPU(cpu);
2835 CPUX86State *env = &x86_cpu->env;
2836
2837 if (run->flags & KVM_RUN_X86_SMM) {
2838 env->hflags |= HF_SMM_MASK;
2839 } else {
2840 env->hflags &= HF_SMM_MASK;
2841 }
2842 if (run->if_flag) {
2843 env->eflags |= IF_MASK;
2844 } else {
2845 env->eflags &= ~IF_MASK;
2846 }
2847
2848 /* We need to protect the apic state against concurrent accesses from
2849 * different threads in case the userspace irqchip is used. */
2850 if (!kvm_irqchip_in_kernel()) {
2851 qemu_mutex_lock_iothread();
2852 }
2853 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2854 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2855 if (!kvm_irqchip_in_kernel()) {
2856 qemu_mutex_unlock_iothread();
2857 }
2858 return cpu_get_mem_attrs(env);
2859 }
2860
2861 int kvm_arch_process_async_events(CPUState *cs)
2862 {
2863 X86CPU *cpu = X86_CPU(cs);
2864 CPUX86State *env = &cpu->env;
2865
2866 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2867 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2868 assert(env->mcg_cap);
2869
2870 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2871
2872 kvm_cpu_synchronize_state(cs);
2873
2874 if (env->exception_injected == EXCP08_DBLE) {
2875 /* this means triple fault */
2876 qemu_system_reset_request();
2877 cs->exit_request = 1;
2878 return 0;
2879 }
2880 env->exception_injected = EXCP12_MCHK;
2881 env->has_error_code = 0;
2882
2883 cs->halted = 0;
2884 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2885 env->mp_state = KVM_MP_STATE_RUNNABLE;
2886 }
2887 }
2888
2889 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2890 !(env->hflags & HF_SMM_MASK)) {
2891 kvm_cpu_synchronize_state(cs);
2892 do_cpu_init(cpu);
2893 }
2894
2895 if (kvm_irqchip_in_kernel()) {
2896 return 0;
2897 }
2898
2899 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2900 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2901 apic_poll_irq(cpu->apic_state);
2902 }
2903 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2904 (env->eflags & IF_MASK)) ||
2905 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2906 cs->halted = 0;
2907 }
2908 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2909 kvm_cpu_synchronize_state(cs);
2910 do_cpu_sipi(cpu);
2911 }
2912 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2913 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2914 kvm_cpu_synchronize_state(cs);
2915 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2916 env->tpr_access_type);
2917 }
2918
2919 return cs->halted;
2920 }
2921
2922 static int kvm_handle_halt(X86CPU *cpu)
2923 {
2924 CPUState *cs = CPU(cpu);
2925 CPUX86State *env = &cpu->env;
2926
2927 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2928 (env->eflags & IF_MASK)) &&
2929 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2930 cs->halted = 1;
2931 return EXCP_HLT;
2932 }
2933
2934 return 0;
2935 }
2936
2937 static int kvm_handle_tpr_access(X86CPU *cpu)
2938 {
2939 CPUState *cs = CPU(cpu);
2940 struct kvm_run *run = cs->kvm_run;
2941
2942 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2943 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2944 : TPR_ACCESS_READ);
2945 return 1;
2946 }
2947
2948 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2949 {
2950 static const uint8_t int3 = 0xcc;
2951
2952 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2953 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2954 return -EINVAL;
2955 }
2956 return 0;
2957 }
2958
2959 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2960 {
2961 uint8_t int3;
2962
2963 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2964 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2965 return -EINVAL;
2966 }
2967 return 0;
2968 }
2969
2970 static struct {
2971 target_ulong addr;
2972 int len;
2973 int type;
2974 } hw_breakpoint[4];
2975
2976 static int nb_hw_breakpoint;
2977
2978 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2979 {
2980 int n;
2981
2982 for (n = 0; n < nb_hw_breakpoint; n++) {
2983 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2984 (hw_breakpoint[n].len == len || len == -1)) {
2985 return n;
2986 }
2987 }
2988 return -1;
2989 }
2990
2991 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2992 target_ulong len, int type)
2993 {
2994 switch (type) {
2995 case GDB_BREAKPOINT_HW:
2996 len = 1;
2997 break;
2998 case GDB_WATCHPOINT_WRITE:
2999 case GDB_WATCHPOINT_ACCESS:
3000 switch (len) {
3001 case 1:
3002 break;
3003 case 2:
3004 case 4:
3005 case 8:
3006 if (addr & (len - 1)) {
3007 return -EINVAL;
3008 }
3009 break;
3010 default:
3011 return -EINVAL;
3012 }
3013 break;
3014 default:
3015 return -ENOSYS;
3016 }
3017
3018 if (nb_hw_breakpoint == 4) {
3019 return -ENOBUFS;
3020 }
3021 if (find_hw_breakpoint(addr, len, type) >= 0) {
3022 return -EEXIST;
3023 }
3024 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3025 hw_breakpoint[nb_hw_breakpoint].len = len;
3026 hw_breakpoint[nb_hw_breakpoint].type = type;
3027 nb_hw_breakpoint++;
3028
3029 return 0;
3030 }
3031
3032 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3033 target_ulong len, int type)
3034 {
3035 int n;
3036
3037 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3038 if (n < 0) {
3039 return -ENOENT;
3040 }
3041 nb_hw_breakpoint--;
3042 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3043
3044 return 0;
3045 }
3046
3047 void kvm_arch_remove_all_hw_breakpoints(void)
3048 {
3049 nb_hw_breakpoint = 0;
3050 }
3051
3052 static CPUWatchpoint hw_watchpoint;
3053
3054 static int kvm_handle_debug(X86CPU *cpu,
3055 struct kvm_debug_exit_arch *arch_info)
3056 {
3057 CPUState *cs = CPU(cpu);
3058 CPUX86State *env = &cpu->env;
3059 int ret = 0;
3060 int n;
3061
3062 if (arch_info->exception == 1) {
3063 if (arch_info->dr6 & (1 << 14)) {
3064 if (cs->singlestep_enabled) {
3065 ret = EXCP_DEBUG;
3066 }
3067 } else {
3068 for (n = 0; n < 4; n++) {
3069 if (arch_info->dr6 & (1 << n)) {
3070 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3071 case 0x0:
3072 ret = EXCP_DEBUG;
3073 break;
3074 case 0x1:
3075 ret = EXCP_DEBUG;
3076 cs->watchpoint_hit = &hw_watchpoint;
3077 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3078 hw_watchpoint.flags = BP_MEM_WRITE;
3079 break;
3080 case 0x3:
3081 ret = EXCP_DEBUG;
3082 cs->watchpoint_hit = &hw_watchpoint;
3083 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3084 hw_watchpoint.flags = BP_MEM_ACCESS;
3085 break;
3086 }
3087 }
3088 }
3089 }
3090 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3091 ret = EXCP_DEBUG;
3092 }
3093 if (ret == 0) {
3094 cpu_synchronize_state(cs);
3095 assert(env->exception_injected == -1);
3096
3097 /* pass to guest */
3098 env->exception_injected = arch_info->exception;
3099 env->has_error_code = 0;
3100 }
3101
3102 return ret;
3103 }
3104
3105 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3106 {
3107 const uint8_t type_code[] = {
3108 [GDB_BREAKPOINT_HW] = 0x0,
3109 [GDB_WATCHPOINT_WRITE] = 0x1,
3110 [GDB_WATCHPOINT_ACCESS] = 0x3
3111 };
3112 const uint8_t len_code[] = {
3113 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3114 };
3115 int n;
3116
3117 if (kvm_sw_breakpoints_active(cpu)) {
3118 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3119 }
3120 if (nb_hw_breakpoint > 0) {
3121 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3122 dbg->arch.debugreg[7] = 0x0600;
3123 for (n = 0; n < nb_hw_breakpoint; n++) {
3124 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3125 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3126 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3127 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3128 }
3129 }
3130 }
3131
3132 static bool host_supports_vmx(void)
3133 {
3134 uint32_t ecx, unused;
3135
3136 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3137 return ecx & CPUID_EXT_VMX;
3138 }
3139
3140 #define VMX_INVALID_GUEST_STATE 0x80000021
3141
3142 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3143 {
3144 X86CPU *cpu = X86_CPU(cs);
3145 uint64_t code;
3146 int ret;
3147
3148 switch (run->exit_reason) {
3149 case KVM_EXIT_HLT:
3150 DPRINTF("handle_hlt\n");
3151 qemu_mutex_lock_iothread();
3152 ret = kvm_handle_halt(cpu);
3153 qemu_mutex_unlock_iothread();
3154 break;
3155 case KVM_EXIT_SET_TPR:
3156 ret = 0;
3157 break;
3158 case KVM_EXIT_TPR_ACCESS:
3159 qemu_mutex_lock_iothread();
3160 ret = kvm_handle_tpr_access(cpu);
3161 qemu_mutex_unlock_iothread();
3162 break;
3163 case KVM_EXIT_FAIL_ENTRY:
3164 code = run->fail_entry.hardware_entry_failure_reason;
3165 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3166 code);
3167 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3168 fprintf(stderr,
3169 "\nIf you're running a guest on an Intel machine without "
3170 "unrestricted mode\n"
3171 "support, the failure can be most likely due to the guest "
3172 "entering an invalid\n"
3173 "state for Intel VT. For example, the guest maybe running "
3174 "in big real mode\n"
3175 "which is not supported on less recent Intel processors."
3176 "\n\n");
3177 }
3178 ret = -1;
3179 break;
3180 case KVM_EXIT_EXCEPTION:
3181 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3182 run->ex.exception, run->ex.error_code);
3183 ret = -1;
3184 break;
3185 case KVM_EXIT_DEBUG:
3186 DPRINTF("kvm_exit_debug\n");
3187 qemu_mutex_lock_iothread();
3188 ret = kvm_handle_debug(cpu, &run->debug.arch);
3189 qemu_mutex_unlock_iothread();
3190 break;
3191 case KVM_EXIT_HYPERV:
3192 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3193 break;
3194 case KVM_EXIT_IOAPIC_EOI:
3195 ioapic_eoi_broadcast(run->eoi.vector);
3196 ret = 0;
3197 break;
3198 default:
3199 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3200 ret = -1;
3201 break;
3202 }
3203
3204 return ret;
3205 }
3206
3207 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3208 {
3209 X86CPU *cpu = X86_CPU(cs);
3210 CPUX86State *env = &cpu->env;
3211
3212 kvm_cpu_synchronize_state(cs);
3213 return !(env->cr[0] & CR0_PE_MASK) ||
3214 ((env->segs[R_CS].selector & 3) != 3);
3215 }
3216
3217 void kvm_arch_init_irq_routing(KVMState *s)
3218 {
3219 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3220 /* If kernel can't do irq routing, interrupt source
3221 * override 0->2 cannot be set up as required by HPET.
3222 * So we have to disable it.
3223 */
3224 no_hpet = 1;
3225 }
3226 /* We know at this point that we're using the in-kernel
3227 * irqchip, so we can use irqfds, and on x86 we know
3228 * we can use msi via irqfd and GSI routing.
3229 */
3230 kvm_msi_via_irqfd_allowed = true;
3231 kvm_gsi_routing_allowed = true;
3232
3233 if (kvm_irqchip_is_split()) {
3234 int i;
3235
3236 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3237 MSI routes for signaling interrupts to the local apics. */
3238 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3239 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3240 error_report("Could not enable split IRQ mode.");
3241 exit(1);
3242 }
3243 }
3244 }
3245 }
3246
3247 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3248 {
3249 int ret;
3250 if (machine_kernel_irqchip_split(ms)) {
3251 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3252 if (ret) {
3253 error_report("Could not enable split irqchip mode: %s",
3254 strerror(-ret));
3255 exit(1);
3256 } else {
3257 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3258 kvm_split_irqchip = true;
3259 return 1;
3260 }
3261 } else {
3262 return 0;
3263 }
3264 }
3265
3266 /* Classic KVM device assignment interface. Will remain x86 only. */
3267 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3268 uint32_t flags, uint32_t *dev_id)
3269 {
3270 struct kvm_assigned_pci_dev dev_data = {
3271 .segnr = dev_addr->domain,
3272 .busnr = dev_addr->bus,
3273 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3274 .flags = flags,
3275 };
3276 int ret;
3277
3278 dev_data.assigned_dev_id =
3279 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3280
3281 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3282 if (ret < 0) {
3283 return ret;
3284 }
3285
3286 *dev_id = dev_data.assigned_dev_id;
3287
3288 return 0;
3289 }
3290
3291 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3292 {
3293 struct kvm_assigned_pci_dev dev_data = {
3294 .assigned_dev_id = dev_id,
3295 };
3296
3297 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3298 }
3299
3300 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3301 uint32_t irq_type, uint32_t guest_irq)
3302 {
3303 struct kvm_assigned_irq assigned_irq = {
3304 .assigned_dev_id = dev_id,
3305 .guest_irq = guest_irq,
3306 .flags = irq_type,
3307 };
3308
3309 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3310 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3311 } else {
3312 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3313 }
3314 }
3315
3316 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3317 uint32_t guest_irq)
3318 {
3319 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3320 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3321
3322 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3323 }
3324
3325 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3326 {
3327 struct kvm_assigned_pci_dev dev_data = {
3328 .assigned_dev_id = dev_id,
3329 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3330 };
3331
3332 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3333 }
3334
3335 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3336 uint32_t type)
3337 {
3338 struct kvm_assigned_irq assigned_irq = {
3339 .assigned_dev_id = dev_id,
3340 .flags = type,
3341 };
3342
3343 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3344 }
3345
3346 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3347 {
3348 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3349 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3350 }
3351
3352 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3353 {
3354 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3355 KVM_DEV_IRQ_GUEST_MSI, virq);
3356 }
3357
3358 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3359 {
3360 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3361 KVM_DEV_IRQ_HOST_MSI);
3362 }
3363
3364 bool kvm_device_msix_supported(KVMState *s)
3365 {
3366 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3367 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3368 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3369 }
3370
3371 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3372 uint32_t nr_vectors)
3373 {
3374 struct kvm_assigned_msix_nr msix_nr = {
3375 .assigned_dev_id = dev_id,
3376 .entry_nr = nr_vectors,
3377 };
3378
3379 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3380 }
3381
3382 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3383 int virq)
3384 {
3385 struct kvm_assigned_msix_entry msix_entry = {
3386 .assigned_dev_id = dev_id,
3387 .gsi = virq,
3388 .entry = vector,
3389 };
3390
3391 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3392 }
3393
3394 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3395 {
3396 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3397 KVM_DEV_IRQ_GUEST_MSIX, 0);
3398 }
3399
3400 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3401 {
3402 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3403 KVM_DEV_IRQ_HOST_MSIX);
3404 }
3405
3406 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3407 uint64_t address, uint32_t data, PCIDevice *dev)
3408 {
3409 X86IOMMUState *iommu = x86_iommu_get_default();
3410
3411 if (iommu) {
3412 int ret;
3413 MSIMessage src, dst;
3414 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3415
3416 src.address = route->u.msi.address_hi;
3417 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3418 src.address |= route->u.msi.address_lo;
3419 src.data = route->u.msi.data;
3420
3421 ret = class->int_remap(iommu, &src, &dst, dev ? \
3422 pci_requester_id(dev) : \
3423 X86_IOMMU_SID_INVALID);
3424 if (ret) {
3425 trace_kvm_x86_fixup_msi_error(route->gsi);
3426 return 1;
3427 }
3428
3429 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3430 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3431 route->u.msi.data = dst.data;
3432 }
3433
3434 return 0;
3435 }
3436
3437 typedef struct MSIRouteEntry MSIRouteEntry;
3438
3439 struct MSIRouteEntry {
3440 PCIDevice *dev; /* Device pointer */
3441 int vector; /* MSI/MSIX vector index */
3442 int virq; /* Virtual IRQ index */
3443 QLIST_ENTRY(MSIRouteEntry) list;
3444 };
3445
3446 /* List of used GSI routes */
3447 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3448 QLIST_HEAD_INITIALIZER(msi_route_list);
3449
3450 static void kvm_update_msi_routes_all(void *private, bool global,
3451 uint32_t index, uint32_t mask)
3452 {
3453 int cnt = 0;
3454 MSIRouteEntry *entry;
3455 MSIMessage msg;
3456 /* TODO: explicit route update */
3457 QLIST_FOREACH(entry, &msi_route_list, list) {
3458 cnt++;
3459 msg = pci_get_msi_message(entry->dev, entry->vector);
3460 kvm_irqchip_update_msi_route(kvm_state, entry->virq,
3461 msg, entry->dev);
3462 }
3463 kvm_irqchip_commit_routes(kvm_state);
3464 trace_kvm_x86_update_msi_routes(cnt);
3465 }
3466
3467 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3468 int vector, PCIDevice *dev)
3469 {
3470 static bool notify_list_inited = false;
3471 MSIRouteEntry *entry;
3472
3473 if (!dev) {
3474 /* These are (possibly) IOAPIC routes only used for split
3475 * kernel irqchip mode, while what we are housekeeping are
3476 * PCI devices only. */
3477 return 0;
3478 }
3479
3480 entry = g_new0(MSIRouteEntry, 1);
3481 entry->dev = dev;
3482 entry->vector = vector;
3483 entry->virq = route->gsi;
3484 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3485
3486 trace_kvm_x86_add_msi_route(route->gsi);
3487
3488 if (!notify_list_inited) {
3489 /* For the first time we do add route, add ourselves into
3490 * IOMMU's IEC notify list if needed. */
3491 X86IOMMUState *iommu = x86_iommu_get_default();
3492 if (iommu) {
3493 x86_iommu_iec_register_notifier(iommu,
3494 kvm_update_msi_routes_all,
3495 NULL);
3496 }
3497 notify_list_inited = true;
3498 }
3499 return 0;
3500 }
3501
3502 int kvm_arch_release_virq_post(int virq)
3503 {
3504 MSIRouteEntry *entry, *next;
3505 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3506 if (entry->virq == virq) {
3507 trace_kvm_x86_remove_msi_route(virq);
3508 QLIST_REMOVE(entry, list);
3509 break;
3510 }
3511 }
3512 return 0;
3513 }
3514
3515 int kvm_arch_msi_data_to_gsi(uint32_t data)
3516 {
3517 abort();
3518 }
AR7 emulation for QEMU