target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22
  23 #include "helper.h"
  24
  25 #if !defined(CONFIG_USER_ONLY)
  26 #include "exec/softmmu_exec.h"
  27 #endif /* !defined(CONFIG_USER_ONLY) */
  28
  29 #ifndef CONFIG_USER_ONLY
  30 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
  31 #endif
  32
  33 /*****************************************************************************/
  34 /* Exceptions processing helpers */
  35
  36 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
  37                                                         uint32_t exception,
  38                                                         int error_code,
  39                                                         uintptr_t pc)
  40 {
  41     if (exception < EXCP_SC) {
  42         qemu_log("%s: %d %d\n", __func__, exception, error_code);
  43     }
  44     env->exception_index = exception;
  45     env->error_code = error_code;
  46
  47     if (pc) {
  48         /* now we have a real cpu fault */
  49         cpu_restore_state(env, pc);
  50     }
  51
  52     cpu_loop_exit(env);
  53 }
  54
  55 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
  56                                                     uint32_t exception,
  57                                                     uintptr_t pc)
  58 {
  59     do_raise_exception_err(env, exception, 0, pc);
  60 }
  61
  62 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  63                                 int error_code)
  64 {
  65     do_raise_exception_err(env, exception, error_code, 0);
  66 }
  67
  68 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  69 {
  70     do_raise_exception(env, exception, 0);
  71 }
  72
  73 #if defined(CONFIG_USER_ONLY)
  74 #define HELPER_LD(name, insn, type)                                     \
  75 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  76                              int mem_idx)                               \
  77 {                                                                       \
  78     return (type) insn##_raw(addr);                                     \
  79 }
  80 #else
  81 #define HELPER_LD(name, insn, type)                                     \
  82 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  83                              int mem_idx)                               \
  84 {                                                                       \
  85     switch (mem_idx)                                                    \
  86     {                                                                   \
  87     case 0: return (type) cpu_##insn##_kernel(env, addr); break;        \
  88     case 1: return (type) cpu_##insn##_super(env, addr); break;         \
  89     default:                                                            \
  90     case 2: return (type) cpu_##insn##_user(env, addr); break;          \
  91     }                                                                   \
  92 }
  93 #endif
  94 HELPER_LD(lbu, ldub, uint8_t)
  95 HELPER_LD(lw, ldl, int32_t)
  96 #ifdef TARGET_MIPS64
  97 HELPER_LD(ld, ldq, int64_t)
  98 #endif
  99 #undef HELPER_LD
 100
 101 #if defined(CONFIG_USER_ONLY)
 102 #define HELPER_ST(name, insn, type)                                     \
 103 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 104                              type val, int mem_idx)                     \
 105 {                                                                       \
 106     insn##_raw(addr, val);                                              \
 107 }
 108 #else
 109 #define HELPER_ST(name, insn, type)                                     \
 110 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 111                              type val, int mem_idx)                     \
 112 {                                                                       \
 113     switch (mem_idx)                                                    \
 114     {                                                                   \
 115     case 0: cpu_##insn##_kernel(env, addr, val); break;                 \
 116     case 1: cpu_##insn##_super(env, addr, val); break;                  \
 117     default:                                                            \
 118     case 2: cpu_##insn##_user(env, addr, val); break;                   \
 119     }                                                                   \
 120 }
 121 #endif
 122 HELPER_ST(sb, stb, uint8_t)
 123 HELPER_ST(sw, stl, uint32_t)
 124 #ifdef TARGET_MIPS64
 125 HELPER_ST(sd, stq, uint64_t)
 126 #endif
 127 #undef HELPER_ST
 128
 129 target_ulong helper_clo (target_ulong arg1)
 130 {
 131     return clo32(arg1);
 132 }
 133
 134 target_ulong helper_clz (target_ulong arg1)
 135 {
 136     return clz32(arg1);
 137 }
 138
 139 #if defined(TARGET_MIPS64)
 140 target_ulong helper_dclo (target_ulong arg1)
 141 {
 142     return clo64(arg1);
 143 }
 144
 145 target_ulong helper_dclz (target_ulong arg1)
 146 {
 147     return clz64(arg1);
 148 }
 149 #endif /* TARGET_MIPS64 */
 150
 151 /* 64 bits arithmetic for 32 bits hosts */
 152 static inline uint64_t get_HILO(CPUMIPSState *env)
 153 {
 154     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 155 }
 156
 157 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
 158 {
 159     target_ulong tmp;
 160     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 161     tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 162     return tmp;
 163 }
 164
 165 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
 166 {
 167     target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 168     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 169     return tmp;
 170 }
 171
 172 /* Multiplication variants of the vr54xx. */
 173 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
 174                          target_ulong arg2)
 175 {
 176     return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
 177                                  (int64_t)(int32_t)arg2));
 178 }
 179
 180 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
 181                           target_ulong arg2)
 182 {
 183     return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
 184                        (uint64_t)(uint32_t)arg2);
 185 }
 186
 187 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
 188                          target_ulong arg2)
 189 {
 190     return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 191                        (int64_t)(int32_t)arg2);
 192 }
 193
 194 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
 195                            target_ulong arg2)
 196 {
 197     return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 198                        (int64_t)(int32_t)arg2);
 199 }
 200
 201 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
 202                           target_ulong arg2)
 203 {
 204     return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
 205                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 206 }
 207
 208 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
 209                             target_ulong arg2)
 210 {
 211     return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
 212                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 213 }
 214
 215 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
 216                          target_ulong arg2)
 217 {
 218     return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 219                        (int64_t)(int32_t)arg2);
 220 }
 221
 222 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
 223                            target_ulong arg2)
 224 {
 225     return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 226                        (int64_t)(int32_t)arg2);
 227 }
 228
 229 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
 230                           target_ulong arg2)
 231 {
 232     return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
 233                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 234 }
 235
 236 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
 237                             target_ulong arg2)
 238 {
 239     return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
 240                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 241 }
 242
 243 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
 244                           target_ulong arg2)
 245 {
 246     return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 247 }
 248
 249 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
 250                            target_ulong arg2)
 251 {
 252     return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
 253                        (uint64_t)(uint32_t)arg2);
 254 }
 255
 256 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
 257                            target_ulong arg2)
 258 {
 259     return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
 260                        (int64_t)(int32_t)arg2);
 261 }
 262
 263 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
 264                             target_ulong arg2)
 265 {
 266     return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
 267                        (uint64_t)(uint32_t)arg2);
 268 }
 269
 270 #ifndef CONFIG_USER_ONLY
 271
 272 static inline hwaddr do_translate_address(CPUMIPSState *env,
 273                                                       target_ulong address,
 274                                                       int rw)
 275 {
 276     hwaddr lladdr;
 277
 278     lladdr = cpu_mips_translate_address(env, address, rw);
 279
 280     if (lladdr == -1LL) {
 281         cpu_loop_exit(env);
 282     } else {
 283         return lladdr;
 284     }
 285 }
 286
 287 #define HELPER_LD_ATOMIC(name, insn)                                          \
 288 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
 289 {                                                                             \
 290     env->lladdr = do_translate_address(env, arg, 0);                          \
 291     env->llval = do_##insn(env, arg, mem_idx);                                \
 292     return env->llval;                                                        \
 293 }
 294 HELPER_LD_ATOMIC(ll, lw)
 295 #ifdef TARGET_MIPS64
 296 HELPER_LD_ATOMIC(lld, ld)
 297 #endif
 298 #undef HELPER_LD_ATOMIC
 299
 300 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 301 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \
 302                            target_ulong arg2, int mem_idx)                    \
 303 {                                                                             \
 304     target_long tmp;                                                          \
 305                                                                               \
 306     if (arg2 & almask) {                                                      \
 307         env->CP0_BadVAddr = arg2;                                             \
 308         helper_raise_exception(env, EXCP_AdES);                               \
 309     }                                                                         \
 310     if (do_translate_address(env, arg2, 1) == env->lladdr) {                  \
 311         tmp = do_##ld_insn(env, arg2, mem_idx);                               \
 312         if (tmp == env->llval) {                                              \
 313             do_##st_insn(env, arg2, arg1, mem_idx);                           \
 314             return 1;                                                         \
 315         }                                                                     \
 316     }                                                                         \
 317     return 0;                                                                 \
 318 }
 319 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 320 #ifdef TARGET_MIPS64
 321 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 322 #endif
 323 #undef HELPER_ST_ATOMIC
 324 #endif
 325
 326 #ifdef TARGET_WORDS_BIGENDIAN
 327 #define GET_LMASK(v) ((v) & 3)
 328 #define GET_OFFSET(addr, offset) (addr + (offset))
 329 #else
 330 #define GET_LMASK(v) (((v) & 3) ^ 3)
 331 #define GET_OFFSET(addr, offset) (addr - (offset))
 332 #endif
 333
 334 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 335                 int mem_idx)
 336 {
 337     do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
 338
 339     if (GET_LMASK(arg2) <= 2)
 340         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
 341
 342     if (GET_LMASK(arg2) <= 1)
 343         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
 344
 345     if (GET_LMASK(arg2) == 0)
 346         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
 347 }
 348
 349 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 350                 int mem_idx)
 351 {
 352     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 353
 354     if (GET_LMASK(arg2) >= 1)
 355         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 356
 357     if (GET_LMASK(arg2) >= 2)
 358         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 359
 360     if (GET_LMASK(arg2) == 3)
 361         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 362 }
 363
 364 #if defined(TARGET_MIPS64)
 365 /* "half" load and stores.  We must do the memory access inline,
 366    or fault handling won't work.  */
 367
 368 #ifdef TARGET_WORDS_BIGENDIAN
 369 #define GET_LMASK64(v) ((v) & 7)
 370 #else
 371 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 372 #endif
 373
 374 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 375                 int mem_idx)
 376 {
 377     do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
 378
 379     if (GET_LMASK64(arg2) <= 6)
 380         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
 381
 382     if (GET_LMASK64(arg2) <= 5)
 383         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
 384
 385     if (GET_LMASK64(arg2) <= 4)
 386         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
 387
 388     if (GET_LMASK64(arg2) <= 3)
 389         do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
 390
 391     if (GET_LMASK64(arg2) <= 2)
 392         do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
 393
 394     if (GET_LMASK64(arg2) <= 1)
 395         do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
 396
 397     if (GET_LMASK64(arg2) <= 0)
 398         do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
 399 }
 400
 401 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 402                 int mem_idx)
 403 {
 404     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 405
 406     if (GET_LMASK64(arg2) >= 1)
 407         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 408
 409     if (GET_LMASK64(arg2) >= 2)
 410         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 411
 412     if (GET_LMASK64(arg2) >= 3)
 413         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 414
 415     if (GET_LMASK64(arg2) >= 4)
 416         do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
 417
 418     if (GET_LMASK64(arg2) >= 5)
 419         do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
 420
 421     if (GET_LMASK64(arg2) >= 6)
 422         do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
 423
 424     if (GET_LMASK64(arg2) == 7)
 425         do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
 426 }
 427 #endif /* TARGET_MIPS64 */
 428
 429 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 430
 431 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 432                 uint32_t mem_idx)
 433 {
 434     target_ulong base_reglist = reglist & 0xf;
 435     target_ulong do_r31 = reglist & 0x10;
 436
 437     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 438         target_ulong i;
 439
 440         for (i = 0; i < base_reglist; i++) {
 441             env->active_tc.gpr[multiple_regs[i]] =
 442                 (target_long)do_lw(env, addr, mem_idx);
 443             addr += 4;
 444         }
 445     }
 446
 447     if (do_r31) {
 448         env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
 449     }
 450 }
 451
 452 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 453                 uint32_t mem_idx)
 454 {
 455     target_ulong base_reglist = reglist & 0xf;
 456     target_ulong do_r31 = reglist & 0x10;
 457
 458     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 459         target_ulong i;
 460
 461         for (i = 0; i < base_reglist; i++) {
 462             do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 463             addr += 4;
 464         }
 465     }
 466
 467     if (do_r31) {
 468         do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
 469     }
 470 }
 471
 472 #if defined(TARGET_MIPS64)
 473 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 474                 uint32_t mem_idx)
 475 {
 476     target_ulong base_reglist = reglist & 0xf;
 477     target_ulong do_r31 = reglist & 0x10;
 478
 479     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 480         target_ulong i;
 481
 482         for (i = 0; i < base_reglist; i++) {
 483             env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);
 484             addr += 8;
 485         }
 486     }
 487
 488     if (do_r31) {
 489         env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
 490     }
 491 }
 492
 493 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 494                 uint32_t mem_idx)
 495 {
 496     target_ulong base_reglist = reglist & 0xf;
 497     target_ulong do_r31 = reglist & 0x10;
 498
 499     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 500         target_ulong i;
 501
 502         for (i = 0; i < base_reglist; i++) {
 503             do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 504             addr += 8;
 505         }
 506     }
 507
 508     if (do_r31) {
 509         do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
 510     }
 511 }
 512 #endif
 513
 514 #ifndef CONFIG_USER_ONLY
 515 /* SMP helpers.  */
 516 static bool mips_vpe_is_wfi(MIPSCPU *c)
 517 {
 518     CPUState *cpu = CPU(c);
 519     CPUMIPSState *env = &c->env;
 520
 521     /* If the VPE is halted but otherwise active, it means it's waiting for
 522        an interrupt.  */
 523     return cpu->halted && mips_vpe_active(env);
 524 }
 525
 526 static inline void mips_vpe_wake(MIPSCPU *c)
 527 {
 528     /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
 529        because there might be other conditions that state that c should
 530        be sleeping.  */
 531     cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
 532 }
 533
 534 static inline void mips_vpe_sleep(MIPSCPU *cpu)
 535 {
 536     CPUState *cs = CPU(cpu);
 537
 538     /* The VPE was shut off, really go to bed.
 539        Reset any old _WAKE requests.  */
 540     cs->halted = 1;
 541     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
 542 }
 543
 544 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
 545 {
 546     CPUMIPSState *c = &cpu->env;
 547
 548     /* FIXME: TC reschedule.  */
 549     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
 550         mips_vpe_wake(cpu);
 551     }
 552 }
 553
 554 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
 555 {
 556     CPUMIPSState *c = &cpu->env;
 557
 558     /* FIXME: TC reschedule.  */
 559     if (!mips_vpe_active(c)) {
 560         mips_vpe_sleep(cpu);
 561     }
 562 }
 563
 564 /**
 565  * mips_cpu_map_tc:
 566  * @env: CPU from which mapping is performed.
 567  * @tc: Should point to an int with the value of the global TC index.
 568  *
 569  * This function will transform @tc into a local index within the
 570  * returned #CPUMIPSState.
 571  */
 572 /* FIXME: This code assumes that all VPEs have the same number of TCs,
 573           which depends on runtime setup. Can probably be fixed by
 574           walking the list of CPUMIPSStates.  */
 575 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 576 {
 577     MIPSCPU *cpu;
 578     CPUState *cs;
 579     CPUState *other_cs;
 580     int vpe_idx;
 581     int tc_idx = *tc;
 582
 583     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 584         /* Not allowed to address other CPUs.  */
 585         *tc = env->current_tc;
 586         return env;
 587     }
 588
 589     cs = CPU(mips_env_get_cpu(env));
 590     vpe_idx = tc_idx / cs->nr_threads;
 591     *tc = tc_idx % cs->nr_threads;
 592     other_cs = qemu_get_cpu(vpe_idx);
 593     if (other_cs == NULL) {
 594         return env;
 595     }
 596     cpu = MIPS_CPU(other_cs);
 597     return &cpu->env;
 598 }
 599
 600 /* The per VPE CP0_Status register shares some fields with the per TC
 601    CP0_TCStatus registers. These fields are wired to the same registers,
 602    so changes to either of them should be reflected on both registers.
 603
 604    Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 605
 606    These helper call synchronizes the regs for a given cpu.  */
 607
 608 /* Called for updates to CP0_Status.  */
 609 static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
 610 {
 611     int32_t tcstatus, *tcst;
 612     uint32_t v = cpu->CP0_Status;
 613     uint32_t cu, mx, asid, ksu;
 614     uint32_t mask = ((1 << CP0TCSt_TCU3)
 615                        | (1 << CP0TCSt_TCU2)
 616                        | (1 << CP0TCSt_TCU1)
 617                        | (1 << CP0TCSt_TCU0)
 618                        | (1 << CP0TCSt_TMX)
 619                        | (3 << CP0TCSt_TKSU)
 620                        | (0xff << CP0TCSt_TASID));
 621
 622     cu = (v >> CP0St_CU0) & 0xf;
 623     mx = (v >> CP0St_MX) & 0x1;
 624     ksu = (v >> CP0St_KSU) & 0x3;
 625     asid = env->CP0_EntryHi & 0xff;
 626
 627     tcstatus = cu << CP0TCSt_TCU0;
 628     tcstatus |= mx << CP0TCSt_TMX;
 629     tcstatus |= ksu << CP0TCSt_TKSU;
 630     tcstatus |= asid;
 631
 632     if (tc == cpu->current_tc) {
 633         tcst = &cpu->active_tc.CP0_TCStatus;
 634     } else {
 635         tcst = &cpu->tcs[tc].CP0_TCStatus;
 636     }
 637
 638     *tcst &= ~mask;
 639     *tcst |= tcstatus;
 640     compute_hflags(cpu);
 641 }
 642
 643 /* Called for updates to CP0_TCStatus.  */
 644 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 645                              target_ulong v)
 646 {
 647     uint32_t status;
 648     uint32_t tcu, tmx, tasid, tksu;
 649     uint32_t mask = ((1 << CP0St_CU3)
 650                        | (1 << CP0St_CU2)
 651                        | (1 << CP0St_CU1)
 652                        | (1 << CP0St_CU0)
 653                        | (1 << CP0St_MX)
 654                        | (3 << CP0St_KSU));
 655
 656     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 657     tmx = (v >> CP0TCSt_TMX) & 0x1;
 658     tasid = v & 0xff;
 659     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 660
 661     status = tcu << CP0St_CU0;
 662     status |= tmx << CP0St_MX;
 663     status |= tksu << CP0St_KSU;
 664
 665     cpu->CP0_Status &= ~mask;
 666     cpu->CP0_Status |= status;
 667
 668     /* Sync the TASID with EntryHi.  */
 669     cpu->CP0_EntryHi &= ~0xff;
 670     cpu->CP0_EntryHi = tasid;
 671
 672     compute_hflags(cpu);
 673 }
 674
 675 /* Called for updates to CP0_EntryHi.  */
 676 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 677 {
 678     int32_t *tcst;
 679     uint32_t asid, v = cpu->CP0_EntryHi;
 680
 681     asid = v & 0xff;
 682
 683     if (tc == cpu->current_tc) {
 684         tcst = &cpu->active_tc.CP0_TCStatus;
 685     } else {
 686         tcst = &cpu->tcs[tc].CP0_TCStatus;
 687     }
 688
 689     *tcst &= ~0xff;
 690     *tcst |= asid;
 691 }
 692
 693 /* CP0 helpers */
 694 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 695 {
 696     return env->mvp->CP0_MVPControl;
 697 }
 698
 699 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 700 {
 701     return env->mvp->CP0_MVPConf0;
 702 }
 703
 704 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 705 {
 706     return env->mvp->CP0_MVPConf1;
 707 }
 708
 709 target_ulong helper_mfc0_random(CPUMIPSState *env)
 710 {
 711     return (int32_t)cpu_mips_get_random(env);
 712 }
 713
 714 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 715 {
 716     return env->active_tc.CP0_TCStatus;
 717 }
 718
 719 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 720 {
 721     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 722     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 723
 724     if (other_tc == other->current_tc)
 725         return other->active_tc.CP0_TCStatus;
 726     else
 727         return other->tcs[other_tc].CP0_TCStatus;
 728 }
 729
 730 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 731 {
 732     return env->active_tc.CP0_TCBind;
 733 }
 734
 735 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 736 {
 737     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 738     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 739
 740     if (other_tc == other->current_tc)
 741         return other->active_tc.CP0_TCBind;
 742     else
 743         return other->tcs[other_tc].CP0_TCBind;
 744 }
 745
 746 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 747 {
 748     return env->active_tc.PC;
 749 }
 750
 751 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 752 {
 753     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 754     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 755
 756     if (other_tc == other->current_tc)
 757         return other->active_tc.PC;
 758     else
 759         return other->tcs[other_tc].PC;
 760 }
 761
 762 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 763 {
 764     return env->active_tc.CP0_TCHalt;
 765 }
 766
 767 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 768 {
 769     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 770     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 771
 772     if (other_tc == other->current_tc)
 773         return other->active_tc.CP0_TCHalt;
 774     else
 775         return other->tcs[other_tc].CP0_TCHalt;
 776 }
 777
 778 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 779 {
 780     return env->active_tc.CP0_TCContext;
 781 }
 782
 783 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 784 {
 785     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 786     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 787
 788     if (other_tc == other->current_tc)
 789         return other->active_tc.CP0_TCContext;
 790     else
 791         return other->tcs[other_tc].CP0_TCContext;
 792 }
 793
 794 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 795 {
 796     return env->active_tc.CP0_TCSchedule;
 797 }
 798
 799 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 800 {
 801     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 802     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 803
 804     if (other_tc == other->current_tc)
 805         return other->active_tc.CP0_TCSchedule;
 806     else
 807         return other->tcs[other_tc].CP0_TCSchedule;
 808 }
 809
 810 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 811 {
 812     return env->active_tc.CP0_TCScheFBack;
 813 }
 814
 815 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 816 {
 817     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 818     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 819
 820     if (other_tc == other->current_tc)
 821         return other->active_tc.CP0_TCScheFBack;
 822     else
 823         return other->tcs[other_tc].CP0_TCScheFBack;
 824 }
 825
 826 target_ulong helper_mfc0_count(CPUMIPSState *env)
 827 {
 828     return (int32_t)cpu_mips_get_count(env);
 829 }
 830
 831 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 832 {
 833     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 834     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 835
 836     return other->CP0_EntryHi;
 837 }
 838
 839 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 840 {
 841     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 842     int32_t tccause;
 843     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 844
 845     if (other_tc == other->current_tc) {
 846         tccause = other->CP0_Cause;
 847     } else {
 848         tccause = other->CP0_Cause;
 849     }
 850
 851     return tccause;
 852 }
 853
 854 target_ulong helper_mftc0_status(CPUMIPSState *env)
 855 {
 856     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 857     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 858
 859     return other->CP0_Status;
 860 }
 861
 862 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
 863 {
 864     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
 865 }
 866
 867 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 868 {
 869     return (int32_t)env->CP0_WatchLo[sel];
 870 }
 871
 872 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 873 {
 874     return env->CP0_WatchHi[sel];
 875 }
 876
 877 target_ulong helper_mfc0_debug(CPUMIPSState *env)
 878 {
 879     target_ulong t0 = env->CP0_Debug;
 880     if (env->hflags & MIPS_HFLAG_DM)
 881         t0 |= 1 << CP0DB_DM;
 882
 883     return t0;
 884 }
 885
 886 target_ulong helper_mftc0_debug(CPUMIPSState *env)
 887 {
 888     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 889     int32_t tcstatus;
 890     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 891
 892     if (other_tc == other->current_tc)
 893         tcstatus = other->active_tc.CP0_Debug_tcstatus;
 894     else
 895         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
 896
 897     /* XXX: Might be wrong, check with EJTAG spec. */
 898     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 899             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 900 }
 901
 902 #if defined(TARGET_MIPS64)
 903 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
 904 {
 905     return env->active_tc.PC;
 906 }
 907
 908 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
 909 {
 910     return env->active_tc.CP0_TCHalt;
 911 }
 912
 913 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
 914 {
 915     return env->active_tc.CP0_TCContext;
 916 }
 917
 918 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
 919 {
 920     return env->active_tc.CP0_TCSchedule;
 921 }
 922
 923 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
 924 {
 925     return env->active_tc.CP0_TCScheFBack;
 926 }
 927
 928 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
 929 {
 930     return env->lladdr >> env->CP0_LLAddr_shift;
 931 }
 932
 933 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 934 {
 935     return env->CP0_WatchLo[sel];
 936 }
 937 #endif /* TARGET_MIPS64 */
 938
 939 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
 940 {
 941     int num = 1;
 942     unsigned int tmp = env->tlb->nb_tlb;
 943
 944     do {
 945         tmp >>= 1;
 946         num <<= 1;
 947     } while (tmp);
 948     env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
 949 }
 950
 951 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
 952 {
 953     uint32_t mask = 0;
 954     uint32_t newval;
 955
 956     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
 957         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 958                 (1 << CP0MVPCo_EVP);
 959     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 960         mask |= (1 << CP0MVPCo_STLB);
 961     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 962
 963     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 964
 965     env->mvp->CP0_MVPControl = newval;
 966 }
 967
 968 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 969 {
 970     uint32_t mask;
 971     uint32_t newval;
 972
 973     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 974            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 975     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
 976
 977     /* Yield scheduler intercept not implemented. */
 978     /* Gating storage scheduler intercept not implemented. */
 979
 980     // TODO: Enable/disable TCs.
 981
 982     env->CP0_VPEControl = newval;
 983 }
 984
 985 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 986 {
 987     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 988     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 989     uint32_t mask;
 990     uint32_t newval;
 991
 992     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 993            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 994     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
 995
 996     /* TODO: Enable/disable TCs.  */
 997
 998     other->CP0_VPEControl = newval;
 999 }
1000
1001 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1002 {
1003     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1004     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1005     /* FIXME: Mask away return zero on read bits.  */
1006     return other->CP0_VPEControl;
1007 }
1008
1009 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1010 {
1011     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1012     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1013
1014     return other->CP0_VPEConf0;
1015 }
1016
1017 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1018 {
1019     uint32_t mask = 0;
1020     uint32_t newval;
1021
1022     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1023         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1024             mask |= (0xff << CP0VPEC0_XTC);
1025         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1026     }
1027     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1028
1029     // TODO: TC exclusive handling due to ERL/EXL.
1030
1031     env->CP0_VPEConf0 = newval;
1032 }
1033
1034 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1035 {
1036     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1037     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1038     uint32_t mask = 0;
1039     uint32_t newval;
1040
1041     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1042     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1043
1044     /* TODO: TC exclusive handling due to ERL/EXL.  */
1045     other->CP0_VPEConf0 = newval;
1046 }
1047
1048 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1049 {
1050     uint32_t mask = 0;
1051     uint32_t newval;
1052
1053     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1054         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1055                 (0xff << CP0VPEC1_NCP1);
1056     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1057
1058     /* UDI not implemented. */
1059     /* CP2 not implemented. */
1060
1061     // TODO: Handle FPU (CP1) binding.
1062
1063     env->CP0_VPEConf1 = newval;
1064 }
1065
1066 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1067 {
1068     /* Yield qualifier inputs not implemented. */
1069     env->CP0_YQMask = 0x00000000;
1070 }
1071
1072 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1073 {
1074     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1075 }
1076
1077 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1078 {
1079     /* Large physaddr (PABITS) not implemented */
1080     /* 1k pages not implemented */
1081     env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
1082 }
1083
1084 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1085 {
1086     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1087     uint32_t newval;
1088
1089     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1090
1091     env->active_tc.CP0_TCStatus = newval;
1092     sync_c0_tcstatus(env, env->current_tc, newval);
1093 }
1094
1095 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1096 {
1097     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1098     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1099
1100     if (other_tc == other->current_tc)
1101         other->active_tc.CP0_TCStatus = arg1;
1102     else
1103         other->tcs[other_tc].CP0_TCStatus = arg1;
1104     sync_c0_tcstatus(other, other_tc, arg1);
1105 }
1106
1107 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1108 {
1109     uint32_t mask = (1 << CP0TCBd_TBE);
1110     uint32_t newval;
1111
1112     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1113         mask |= (1 << CP0TCBd_CurVPE);
1114     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1115     env->active_tc.CP0_TCBind = newval;
1116 }
1117
1118 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1119 {
1120     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1121     uint32_t mask = (1 << CP0TCBd_TBE);
1122     uint32_t newval;
1123     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1124
1125     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1126         mask |= (1 << CP0TCBd_CurVPE);
1127     if (other_tc == other->current_tc) {
1128         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1129         other->active_tc.CP0_TCBind = newval;
1130     } else {
1131         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1132         other->tcs[other_tc].CP0_TCBind = newval;
1133     }
1134 }
1135
1136 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1137 {
1138     env->active_tc.PC = arg1;
1139     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1140     env->lladdr = 0ULL;
1141     /* MIPS16 not implemented. */
1142 }
1143
1144 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1145 {
1146     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1147     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1148
1149     if (other_tc == other->current_tc) {
1150         other->active_tc.PC = arg1;
1151         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1152         other->lladdr = 0ULL;
1153         /* MIPS16 not implemented. */
1154     } else {
1155         other->tcs[other_tc].PC = arg1;
1156         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1157         other->lladdr = 0ULL;
1158         /* MIPS16 not implemented. */
1159     }
1160 }
1161
1162 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1163 {
1164     MIPSCPU *cpu = mips_env_get_cpu(env);
1165
1166     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1167
1168     // TODO: Halt TC / Restart (if allocated+active) TC.
1169     if (env->active_tc.CP0_TCHalt & 1) {
1170         mips_tc_sleep(cpu, env->current_tc);
1171     } else {
1172         mips_tc_wake(cpu, env->current_tc);
1173     }
1174 }
1175
1176 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1177 {
1178     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1179     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1180     MIPSCPU *other_cpu = mips_env_get_cpu(other);
1181
1182     // TODO: Halt TC / Restart (if allocated+active) TC.
1183
1184     if (other_tc == other->current_tc)
1185         other->active_tc.CP0_TCHalt = arg1;
1186     else
1187         other->tcs[other_tc].CP0_TCHalt = arg1;
1188
1189     if (arg1 & 1) {
1190         mips_tc_sleep(other_cpu, other_tc);
1191     } else {
1192         mips_tc_wake(other_cpu, other_tc);
1193     }
1194 }
1195
1196 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1197 {
1198     env->active_tc.CP0_TCContext = arg1;
1199 }
1200
1201 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1202 {
1203     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1204     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1205
1206     if (other_tc == other->current_tc)
1207         other->active_tc.CP0_TCContext = arg1;
1208     else
1209         other->tcs[other_tc].CP0_TCContext = arg1;
1210 }
1211
1212 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1213 {
1214     env->active_tc.CP0_TCSchedule = arg1;
1215 }
1216
1217 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1218 {
1219     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1220     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1221
1222     if (other_tc == other->current_tc)
1223         other->active_tc.CP0_TCSchedule = arg1;
1224     else
1225         other->tcs[other_tc].CP0_TCSchedule = arg1;
1226 }
1227
1228 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1229 {
1230     env->active_tc.CP0_TCScheFBack = arg1;
1231 }
1232
1233 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1234 {
1235     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1236     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1237
1238     if (other_tc == other->current_tc)
1239         other->active_tc.CP0_TCScheFBack = arg1;
1240     else
1241         other->tcs[other_tc].CP0_TCScheFBack = arg1;
1242 }
1243
1244 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1245 {
1246     /* Large physaddr (PABITS) not implemented */
1247     /* 1k pages not implemented */
1248     env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1249 }
1250
1251 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1252 {
1253     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1254 }
1255
1256 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1257 {
1258     /* 1k pages not implemented */
1259     env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1260 }
1261
1262 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1263 {
1264     /* SmartMIPS not implemented */
1265     /* Large physaddr (PABITS) not implemented */
1266     /* 1k pages not implemented */
1267     env->CP0_PageGrain = 0;
1268 }
1269
1270 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1271 {
1272     env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1273 }
1274
1275 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1276 {
1277     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1278 }
1279
1280 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1281 {
1282     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1283 }
1284
1285 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1286 {
1287     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1288 }
1289
1290 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1291 {
1292     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1293 }
1294
1295 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1296 {
1297     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1298 }
1299
1300 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1301 {
1302     env->CP0_HWREna = arg1 & 0x0000000F;
1303 }
1304
1305 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1306 {
1307     cpu_mips_store_count(env, arg1);
1308 }
1309
1310 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1311 {
1312     target_ulong old, val;
1313
1314     /* 1k pages not implemented */
1315     val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1316 #if defined(TARGET_MIPS64)
1317     val &= env->SEGMask;
1318 #endif
1319     old = env->CP0_EntryHi;
1320     env->CP0_EntryHi = val;
1321     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1322         sync_c0_entryhi(env, env->current_tc);
1323     }
1324     /* If the ASID changes, flush qemu's TLB.  */
1325     if ((old & 0xFF) != (val & 0xFF))
1326         cpu_mips_tlb_flush(env, 1);
1327 }
1328
1329 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1330 {
1331     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1332     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1333
1334     other->CP0_EntryHi = arg1;
1335     sync_c0_entryhi(other, other_tc);
1336 }
1337
1338 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1339 {
1340     cpu_mips_store_compare(env, arg1);
1341 }
1342
1343 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1344 {
1345     uint32_t val, old;
1346     uint32_t mask = env->CP0_Status_rw_bitmask;
1347
1348     val = arg1 & mask;
1349     old = env->CP0_Status;
1350     env->CP0_Status = (env->CP0_Status & ~mask) | val;
1351     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1352         sync_c0_status(env, env, env->current_tc);
1353     } else {
1354         compute_hflags(env);
1355     }
1356
1357     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1358         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1359                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1360                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1361                 env->CP0_Cause);
1362         switch (env->hflags & MIPS_HFLAG_KSU) {
1363         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1364         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1365         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1366         default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1367         }
1368     }
1369 }
1370
1371 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1372 {
1373     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1374     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1375
1376     other->CP0_Status = arg1 & ~0xf1000018;
1377     sync_c0_status(env, other, other_tc);
1378 }
1379
1380 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1381 {
1382     /* vectored interrupts not implemented, no performance counters. */
1383     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1384 }
1385
1386 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1387 {
1388     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1389     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1390 }
1391
1392 static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
1393 {
1394     uint32_t mask = 0x00C00300;
1395     uint32_t old = cpu->CP0_Cause;
1396     int i;
1397
1398     if (cpu->insn_flags & ISA_MIPS32R2) {
1399         mask |= 1 << CP0Ca_DC;
1400     }
1401
1402     cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask);
1403
1404     if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) {
1405         if (cpu->CP0_Cause & (1 << CP0Ca_DC)) {
1406             cpu_mips_stop_count(cpu);
1407         } else {
1408             cpu_mips_start_count(cpu);
1409         }
1410     }
1411
1412     /* Set/reset software interrupts */
1413     for (i = 0 ; i < 2 ; i++) {
1414         if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1415             cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i)));
1416         }
1417     }
1418 }
1419
1420 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1421 {
1422     mtc0_cause(env, arg1);
1423 }
1424
1425 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1426 {
1427     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1428     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1429
1430     mtc0_cause(other, arg1);
1431 }
1432
1433 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1434 {
1435     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1436     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1437
1438     return other->CP0_EPC;
1439 }
1440
1441 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1442 {
1443     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1444     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1445
1446     return other->CP0_EBase;
1447 }
1448
1449 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1450 {
1451     /* vectored interrupts not implemented */
1452     env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1453 }
1454
1455 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1456 {
1457     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1458     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1459     other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1460 }
1461
1462 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1463 {
1464     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1465     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1466
1467     switch (idx) {
1468     case 0: return other->CP0_Config0;
1469     case 1: return other->CP0_Config1;
1470     case 2: return other->CP0_Config2;
1471     case 3: return other->CP0_Config3;
1472     /* 4 and 5 are reserved.  */
1473     case 6: return other->CP0_Config6;
1474     case 7: return other->CP0_Config7;
1475     default:
1476         break;
1477     }
1478     return 0;
1479 }
1480
1481 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1482 {
1483     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1484 }
1485
1486 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1487 {
1488     /* tertiary/secondary caches not implemented */
1489     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1490 }
1491
1492 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1493 {
1494     env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1495                        (arg1 & env->CP0_Config4_rw_bitmask);
1496 }
1497
1498 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1499 {
1500     env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1501                        (arg1 & env->CP0_Config5_rw_bitmask);
1502 }
1503
1504 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1505 {
1506     target_long mask = env->CP0_LLAddr_rw_bitmask;
1507     arg1 = arg1 << env->CP0_LLAddr_shift;
1508     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1509 }
1510
1511 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1512 {
1513     /* Watch exceptions for instructions, data loads, data stores
1514        not implemented. */
1515     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1516 }
1517
1518 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1519 {
1520     env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1521     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1522 }
1523
1524 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1525 {
1526     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1527     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1528 }
1529
1530 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1531 {
1532     env->CP0_Framemask = arg1; /* XXX */
1533 }
1534
1535 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1536 {
1537     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1538     if (arg1 & (1 << CP0DB_DM))
1539         env->hflags |= MIPS_HFLAG_DM;
1540     else
1541         env->hflags &= ~MIPS_HFLAG_DM;
1542 }
1543
1544 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1545 {
1546     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1547     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1548     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1549
1550     /* XXX: Might be wrong, check with EJTAG spec. */
1551     if (other_tc == other->current_tc)
1552         other->active_tc.CP0_Debug_tcstatus = val;
1553     else
1554         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1555     other->CP0_Debug = (other->CP0_Debug &
1556                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1557                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1558 }
1559
1560 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1561 {
1562     env->CP0_Performance0 = arg1 & 0x000007ff;
1563 }
1564
1565 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1566 {
1567     env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1568 }
1569
1570 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1571 {
1572     env->CP0_DataLo = arg1; /* XXX */
1573 }
1574
1575 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1576 {
1577     env->CP0_TagHi = arg1; /* XXX */
1578 }
1579
1580 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1581 {
1582     env->CP0_DataHi = arg1; /* XXX */
1583 }
1584
1585 /* MIPS MT functions */
1586 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1587 {
1588     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1589     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1590
1591     if (other_tc == other->current_tc)
1592         return other->active_tc.gpr[sel];
1593     else
1594         return other->tcs[other_tc].gpr[sel];
1595 }
1596
1597 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1598 {
1599     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1600     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1601
1602     if (other_tc == other->current_tc)
1603         return other->active_tc.LO[sel];
1604     else
1605         return other->tcs[other_tc].LO[sel];
1606 }
1607
1608 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1609 {
1610     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1611     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1612
1613     if (other_tc == other->current_tc)
1614         return other->active_tc.HI[sel];
1615     else
1616         return other->tcs[other_tc].HI[sel];
1617 }
1618
1619 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1620 {
1621     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1622     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1623
1624     if (other_tc == other->current_tc)
1625         return other->active_tc.ACX[sel];
1626     else
1627         return other->tcs[other_tc].ACX[sel];
1628 }
1629
1630 target_ulong helper_mftdsp(CPUMIPSState *env)
1631 {
1632     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1633     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1634
1635     if (other_tc == other->current_tc)
1636         return other->active_tc.DSPControl;
1637     else
1638         return other->tcs[other_tc].DSPControl;
1639 }
1640
1641 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1642 {
1643     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1644     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1645
1646     if (other_tc == other->current_tc)
1647         other->active_tc.gpr[sel] = arg1;
1648     else
1649         other->tcs[other_tc].gpr[sel] = arg1;
1650 }
1651
1652 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1653 {
1654     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1655     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1656
1657     if (other_tc == other->current_tc)
1658         other->active_tc.LO[sel] = arg1;
1659     else
1660         other->tcs[other_tc].LO[sel] = arg1;
1661 }
1662
1663 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1664 {
1665     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1666     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1667
1668     if (other_tc == other->current_tc)
1669         other->active_tc.HI[sel] = arg1;
1670     else
1671         other->tcs[other_tc].HI[sel] = arg1;
1672 }
1673
1674 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1675 {
1676     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1677     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1678
1679     if (other_tc == other->current_tc)
1680         other->active_tc.ACX[sel] = arg1;
1681     else
1682         other->tcs[other_tc].ACX[sel] = arg1;
1683 }
1684
1685 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1686 {
1687     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1688     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1689
1690     if (other_tc == other->current_tc)
1691         other->active_tc.DSPControl = arg1;
1692     else
1693         other->tcs[other_tc].DSPControl = arg1;
1694 }
1695
1696 /* MIPS MT functions */
1697 target_ulong helper_dmt(void)
1698 {
1699     // TODO
1700      return 0;
1701 }
1702
1703 target_ulong helper_emt(void)
1704 {
1705     // TODO
1706     return 0;
1707 }
1708
1709 target_ulong helper_dvpe(CPUMIPSState *env)
1710 {
1711     CPUState *other_cs = first_cpu;
1712     target_ulong prev = env->mvp->CP0_MVPControl;
1713
1714     CPU_FOREACH(other_cs) {
1715         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1716         /* Turn off all VPEs except the one executing the dvpe.  */
1717         if (&other_cpu->env != env) {
1718             other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1719             mips_vpe_sleep(other_cpu);
1720         }
1721     }
1722     return prev;
1723 }
1724
1725 target_ulong helper_evpe(CPUMIPSState *env)
1726 {
1727     CPUState *other_cs = first_cpu;
1728     target_ulong prev = env->mvp->CP0_MVPControl;
1729
1730     CPU_FOREACH(other_cs) {
1731         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1732
1733         if (&other_cpu->env != env
1734             /* If the VPE is WFI, don't disturb its sleep.  */
1735             && !mips_vpe_is_wfi(other_cpu)) {
1736             /* Enable the VPE.  */
1737             other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1738             mips_vpe_wake(other_cpu); /* And wake it up.  */
1739         }
1740     }
1741     return prev;
1742 }
1743 #endif /* !CONFIG_USER_ONLY */
1744
1745 void helper_fork(target_ulong arg1, target_ulong arg2)
1746 {
1747     // arg1 = rt, arg2 = rs
1748     // TODO: store to TC register
1749 }
1750
1751 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1752 {
1753     target_long arg1 = arg;
1754
1755     if (arg1 < 0) {
1756         /* No scheduling policy implemented. */
1757         if (arg1 != -2) {
1758             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1759                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1760                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1761                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1762                 helper_raise_exception(env, EXCP_THREAD);
1763             }
1764         }
1765     } else if (arg1 == 0) {
1766         if (0 /* TODO: TC underflow */) {
1767             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1768             helper_raise_exception(env, EXCP_THREAD);
1769         } else {
1770             // TODO: Deallocate TC
1771         }
1772     } else if (arg1 > 0) {
1773         /* Yield qualifier inputs not implemented. */
1774         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1775         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1776         helper_raise_exception(env, EXCP_THREAD);
1777     }
1778     return env->CP0_YQMask;
1779 }
1780
1781 #ifndef CONFIG_USER_ONLY
1782 /* TLB management */
1783 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1784 {
1785     /* Flush qemu's TLB and discard all shadowed entries.  */
1786     tlb_flush (env, flush_global);
1787     env->tlb->tlb_in_use = env->tlb->nb_tlb;
1788 }
1789
1790 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1791 {
1792     /* Discard entries from env->tlb[first] onwards.  */
1793     while (env->tlb->tlb_in_use > first) {
1794         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1795     }
1796 }
1797
1798 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1799 {
1800     r4k_tlb_t *tlb;
1801
1802     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1803     tlb = &env->tlb->mmu.r4k.tlb[idx];
1804     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1805 #if defined(TARGET_MIPS64)
1806     tlb->VPN &= env->SEGMask;
1807 #endif
1808     tlb->ASID = env->CP0_EntryHi & 0xFF;
1809     tlb->PageMask = env->CP0_PageMask;
1810     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1811     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1812     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1813     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1814     tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1815     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1816     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1817     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1818     tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1819 }
1820
1821 void r4k_helper_tlbwi(CPUMIPSState *env)
1822 {
1823     r4k_tlb_t *tlb;
1824     int idx;
1825     target_ulong VPN;
1826     uint8_t ASID;
1827     bool G, V0, D0, V1, D1;
1828
1829     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1830     tlb = &env->tlb->mmu.r4k.tlb[idx];
1831     VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1832 #if defined(TARGET_MIPS64)
1833     VPN &= env->SEGMask;
1834 #endif
1835     ASID = env->CP0_EntryHi & 0xff;
1836     G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1837     V0 = (env->CP0_EntryLo0 & 2) != 0;
1838     D0 = (env->CP0_EntryLo0 & 4) != 0;
1839     V1 = (env->CP0_EntryLo1 & 2) != 0;
1840     D1 = (env->CP0_EntryLo1 & 4) != 0;
1841
1842     /* Discard cached TLB entries, unless tlbwi is just upgrading access
1843        permissions on the current entry. */
1844     if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1845         (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1846         (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1847         r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1848     }
1849
1850     r4k_invalidate_tlb(env, idx, 0);
1851     r4k_fill_tlb(env, idx);
1852 }
1853
1854 void r4k_helper_tlbwr(CPUMIPSState *env)
1855 {
1856     int r = cpu_mips_get_random(env);
1857
1858     r4k_invalidate_tlb(env, r, 1);
1859     r4k_fill_tlb(env, r);
1860 }
1861
1862 void r4k_helper_tlbp(CPUMIPSState *env)
1863 {
1864     r4k_tlb_t *tlb;
1865     target_ulong mask;
1866     target_ulong tag;
1867     target_ulong VPN;
1868     uint8_t ASID;
1869     int i;
1870
1871     ASID = env->CP0_EntryHi & 0xFF;
1872     for (i = 0; i < env->tlb->nb_tlb; i++) {
1873         tlb = &env->tlb->mmu.r4k.tlb[i];
1874         /* 1k pages are not supported. */
1875         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1876         tag = env->CP0_EntryHi & ~mask;
1877         VPN = tlb->VPN & ~mask;
1878 #if defined(TARGET_MIPS64)
1879         tag &= env->SEGMask;
1880 #endif
1881         /* Check ASID, virtual page number & size */
1882         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1883             /* TLB match */
1884             env->CP0_Index = i;
1885             break;
1886         }
1887     }
1888     if (i == env->tlb->nb_tlb) {
1889         /* No match.  Discard any shadow entries, if any of them match.  */
1890         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1891             tlb = &env->tlb->mmu.r4k.tlb[i];
1892             /* 1k pages are not supported. */
1893             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1894             tag = env->CP0_EntryHi & ~mask;
1895             VPN = tlb->VPN & ~mask;
1896 #if defined(TARGET_MIPS64)
1897             tag &= env->SEGMask;
1898 #endif
1899             /* Check ASID, virtual page number & size */
1900             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1901                 r4k_mips_tlb_flush_extra (env, i);
1902                 break;
1903             }
1904         }
1905
1906         env->CP0_Index |= 0x80000000;
1907     }
1908 }
1909
1910 void r4k_helper_tlbr(CPUMIPSState *env)
1911 {
1912     r4k_tlb_t *tlb;
1913     uint8_t ASID;
1914     int idx;
1915
1916     ASID = env->CP0_EntryHi & 0xFF;
1917     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1918     tlb = &env->tlb->mmu.r4k.tlb[idx];
1919
1920     /* If this will change the current ASID, flush qemu's TLB.  */
1921     if (ASID != tlb->ASID)
1922         cpu_mips_tlb_flush (env, 1);
1923
1924     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1925
1926     env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1927     env->CP0_PageMask = tlb->PageMask;
1928     env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1929                         (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1930     env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1931                         (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1932 }
1933
1934 void helper_tlbwi(CPUMIPSState *env)
1935 {
1936     env->tlb->helper_tlbwi(env);
1937 }
1938
1939 void helper_tlbwr(CPUMIPSState *env)
1940 {
1941     env->tlb->helper_tlbwr(env);
1942 }
1943
1944 void helper_tlbp(CPUMIPSState *env)
1945 {
1946     env->tlb->helper_tlbp(env);
1947 }
1948
1949 void helper_tlbr(CPUMIPSState *env)
1950 {
1951     env->tlb->helper_tlbr(env);
1952 }
1953
1954 /* Specials */
1955 target_ulong helper_di(CPUMIPSState *env)
1956 {
1957     target_ulong t0 = env->CP0_Status;
1958
1959     env->CP0_Status = t0 & ~(1 << CP0St_IE);
1960     return t0;
1961 }
1962
1963 target_ulong helper_ei(CPUMIPSState *env)
1964 {
1965     target_ulong t0 = env->CP0_Status;
1966
1967     env->CP0_Status = t0 | (1 << CP0St_IE);
1968     return t0;
1969 }
1970
1971 static void debug_pre_eret(CPUMIPSState *env)
1972 {
1973     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1974         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1975                 env->active_tc.PC, env->CP0_EPC);
1976         if (env->CP0_Status & (1 << CP0St_ERL))
1977             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1978         if (env->hflags & MIPS_HFLAG_DM)
1979             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1980         qemu_log("\n");
1981     }
1982 }
1983
1984 static void debug_post_eret(CPUMIPSState *env)
1985 {
1986     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1987         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1988                 env->active_tc.PC, env->CP0_EPC);
1989         if (env->CP0_Status & (1 << CP0St_ERL))
1990             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1991         if (env->hflags & MIPS_HFLAG_DM)
1992             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1993         switch (env->hflags & MIPS_HFLAG_KSU) {
1994         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1995         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1996         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1997         default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1998         }
1999     }
2000 }
2001
2002 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2003 {
2004     env->active_tc.PC = error_pc & ~(target_ulong)1;
2005     if (error_pc & 1) {
2006         env->hflags |= MIPS_HFLAG_M16;
2007     } else {
2008         env->hflags &= ~(MIPS_HFLAG_M16);
2009     }
2010 }
2011
2012 void helper_eret(CPUMIPSState *env)
2013 {
2014     debug_pre_eret(env);
2015     if (env->CP0_Status & (1 << CP0St_ERL)) {
2016         set_pc(env, env->CP0_ErrorEPC);
2017         env->CP0_Status &= ~(1 << CP0St_ERL);
2018     } else {
2019         set_pc(env, env->CP0_EPC);
2020         env->CP0_Status &= ~(1 << CP0St_EXL);
2021     }
2022     compute_hflags(env);
2023     debug_post_eret(env);
2024     env->lladdr = 1;
2025 }
2026
2027 void helper_deret(CPUMIPSState *env)
2028 {
2029     debug_pre_eret(env);
2030     set_pc(env, env->CP0_DEPC);
2031
2032     env->hflags &= MIPS_HFLAG_DM;
2033     compute_hflags(env);
2034     debug_post_eret(env);
2035     env->lladdr = 1;
2036 }
2037 #endif /* !CONFIG_USER_ONLY */
2038
2039 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2040 {
2041     if ((env->hflags & MIPS_HFLAG_CP0) ||
2042         (env->CP0_HWREna & (1 << 0)))
2043         return env->CP0_EBase & 0x3ff;
2044     else
2045         helper_raise_exception(env, EXCP_RI);
2046
2047     return 0;
2048 }
2049
2050 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2051 {
2052     if ((env->hflags & MIPS_HFLAG_CP0) ||
2053         (env->CP0_HWREna & (1 << 1)))
2054         return env->SYNCI_Step;
2055     else
2056         helper_raise_exception(env, EXCP_RI);
2057
2058     return 0;
2059 }
2060
2061 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2062 {
2063     if ((env->hflags & MIPS_HFLAG_CP0) ||
2064         (env->CP0_HWREna & (1 << 2)))
2065         return env->CP0_Count;
2066     else
2067         helper_raise_exception(env, EXCP_RI);
2068
2069     return 0;
2070 }
2071
2072 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2073 {
2074     if ((env->hflags & MIPS_HFLAG_CP0) ||
2075         (env->CP0_HWREna & (1 << 3)))
2076         return env->CCRes;
2077     else
2078         helper_raise_exception(env, EXCP_RI);
2079
2080     return 0;
2081 }
2082
2083 void helper_pmon(CPUMIPSState *env, int function)
2084 {
2085     function /= 2;
2086     switch (function) {
2087     case 2: /* TODO: char inbyte(int waitflag); */
2088         if (env->active_tc.gpr[4] == 0)
2089             env->active_tc.gpr[2] = -1;
2090         /* Fall through */
2091     case 11: /* TODO: char inbyte (void); */
2092         env->active_tc.gpr[2] = -1;
2093         break;
2094     case 3:
2095     case 12:
2096         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2097         break;
2098     case 17:
2099         break;
2100     case 158:
2101         {
2102             unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2103             printf("%s", fmt);
2104         }
2105         break;
2106     }
2107 }
2108
2109 void helper_wait(CPUMIPSState *env)
2110 {
2111     CPUState *cs = CPU(mips_env_get_cpu(env));
2112
2113     cs->halted = 1;
2114     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2115     helper_raise_exception(env, EXCP_HLT);
2116 }
2117
2118 #if !defined(CONFIG_USER_ONLY)
2119
2120 static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env,
2121                                               target_ulong addr, int is_write,
2122                                               int is_user, uintptr_t retaddr);
2123
2124 #define MMUSUFFIX _mmu
2125 #define ALIGNED_ONLY
2126
2127 #define SHIFT 0
2128 #include "exec/softmmu_template.h"
2129
2130 #define SHIFT 1
2131 #include "exec/softmmu_template.h"
2132
2133 #define SHIFT 2
2134 #include "exec/softmmu_template.h"
2135
2136 #define SHIFT 3
2137 #include "exec/softmmu_template.h"
2138
2139 static void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
2140                                 int is_write, int is_user, uintptr_t retaddr)
2141 {
2142     env->CP0_BadVAddr = addr;
2143     do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr);
2144 }
2145
2146 void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx,
2147               uintptr_t retaddr)
2148 {
2149     int ret;
2150
2151     ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx);
2152     if (ret) {
2153         do_raise_exception_err(env, env->exception_index,
2154                                env->error_code, retaddr);
2155     }
2156 }
2157
2158 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2159                                 bool is_write, bool is_exec, int unused,
2160                                 unsigned size)
2161 {
2162     MIPSCPU *cpu = MIPS_CPU(cs);
2163     CPUMIPSState *env = &cpu->env;
2164
2165     if (is_exec) {
2166         helper_raise_exception(env, EXCP_IBE);
2167     } else {
2168         helper_raise_exception(env, EXCP_DBE);
2169     }
2170 }
2171 #endif /* !CONFIG_USER_ONLY */
2172
2173 /* Complex FPU operations which may need stack space. */
2174
2175 #define FLOAT_TWO32 make_float32(1 << 30)
2176 #define FLOAT_TWO64 make_float64(1ULL << 62)
2177 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2178 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2179
2180 /* convert MIPS rounding mode in FCR31 to IEEE library */
2181 static unsigned int ieee_rm[] = {
2182     float_round_nearest_even,
2183     float_round_to_zero,
2184     float_round_up,
2185     float_round_down
2186 };
2187
2188 static inline void restore_rounding_mode(CPUMIPSState *env)
2189 {
2190     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
2191                             &env->active_fpu.fp_status);
2192 }
2193
2194 static inline void restore_flush_mode(CPUMIPSState *env)
2195 {
2196     set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
2197                       &env->active_fpu.fp_status);
2198 }
2199
2200 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2201 {
2202     target_ulong arg1 = 0;
2203
2204     switch (reg) {
2205     case 0:
2206         arg1 = (int32_t)env->active_fpu.fcr0;
2207         break;
2208     case 1:
2209         /* UFR Support - Read Status FR */
2210         if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2211             if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2212                 arg1 = (int32_t)
2213                        ((env->CP0_Status & (1  << CP0St_FR)) >> CP0St_FR);
2214             } else {
2215                 helper_raise_exception(env, EXCP_RI);
2216             }
2217         }
2218         break;
2219     case 25:
2220         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2221         break;
2222     case 26:
2223         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2224         break;
2225     case 28:
2226         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2227         break;
2228     default:
2229         arg1 = (int32_t)env->active_fpu.fcr31;
2230         break;
2231     }
2232
2233     return arg1;
2234 }
2235
2236 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2237 {
2238     switch (fs) {
2239     case 1:
2240         /* UFR Alias - Reset Status FR */
2241         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2242             return;
2243         }
2244         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2245             env->CP0_Status &= ~(1 << CP0St_FR);
2246             compute_hflags(env);
2247         } else {
2248             helper_raise_exception(env, EXCP_RI);
2249         }
2250         break;
2251     case 4:
2252         /* UNFR Alias - Set Status FR */
2253         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2254             return;
2255         }
2256         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2257             env->CP0_Status |= (1 << CP0St_FR);
2258             compute_hflags(env);
2259         } else {
2260             helper_raise_exception(env, EXCP_RI);
2261         }
2262         break;
2263     case 25:
2264         if (arg1 & 0xffffff00)
2265             return;
2266         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2267                      ((arg1 & 0x1) << 23);
2268         break;
2269     case 26:
2270         if (arg1 & 0x007c0000)
2271             return;
2272         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2273         break;
2274     case 28:
2275         if (arg1 & 0x007c0000)
2276             return;
2277         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2278                      ((arg1 & 0x4) << 22);
2279         break;
2280     case 31:
2281         if (arg1 & 0x007c0000)
2282             return;
2283         env->active_fpu.fcr31 = arg1;
2284         break;
2285     default:
2286         return;
2287     }
2288     /* set rounding mode */
2289     restore_rounding_mode(env);
2290     /* set flush-to-zero mode */
2291     restore_flush_mode(env);
2292     set_float_exception_flags(0, &env->active_fpu.fp_status);
2293     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2294         do_raise_exception(env, EXCP_FPE, GETPC());
2295 }
2296
2297 static inline int ieee_ex_to_mips(int xcpt)
2298 {
2299     int ret = 0;
2300     if (xcpt) {
2301         if (xcpt & float_flag_invalid) {
2302             ret |= FP_INVALID;
2303         }
2304         if (xcpt & float_flag_overflow) {
2305             ret |= FP_OVERFLOW;
2306         }
2307         if (xcpt & float_flag_underflow) {
2308             ret |= FP_UNDERFLOW;
2309         }
2310         if (xcpt & float_flag_divbyzero) {
2311             ret |= FP_DIV0;
2312         }
2313         if (xcpt & float_flag_inexact) {
2314             ret |= FP_INEXACT;
2315         }
2316     }
2317     return ret;
2318 }
2319
2320 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2321 {
2322     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2323
2324     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2325
2326     if (tmp) {
2327         set_float_exception_flags(0, &env->active_fpu.fp_status);
2328
2329         if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2330             do_raise_exception(env, EXCP_FPE, pc);
2331         } else {
2332             UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2333         }
2334     }
2335 }
2336
2337 /* Float support.
2338    Single precition routines have a "s" suffix, double precision a
2339    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2340    paired single lower "pl", paired single upper "pu".  */
2341
2342 /* unary operations, modifying fp status  */
2343 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2344 {
2345     fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2346     update_fcr31(env, GETPC());
2347     return fdt0;
2348 }
2349
2350 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2351 {
2352     fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2353     update_fcr31(env, GETPC());
2354     return fst0;
2355 }
2356
2357 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2358 {
2359     uint64_t fdt2;
2360
2361     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2362     update_fcr31(env, GETPC());
2363     return fdt2;
2364 }
2365
2366 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2367 {
2368     uint64_t fdt2;
2369
2370     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2371     update_fcr31(env, GETPC());
2372     return fdt2;
2373 }
2374
2375 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2376 {
2377     uint64_t fdt2;
2378
2379     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2380     update_fcr31(env, GETPC());
2381     return fdt2;
2382 }
2383
2384 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2385 {
2386     uint64_t dt2;
2387
2388     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2389     if (get_float_exception_flags(&env->active_fpu.fp_status)
2390         & (float_flag_invalid | float_flag_overflow)) {
2391         dt2 = FP_TO_INT64_OVERFLOW;
2392     }
2393     update_fcr31(env, GETPC());
2394     return dt2;
2395 }
2396
2397 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2398 {
2399     uint64_t dt2;
2400
2401     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2402     if (get_float_exception_flags(&env->active_fpu.fp_status)
2403         & (float_flag_invalid | float_flag_overflow)) {
2404         dt2 = FP_TO_INT64_OVERFLOW;
2405     }
2406     update_fcr31(env, GETPC());
2407     return dt2;
2408 }
2409
2410 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2411 {
2412     uint32_t fst2;
2413     uint32_t fsth2;
2414
2415     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2416     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2417     update_fcr31(env, GETPC());
2418     return ((uint64_t)fsth2 << 32) | fst2;
2419 }
2420
2421 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2422 {
2423     uint32_t wt2;
2424     uint32_t wth2;
2425     int excp, excph;
2426
2427     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2428     excp = get_float_exception_flags(&env->active_fpu.fp_status);
2429     if (excp & (float_flag_overflow | float_flag_invalid)) {
2430         wt2 = FP_TO_INT32_OVERFLOW;
2431     }
2432
2433     set_float_exception_flags(0, &env->active_fpu.fp_status);
2434     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2435     excph = get_float_exception_flags(&env->active_fpu.fp_status);
2436     if (excph & (float_flag_overflow | float_flag_invalid)) {
2437         wth2 = FP_TO_INT32_OVERFLOW;
2438     }
2439
2440     set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2441     update_fcr31(env, GETPC());
2442
2443     return ((uint64_t)wth2 << 32) | wt2;
2444 }
2445
2446 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2447 {
2448     uint32_t fst2;
2449
2450     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2451     update_fcr31(env, GETPC());
2452     return fst2;
2453 }
2454
2455 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2456 {
2457     uint32_t fst2;
2458
2459     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2460     update_fcr31(env, GETPC());
2461     return fst2;
2462 }
2463
2464 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2465 {
2466     uint32_t fst2;
2467
2468     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2469     update_fcr31(env, GETPC());
2470     return fst2;
2471 }
2472
2473 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2474 {
2475     uint32_t wt2;
2476
2477     wt2 = wt0;
2478     update_fcr31(env, GETPC());
2479     return wt2;
2480 }
2481
2482 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2483 {
2484     uint32_t wt2;
2485
2486     wt2 = wth0;
2487     update_fcr31(env, GETPC());
2488     return wt2;
2489 }
2490
2491 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2492 {
2493     uint32_t wt2;
2494
2495     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2496     update_fcr31(env, GETPC());
2497     if (get_float_exception_flags(&env->active_fpu.fp_status)
2498         & (float_flag_invalid | float_flag_overflow)) {
2499         wt2 = FP_TO_INT32_OVERFLOW;
2500     }
2501     return wt2;
2502 }
2503
2504 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2505 {
2506     uint32_t wt2;
2507
2508     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2509     if (get_float_exception_flags(&env->active_fpu.fp_status)
2510         & (float_flag_invalid | float_flag_overflow)) {
2511         wt2 = FP_TO_INT32_OVERFLOW;
2512     }
2513     update_fcr31(env, GETPC());
2514     return wt2;
2515 }
2516
2517 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2518 {
2519     uint64_t dt2;
2520
2521     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2522     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2523     restore_rounding_mode(env);
2524     if (get_float_exception_flags(&env->active_fpu.fp_status)
2525         & (float_flag_invalid | float_flag_overflow)) {
2526         dt2 = FP_TO_INT64_OVERFLOW;
2527     }
2528     update_fcr31(env, GETPC());
2529     return dt2;
2530 }
2531
2532 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2533 {
2534     uint64_t dt2;
2535
2536     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2537     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2538     restore_rounding_mode(env);
2539     if (get_float_exception_flags(&env->active_fpu.fp_status)
2540         & (float_flag_invalid | float_flag_overflow)) {
2541         dt2 = FP_TO_INT64_OVERFLOW;
2542     }
2543     update_fcr31(env, GETPC());
2544     return dt2;
2545 }
2546
2547 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2548 {
2549     uint32_t wt2;
2550
2551     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2552     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2553     restore_rounding_mode(env);
2554     if (get_float_exception_flags(&env->active_fpu.fp_status)
2555         & (float_flag_invalid | float_flag_overflow)) {
2556         wt2 = FP_TO_INT32_OVERFLOW;
2557     }
2558     update_fcr31(env, GETPC());
2559     return wt2;
2560 }
2561
2562 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2563 {
2564     uint32_t wt2;
2565
2566     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2567     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2568     restore_rounding_mode(env);
2569     if (get_float_exception_flags(&env->active_fpu.fp_status)
2570         & (float_flag_invalid | float_flag_overflow)) {
2571         wt2 = FP_TO_INT32_OVERFLOW;
2572     }
2573     update_fcr31(env, GETPC());
2574     return wt2;
2575 }
2576
2577 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2578 {
2579     uint64_t dt2;
2580
2581     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2582     if (get_float_exception_flags(&env->active_fpu.fp_status)
2583         & (float_flag_invalid | float_flag_overflow)) {
2584         dt2 = FP_TO_INT64_OVERFLOW;
2585     }
2586     update_fcr31(env, GETPC());
2587     return dt2;
2588 }
2589
2590 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2591 {
2592     uint64_t dt2;
2593
2594     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2595     if (get_float_exception_flags(&env->active_fpu.fp_status)
2596         & (float_flag_invalid | float_flag_overflow)) {
2597         dt2 = FP_TO_INT64_OVERFLOW;
2598     }
2599     update_fcr31(env, GETPC());
2600     return dt2;
2601 }
2602
2603 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2604 {
2605     uint32_t wt2;
2606
2607     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2608     if (get_float_exception_flags(&env->active_fpu.fp_status)
2609         & (float_flag_invalid | float_flag_overflow)) {
2610         wt2 = FP_TO_INT32_OVERFLOW;
2611     }
2612     update_fcr31(env, GETPC());
2613     return wt2;
2614 }
2615
2616 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2617 {
2618     uint32_t wt2;
2619
2620     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2621     if (get_float_exception_flags(&env->active_fpu.fp_status)
2622         & (float_flag_invalid | float_flag_overflow)) {
2623         wt2 = FP_TO_INT32_OVERFLOW;
2624     }
2625     update_fcr31(env, GETPC());
2626     return wt2;
2627 }
2628
2629 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2630 {
2631     uint64_t dt2;
2632
2633     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2634     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2635     restore_rounding_mode(env);
2636     if (get_float_exception_flags(&env->active_fpu.fp_status)
2637         & (float_flag_invalid | float_flag_overflow)) {
2638         dt2 = FP_TO_INT64_OVERFLOW;
2639     }
2640     update_fcr31(env, GETPC());
2641     return dt2;
2642 }
2643
2644 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2645 {
2646     uint64_t dt2;
2647
2648     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2649     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2650     restore_rounding_mode(env);
2651     if (get_float_exception_flags(&env->active_fpu.fp_status)
2652         & (float_flag_invalid | float_flag_overflow)) {
2653         dt2 = FP_TO_INT64_OVERFLOW;
2654     }
2655     update_fcr31(env, GETPC());
2656     return dt2;
2657 }
2658
2659 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2660 {
2661     uint32_t wt2;
2662
2663     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2664     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2665     restore_rounding_mode(env);
2666     if (get_float_exception_flags(&env->active_fpu.fp_status)
2667         & (float_flag_invalid | float_flag_overflow)) {
2668         wt2 = FP_TO_INT32_OVERFLOW;
2669     }
2670     update_fcr31(env, GETPC());
2671     return wt2;
2672 }
2673
2674 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2675 {
2676     uint32_t wt2;
2677
2678     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2679     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2680     restore_rounding_mode(env);
2681     if (get_float_exception_flags(&env->active_fpu.fp_status)
2682         & (float_flag_invalid | float_flag_overflow)) {
2683         wt2 = FP_TO_INT32_OVERFLOW;
2684     }
2685     update_fcr31(env, GETPC());
2686     return wt2;
2687 }
2688
2689 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2690 {
2691     uint64_t dt2;
2692
2693     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2694     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2695     restore_rounding_mode(env);
2696     if (get_float_exception_flags(&env->active_fpu.fp_status)
2697         & (float_flag_invalid | float_flag_overflow)) {
2698         dt2 = FP_TO_INT64_OVERFLOW;
2699     }
2700     update_fcr31(env, GETPC());
2701     return dt2;
2702 }
2703
2704 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2705 {
2706     uint64_t dt2;
2707
2708     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2709     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2710     restore_rounding_mode(env);
2711     if (get_float_exception_flags(&env->active_fpu.fp_status)
2712         & (float_flag_invalid | float_flag_overflow)) {
2713         dt2 = FP_TO_INT64_OVERFLOW;
2714     }
2715     update_fcr31(env, GETPC());
2716     return dt2;
2717 }
2718
2719 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2720 {
2721     uint32_t wt2;
2722
2723     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2724     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2725     restore_rounding_mode(env);
2726     if (get_float_exception_flags(&env->active_fpu.fp_status)
2727         & (float_flag_invalid | float_flag_overflow)) {
2728         wt2 = FP_TO_INT32_OVERFLOW;
2729     }
2730     update_fcr31(env, GETPC());
2731     return wt2;
2732 }
2733
2734 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2735 {
2736     uint32_t wt2;
2737
2738     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2739     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2740     restore_rounding_mode(env);
2741     if (get_float_exception_flags(&env->active_fpu.fp_status)
2742         & (float_flag_invalid | float_flag_overflow)) {
2743         wt2 = FP_TO_INT32_OVERFLOW;
2744     }
2745     update_fcr31(env, GETPC());
2746     return wt2;
2747 }
2748
2749 /* unary operations, not modifying fp status  */
2750 #define FLOAT_UNOP(name)                                       \
2751 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2752 {                                                              \
2753     return float64_ ## name(fdt0);                             \
2754 }                                                              \
2755 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2756 {                                                              \
2757     return float32_ ## name(fst0);                             \
2758 }                                                              \
2759 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2760 {                                                              \
2761     uint32_t wt0;                                              \
2762     uint32_t wth0;                                             \
2763                                                                \
2764     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
2765     wth0 = float32_ ## name(fdt0 >> 32);                       \
2766     return ((uint64_t)wth0 << 32) | wt0;                       \
2767 }
2768 FLOAT_UNOP(abs)
2769 FLOAT_UNOP(chs)
2770 #undef FLOAT_UNOP
2771
2772 /* MIPS specific unary operations */
2773 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2774 {
2775     uint64_t fdt2;
2776
2777     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2778     update_fcr31(env, GETPC());
2779     return fdt2;
2780 }
2781
2782 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2783 {
2784     uint32_t fst2;
2785
2786     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2787     update_fcr31(env, GETPC());
2788     return fst2;
2789 }
2790
2791 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2792 {
2793     uint64_t fdt2;
2794
2795     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2796     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2797     update_fcr31(env, GETPC());
2798     return fdt2;
2799 }
2800
2801 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2802 {
2803     uint32_t fst2;
2804
2805     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2806     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2807     update_fcr31(env, GETPC());
2808     return fst2;
2809 }
2810
2811 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
2812 {
2813     uint64_t fdt2;
2814
2815     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2816     update_fcr31(env, GETPC());
2817     return fdt2;
2818 }
2819
2820 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
2821 {
2822     uint32_t fst2;
2823
2824     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2825     update_fcr31(env, GETPC());
2826     return fst2;
2827 }
2828
2829 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
2830 {
2831     uint32_t fst2;
2832     uint32_t fsth2;
2833
2834     fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2835     fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
2836     update_fcr31(env, GETPC());
2837     return ((uint64_t)fsth2 << 32) | fst2;
2838 }
2839
2840 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
2841 {
2842     uint64_t fdt2;
2843
2844     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2845     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2846     update_fcr31(env, GETPC());
2847     return fdt2;
2848 }
2849
2850 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
2851 {
2852     uint32_t fst2;
2853
2854     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2855     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2856     update_fcr31(env, GETPC());
2857     return fst2;
2858 }
2859
2860 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
2861 {
2862     uint32_t fst2;
2863     uint32_t fsth2;
2864
2865     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2866     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2867     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2868     fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
2869     update_fcr31(env, GETPC());
2870     return ((uint64_t)fsth2 << 32) | fst2;
2871 }
2872
2873 #define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env)
2874
2875 /* binary operations */
2876 #define FLOAT_BINOP(name)                                          \
2877 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,            \
2878                                      uint64_t fdt0, uint64_t fdt1) \
2879 {                                                                  \
2880     uint64_t dt2;                                                  \
2881                                                                    \
2882     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
2883     update_fcr31(env, GETPC());                                    \
2884     return dt2;                                                    \
2885 }                                                                  \
2886                                                                    \
2887 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,            \
2888                                      uint32_t fst0, uint32_t fst1) \
2889 {                                                                  \
2890     uint32_t wt2;                                                  \
2891                                                                    \
2892     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2893     update_fcr31(env, GETPC());                                    \
2894     return wt2;                                                    \
2895 }                                                                  \
2896                                                                    \
2897 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,           \
2898                                       uint64_t fdt0,               \
2899                                       uint64_t fdt1)               \
2900 {                                                                  \
2901     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
2902     uint32_t fsth0 = fdt0 >> 32;                                   \
2903     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
2904     uint32_t fsth1 = fdt1 >> 32;                                   \
2905     uint32_t wt2;                                                  \
2906     uint32_t wth2;                                                 \
2907                                                                    \
2908     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2909     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
2910     update_fcr31(env, GETPC());                                    \
2911     return ((uint64_t)wth2 << 32) | wt2;                           \
2912 }
2913
2914 FLOAT_BINOP(add)
2915 FLOAT_BINOP(sub)
2916 FLOAT_BINOP(mul)
2917 FLOAT_BINOP(div)
2918 #undef FLOAT_BINOP
2919
2920 #define UNFUSED_FMA(prefix, a, b, c, flags)                          \
2921 {                                                                    \
2922     a = prefix##_mul(a, b, &env->active_fpu.fp_status);              \
2923     if ((flags) & float_muladd_negate_c) {                           \
2924         a = prefix##_sub(a, c, &env->active_fpu.fp_status);          \
2925     } else {                                                         \
2926         a = prefix##_add(a, c, &env->active_fpu.fp_status);          \
2927     }                                                                \
2928     if ((flags) & float_muladd_negate_result) {                      \
2929         a = prefix##_chs(a);                                         \
2930     }                                                                \
2931 }
2932
2933 /* FMA based operations */
2934 #define FLOAT_FMA(name, type)                                        \
2935 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,              \
2936                                      uint64_t fdt0, uint64_t fdt1,   \
2937                                      uint64_t fdt2)                  \
2938 {                                                                    \
2939     UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type);                    \
2940     update_fcr31(env, GETPC());                                      \
2941     return fdt0;                                                     \
2942 }                                                                    \
2943                                                                      \
2944 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,              \
2945                                      uint32_t fst0, uint32_t fst1,   \
2946                                      uint32_t fst2)                  \
2947 {                                                                    \
2948     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
2949     update_fcr31(env, GETPC());                                      \
2950     return fst0;                                                     \
2951 }                                                                    \
2952                                                                      \
2953 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,             \
2954                                       uint64_t fdt0, uint64_t fdt1,  \
2955                                       uint64_t fdt2)                 \
2956 {                                                                    \
2957     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                               \
2958     uint32_t fsth0 = fdt0 >> 32;                                     \
2959     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                               \
2960     uint32_t fsth1 = fdt1 >> 32;                                     \
2961     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                               \
2962     uint32_t fsth2 = fdt2 >> 32;                                     \
2963                                                                      \
2964     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
2965     UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type);                 \
2966     update_fcr31(env, GETPC());                                      \
2967     return ((uint64_t)fsth0 << 32) | fst0;                           \
2968 }
2969 FLOAT_FMA(madd, 0)
2970 FLOAT_FMA(msub, float_muladd_negate_c)
2971 FLOAT_FMA(nmadd, float_muladd_negate_result)
2972 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
2973 #undef FLOAT_FMA
2974
2975 /* MIPS specific binary operations */
2976 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2977 {
2978     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2979     fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
2980     update_fcr31(env, GETPC());
2981     return fdt2;
2982 }
2983
2984 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
2985 {
2986     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2987     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
2988     update_fcr31(env, GETPC());
2989     return fst2;
2990 }
2991
2992 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2993 {
2994     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2995     uint32_t fsth0 = fdt0 >> 32;
2996     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2997     uint32_t fsth2 = fdt2 >> 32;
2998
2999     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3000     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3001     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3002     fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3003     update_fcr31(env, GETPC());
3004     return ((uint64_t)fsth2 << 32) | fst2;
3005 }
3006
3007 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3008 {
3009     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3010     fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3011     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3012     update_fcr31(env, GETPC());
3013     return fdt2;
3014 }
3015
3016 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3017 {
3018     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3019     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3020     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3021     update_fcr31(env, GETPC());
3022     return fst2;
3023 }
3024
3025 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3026 {
3027     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3028     uint32_t fsth0 = fdt0 >> 32;
3029     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3030     uint32_t fsth2 = fdt2 >> 32;
3031
3032     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3033     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3034     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3035     fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3036     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3037     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3038     update_fcr31(env, GETPC());
3039     return ((uint64_t)fsth2 << 32) | fst2;
3040 }
3041
3042 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3043 {
3044     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3045     uint32_t fsth0 = fdt0 >> 32;
3046     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3047     uint32_t fsth1 = fdt1 >> 32;
3048     uint32_t fst2;
3049     uint32_t fsth2;
3050
3051     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3052     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3053     update_fcr31(env, GETPC());
3054     return ((uint64_t)fsth2 << 32) | fst2;
3055 }
3056
3057 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3058 {
3059     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3060     uint32_t fsth0 = fdt0 >> 32;
3061     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3062     uint32_t fsth1 = fdt1 >> 32;
3063     uint32_t fst2;
3064     uint32_t fsth2;
3065
3066     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3067     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3068     update_fcr31(env, GETPC());
3069     return ((uint64_t)fsth2 << 32) | fst2;
3070 }
3071
3072 /* compare operations */
3073 #define FOP_COND_D(op, cond)                                   \
3074 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3075                          uint64_t fdt1, int cc)                \
3076 {                                                              \
3077     int c;                                                     \
3078     c = cond;                                                  \
3079     update_fcr31(env, GETPC());                                \
3080     if (c)                                                     \
3081         SET_FP_COND(cc, env->active_fpu);                      \
3082     else                                                       \
3083         CLEAR_FP_COND(cc, env->active_fpu);                    \
3084 }                                                              \
3085 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3086                             uint64_t fdt1, int cc)             \
3087 {                                                              \
3088     int c;                                                     \
3089     fdt0 = float64_abs(fdt0);                                  \
3090     fdt1 = float64_abs(fdt1);                                  \
3091     c = cond;                                                  \
3092     update_fcr31(env, GETPC());                                \
3093     if (c)                                                     \
3094         SET_FP_COND(cc, env->active_fpu);                      \
3095     else                                                       \
3096         CLEAR_FP_COND(cc, env->active_fpu);                    \
3097 }
3098
3099 /* NOTE: the comma operator will make "cond" to eval to false,
3100  * but float64_unordered_quiet() is still called. */
3101 FOP_COND_D(f,   (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3102 FOP_COND_D(un,  float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3103 FOP_COND_D(eq,  float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3104 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3105 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3106 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3107 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3108 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3109 /* NOTE: the comma operator will make "cond" to eval to false,
3110  * but float64_unordered() is still called. */
3111 FOP_COND_D(sf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3112 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3113 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3114 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3115 FOP_COND_D(lt,  float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3116 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3117 FOP_COND_D(le,  float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3118 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3119
3120 #define FOP_COND_S(op, cond)                                   \
3121 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0,     \
3122                          uint32_t fst1, int cc)                \
3123 {                                                              \
3124     int c;                                                     \
3125     c = cond;                                                  \
3126     update_fcr31(env, GETPC());                                \
3127     if (c)                                                     \
3128         SET_FP_COND(cc, env->active_fpu);                      \
3129     else                                                       \
3130         CLEAR_FP_COND(cc, env->active_fpu);                    \
3131 }                                                              \
3132 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0,  \
3133                             uint32_t fst1, int cc)             \
3134 {                                                              \
3135     int c;                                                     \
3136     fst0 = float32_abs(fst0);                                  \
3137     fst1 = float32_abs(fst1);                                  \
3138     c = cond;                                                  \
3139     update_fcr31(env, GETPC());                                \
3140     if (c)                                                     \
3141         SET_FP_COND(cc, env->active_fpu);                      \
3142     else                                                       \
3143         CLEAR_FP_COND(cc, env->active_fpu);                    \
3144 }
3145
3146 /* NOTE: the comma operator will make "cond" to eval to false,
3147  * but float32_unordered_quiet() is still called. */
3148 FOP_COND_S(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3149 FOP_COND_S(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3150 FOP_COND_S(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3151 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3152 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3153 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3154 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3155 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3156 /* NOTE: the comma operator will make "cond" to eval to false,
3157  * but float32_unordered() is still called. */
3158 FOP_COND_S(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3159 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3160 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3161 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3162 FOP_COND_S(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3163 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3164 FOP_COND_S(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status))
3165 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3166
3167 #define FOP_COND_PS(op, condl, condh)                           \
3168 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3169                           uint64_t fdt1, int cc)                \
3170 {                                                               \
3171     uint32_t fst0, fsth0, fst1, fsth1;                          \
3172     int ch, cl;                                                 \
3173     fst0 = fdt0 & 0XFFFFFFFF;                                   \
3174     fsth0 = fdt0 >> 32;                                         \
3175     fst1 = fdt1 & 0XFFFFFFFF;                                   \
3176     fsth1 = fdt1 >> 32;                                         \
3177     cl = condl;                                                 \
3178     ch = condh;                                                 \
3179     update_fcr31(env, GETPC());                                 \
3180     if (cl)                                                     \
3181         SET_FP_COND(cc, env->active_fpu);                       \
3182     else                                                        \
3183         CLEAR_FP_COND(cc, env->active_fpu);                     \
3184     if (ch)                                                     \
3185         SET_FP_COND(cc + 1, env->active_fpu);                   \
3186     else                                                        \
3187         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3188 }                                                               \
3189 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3190                              uint64_t fdt1, int cc)             \
3191 {                                                               \
3192     uint32_t fst0, fsth0, fst1, fsth1;                          \
3193     int ch, cl;                                                 \
3194     fst0 = float32_abs(fdt0 & 0XFFFFFFFF);                      \
3195     fsth0 = float32_abs(fdt0 >> 32);                            \
3196     fst1 = float32_abs(fdt1 & 0XFFFFFFFF);                      \
3197     fsth1 = float32_abs(fdt1 >> 32);                            \
3198     cl = condl;                                                 \
3199     ch = condh;                                                 \
3200     update_fcr31(env, GETPC());                                 \
3201     if (cl)                                                     \
3202         SET_FP_COND(cc, env->active_fpu);                       \
3203     else                                                        \
3204         CLEAR_FP_COND(cc, env->active_fpu);                     \
3205     if (ch)                                                     \
3206         SET_FP_COND(cc + 1, env->active_fpu);                   \
3207     else                                                        \
3208         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3209 }
3210
3211 /* NOTE: the comma operator will make "cond" to eval to false,
3212  * but float32_unordered_quiet() is still called. */
3213 FOP_COND_PS(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3214                  (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3215 FOP_COND_PS(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3216                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3217 FOP_COND_PS(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3218                  float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3219 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3220                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3221 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3222                  float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3223 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3224                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3225 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3226                  float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3227 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3228                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3229 /* NOTE: the comma operator will make "cond" to eval to false,
3230  * but float32_unordered() is still called. */
3231 FOP_COND_PS(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3232                  (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3233 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3234                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3235 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3236                  float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3237 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3238                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3239 FOP_COND_PS(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3240                  float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3241 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3242                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3243 FOP_COND_PS(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status),
3244                  float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3245 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3246                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))