5 #include "exec/memory.h"
6 #include "sysemu/dma.h"
8 /* PCI includes legacy ISA access. */
9 #include "hw/isa/isa.h"
11 #include "hw/pci/pcie.h"
15 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
16 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
17 #define PCI_FUNC(devfn) ((devfn) & 0x07)
18 #define PCI_SLOT_MAX 32
19 #define PCI_FUNC_MAX 8
21 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
22 #include "hw/pci/pci_ids.h"
24 /* QEMU-specific Vendor and Device ID definitions */
27 #define PCI_DEVICE_ID_IBM_440GX 0x027f
28 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
30 /* Hitachi (0x1054) */
31 #define PCI_VENDOR_ID_HITACHI 0x1054
32 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
35 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
36 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
37 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
38 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
39 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
41 /* Realtek (0x10ec) */
42 #define PCI_DEVICE_ID_REALTEK_8029 0x8029
45 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
47 /* Marvell (0x11ab) */
48 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
50 /* QEMU/Bochs VGA (0x1234) */
51 #define PCI_VENDOR_ID_QEMU 0x1234
52 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
55 #define PCI_VENDOR_ID_VMWARE 0x15ad
56 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
57 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
58 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
59 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
60 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0
61 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
62 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
65 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209
66 #define PCI_DEVICE_ID_INTEL_82557 0x1229
67 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922
69 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
70 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
71 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
72 #define PCI_SUBDEVICE_ID_QEMU 0x1100
74 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
75 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
76 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
77 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
78 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004
79 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005
80 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009
82 #define PCI_VENDOR_ID_REDHAT 0x1b36
83 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001
84 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002
85 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003
86 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004
87 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005
88 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006
89 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007
90 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008
91 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009
92 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
93 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b
94 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100
96 #define FMT_PCIBUS PRIx64
98 typedef uint64_t pcibus_t
;
100 struct PCIHostDeviceAddress
{
104 unsigned int function
;
107 typedef void PCIConfigWriteFunc(PCIDevice
*pci_dev
,
108 uint32_t address
, uint32_t data
, int len
);
109 typedef uint32_t PCIConfigReadFunc(PCIDevice
*pci_dev
,
110 uint32_t address
, int len
);
111 typedef void PCIMapIORegionFunc(PCIDevice
*pci_dev
, int region_num
,
112 pcibus_t addr
, pcibus_t size
, int type
);
113 typedef void PCIUnregisterFunc(PCIDevice
*pci_dev
);
115 typedef struct PCIIORegion
{
116 pcibus_t addr
; /* current PCI mapping address. -1 means not mapped */
117 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
120 MemoryRegion
*memory
;
121 MemoryRegion
*address_space
;
124 #define PCI_ROM_SLOT 6
125 #define PCI_NUM_REGIONS 7
131 QEMU_PCI_VGA_NUM_REGIONS
,
134 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
135 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
136 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
137 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
138 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
139 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
141 #include "hw/pci/pci_regs.h"
143 /* PCI HEADER_TYPE */
144 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
146 /* Size of the standard PCI config header */
147 #define PCI_CONFIG_HEADER_SIZE 0x40
148 /* Size of the standard PCI config space */
149 #define PCI_CONFIG_SPACE_SIZE 0x100
150 /* Size of the standard PCIe config space: 4KB */
151 #define PCIE_CONFIG_SPACE_SIZE 0x1000
153 #define PCI_NUM_PINS 4 /* A-D */
155 /* Bits in cap_present field. */
157 QEMU_PCI_CAP_MSI
= 0x1,
158 QEMU_PCI_CAP_MSIX
= 0x2,
159 QEMU_PCI_CAP_EXPRESS
= 0x4,
161 /* multifunction capable device */
162 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
163 QEMU_PCI_CAP_MULTIFUNCTION
= (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR
),
165 /* command register SERR bit enabled */
166 #define QEMU_PCI_CAP_SERR_BITNR 4
167 QEMU_PCI_CAP_SERR
= (1 << QEMU_PCI_CAP_SERR_BITNR
),
168 /* Standard hot plug controller. */
169 #define QEMU_PCI_SHPC_BITNR 5
170 QEMU_PCI_CAP_SHPC
= (1 << QEMU_PCI_SHPC_BITNR
),
171 #define QEMU_PCI_SLOTID_BITNR 6
172 QEMU_PCI_CAP_SLOTID
= (1 << QEMU_PCI_SLOTID_BITNR
),
173 /* PCI Express capability - Power Controller Present */
174 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7
175 QEMU_PCIE_SLTCAP_PCP
= (1 << QEMU_PCIE_SLTCAP_PCP_BITNR
),
178 #define TYPE_PCI_DEVICE "pci-device"
179 #define PCI_DEVICE(obj) \
180 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
181 #define PCI_DEVICE_CLASS(klass) \
182 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
183 #define PCI_DEVICE_GET_CLASS(obj) \
184 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
186 typedef struct PCIINTxRoute
{
195 typedef struct PCIDeviceClass
{
196 DeviceClass parent_class
;
198 void (*realize
)(PCIDevice
*dev
, Error
**errp
);
199 int (*init
)(PCIDevice
*dev
);/* TODO convert to realize() and remove */
200 PCIUnregisterFunc
*exit
;
201 PCIConfigReadFunc
*config_read
;
202 PCIConfigWriteFunc
*config_write
;
208 uint16_t subsystem_vendor_id
; /* only for header type = 0 */
209 uint16_t subsystem_id
; /* only for header type = 0 */
212 * pci-to-pci bridge or normal device.
213 * This doesn't mean pci host switch.
214 * When card bus bridge is supported, this would be enhanced.
219 int is_express
; /* is this device pci express? */
225 typedef void (*PCIINTxRoutingNotifier
)(PCIDevice
*dev
);
226 typedef int (*MSIVectorUseNotifier
)(PCIDevice
*dev
, unsigned int vector
,
228 typedef void (*MSIVectorReleaseNotifier
)(PCIDevice
*dev
, unsigned int vector
);
229 typedef void (*MSIVectorPollNotifier
)(PCIDevice
*dev
,
230 unsigned int vector_start
,
231 unsigned int vector_end
);
236 /* PCI config space */
239 /* Used to enable config checks on load. Note that writable bits are
240 * never checked even if set in cmask. */
243 /* Used to implement R/W bytes */
246 /* Used to implement RW1C(Write 1 to Clear) bytes */
249 /* Used to allocate config space for capabilities. */
252 /* the following fields are read only */
256 PCIIORegion io_regions
[PCI_NUM_REGIONS
];
257 AddressSpace bus_master_as
;
258 MemoryRegion bus_master_enable_region
;
260 /* do not access the following fields */
261 PCIConfigReadFunc
*config_read
;
262 PCIConfigWriteFunc
*config_write
;
264 /* Legacy PCI VGA regions */
265 MemoryRegion
*vga_regions
[QEMU_PCI_VGA_NUM_REGIONS
];
268 /* Current IRQ levels. Used internally by the generic PCI code. */
271 /* Capability bits */
272 uint32_t cap_present
;
274 /* Offset of MSI-X capability in config space */
280 /* Space to store MSIX table & pending bit array */
283 /* MemoryRegion container for msix exclusive BAR setup */
284 MemoryRegion msix_exclusive_bar
;
285 /* Memory Regions for MSIX table and pending bit entries. */
286 MemoryRegion msix_table_mmio
;
287 MemoryRegion msix_pba_mmio
;
288 /* Reference-count for entries actually in use by driver. */
289 unsigned *msix_entry_used
;
290 /* MSIX function mask set or MSIX disabled */
291 bool msix_function_masked
;
292 /* Version id needed for VMState */
295 /* Offset of MSI capability in config space */
299 PCIExpressDevice exp
;
304 /* Location of option rom */
310 /* INTx routing notifier */
311 PCIINTxRoutingNotifier intx_routing_notifier
;
313 /* MSI-X notifiers */
314 MSIVectorUseNotifier msix_vector_use_notifier
;
315 MSIVectorReleaseNotifier msix_vector_release_notifier
;
316 MSIVectorPollNotifier msix_vector_poll_notifier
;
319 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
320 uint8_t attr
, MemoryRegion
*memory
);
321 void pci_register_vga(PCIDevice
*pci_dev
, MemoryRegion
*mem
,
322 MemoryRegion
*io_lo
, MemoryRegion
*io_hi
);
323 void pci_unregister_vga(PCIDevice
*pci_dev
);
324 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
);
326 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
327 uint8_t offset
, uint8_t size
);
328 int pci_add_capability2(PCIDevice
*pdev
, uint8_t cap_id
,
329 uint8_t offset
, uint8_t size
,
332 void pci_del_capability(PCIDevice
*pci_dev
, uint8_t cap_id
, uint8_t cap_size
);
334 uint8_t pci_find_capability(PCIDevice
*pci_dev
, uint8_t cap_id
);
337 uint32_t pci_default_read_config(PCIDevice
*d
,
338 uint32_t address
, int len
);
339 void pci_default_write_config(PCIDevice
*d
,
340 uint32_t address
, uint32_t val
, int len
);
341 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
);
342 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
);
343 MemoryRegion
*pci_address_space(PCIDevice
*dev
);
344 MemoryRegion
*pci_address_space_io(PCIDevice
*dev
);
347 * Should not normally be used by devices. For use by sPAPR target
348 * where QEMU emulates firmware.
350 int pci_bar(PCIDevice
*d
, int reg
);
352 typedef void (*pci_set_irq_fn
)(void *opaque
, int irq_num
, int level
);
353 typedef int (*pci_map_irq_fn
)(PCIDevice
*pci_dev
, int irq_num
);
354 typedef PCIINTxRoute (*pci_route_irq_fn
)(void *opaque
, int pin
);
356 #define TYPE_PCI_BUS "PCI"
357 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
358 #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS)
359 #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS)
360 #define TYPE_PCIE_BUS "PCIE"
362 bool pci_bus_is_express(PCIBus
*bus
);
363 bool pci_bus_is_root(PCIBus
*bus
);
364 void pci_bus_new_inplace(PCIBus
*bus
, size_t bus_size
, DeviceState
*parent
,
366 MemoryRegion
*address_space_mem
,
367 MemoryRegion
*address_space_io
,
368 uint8_t devfn_min
, const char *typename
);
369 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
,
370 MemoryRegion
*address_space_mem
,
371 MemoryRegion
*address_space_io
,
372 uint8_t devfn_min
, const char *typename
);
373 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
374 void *irq_opaque
, int nirq
);
375 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
);
376 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
377 int pci_swizzle_map_irq_fn(PCIDevice
*pci_dev
, int pin
);
378 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
379 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
381 MemoryRegion
*address_space_mem
,
382 MemoryRegion
*address_space_io
,
383 uint8_t devfn_min
, int nirq
, const char *typename
);
384 void pci_bus_set_route_irq_fn(PCIBus
*, pci_route_irq_fn
);
385 PCIINTxRoute
pci_device_route_intx_to_irq(PCIDevice
*dev
, int pin
);
386 bool pci_intx_route_changed(PCIINTxRoute
*old
, PCIINTxRoute
*new);
387 void pci_bus_fire_intx_routing_notifier(PCIBus
*bus
);
388 void pci_device_set_intx_routing_notifier(PCIDevice
*dev
,
389 PCIINTxRoutingNotifier notifier
);
390 void pci_device_reset(PCIDevice
*dev
);
392 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, PCIBus
*rootbus
,
393 const char *default_model
,
394 const char *default_devaddr
);
396 PCIDevice
*pci_vga_init(PCIBus
*bus
);
398 int pci_bus_num(PCIBus
*s
);
399 int pci_bus_numa_node(PCIBus
*bus
);
400 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
401 void (*fn
)(PCIBus
*bus
, PCIDevice
*d
, void *opaque
),
403 void pci_for_each_bus_depth_first(PCIBus
*bus
,
404 void *(*begin
)(PCIBus
*bus
, void *parent_state
),
405 void (*end
)(PCIBus
*bus
, void *state
),
407 PCIDevice
*pci_get_function_0(PCIDevice
*pci_dev
);
409 /* Use this wrapper when specific scan order is not required. */
411 void pci_for_each_bus(PCIBus
*bus
,
412 void (*fn
)(PCIBus
*bus
, void *opaque
),
415 pci_for_each_bus_depth_first(bus
, NULL
, fn
, opaque
);
418 PCIBus
*pci_find_primary_bus(void);
419 PCIBus
*pci_device_root_bus(const PCIDevice
*d
);
420 const char *pci_root_bus_path(PCIDevice
*dev
);
421 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
);
422 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
);
423 void pci_bus_get_w64_range(PCIBus
*bus
, Range
*range
);
425 void pci_device_deassert_intx(PCIDevice
*dev
);
427 typedef AddressSpace
*(*PCIIOMMUFunc
)(PCIBus
*, void *, int);
429 AddressSpace
*pci_device_iommu_address_space(PCIDevice
*dev
);
430 void pci_setup_iommu(PCIBus
*bus
, PCIIOMMUFunc fn
, void *opaque
);
433 pci_set_byte(uint8_t *config
, uint8_t val
)
438 static inline uint8_t
439 pci_get_byte(const uint8_t *config
)
445 pci_set_word(uint8_t *config
, uint16_t val
)
447 stw_le_p(config
, val
);
450 static inline uint16_t
451 pci_get_word(const uint8_t *config
)
453 return lduw_le_p(config
);
457 pci_set_long(uint8_t *config
, uint32_t val
)
459 stl_le_p(config
, val
);
462 static inline uint32_t
463 pci_get_long(const uint8_t *config
)
465 return ldl_le_p(config
);
469 * PCI capabilities and/or their fields
470 * are generally DWORD aligned only so
471 * mechanism used by pci_set/get_quad()
472 * must be tolerant to unaligned pointers
476 pci_set_quad(uint8_t *config
, uint64_t val
)
478 stq_le_p(config
, val
);
481 static inline uint64_t
482 pci_get_quad(const uint8_t *config
)
484 return ldq_le_p(config
);
488 pci_config_set_vendor_id(uint8_t *pci_config
, uint16_t val
)
490 pci_set_word(&pci_config
[PCI_VENDOR_ID
], val
);
494 pci_config_set_device_id(uint8_t *pci_config
, uint16_t val
)
496 pci_set_word(&pci_config
[PCI_DEVICE_ID
], val
);
500 pci_config_set_revision(uint8_t *pci_config
, uint8_t val
)
502 pci_set_byte(&pci_config
[PCI_REVISION_ID
], val
);
506 pci_config_set_class(uint8_t *pci_config
, uint16_t val
)
508 pci_set_word(&pci_config
[PCI_CLASS_DEVICE
], val
);
512 pci_config_set_prog_interface(uint8_t *pci_config
, uint8_t val
)
514 pci_set_byte(&pci_config
[PCI_CLASS_PROG
], val
);
518 pci_config_set_interrupt_pin(uint8_t *pci_config
, uint8_t val
)
520 pci_set_byte(&pci_config
[PCI_INTERRUPT_PIN
], val
);
524 * helper functions to do bit mask operation on configuration space.
525 * Just to set bit, use test-and-set and discard returned value.
526 * Just to clear bit, use test-and-clear and discard returned value.
527 * NOTE: They aren't atomic.
529 static inline uint8_t
530 pci_byte_test_and_clear_mask(uint8_t *config
, uint8_t mask
)
532 uint8_t val
= pci_get_byte(config
);
533 pci_set_byte(config
, val
& ~mask
);
537 static inline uint8_t
538 pci_byte_test_and_set_mask(uint8_t *config
, uint8_t mask
)
540 uint8_t val
= pci_get_byte(config
);
541 pci_set_byte(config
, val
| mask
);
545 static inline uint16_t
546 pci_word_test_and_clear_mask(uint8_t *config
, uint16_t mask
)
548 uint16_t val
= pci_get_word(config
);
549 pci_set_word(config
, val
& ~mask
);
553 static inline uint16_t
554 pci_word_test_and_set_mask(uint8_t *config
, uint16_t mask
)
556 uint16_t val
= pci_get_word(config
);
557 pci_set_word(config
, val
| mask
);
561 static inline uint32_t
562 pci_long_test_and_clear_mask(uint8_t *config
, uint32_t mask
)
564 uint32_t val
= pci_get_long(config
);
565 pci_set_long(config
, val
& ~mask
);
569 static inline uint32_t
570 pci_long_test_and_set_mask(uint8_t *config
, uint32_t mask
)
572 uint32_t val
= pci_get_long(config
);
573 pci_set_long(config
, val
| mask
);
577 static inline uint64_t
578 pci_quad_test_and_clear_mask(uint8_t *config
, uint64_t mask
)
580 uint64_t val
= pci_get_quad(config
);
581 pci_set_quad(config
, val
& ~mask
);
585 static inline uint64_t
586 pci_quad_test_and_set_mask(uint8_t *config
, uint64_t mask
)
588 uint64_t val
= pci_get_quad(config
);
589 pci_set_quad(config
, val
| mask
);
593 /* Access a register specified by a mask */
595 pci_set_byte_by_mask(uint8_t *config
, uint8_t mask
, uint8_t reg
)
597 uint8_t val
= pci_get_byte(config
);
598 uint8_t rval
= reg
<< ctz32(mask
);
599 pci_set_byte(config
, (~mask
& val
) | (mask
& rval
));
602 static inline uint8_t
603 pci_get_byte_by_mask(uint8_t *config
, uint8_t mask
)
605 uint8_t val
= pci_get_byte(config
);
606 return (val
& mask
) >> ctz32(mask
);
610 pci_set_word_by_mask(uint8_t *config
, uint16_t mask
, uint16_t reg
)
612 uint16_t val
= pci_get_word(config
);
613 uint16_t rval
= reg
<< ctz32(mask
);
614 pci_set_word(config
, (~mask
& val
) | (mask
& rval
));
617 static inline uint16_t
618 pci_get_word_by_mask(uint8_t *config
, uint16_t mask
)
620 uint16_t val
= pci_get_word(config
);
621 return (val
& mask
) >> ctz32(mask
);
625 pci_set_long_by_mask(uint8_t *config
, uint32_t mask
, uint32_t reg
)
627 uint32_t val
= pci_get_long(config
);
628 uint32_t rval
= reg
<< ctz32(mask
);
629 pci_set_long(config
, (~mask
& val
) | (mask
& rval
));
632 static inline uint32_t
633 pci_get_long_by_mask(uint8_t *config
, uint32_t mask
)
635 uint32_t val
= pci_get_long(config
);
636 return (val
& mask
) >> ctz32(mask
);
640 pci_set_quad_by_mask(uint8_t *config
, uint64_t mask
, uint64_t reg
)
642 uint64_t val
= pci_get_quad(config
);
643 uint64_t rval
= reg
<< ctz32(mask
);
644 pci_set_quad(config
, (~mask
& val
) | (mask
& rval
));
647 static inline uint64_t
648 pci_get_quad_by_mask(uint8_t *config
, uint64_t mask
)
650 uint64_t val
= pci_get_quad(config
);
651 return (val
& mask
) >> ctz32(mask
);
654 PCIDevice
*pci_create_multifunction(PCIBus
*bus
, int devfn
, bool multifunction
,
656 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
659 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
);
660 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
);
662 qemu_irq
pci_allocate_irq(PCIDevice
*pci_dev
);
663 void pci_set_irq(PCIDevice
*pci_dev
, int level
);
665 static inline void pci_irq_assert(PCIDevice
*pci_dev
)
667 pci_set_irq(pci_dev
, 1);
670 static inline void pci_irq_deassert(PCIDevice
*pci_dev
)
672 pci_set_irq(pci_dev
, 0);
676 * FIXME: PCI does not work this way.
677 * All the callers to this method should be fixed.
679 static inline void pci_irq_pulse(PCIDevice
*pci_dev
)
681 pci_irq_assert(pci_dev
);
682 pci_irq_deassert(pci_dev
);
685 static inline int pci_is_express(const PCIDevice
*d
)
687 return d
->cap_present
& QEMU_PCI_CAP_EXPRESS
;
690 static inline uint32_t pci_config_size(const PCIDevice
*d
)
692 return pci_is_express(d
) ? PCIE_CONFIG_SPACE_SIZE
: PCI_CONFIG_SPACE_SIZE
;
695 static inline uint16_t pci_requester_id(PCIDevice
*dev
)
697 return (pci_bus_num(dev
->bus
) << 8) | dev
->devfn
;
700 /* DMA access functions */
701 static inline AddressSpace
*pci_get_address_space(PCIDevice
*dev
)
703 return &dev
->bus_master_as
;
706 static inline int pci_dma_rw(PCIDevice
*dev
, dma_addr_t addr
,
707 void *buf
, dma_addr_t len
, DMADirection dir
)
709 dma_memory_rw(pci_get_address_space(dev
), addr
, buf
, len
, dir
);
713 static inline int pci_dma_read(PCIDevice
*dev
, dma_addr_t addr
,
714 void *buf
, dma_addr_t len
)
716 return pci_dma_rw(dev
, addr
, buf
, len
, DMA_DIRECTION_TO_DEVICE
);
719 static inline int pci_dma_write(PCIDevice
*dev
, dma_addr_t addr
,
720 const void *buf
, dma_addr_t len
)
722 return pci_dma_rw(dev
, addr
, (void *) buf
, len
, DMA_DIRECTION_FROM_DEVICE
);
725 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
726 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \
729 return ld##_l##_dma(pci_get_address_space(dev), addr); \
731 static inline void st##_s##_pci_dma(PCIDevice *dev, \
732 dma_addr_t addr, uint##_bits##_t val) \
734 st##_s##_dma(pci_get_address_space(dev), addr, val); \
737 PCI_DMA_DEFINE_LDST(ub
, b
, 8);
738 PCI_DMA_DEFINE_LDST(uw_le
, w_le
, 16)
739 PCI_DMA_DEFINE_LDST(l_le
, l_le
, 32);
740 PCI_DMA_DEFINE_LDST(q_le
, q_le
, 64);
741 PCI_DMA_DEFINE_LDST(uw_be
, w_be
, 16)
742 PCI_DMA_DEFINE_LDST(l_be
, l_be
, 32);
743 PCI_DMA_DEFINE_LDST(q_be
, q_be
, 64);
745 #undef PCI_DMA_DEFINE_LDST
747 static inline void *pci_dma_map(PCIDevice
*dev
, dma_addr_t addr
,
748 dma_addr_t
*plen
, DMADirection dir
)
752 buf
= dma_memory_map(pci_get_address_space(dev
), addr
, plen
, dir
);
756 static inline void pci_dma_unmap(PCIDevice
*dev
, void *buffer
, dma_addr_t len
,
757 DMADirection dir
, dma_addr_t access_len
)
759 dma_memory_unmap(pci_get_address_space(dev
), buffer
, len
, dir
, access_len
);
762 static inline void pci_dma_sglist_init(QEMUSGList
*qsg
, PCIDevice
*dev
,
765 qemu_sglist_init(qsg
, DEVICE(dev
), alloc_hint
, pci_get_address_space(dev
));
768 extern const VMStateDescription vmstate_pci_device
;
770 #define VMSTATE_PCI_DEVICE(_field, _state) { \
771 .name = (stringify(_field)), \
772 .size = sizeof(PCIDevice), \
773 .vmsd = &vmstate_pci_device, \
774 .flags = VMS_STRUCT, \
775 .offset = vmstate_offset_value(_state, _field, PCIDevice), \
778 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
779 .name = (stringify(_field)), \
780 .size = sizeof(PCIDevice), \
781 .vmsd = &vmstate_pci_device, \
782 .flags = VMS_STRUCT|VMS_POINTER, \
783 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \