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ast2600: Configure CNTFRQ at 1125MHz
[qemu/ar7.git] / hw / arm / aspeed_ast2600.c
blob89e4b009504164c3776b7f6493802bef6449704d
1 /*
2 * ASPEED SoC 2600 family
3 *
4 * Copyright (c) 2016-2019, IBM Corporation.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 */
9
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "cpu.h"
13 #include "exec/address-spaces.h"
14 #include "hw/misc/unimp.h"
15 #include "hw/arm/aspeed_soc.h"
16 #include "hw/char/serial.h"
17 #include "qemu/log.h"
18 #include "qemu/module.h"
19 #include "qemu/error-report.h"
20 #include "hw/i2c/aspeed_i2c.h"
21 #include "net/net.h"
22 #include "sysemu/sysemu.h"
23
24 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
25
26 static const hwaddr aspeed_soc_ast2600_memmap[] = {
27 [ASPEED_SRAM] = 0x10000000,
28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
29 [ASPEED_IOMEM] = 0x1E600000,
30 [ASPEED_PWM] = 0x1E610000,
31 [ASPEED_FMC] = 0x1E620000,
32 [ASPEED_SPI1] = 0x1E630000,
33 [ASPEED_SPI2] = 0x1E641000,
34 [ASPEED_MII1] = 0x1E650000,
35 [ASPEED_MII2] = 0x1E650008,
36 [ASPEED_MII3] = 0x1E650010,
37 [ASPEED_MII4] = 0x1E650018,
38 [ASPEED_ETH1] = 0x1E660000,
39 [ASPEED_ETH3] = 0x1E670000,
40 [ASPEED_ETH2] = 0x1E680000,
41 [ASPEED_ETH4] = 0x1E690000,
42 [ASPEED_VIC] = 0x1E6C0000,
43 [ASPEED_SDMC] = 0x1E6E0000,
44 [ASPEED_SCU] = 0x1E6E2000,
45 [ASPEED_XDMA] = 0x1E6E7000,
46 [ASPEED_ADC] = 0x1E6E9000,
47 [ASPEED_VIDEO] = 0x1E700000,
48 [ASPEED_SDHCI] = 0x1E740000,
49 [ASPEED_GPIO] = 0x1E780000,
50 [ASPEED_GPIO_1_8V] = 0x1E780800,
51 [ASPEED_RTC] = 0x1E781000,
52 [ASPEED_TIMER1] = 0x1E782000,
53 [ASPEED_WDT] = 0x1E785000,
54 [ASPEED_LPC] = 0x1E789000,
55 [ASPEED_IBT] = 0x1E789140,
56 [ASPEED_I2C] = 0x1E78A000,
57 [ASPEED_UART1] = 0x1E783000,
58 [ASPEED_UART5] = 0x1E784000,
59 [ASPEED_VUART] = 0x1E787000,
60 [ASPEED_SDRAM] = 0x80000000,
61 };
62
63 #define ASPEED_A7MPCORE_ADDR 0x40460000
64
65 #define ASPEED_SOC_AST2600_MAX_IRQ 128
66
67 static const int aspeed_soc_ast2600_irqmap[] = {
68 [ASPEED_UART1] = 47,
69 [ASPEED_UART2] = 48,
70 [ASPEED_UART3] = 49,
71 [ASPEED_UART4] = 50,
72 [ASPEED_UART5] = 8,
73 [ASPEED_VUART] = 8,
74 [ASPEED_FMC] = 39,
75 [ASPEED_SDMC] = 0,
76 [ASPEED_SCU] = 12,
77 [ASPEED_ADC] = 78,
78 [ASPEED_XDMA] = 6,
79 [ASPEED_SDHCI] = 43,
80 [ASPEED_GPIO] = 40,
81 [ASPEED_GPIO_1_8V] = 11,
82 [ASPEED_RTC] = 13,
83 [ASPEED_TIMER1] = 16,
84 [ASPEED_TIMER2] = 17,
85 [ASPEED_TIMER3] = 18,
86 [ASPEED_TIMER4] = 19,
87 [ASPEED_TIMER5] = 20,
88 [ASPEED_TIMER6] = 21,
89 [ASPEED_TIMER7] = 22,
90 [ASPEED_TIMER8] = 23,
91 [ASPEED_WDT] = 24,
92 [ASPEED_PWM] = 44,
93 [ASPEED_LPC] = 35,
94 [ASPEED_IBT] = 35, /* LPC */
95 [ASPEED_I2C] = 110, /* 110 -> 125 */
96 [ASPEED_ETH1] = 2,
97 [ASPEED_ETH2] = 3,
98 [ASPEED_ETH3] = 32,
99 [ASPEED_ETH4] = 33,
100
101 };
102
103 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
104 {
105 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
106
107 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]);
108 }
109
110 static void aspeed_soc_ast2600_init(Object *obj)
111 {
112 AspeedSoCState *s = ASPEED_SOC(obj);
113 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
114 int i;
115 char socname[8];
116 char typename[64];
117
118 if (sscanf(sc->name, "%7s", socname) != 1) {
119 g_assert_not_reached();
120 }
121
122 for (i = 0; i < sc->num_cpus; i++) {
123 object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
124 sizeof(s->cpu[i]), sc->cpu_type,
125 &error_abort, NULL);
126 }
127
128 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
129 sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
130 typename);
131 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
132 sc->silicon_rev);
133 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
134 "hw-strap1", &error_abort);
135 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
136 "hw-strap2", &error_abort);
137 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
138 "hw-prot-key", &error_abort);
139
140 sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore,
141 sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV);
142
143 sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
144 TYPE_ASPEED_RTC);
145
146 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
147 sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
148 sizeof(s->timerctrl), typename);
149
150 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
151 sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
152 typename);
153
154 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
155 sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
156 typename);
157 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
158 &error_abort);
159
160 for (i = 0; i < sc->spis_num; i++) {
161 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
162 sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
163 sizeof(s->spi[i]), typename);
164 }
165
166 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
167 sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
168 typename);
169 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
170 "ram-size", &error_abort);
171 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
172 "max-ram-size", &error_abort);
173
174 for (i = 0; i < sc->wdts_num; i++) {
175 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
176 sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
177 sizeof(s->wdt[i]), typename);
178 }
179
180 for (i = 0; i < sc->macs_num; i++) {
181 sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
182 sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
183
184 sysbus_init_child_obj(obj, "mii[*]", &s->mii[i], sizeof(s->mii[i]),
185 TYPE_ASPEED_MII);
186 }
187
188 sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
189 TYPE_ASPEED_XDMA);
190
191 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
192 sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),
193 typename);
194
195 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname);
196 sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v),
197 sizeof(s->gpio_1_8v), typename);
198
199 sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
200 TYPE_ASPEED_SDHCI);
201
202 /* Init sd card slot class here so that they're under the correct parent */
203 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
204 sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
205 sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
206 }
207 }
208
209 /*
210 * ASPEED ast2600 has 0xf as cluster ID
211 *
212 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html
213 */
214 static uint64_t aspeed_calc_affinity(int cpu)
215 {
216 return (0xf << ARM_AFF1_SHIFT) | cpu;
217 }
218
219 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
220 {
221 int i;
222 AspeedSoCState *s = ASPEED_SOC(dev);
223 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
224 Error *err = NULL, *local_err = NULL;
225 qemu_irq irq;
226
227 /* IO space */
228 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM],
229 ASPEED_SOC_IOMEM_SIZE);
230
231 /* Video engine stub */
232 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO],
233 0x1000);
234
235 if (s->num_cpus > sc->num_cpus) {
236 warn_report("%s: invalid number of CPUs %d, using default %d",
237 sc->name, s->num_cpus, sc->num_cpus);
238 s->num_cpus = sc->num_cpus;
239 }
240
241 /* CPU */
242 for (i = 0; i < s->num_cpus; i++) {
243 object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC,
244 "psci-conduit", &error_abort);
245 if (s->num_cpus > 1) {
246 object_property_set_int(OBJECT(&s->cpu[i]),
247 ASPEED_A7MPCORE_ADDR,
248 "reset-cbar", &error_abort);
249 }
250 object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i),
251 "mp-affinity", &error_abort);
252
253 object_property_set_int(OBJECT(&s->cpu[i]), 1125000000, "cntfrq",
254 &error_abort);
255
256 /*
257 * TODO: the secondary CPUs are started and a boot helper
258 * is needed when using -kernel
259 */
260
261 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
262 if (err) {
263 error_propagate(errp, err);
264 return;
265 }
266 }
267
268 /* A7MPCORE */
269 object_property_set_int(OBJECT(&s->a7mpcore), s->num_cpus, "num-cpu",
270 &error_abort);
271 object_property_set_int(OBJECT(&s->a7mpcore),
272 ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL,
273 "num-irq", &error_abort);
274
275 object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
276 &error_abort);
277 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
278
279 for (i = 0; i < s->num_cpus; i++) {
280 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
281 DeviceState *d = DEVICE(qemu_get_cpu(i));
282
283 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
284 sysbus_connect_irq(sbd, i, irq);
285 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
286 sysbus_connect_irq(sbd, i + s->num_cpus, irq);
287 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
288 sysbus_connect_irq(sbd, i + 2 * s->num_cpus, irq);
289 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
290 sysbus_connect_irq(sbd, i + 3 * s->num_cpus, irq);
291 }
292
293 /* SRAM */
294 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
295 sc->sram_size, &err);
296 if (err) {
297 error_propagate(errp, err);
298 return;
299 }
300 memory_region_add_subregion(get_system_memory(),
301 sc->memmap[ASPEED_SRAM], &s->sram);
302
303 /* SCU */
304 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
305 if (err) {
306 error_propagate(errp, err);
307 return;
308 }
309 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);
310
311 /* RTC */
312 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
313 if (err) {
314 error_propagate(errp, err);
315 return;
316 }
317 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]);
318 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
319 aspeed_soc_get_irq(s, ASPEED_RTC));
320
321 /* Timer */
322 object_property_set_link(OBJECT(&s->timerctrl),
323 OBJECT(&s->scu), "scu", &error_abort);
324 object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
325 if (err) {
326 error_propagate(errp, err);
327 return;
328 }
329 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
330 sc->memmap[ASPEED_TIMER1]);
331 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
332 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
333 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
334 }
335
336 /* UART - attach an 8250 to the IO space as our UART5 */
337 if (serial_hd(0)) {
338 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
339 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2,
340 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
341 }
342
343 /* I2C */
344 object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err);
345 if (err) {
346 error_propagate(errp, err);
347 return;
348 }
349 object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
350 if (err) {
351 error_propagate(errp, err);
352 return;
353 }
354 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]);
355 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
356 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
357 sc->irqmap[ASPEED_I2C] + i);
358 /*
359 * The AST2600 SoC has one IRQ per I2C bus. Skip the common
360 * IRQ (AST2400 and AST2500) and connect all bussses.
361 */
362 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq);
363 }
364
365 /* FMC, The number of CS is set at the board level */
366 object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err);
367 if (err) {
368 error_propagate(errp, err);
369 return;
370 }
371 object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],
372 "sdram-base", &err);
373 if (err) {
374 error_propagate(errp, err);
375 return;
376 }
377 object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
378 if (err) {
379 error_propagate(errp, err);
380 return;
381 }
382 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]);
383 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
384 s->fmc.ctrl->flash_window_base);
385 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
386 aspeed_soc_get_irq(s, ASPEED_FMC));
387
388 /* SPI */
389 for (i = 0; i < sc->spis_num; i++) {
390 object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
391 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
392 &local_err);
393 error_propagate(&err, local_err);
394 if (err) {
395 error_propagate(errp, err);
396 return;
397 }
398 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
399 sc->memmap[ASPEED_SPI1 + i]);
400 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
401 s->spi[i].ctrl->flash_window_base);
402 }
403
404 /* SDMC - SDRAM Memory Controller */
405 object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
406 if (err) {
407 error_propagate(errp, err);
408 return;
409 }
410 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]);
411
412 /* Watch dog */
413 for (i = 0; i < sc->wdts_num; i++) {
414 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
415
416 object_property_set_link(OBJECT(&s->wdt[i]),
417 OBJECT(&s->scu), "scu", &error_abort);
418 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
419 if (err) {
420 error_propagate(errp, err);
421 return;
422 }
423 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
424 sc->memmap[ASPEED_WDT] + i * awc->offset);
425 }
426
427 /* Net */
428 for (i = 0; i < nb_nics && i < sc->macs_num; i++) {
429 qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
430 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
431 &err);
432 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
433 &local_err);
434 error_propagate(&err, local_err);
435 if (err) {
436 error_propagate(errp, err);
437 return;
438 }
439 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
440 sc->memmap[ASPEED_ETH1 + i]);
441 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
442 aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
443
444 object_property_set_link(OBJECT(&s->mii[i]), OBJECT(&s->ftgmac100[i]),
445 "nic", &error_abort);
446 object_property_set_bool(OBJECT(&s->mii[i]), true, "realized",
447 &err);
448 if (err) {
449 error_propagate(errp, err);
450 return;
451 }
452
453 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0,
454 sc->memmap[ASPEED_MII1 + i]);
455 }
456
457 /* XDMA */
458 object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
459 if (err) {
460 error_propagate(errp, err);
461 return;
462 }
463 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
464 sc->memmap[ASPEED_XDMA]);
465 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
466 aspeed_soc_get_irq(s, ASPEED_XDMA));
467
468 /* GPIO */
469 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
470 if (err) {
471 error_propagate(errp, err);
472 return;
473 }
474 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]);
475 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
476 aspeed_soc_get_irq(s, ASPEED_GPIO));
477
478 object_property_set_bool(OBJECT(&s->gpio_1_8v), true, "realized", &err);
479 if (err) {
480 error_propagate(errp, err);
481 return;
482 }
483 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
484 sc->memmap[ASPEED_GPIO_1_8V]);
485 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
486 aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V));
487
488 /* SDHCI */
489 object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
490 if (err) {
491 error_propagate(errp, err);
492 return;
493 }
494 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
495 sc->memmap[ASPEED_SDHCI]);
496 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
497 aspeed_soc_get_irq(s, ASPEED_SDHCI));
498 }
499
500 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
501 {
502 DeviceClass *dc = DEVICE_CLASS(oc);
503 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
504
505 dc->realize = aspeed_soc_ast2600_realize;
506
507 sc->name = "ast2600-a0";
508 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
509 sc->silicon_rev = AST2600_A0_SILICON_REV;
510 sc->sram_size = 0x10000;
511 sc->spis_num = 2;
512 sc->wdts_num = 4;
513 sc->macs_num = 4;
514 sc->irqmap = aspeed_soc_ast2600_irqmap;
515 sc->memmap = aspeed_soc_ast2600_memmap;
516 sc->num_cpus = 2;
517 }
518
519 static const TypeInfo aspeed_soc_ast2600_type_info = {
520 .name = "ast2600-a0",
521 .parent = TYPE_ASPEED_SOC,
522 .instance_size = sizeof(AspeedSoCState),
523 .instance_init = aspeed_soc_ast2600_init,
524 .class_init = aspeed_soc_ast2600_class_init,
525 .class_size = sizeof(AspeedSoCClass),
526 };
527
528 static void aspeed_soc_register_types(void)
529 {
530 type_register_static(&aspeed_soc_ast2600_type_info);
531 };
532
533 type_init(aspeed_soc_register_types)
AR7 emulation for QEMU