hw/alpha/pci.c

   1 /*
   2  * QEMU Alpha PCI support functions.
   3  *
   4  * Some of this isn't very Alpha specific at all.
   5  *
   6  * ??? Sparse memory access not implemented.
   7  */
   8
   9 #include "config.h"
  10 #include "alpha_sys.h"
  11 #include "qemu/log.h"
  12 #include "sysemu/sysemu.h"
  13
  14
  15 /* PCI config space reads/writes, to byte-word addressable memory.  */
  16 static uint64_t bw_conf1_read(void *opaque, hwaddr addr,
  17                               unsigned size)
  18 {
  19     PCIBus *b = opaque;
  20     return pci_data_read(b, addr, size);
  21 }
  22
  23 static void bw_conf1_write(void *opaque, hwaddr addr,
  24                            uint64_t val, unsigned size)
  25 {
  26     PCIBus *b = opaque;
  27     pci_data_write(b, addr, val, size);
  28 }
  29
  30 const MemoryRegionOps alpha_pci_conf1_ops = {
  31     .read = bw_conf1_read,
  32     .write = bw_conf1_write,
  33     .endianness = DEVICE_LITTLE_ENDIAN,
  34     .impl = {
  35         .min_access_size = 1,
  36         .max_access_size = 4,
  37     },
  38 };
  39
  40 /* PCI/EISA Interrupt Acknowledge Cycle.  */
  41
  42 static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size)
  43 {
  44     return pic_read_irq(isa_pic);
  45 }
  46
  47 static void special_write(void *opaque, hwaddr addr,
  48                           uint64_t val, unsigned size)
  49 {
  50     qemu_log("pci: special write cycle");
  51 }
  52
  53 const MemoryRegionOps alpha_pci_iack_ops = {
  54     .read = iack_read,
  55     .write = special_write,
  56     .endianness = DEVICE_LITTLE_ENDIAN,
  57     .valid = {
  58         .min_access_size = 4,
  59         .max_access_size = 4,
  60     },
  61     .impl = {
  62         .min_access_size = 4,
  63         .max_access_size = 4,
  64     },
  65 };